msm8916-wcd-digital.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2016, The Linux Foundation. All rights reserved.
  3. #include <linux/module.h>
  4. #include <linux/err.h>
  5. #include <linux/kernel.h>
  6. #include <linux/delay.h>
  7. #include <linux/types.h>
  8. #include <linux/clk.h>
  9. #include <linux/of.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/regmap.h>
  12. #include <linux/mfd/syscon.h>
  13. #include <sound/soc.h>
  14. #include <sound/pcm.h>
  15. #include <sound/pcm_params.h>
  16. #include <sound/tlv.h>
  17. #define LPASS_CDC_CLK_RX_RESET_CTL (0x000)
  18. #define LPASS_CDC_CLK_TX_RESET_B1_CTL (0x004)
  19. #define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK BIT(0)
  20. #define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK BIT(1)
  21. #define LPASS_CDC_CLK_DMIC_B1_CTL (0x008)
  22. #define DMIC_B1_CTL_DMIC0_CLK_SEL_MASK GENMASK(3, 1)
  23. #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV2 (0x0 << 1)
  24. #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3 (0x1 << 1)
  25. #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV4 (0x2 << 1)
  26. #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV6 (0x3 << 1)
  27. #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV16 (0x4 << 1)
  28. #define DMIC_B1_CTL_DMIC0_CLK_EN_MASK BIT(0)
  29. #define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE BIT(0)
  30. #define LPASS_CDC_CLK_RX_I2S_CTL (0x00C)
  31. #define RX_I2S_CTL_RX_I2S_MODE_MASK BIT(5)
  32. #define RX_I2S_CTL_RX_I2S_MODE_16 BIT(5)
  33. #define RX_I2S_CTL_RX_I2S_MODE_32 0
  34. #define RX_I2S_CTL_RX_I2S_FS_RATE_MASK GENMASK(2, 0)
  35. #define RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ 0x0
  36. #define RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ 0x1
  37. #define RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ 0x2
  38. #define RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ 0x3
  39. #define RX_I2S_CTL_RX_I2S_FS_RATE_F_96_KHZ 0x4
  40. #define RX_I2S_CTL_RX_I2S_FS_RATE_F_192_KHZ 0x5
  41. #define LPASS_CDC_CLK_TX_I2S_CTL (0x010)
  42. #define TX_I2S_CTL_TX_I2S_MODE_MASK BIT(5)
  43. #define TX_I2S_CTL_TX_I2S_MODE_16 BIT(5)
  44. #define TX_I2S_CTL_TX_I2S_MODE_32 0
  45. #define TX_I2S_CTL_TX_I2S_FS_RATE_MASK GENMASK(2, 0)
  46. #define TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ 0x0
  47. #define TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ 0x1
  48. #define TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ 0x2
  49. #define TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ 0x3
  50. #define TX_I2S_CTL_TX_I2S_FS_RATE_F_96_KHZ 0x4
  51. #define TX_I2S_CTL_TX_I2S_FS_RATE_F_192_KHZ 0x5
  52. #define LPASS_CDC_CLK_OTHR_RESET_B1_CTL (0x014)
  53. #define LPASS_CDC_CLK_TX_CLK_EN_B1_CTL (0x018)
  54. #define LPASS_CDC_CLK_OTHR_CTL (0x01C)
  55. #define LPASS_CDC_CLK_RX_B1_CTL (0x020)
  56. #define LPASS_CDC_CLK_MCLK_CTL (0x024)
  57. #define MCLK_CTL_MCLK_EN_MASK BIT(0)
  58. #define MCLK_CTL_MCLK_EN_ENABLE BIT(0)
  59. #define MCLK_CTL_MCLK_EN_DISABLE 0
  60. #define LPASS_CDC_CLK_PDM_CTL (0x028)
  61. #define LPASS_CDC_CLK_PDM_CTL_PDM_EN_MASK BIT(0)
  62. #define LPASS_CDC_CLK_PDM_CTL_PDM_EN BIT(0)
  63. #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK BIT(1)
  64. #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB BIT(1)
  65. #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_PDM_CLK 0
  66. #define LPASS_CDC_CLK_SD_CTL (0x02C)
  67. #define LPASS_CDC_RX1_B1_CTL (0x040)
  68. #define LPASS_CDC_RX2_B1_CTL (0x060)
  69. #define LPASS_CDC_RX3_B1_CTL (0x080)
  70. #define LPASS_CDC_RX1_B2_CTL (0x044)
  71. #define LPASS_CDC_RX2_B2_CTL (0x064)
  72. #define LPASS_CDC_RX3_B2_CTL (0x084)
  73. #define LPASS_CDC_RX1_B3_CTL (0x048)
  74. #define LPASS_CDC_RX2_B3_CTL (0x068)
  75. #define LPASS_CDC_RX3_B3_CTL (0x088)
  76. #define LPASS_CDC_RX1_B4_CTL (0x04C)
  77. #define LPASS_CDC_RX2_B4_CTL (0x06C)
  78. #define LPASS_CDC_RX3_B4_CTL (0x08C)
  79. #define LPASS_CDC_RX1_B5_CTL (0x050)
  80. #define LPASS_CDC_RX2_B5_CTL (0x070)
  81. #define LPASS_CDC_RX3_B5_CTL (0x090)
  82. #define LPASS_CDC_RX1_B6_CTL (0x054)
  83. #define RXn_B6_CTL_MUTE_MASK BIT(0)
  84. #define RXn_B6_CTL_MUTE_ENABLE BIT(0)
  85. #define RXn_B6_CTL_MUTE_DISABLE 0
  86. #define LPASS_CDC_RX2_B6_CTL (0x074)
  87. #define LPASS_CDC_RX3_B6_CTL (0x094)
  88. #define LPASS_CDC_RX1_VOL_CTL_B1_CTL (0x058)
  89. #define LPASS_CDC_RX2_VOL_CTL_B1_CTL (0x078)
  90. #define LPASS_CDC_RX3_VOL_CTL_B1_CTL (0x098)
  91. #define LPASS_CDC_RX1_VOL_CTL_B2_CTL (0x05C)
  92. #define LPASS_CDC_RX2_VOL_CTL_B2_CTL (0x07C)
  93. #define LPASS_CDC_RX3_VOL_CTL_B2_CTL (0x09C)
  94. #define LPASS_CDC_TOP_GAIN_UPDATE (0x0A0)
  95. #define LPASS_CDC_TOP_CTL (0x0A4)
  96. #define TOP_CTL_DIG_MCLK_FREQ_MASK BIT(0)
  97. #define TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ 0
  98. #define TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ BIT(0)
  99. #define LPASS_CDC_DEBUG_DESER1_CTL (0x0E0)
  100. #define LPASS_CDC_DEBUG_DESER2_CTL (0x0E4)
  101. #define LPASS_CDC_DEBUG_B1_CTL_CFG (0x0E8)
  102. #define LPASS_CDC_DEBUG_B2_CTL_CFG (0x0EC)
  103. #define LPASS_CDC_DEBUG_B3_CTL_CFG (0x0F0)
  104. #define LPASS_CDC_IIR1_GAIN_B1_CTL (0x100)
  105. #define LPASS_CDC_IIR2_GAIN_B1_CTL (0x140)
  106. #define LPASS_CDC_IIR1_GAIN_B2_CTL (0x104)
  107. #define LPASS_CDC_IIR2_GAIN_B2_CTL (0x144)
  108. #define LPASS_CDC_IIR1_GAIN_B3_CTL (0x108)
  109. #define LPASS_CDC_IIR2_GAIN_B3_CTL (0x148)
  110. #define LPASS_CDC_IIR1_GAIN_B4_CTL (0x10C)
  111. #define LPASS_CDC_IIR2_GAIN_B4_CTL (0x14C)
  112. #define LPASS_CDC_IIR1_GAIN_B5_CTL (0x110)
  113. #define LPASS_CDC_IIR2_GAIN_B5_CTL (0x150)
  114. #define LPASS_CDC_IIR1_GAIN_B6_CTL (0x114)
  115. #define LPASS_CDC_IIR2_GAIN_B6_CTL (0x154)
  116. #define LPASS_CDC_IIR1_GAIN_B7_CTL (0x118)
  117. #define LPASS_CDC_IIR2_GAIN_B7_CTL (0x158)
  118. #define LPASS_CDC_IIR1_GAIN_B8_CTL (0x11C)
  119. #define LPASS_CDC_IIR2_GAIN_B8_CTL (0x15C)
  120. #define LPASS_CDC_IIR1_CTL (0x120)
  121. #define LPASS_CDC_IIR2_CTL (0x160)
  122. #define LPASS_CDC_IIR1_GAIN_TIMER_CTL (0x124)
  123. #define LPASS_CDC_IIR2_GAIN_TIMER_CTL (0x164)
  124. #define LPASS_CDC_IIR1_COEF_B1_CTL (0x128)
  125. #define LPASS_CDC_IIR2_COEF_B1_CTL (0x168)
  126. #define LPASS_CDC_IIR1_COEF_B2_CTL (0x12C)
  127. #define LPASS_CDC_IIR2_COEF_B2_CTL (0x16C)
  128. #define LPASS_CDC_CONN_RX1_B1_CTL (0x180)
  129. #define LPASS_CDC_CONN_RX1_B2_CTL (0x184)
  130. #define LPASS_CDC_CONN_RX1_B3_CTL (0x188)
  131. #define LPASS_CDC_CONN_RX2_B1_CTL (0x18C)
  132. #define LPASS_CDC_CONN_RX2_B2_CTL (0x190)
  133. #define LPASS_CDC_CONN_RX2_B3_CTL (0x194)
  134. #define LPASS_CDC_CONN_RX3_B1_CTL (0x198)
  135. #define LPASS_CDC_CONN_RX3_B2_CTL (0x19C)
  136. #define LPASS_CDC_CONN_TX_B1_CTL (0x1A0)
  137. #define LPASS_CDC_CONN_EQ1_B1_CTL (0x1A8)
  138. #define LPASS_CDC_CONN_EQ1_B2_CTL (0x1AC)
  139. #define LPASS_CDC_CONN_EQ1_B3_CTL (0x1B0)
  140. #define LPASS_CDC_CONN_EQ1_B4_CTL (0x1B4)
  141. #define LPASS_CDC_CONN_EQ2_B1_CTL (0x1B8)
  142. #define LPASS_CDC_CONN_EQ2_B2_CTL (0x1BC)
  143. #define LPASS_CDC_CONN_EQ2_B3_CTL (0x1C0)
  144. #define LPASS_CDC_CONN_EQ2_B4_CTL (0x1C4)
  145. #define LPASS_CDC_CONN_TX_I2S_SD1_CTL (0x1C8)
  146. #define LPASS_CDC_TX1_VOL_CTL_TIMER (0x280)
  147. #define LPASS_CDC_TX2_VOL_CTL_TIMER (0x2A0)
  148. #define LPASS_CDC_TX1_VOL_CTL_GAIN (0x284)
  149. #define LPASS_CDC_TX2_VOL_CTL_GAIN (0x2A4)
  150. #define LPASS_CDC_TX1_VOL_CTL_CFG (0x288)
  151. #define TX_VOL_CTL_CFG_MUTE_EN_MASK BIT(0)
  152. #define TX_VOL_CTL_CFG_MUTE_EN_ENABLE BIT(0)
  153. #define LPASS_CDC_TX2_VOL_CTL_CFG (0x2A8)
  154. #define LPASS_CDC_TX1_MUX_CTL (0x28C)
  155. #define TX_MUX_CTL_CUT_OFF_FREQ_MASK GENMASK(5, 4)
  156. #define TX_MUX_CTL_CUT_OFF_FREQ_SHIFT 4
  157. #define TX_MUX_CTL_CF_NEG_3DB_4HZ (0x0 << 4)
  158. #define TX_MUX_CTL_CF_NEG_3DB_75HZ (0x1 << 4)
  159. #define TX_MUX_CTL_CF_NEG_3DB_150HZ (0x2 << 4)
  160. #define TX_MUX_CTL_HPF_BP_SEL_MASK BIT(3)
  161. #define TX_MUX_CTL_HPF_BP_SEL_BYPASS BIT(3)
  162. #define TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS 0
  163. #define LPASS_CDC_TX2_MUX_CTL (0x2AC)
  164. #define LPASS_CDC_TX1_CLK_FS_CTL (0x290)
  165. #define LPASS_CDC_TX2_CLK_FS_CTL (0x2B0)
  166. #define LPASS_CDC_TX1_DMIC_CTL (0x294)
  167. #define LPASS_CDC_TX2_DMIC_CTL (0x2B4)
  168. #define TXN_DMIC_CTL_CLK_SEL_MASK GENMASK(2, 0)
  169. #define TXN_DMIC_CTL_CLK_SEL_DIV2 0x0
  170. #define TXN_DMIC_CTL_CLK_SEL_DIV3 0x1
  171. #define TXN_DMIC_CTL_CLK_SEL_DIV4 0x2
  172. #define TXN_DMIC_CTL_CLK_SEL_DIV6 0x3
  173. #define TXN_DMIC_CTL_CLK_SEL_DIV16 0x4
  174. #define MSM8916_WCD_DIGITAL_RATES (SNDRV_PCM_RATE_8000 | \
  175. SNDRV_PCM_RATE_16000 | \
  176. SNDRV_PCM_RATE_32000 | \
  177. SNDRV_PCM_RATE_48000)
  178. #define MSM8916_WCD_DIGITAL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  179. SNDRV_PCM_FMTBIT_S32_LE)
  180. /* Codec supports 2 IIR filters */
  181. enum {
  182. IIR1 = 0,
  183. IIR2,
  184. IIR_MAX,
  185. };
  186. /* Codec supports 5 bands */
  187. enum {
  188. BAND1 = 0,
  189. BAND2,
  190. BAND3,
  191. BAND4,
  192. BAND5,
  193. BAND_MAX,
  194. };
  195. #define WCD_IIR_FILTER_SIZE (sizeof(u32)*BAND_MAX)
  196. #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
  197. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  198. .info = wcd_iir_filter_info, \
  199. .get = msm8x16_wcd_get_iir_band_audio_mixer, \
  200. .put = msm8x16_wcd_put_iir_band_audio_mixer, \
  201. .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
  202. .iir_idx = iidx, \
  203. .band_idx = bidx, \
  204. .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
  205. } \
  206. }
  207. struct wcd_iir_filter_ctl {
  208. unsigned int iir_idx;
  209. unsigned int band_idx;
  210. struct soc_bytes_ext bytes_ext;
  211. };
  212. struct msm8916_wcd_digital_priv {
  213. struct clk *ahbclk, *mclk;
  214. };
  215. static const unsigned long rx_gain_reg[] = {
  216. LPASS_CDC_RX1_VOL_CTL_B2_CTL,
  217. LPASS_CDC_RX2_VOL_CTL_B2_CTL,
  218. LPASS_CDC_RX3_VOL_CTL_B2_CTL,
  219. };
  220. static const unsigned long tx_gain_reg[] = {
  221. LPASS_CDC_TX1_VOL_CTL_GAIN,
  222. LPASS_CDC_TX2_VOL_CTL_GAIN,
  223. };
  224. static const char *const rx_mix1_text[] = {
  225. "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
  226. };
  227. static const char * const rx_mix2_text[] = {
  228. "ZERO", "IIR1", "IIR2"
  229. };
  230. static const char *const dec_mux_text[] = {
  231. "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2"
  232. };
  233. static const char *const cic_mux_text[] = { "AMIC", "DMIC" };
  234. /* RX1 MIX1 */
  235. static const struct soc_enum rx_mix1_inp_enum[] = {
  236. SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 0, 6, rx_mix1_text),
  237. SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 3, 6, rx_mix1_text),
  238. SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B2_CTL, 0, 6, rx_mix1_text),
  239. };
  240. /* RX2 MIX1 */
  241. static const struct soc_enum rx2_mix1_inp_enum[] = {
  242. SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text),
  243. SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 3, 6, rx_mix1_text),
  244. SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B2_CTL, 0, 6, rx_mix1_text),
  245. };
  246. /* RX3 MIX1 */
  247. static const struct soc_enum rx3_mix1_inp_enum[] = {
  248. SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text),
  249. SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 3, 6, rx_mix1_text),
  250. SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B2_CTL, 0, 6, rx_mix1_text),
  251. };
  252. /* RX1 MIX2 */
  253. static const struct soc_enum rx_mix2_inp1_chain_enum =
  254. SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B3_CTL,
  255. 0, 3, rx_mix2_text);
  256. /* RX2 MIX2 */
  257. static const struct soc_enum rx2_mix2_inp1_chain_enum =
  258. SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B3_CTL,
  259. 0, 3, rx_mix2_text);
  260. /* DEC */
  261. static const struct soc_enum dec1_mux_enum = SOC_ENUM_SINGLE(
  262. LPASS_CDC_CONN_TX_B1_CTL, 0, 6, dec_mux_text);
  263. static const struct soc_enum dec2_mux_enum = SOC_ENUM_SINGLE(
  264. LPASS_CDC_CONN_TX_B1_CTL, 3, 6, dec_mux_text);
  265. /* CIC */
  266. static const struct soc_enum cic1_mux_enum = SOC_ENUM_SINGLE(
  267. LPASS_CDC_TX1_MUX_CTL, 0, 2, cic_mux_text);
  268. static const struct soc_enum cic2_mux_enum = SOC_ENUM_SINGLE(
  269. LPASS_CDC_TX2_MUX_CTL, 0, 2, cic_mux_text);
  270. /* RDAC2 MUX */
  271. static const struct snd_kcontrol_new dec1_mux = SOC_DAPM_ENUM(
  272. "DEC1 MUX Mux", dec1_mux_enum);
  273. static const struct snd_kcontrol_new dec2_mux = SOC_DAPM_ENUM(
  274. "DEC2 MUX Mux", dec2_mux_enum);
  275. static const struct snd_kcontrol_new cic1_mux = SOC_DAPM_ENUM(
  276. "CIC1 MUX Mux", cic1_mux_enum);
  277. static const struct snd_kcontrol_new cic2_mux = SOC_DAPM_ENUM(
  278. "CIC2 MUX Mux", cic2_mux_enum);
  279. static const struct snd_kcontrol_new rx_mix1_inp1_mux = SOC_DAPM_ENUM(
  280. "RX1 MIX1 INP1 Mux", rx_mix1_inp_enum[0]);
  281. static const struct snd_kcontrol_new rx_mix1_inp2_mux = SOC_DAPM_ENUM(
  282. "RX1 MIX1 INP2 Mux", rx_mix1_inp_enum[1]);
  283. static const struct snd_kcontrol_new rx_mix1_inp3_mux = SOC_DAPM_ENUM(
  284. "RX1 MIX1 INP3 Mux", rx_mix1_inp_enum[2]);
  285. static const struct snd_kcontrol_new rx2_mix1_inp1_mux = SOC_DAPM_ENUM(
  286. "RX2 MIX1 INP1 Mux", rx2_mix1_inp_enum[0]);
  287. static const struct snd_kcontrol_new rx2_mix1_inp2_mux = SOC_DAPM_ENUM(
  288. "RX2 MIX1 INP2 Mux", rx2_mix1_inp_enum[1]);
  289. static const struct snd_kcontrol_new rx2_mix1_inp3_mux = SOC_DAPM_ENUM(
  290. "RX2 MIX1 INP3 Mux", rx2_mix1_inp_enum[2]);
  291. static const struct snd_kcontrol_new rx3_mix1_inp1_mux = SOC_DAPM_ENUM(
  292. "RX3 MIX1 INP1 Mux", rx3_mix1_inp_enum[0]);
  293. static const struct snd_kcontrol_new rx3_mix1_inp2_mux = SOC_DAPM_ENUM(
  294. "RX3 MIX1 INP2 Mux", rx3_mix1_inp_enum[1]);
  295. static const struct snd_kcontrol_new rx3_mix1_inp3_mux = SOC_DAPM_ENUM(
  296. "RX3 MIX1 INP3 Mux", rx3_mix1_inp_enum[2]);
  297. static const struct snd_kcontrol_new rx1_mix2_inp1_mux = SOC_DAPM_ENUM(
  298. "RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum);
  299. static const struct snd_kcontrol_new rx2_mix2_inp1_mux = SOC_DAPM_ENUM(
  300. "RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
  301. /* Digital Gain control -38.4 dB to +38.4 dB in 0.3 dB steps */
  302. static const DECLARE_TLV_DB_SCALE(digital_gain, -3840, 30, 0);
  303. /* Cutoff Freq for High Pass Filter at -3dB */
  304. static const char * const hpf_cutoff_text[] = {
  305. "4Hz", "75Hz", "150Hz",
  306. };
  307. static SOC_ENUM_SINGLE_DECL(tx1_hpf_cutoff_enum, LPASS_CDC_TX1_MUX_CTL, 4,
  308. hpf_cutoff_text);
  309. static SOC_ENUM_SINGLE_DECL(tx2_hpf_cutoff_enum, LPASS_CDC_TX2_MUX_CTL, 4,
  310. hpf_cutoff_text);
  311. /* cut off for dc blocker inside rx chain */
  312. static const char * const dc_blocker_cutoff_text[] = {
  313. "4Hz", "75Hz", "150Hz",
  314. };
  315. static SOC_ENUM_SINGLE_DECL(rx1_dcb_cutoff_enum, LPASS_CDC_RX1_B4_CTL, 0,
  316. dc_blocker_cutoff_text);
  317. static SOC_ENUM_SINGLE_DECL(rx2_dcb_cutoff_enum, LPASS_CDC_RX2_B4_CTL, 0,
  318. dc_blocker_cutoff_text);
  319. static SOC_ENUM_SINGLE_DECL(rx3_dcb_cutoff_enum, LPASS_CDC_RX3_B4_CTL, 0,
  320. dc_blocker_cutoff_text);
  321. static int msm8x16_wcd_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
  322. struct snd_kcontrol *kcontrol, int event)
  323. {
  324. struct snd_soc_component *component =
  325. snd_soc_dapm_to_component(w->dapm);
  326. int value = 0, reg = 0;
  327. switch (event) {
  328. case SND_SOC_DAPM_POST_PMU:
  329. if (w->shift == 0)
  330. reg = LPASS_CDC_IIR1_GAIN_B1_CTL;
  331. else if (w->shift == 1)
  332. reg = LPASS_CDC_IIR2_GAIN_B1_CTL;
  333. value = snd_soc_component_read(component, reg);
  334. snd_soc_component_write(component, reg, value);
  335. break;
  336. default:
  337. break;
  338. }
  339. return 0;
  340. }
  341. static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
  342. int iir_idx, int band_idx,
  343. int coeff_idx)
  344. {
  345. uint32_t value = 0;
  346. /* Address does not automatically update if reading */
  347. snd_soc_component_write(component,
  348. (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
  349. ((band_idx * BAND_MAX + coeff_idx)
  350. * sizeof(uint32_t)) & 0x7F);
  351. value |= snd_soc_component_read(component,
  352. (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx));
  353. snd_soc_component_write(component,
  354. (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
  355. ((band_idx * BAND_MAX + coeff_idx)
  356. * sizeof(uint32_t) + 1) & 0x7F);
  357. value |= (snd_soc_component_read(component,
  358. (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 8);
  359. snd_soc_component_write(component,
  360. (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
  361. ((band_idx * BAND_MAX + coeff_idx)
  362. * sizeof(uint32_t) + 2) & 0x7F);
  363. value |= (snd_soc_component_read(component,
  364. (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 16);
  365. snd_soc_component_write(component,
  366. (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
  367. ((band_idx * BAND_MAX + coeff_idx)
  368. * sizeof(uint32_t) + 3) & 0x7F);
  369. /* Mask bits top 2 bits since they are reserved */
  370. value |= ((snd_soc_component_read(component,
  371. (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) & 0x3f) << 24);
  372. return value;
  373. }
  374. static int msm8x16_wcd_get_iir_band_audio_mixer(
  375. struct snd_kcontrol *kcontrol,
  376. struct snd_ctl_elem_value *ucontrol)
  377. {
  378. struct snd_soc_component *component =
  379. snd_soc_kcontrol_component(kcontrol);
  380. struct wcd_iir_filter_ctl *ctl =
  381. (struct wcd_iir_filter_ctl *)kcontrol->private_value;
  382. struct soc_bytes_ext *params = &ctl->bytes_ext;
  383. int iir_idx = ctl->iir_idx;
  384. int band_idx = ctl->band_idx;
  385. u32 coeff[BAND_MAX];
  386. coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
  387. coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
  388. coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
  389. coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
  390. coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
  391. memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
  392. return 0;
  393. }
  394. static void set_iir_band_coeff(struct snd_soc_component *component,
  395. int iir_idx, int band_idx,
  396. uint32_t value)
  397. {
  398. snd_soc_component_write(component,
  399. (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
  400. (value & 0xFF));
  401. snd_soc_component_write(component,
  402. (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
  403. (value >> 8) & 0xFF);
  404. snd_soc_component_write(component,
  405. (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
  406. (value >> 16) & 0xFF);
  407. /* Mask top 2 bits, 7-8 are reserved */
  408. snd_soc_component_write(component,
  409. (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
  410. (value >> 24) & 0x3F);
  411. }
  412. static int msm8x16_wcd_put_iir_band_audio_mixer(
  413. struct snd_kcontrol *kcontrol,
  414. struct snd_ctl_elem_value *ucontrol)
  415. {
  416. struct snd_soc_component *component =
  417. snd_soc_kcontrol_component(kcontrol);
  418. struct wcd_iir_filter_ctl *ctl =
  419. (struct wcd_iir_filter_ctl *)kcontrol->private_value;
  420. struct soc_bytes_ext *params = &ctl->bytes_ext;
  421. int iir_idx = ctl->iir_idx;
  422. int band_idx = ctl->band_idx;
  423. u32 coeff[BAND_MAX];
  424. memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
  425. /* Mask top bit it is reserved */
  426. /* Updates addr automatically for each B2 write */
  427. snd_soc_component_write(component,
  428. (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
  429. (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F);
  430. set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
  431. set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
  432. set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
  433. set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
  434. set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
  435. return 0;
  436. }
  437. static int wcd_iir_filter_info(struct snd_kcontrol *kcontrol,
  438. struct snd_ctl_elem_info *ucontrol)
  439. {
  440. struct wcd_iir_filter_ctl *ctl =
  441. (struct wcd_iir_filter_ctl *)kcontrol->private_value;
  442. struct soc_bytes_ext *params = &ctl->bytes_ext;
  443. ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  444. ucontrol->count = params->max;
  445. return 0;
  446. }
  447. static const struct snd_kcontrol_new msm8916_wcd_digital_snd_controls[] = {
  448. SOC_SINGLE_S8_TLV("RX1 Digital Volume", LPASS_CDC_RX1_VOL_CTL_B2_CTL,
  449. -128, 127, digital_gain),
  450. SOC_SINGLE_S8_TLV("RX2 Digital Volume", LPASS_CDC_RX2_VOL_CTL_B2_CTL,
  451. -128, 127, digital_gain),
  452. SOC_SINGLE_S8_TLV("RX3 Digital Volume", LPASS_CDC_RX3_VOL_CTL_B2_CTL,
  453. -128, 127, digital_gain),
  454. SOC_SINGLE_S8_TLV("TX1 Digital Volume", LPASS_CDC_TX1_VOL_CTL_GAIN,
  455. -128, 127, digital_gain),
  456. SOC_SINGLE_S8_TLV("TX2 Digital Volume", LPASS_CDC_TX2_VOL_CTL_GAIN,
  457. -128, 127, digital_gain),
  458. SOC_ENUM("TX1 HPF Cutoff", tx1_hpf_cutoff_enum),
  459. SOC_ENUM("TX2 HPF Cutoff", tx2_hpf_cutoff_enum),
  460. SOC_SINGLE("TX1 HPF Switch", LPASS_CDC_TX1_MUX_CTL, 3, 1, 0),
  461. SOC_SINGLE("TX2 HPF Switch", LPASS_CDC_TX2_MUX_CTL, 3, 1, 0),
  462. SOC_ENUM("RX1 DCB Cutoff", rx1_dcb_cutoff_enum),
  463. SOC_ENUM("RX2 DCB Cutoff", rx2_dcb_cutoff_enum),
  464. SOC_ENUM("RX3 DCB Cutoff", rx3_dcb_cutoff_enum),
  465. SOC_SINGLE("RX1 DCB Switch", LPASS_CDC_RX1_B5_CTL, 2, 1, 0),
  466. SOC_SINGLE("RX2 DCB Switch", LPASS_CDC_RX2_B5_CTL, 2, 1, 0),
  467. SOC_SINGLE("RX3 DCB Switch", LPASS_CDC_RX3_B5_CTL, 2, 1, 0),
  468. SOC_SINGLE("RX1 Mute Switch", LPASS_CDC_RX1_B6_CTL, 0, 1, 0),
  469. SOC_SINGLE("RX2 Mute Switch", LPASS_CDC_RX2_B6_CTL, 0, 1, 0),
  470. SOC_SINGLE("RX3 Mute Switch", LPASS_CDC_RX3_B6_CTL, 0, 1, 0),
  471. SOC_SINGLE("IIR1 Band1 Switch", LPASS_CDC_IIR1_CTL, 0, 1, 0),
  472. SOC_SINGLE("IIR1 Band2 Switch", LPASS_CDC_IIR1_CTL, 1, 1, 0),
  473. SOC_SINGLE("IIR1 Band3 Switch", LPASS_CDC_IIR1_CTL, 2, 1, 0),
  474. SOC_SINGLE("IIR1 Band4 Switch", LPASS_CDC_IIR1_CTL, 3, 1, 0),
  475. SOC_SINGLE("IIR1 Band5 Switch", LPASS_CDC_IIR1_CTL, 4, 1, 0),
  476. SOC_SINGLE("IIR2 Band1 Switch", LPASS_CDC_IIR2_CTL, 0, 1, 0),
  477. SOC_SINGLE("IIR2 Band2 Switch", LPASS_CDC_IIR2_CTL, 1, 1, 0),
  478. SOC_SINGLE("IIR2 Band3 Switch", LPASS_CDC_IIR2_CTL, 2, 1, 0),
  479. SOC_SINGLE("IIR2 Band4 Switch", LPASS_CDC_IIR2_CTL, 3, 1, 0),
  480. SOC_SINGLE("IIR2 Band5 Switch", LPASS_CDC_IIR2_CTL, 4, 1, 0),
  481. WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
  482. WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
  483. WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
  484. WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
  485. WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
  486. WCD_IIR_FILTER_CTL("IIR2 Band1", IIR2, BAND1),
  487. WCD_IIR_FILTER_CTL("IIR2 Band2", IIR2, BAND2),
  488. WCD_IIR_FILTER_CTL("IIR2 Band3", IIR2, BAND3),
  489. WCD_IIR_FILTER_CTL("IIR2 Band4", IIR2, BAND4),
  490. WCD_IIR_FILTER_CTL("IIR2 Band5", IIR2, BAND5),
  491. SOC_SINGLE_SX_TLV("IIR1 INP1 Volume", LPASS_CDC_IIR1_GAIN_B1_CTL,
  492. 0, -84, 40, digital_gain),
  493. SOC_SINGLE_SX_TLV("IIR1 INP2 Volume", LPASS_CDC_IIR1_GAIN_B2_CTL,
  494. 0, -84, 40, digital_gain),
  495. SOC_SINGLE_SX_TLV("IIR1 INP3 Volume", LPASS_CDC_IIR1_GAIN_B3_CTL,
  496. 0, -84, 40, digital_gain),
  497. SOC_SINGLE_SX_TLV("IIR1 INP4 Volume", LPASS_CDC_IIR1_GAIN_B4_CTL,
  498. 0, -84, 40, digital_gain),
  499. SOC_SINGLE_SX_TLV("IIR2 INP1 Volume", LPASS_CDC_IIR2_GAIN_B1_CTL,
  500. 0, -84, 40, digital_gain),
  501. SOC_SINGLE_SX_TLV("IIR2 INP2 Volume", LPASS_CDC_IIR2_GAIN_B2_CTL,
  502. 0, -84, 40, digital_gain),
  503. SOC_SINGLE_SX_TLV("IIR2 INP3 Volume", LPASS_CDC_IIR2_GAIN_B3_CTL,
  504. 0, -84, 40, digital_gain),
  505. SOC_SINGLE_SX_TLV("IIR2 INP4 Volume", LPASS_CDC_IIR2_GAIN_B4_CTL,
  506. 0, -84, 40, digital_gain),
  507. };
  508. static int msm8916_wcd_digital_enable_interpolator(
  509. struct snd_soc_dapm_widget *w,
  510. struct snd_kcontrol *kcontrol,
  511. int event)
  512. {
  513. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  514. switch (event) {
  515. case SND_SOC_DAPM_POST_PMU:
  516. /* apply the digital gain after the interpolator is enabled */
  517. usleep_range(10000, 10100);
  518. snd_soc_component_write(component, rx_gain_reg[w->shift],
  519. snd_soc_component_read(component, rx_gain_reg[w->shift]));
  520. break;
  521. case SND_SOC_DAPM_POST_PMD:
  522. snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL,
  523. 1 << w->shift, 1 << w->shift);
  524. snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL,
  525. 1 << w->shift, 0x0);
  526. break;
  527. }
  528. return 0;
  529. }
  530. static int msm8916_wcd_digital_enable_dec(struct snd_soc_dapm_widget *w,
  531. struct snd_kcontrol *kcontrol,
  532. int event)
  533. {
  534. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  535. unsigned int decimator = w->shift + 1;
  536. u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
  537. u8 dec_hpf_cut_of_freq;
  538. dec_reset_reg = LPASS_CDC_CLK_TX_RESET_B1_CTL;
  539. tx_vol_ctl_reg = LPASS_CDC_TX1_VOL_CTL_CFG + 32 * (decimator - 1);
  540. tx_mux_ctl_reg = LPASS_CDC_TX1_MUX_CTL + 32 * (decimator - 1);
  541. switch (event) {
  542. case SND_SOC_DAPM_PRE_PMU:
  543. /* Enable TX digital mute */
  544. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  545. TX_VOL_CTL_CFG_MUTE_EN_MASK,
  546. TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
  547. dec_hpf_cut_of_freq = snd_soc_component_read(component, tx_mux_ctl_reg) &
  548. TX_MUX_CTL_CUT_OFF_FREQ_MASK;
  549. dec_hpf_cut_of_freq >>= TX_MUX_CTL_CUT_OFF_FREQ_SHIFT;
  550. if (dec_hpf_cut_of_freq != TX_MUX_CTL_CF_NEG_3DB_150HZ) {
  551. /* set cut of freq to CF_MIN_3DB_150HZ (0x1) */
  552. snd_soc_component_update_bits(component, tx_mux_ctl_reg,
  553. TX_MUX_CTL_CUT_OFF_FREQ_MASK,
  554. TX_MUX_CTL_CF_NEG_3DB_150HZ);
  555. }
  556. break;
  557. case SND_SOC_DAPM_POST_PMU:
  558. /* enable HPF */
  559. snd_soc_component_update_bits(component, tx_mux_ctl_reg,
  560. TX_MUX_CTL_HPF_BP_SEL_MASK,
  561. TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS);
  562. /* apply the digital gain after the decimator is enabled */
  563. snd_soc_component_write(component, tx_gain_reg[w->shift],
  564. snd_soc_component_read(component, tx_gain_reg[w->shift]));
  565. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  566. TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
  567. break;
  568. case SND_SOC_DAPM_PRE_PMD:
  569. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  570. TX_VOL_CTL_CFG_MUTE_EN_MASK,
  571. TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
  572. snd_soc_component_update_bits(component, tx_mux_ctl_reg,
  573. TX_MUX_CTL_HPF_BP_SEL_MASK,
  574. TX_MUX_CTL_HPF_BP_SEL_BYPASS);
  575. break;
  576. case SND_SOC_DAPM_POST_PMD:
  577. snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift,
  578. 1 << w->shift);
  579. snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift, 0x0);
  580. snd_soc_component_update_bits(component, tx_mux_ctl_reg,
  581. TX_MUX_CTL_HPF_BP_SEL_MASK,
  582. TX_MUX_CTL_HPF_BP_SEL_BYPASS);
  583. snd_soc_component_update_bits(component, tx_vol_ctl_reg,
  584. TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
  585. break;
  586. }
  587. return 0;
  588. }
  589. static int msm8916_wcd_digital_enable_dmic(struct snd_soc_dapm_widget *w,
  590. struct snd_kcontrol *kcontrol,
  591. int event)
  592. {
  593. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  594. unsigned int dmic;
  595. int ret;
  596. /* get dmic number out of widget name */
  597. char *dmic_num = strpbrk(w->name, "12");
  598. if (dmic_num == NULL) {
  599. dev_err(component->dev, "Invalid DMIC\n");
  600. return -EINVAL;
  601. }
  602. ret = kstrtouint(dmic_num, 10, &dmic);
  603. if (ret < 0 || dmic > 2) {
  604. dev_err(component->dev, "Invalid DMIC line on the component\n");
  605. return -EINVAL;
  606. }
  607. switch (event) {
  608. case SND_SOC_DAPM_PRE_PMU:
  609. snd_soc_component_update_bits(component, LPASS_CDC_CLK_DMIC_B1_CTL,
  610. DMIC_B1_CTL_DMIC0_CLK_SEL_MASK,
  611. DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3);
  612. switch (dmic) {
  613. case 1:
  614. snd_soc_component_update_bits(component, LPASS_CDC_TX1_DMIC_CTL,
  615. TXN_DMIC_CTL_CLK_SEL_MASK,
  616. TXN_DMIC_CTL_CLK_SEL_DIV3);
  617. break;
  618. case 2:
  619. snd_soc_component_update_bits(component, LPASS_CDC_TX2_DMIC_CTL,
  620. TXN_DMIC_CTL_CLK_SEL_MASK,
  621. TXN_DMIC_CTL_CLK_SEL_DIV3);
  622. break;
  623. }
  624. break;
  625. }
  626. return 0;
  627. }
  628. static const char * const iir_inp1_text[] = {
  629. "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
  630. };
  631. static const struct soc_enum iir1_inp1_mux_enum =
  632. SOC_ENUM_SINGLE(LPASS_CDC_CONN_EQ1_B1_CTL,
  633. 0, 6, iir_inp1_text);
  634. static const struct soc_enum iir2_inp1_mux_enum =
  635. SOC_ENUM_SINGLE(LPASS_CDC_CONN_EQ2_B1_CTL,
  636. 0, 6, iir_inp1_text);
  637. static const struct snd_kcontrol_new iir1_inp1_mux =
  638. SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
  639. static const struct snd_kcontrol_new iir2_inp1_mux =
  640. SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum);
  641. static const struct snd_soc_dapm_widget msm8916_wcd_digital_dapm_widgets[] = {
  642. /*RX stuff */
  643. SND_SOC_DAPM_AIF_IN("I2S RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
  644. SND_SOC_DAPM_AIF_IN("I2S RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
  645. SND_SOC_DAPM_AIF_IN("I2S RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
  646. SND_SOC_DAPM_OUTPUT("PDM_RX1"),
  647. SND_SOC_DAPM_OUTPUT("PDM_RX2"),
  648. SND_SOC_DAPM_OUTPUT("PDM_RX3"),
  649. SND_SOC_DAPM_INPUT("LPASS_PDM_TX"),
  650. SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  651. SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  652. SND_SOC_DAPM_MIXER("RX3 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  653. /* Interpolator */
  654. SND_SOC_DAPM_MIXER_E("RX1 INT", LPASS_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
  655. 0, msm8916_wcd_digital_enable_interpolator,
  656. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  657. SND_SOC_DAPM_MIXER_E("RX2 INT", LPASS_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
  658. 0, msm8916_wcd_digital_enable_interpolator,
  659. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  660. SND_SOC_DAPM_MIXER_E("RX3 INT", LPASS_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
  661. 0, msm8916_wcd_digital_enable_interpolator,
  662. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  663. SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  664. &rx_mix1_inp1_mux),
  665. SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  666. &rx_mix1_inp2_mux),
  667. SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
  668. &rx_mix1_inp3_mux),
  669. SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  670. &rx2_mix1_inp1_mux),
  671. SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  672. &rx2_mix1_inp2_mux),
  673. SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0,
  674. &rx2_mix1_inp3_mux),
  675. SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  676. &rx3_mix1_inp1_mux),
  677. SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  678. &rx3_mix1_inp2_mux),
  679. SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0,
  680. &rx3_mix1_inp3_mux),
  681. SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
  682. &rx1_mix2_inp1_mux),
  683. SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
  684. &rx2_mix2_inp1_mux),
  685. SND_SOC_DAPM_MUX("CIC1 MUX", SND_SOC_NOPM, 0, 0, &cic1_mux),
  686. SND_SOC_DAPM_MUX("CIC2 MUX", SND_SOC_NOPM, 0, 0, &cic2_mux),
  687. /* TX */
  688. SND_SOC_DAPM_MIXER("ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  689. SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  690. SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  691. SND_SOC_DAPM_MUX_E("DEC1 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
  692. &dec1_mux, msm8916_wcd_digital_enable_dec,
  693. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  694. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  695. SND_SOC_DAPM_MUX_E("DEC2 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
  696. &dec2_mux, msm8916_wcd_digital_enable_dec,
  697. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  698. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  699. SND_SOC_DAPM_AIF_OUT("I2S TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
  700. SND_SOC_DAPM_AIF_OUT("I2S TX2", NULL, 0, SND_SOC_NOPM, 0, 0),
  701. SND_SOC_DAPM_AIF_OUT("I2S TX3", NULL, 0, SND_SOC_NOPM, 0, 0),
  702. /* Digital Mic Inputs */
  703. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  704. msm8916_wcd_digital_enable_dmic,
  705. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  706. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
  707. msm8916_wcd_digital_enable_dmic,
  708. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  709. SND_SOC_DAPM_SUPPLY("DMIC_CLK", LPASS_CDC_CLK_DMIC_B1_CTL, 0, 0,
  710. NULL, 0),
  711. SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", LPASS_CDC_CLK_RX_I2S_CTL,
  712. 4, 0, NULL, 0),
  713. SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", LPASS_CDC_CLK_TX_I2S_CTL, 4, 0,
  714. NULL, 0),
  715. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
  716. SND_SOC_DAPM_SUPPLY("PDM_CLK", LPASS_CDC_CLK_PDM_CTL, 0, 0, NULL, 0),
  717. /* Connectivity Clock */
  718. SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, LPASS_CDC_CLK_OTHR_CTL, 2, 0,
  719. NULL, 0),
  720. SND_SOC_DAPM_MIC("Digital Mic1", NULL),
  721. SND_SOC_DAPM_MIC("Digital Mic2", NULL),
  722. /* Sidetone */
  723. SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
  724. SND_SOC_DAPM_PGA_E("IIR1", LPASS_CDC_CLK_SD_CTL, 0, 0, NULL, 0,
  725. msm8x16_wcd_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU),
  726. SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux),
  727. SND_SOC_DAPM_PGA_E("IIR2", LPASS_CDC_CLK_SD_CTL, 1, 0, NULL, 0,
  728. msm8x16_wcd_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU),
  729. };
  730. static int msm8916_wcd_digital_get_clks(struct platform_device *pdev,
  731. struct msm8916_wcd_digital_priv *priv)
  732. {
  733. struct device *dev = &pdev->dev;
  734. priv->ahbclk = devm_clk_get(dev, "ahbix-clk");
  735. if (IS_ERR(priv->ahbclk)) {
  736. dev_err(dev, "failed to get ahbix clk\n");
  737. return PTR_ERR(priv->ahbclk);
  738. }
  739. priv->mclk = devm_clk_get(dev, "mclk");
  740. if (IS_ERR(priv->mclk)) {
  741. dev_err(dev, "failed to get mclk\n");
  742. return PTR_ERR(priv->mclk);
  743. }
  744. return 0;
  745. }
  746. static int msm8916_wcd_digital_component_probe(struct snd_soc_component *component)
  747. {
  748. struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(component->dev);
  749. snd_soc_component_set_drvdata(component, priv);
  750. return 0;
  751. }
  752. static int msm8916_wcd_digital_component_set_sysclk(struct snd_soc_component *component,
  753. int clk_id, int source,
  754. unsigned int freq, int dir)
  755. {
  756. struct msm8916_wcd_digital_priv *p = dev_get_drvdata(component->dev);
  757. return clk_set_rate(p->mclk, freq);
  758. }
  759. static int msm8916_wcd_digital_hw_params(struct snd_pcm_substream *substream,
  760. struct snd_pcm_hw_params *params,
  761. struct snd_soc_dai *dai)
  762. {
  763. u8 tx_fs_rate;
  764. u8 rx_fs_rate;
  765. switch (params_rate(params)) {
  766. case 8000:
  767. tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ;
  768. rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ;
  769. break;
  770. case 16000:
  771. tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ;
  772. rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ;
  773. break;
  774. case 32000:
  775. tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ;
  776. rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ;
  777. break;
  778. case 48000:
  779. tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ;
  780. rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ;
  781. break;
  782. default:
  783. dev_err(dai->component->dev, "Invalid sampling rate %d\n",
  784. params_rate(params));
  785. return -EINVAL;
  786. }
  787. switch (substream->stream) {
  788. case SNDRV_PCM_STREAM_CAPTURE:
  789. snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
  790. TX_I2S_CTL_TX_I2S_FS_RATE_MASK, tx_fs_rate);
  791. break;
  792. case SNDRV_PCM_STREAM_PLAYBACK:
  793. snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
  794. RX_I2S_CTL_RX_I2S_FS_RATE_MASK, rx_fs_rate);
  795. break;
  796. default:
  797. return -EINVAL;
  798. }
  799. switch (params_format(params)) {
  800. case SNDRV_PCM_FORMAT_S16_LE:
  801. snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
  802. TX_I2S_CTL_TX_I2S_MODE_MASK,
  803. TX_I2S_CTL_TX_I2S_MODE_16);
  804. snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
  805. RX_I2S_CTL_RX_I2S_MODE_MASK,
  806. RX_I2S_CTL_RX_I2S_MODE_16);
  807. break;
  808. case SNDRV_PCM_FORMAT_S32_LE:
  809. snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
  810. TX_I2S_CTL_TX_I2S_MODE_MASK,
  811. TX_I2S_CTL_TX_I2S_MODE_32);
  812. snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
  813. RX_I2S_CTL_RX_I2S_MODE_MASK,
  814. RX_I2S_CTL_RX_I2S_MODE_32);
  815. break;
  816. default:
  817. dev_err(dai->dev, "%s: wrong format selected\n", __func__);
  818. return -EINVAL;
  819. }
  820. return 0;
  821. }
  822. static const struct snd_soc_dapm_route msm8916_wcd_digital_audio_map[] = {
  823. {"I2S RX1", NULL, "AIF1 Playback"},
  824. {"I2S RX2", NULL, "AIF1 Playback"},
  825. {"I2S RX3", NULL, "AIF1 Playback"},
  826. {"AIF1 Capture", NULL, "I2S TX1"},
  827. {"AIF1 Capture", NULL, "I2S TX2"},
  828. {"AIF1 Capture", NULL, "I2S TX3"},
  829. {"CIC1 MUX", "DMIC", "DEC1 MUX"},
  830. {"CIC1 MUX", "AMIC", "DEC1 MUX"},
  831. {"CIC2 MUX", "DMIC", "DEC2 MUX"},
  832. {"CIC2 MUX", "AMIC", "DEC2 MUX"},
  833. /* Decimator Inputs */
  834. {"DEC1 MUX", "DMIC1", "DMIC1"},
  835. {"DEC1 MUX", "DMIC2", "DMIC2"},
  836. {"DEC1 MUX", "ADC1", "ADC1"},
  837. {"DEC1 MUX", "ADC2", "ADC2"},
  838. {"DEC1 MUX", "ADC3", "ADC3"},
  839. {"DEC1 MUX", NULL, "CDC_CONN"},
  840. {"DEC2 MUX", "DMIC1", "DMIC1"},
  841. {"DEC2 MUX", "DMIC2", "DMIC2"},
  842. {"DEC2 MUX", "ADC1", "ADC1"},
  843. {"DEC2 MUX", "ADC2", "ADC2"},
  844. {"DEC2 MUX", "ADC3", "ADC3"},
  845. {"DEC2 MUX", NULL, "CDC_CONN"},
  846. {"DMIC1", NULL, "DMIC_CLK"},
  847. {"DMIC2", NULL, "DMIC_CLK"},
  848. {"I2S TX1", NULL, "CIC1 MUX"},
  849. {"I2S TX2", NULL, "CIC2 MUX"},
  850. {"I2S TX1", NULL, "TX_I2S_CLK"},
  851. {"I2S TX2", NULL, "TX_I2S_CLK"},
  852. {"TX_I2S_CLK", NULL, "MCLK"},
  853. {"TX_I2S_CLK", NULL, "PDM_CLK"},
  854. {"ADC1", NULL, "LPASS_PDM_TX"},
  855. {"ADC2", NULL, "LPASS_PDM_TX"},
  856. {"ADC3", NULL, "LPASS_PDM_TX"},
  857. {"I2S RX1", NULL, "RX_I2S_CLK"},
  858. {"I2S RX2", NULL, "RX_I2S_CLK"},
  859. {"I2S RX3", NULL, "RX_I2S_CLK"},
  860. {"RX_I2S_CLK", NULL, "PDM_CLK"},
  861. {"RX_I2S_CLK", NULL, "MCLK"},
  862. {"RX_I2S_CLK", NULL, "CDC_CONN"},
  863. /* RX1 PATH.. */
  864. {"PDM_RX1", NULL, "RX1 INT"},
  865. {"RX1 INT", NULL, "RX1 MIX1"},
  866. {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
  867. {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
  868. {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
  869. {"RX1 MIX1 INP1", "RX1", "I2S RX1"},
  870. {"RX1 MIX1 INP1", "RX2", "I2S RX2"},
  871. {"RX1 MIX1 INP1", "RX3", "I2S RX3"},
  872. {"RX1 MIX1 INP1", "IIR1", "IIR1"},
  873. {"RX1 MIX1 INP1", "IIR2", "IIR2"},
  874. {"RX1 MIX1 INP2", "RX1", "I2S RX1"},
  875. {"RX1 MIX1 INP2", "RX2", "I2S RX2"},
  876. {"RX1 MIX1 INP2", "RX3", "I2S RX3"},
  877. {"RX1 MIX1 INP2", "IIR1", "IIR1"},
  878. {"RX1 MIX1 INP2", "IIR2", "IIR2"},
  879. {"RX1 MIX1 INP3", "RX1", "I2S RX1"},
  880. {"RX1 MIX1 INP3", "RX2", "I2S RX2"},
  881. {"RX1 MIX1 INP3", "RX3", "I2S RX3"},
  882. /* RX2 PATH */
  883. {"PDM_RX2", NULL, "RX2 INT"},
  884. {"RX2 INT", NULL, "RX2 MIX1"},
  885. {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
  886. {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
  887. {"RX2 MIX1", NULL, "RX2 MIX1 INP3"},
  888. {"RX2 MIX1 INP1", "RX1", "I2S RX1"},
  889. {"RX2 MIX1 INP1", "RX2", "I2S RX2"},
  890. {"RX2 MIX1 INP1", "RX3", "I2S RX3"},
  891. {"RX2 MIX1 INP1", "IIR1", "IIR1"},
  892. {"RX2 MIX1 INP1", "IIR2", "IIR2"},
  893. {"RX2 MIX1 INP2", "RX1", "I2S RX1"},
  894. {"RX2 MIX1 INP2", "RX2", "I2S RX2"},
  895. {"RX2 MIX1 INP2", "RX3", "I2S RX3"},
  896. {"RX2 MIX1 INP1", "IIR1", "IIR1"},
  897. {"RX2 MIX1 INP1", "IIR2", "IIR2"},
  898. {"RX2 MIX1 INP3", "RX1", "I2S RX1"},
  899. {"RX2 MIX1 INP3", "RX2", "I2S RX2"},
  900. {"RX2 MIX1 INP3", "RX3", "I2S RX3"},
  901. /* RX3 PATH */
  902. {"PDM_RX3", NULL, "RX3 INT"},
  903. {"RX3 INT", NULL, "RX3 MIX1"},
  904. {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
  905. {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
  906. {"RX3 MIX1", NULL, "RX3 MIX1 INP3"},
  907. {"RX3 MIX1 INP1", "RX1", "I2S RX1"},
  908. {"RX3 MIX1 INP1", "RX2", "I2S RX2"},
  909. {"RX3 MIX1 INP1", "RX3", "I2S RX3"},
  910. {"RX3 MIX1 INP1", "IIR1", "IIR1"},
  911. {"RX3 MIX1 INP1", "IIR2", "IIR2"},
  912. {"RX3 MIX1 INP2", "RX1", "I2S RX1"},
  913. {"RX3 MIX1 INP2", "RX2", "I2S RX2"},
  914. {"RX3 MIX1 INP2", "RX3", "I2S RX3"},
  915. {"RX3 MIX1 INP2", "IIR1", "IIR1"},
  916. {"RX3 MIX1 INP2", "IIR2", "IIR2"},
  917. {"RX1 MIX2 INP1", "IIR1", "IIR1"},
  918. {"RX2 MIX2 INP1", "IIR1", "IIR1"},
  919. {"RX1 MIX2 INP1", "IIR2", "IIR2"},
  920. {"RX2 MIX2 INP1", "IIR2", "IIR2"},
  921. {"IIR1", NULL, "IIR1 INP1 MUX"},
  922. {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
  923. {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
  924. {"IIR2", NULL, "IIR2 INP1 MUX"},
  925. {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"},
  926. {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"},
  927. {"RX3 MIX1 INP3", "RX1", "I2S RX1"},
  928. {"RX3 MIX1 INP3", "RX2", "I2S RX2"},
  929. {"RX3 MIX1 INP3", "RX3", "I2S RX3"},
  930. };
  931. static int msm8916_wcd_digital_startup(struct snd_pcm_substream *substream,
  932. struct snd_soc_dai *dai)
  933. {
  934. struct snd_soc_component *component = dai->component;
  935. struct msm8916_wcd_digital_priv *msm8916_wcd;
  936. unsigned long mclk_rate;
  937. msm8916_wcd = snd_soc_component_get_drvdata(component);
  938. snd_soc_component_update_bits(component, LPASS_CDC_CLK_MCLK_CTL,
  939. MCLK_CTL_MCLK_EN_MASK,
  940. MCLK_CTL_MCLK_EN_ENABLE);
  941. snd_soc_component_update_bits(component, LPASS_CDC_CLK_PDM_CTL,
  942. LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK,
  943. LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB);
  944. mclk_rate = clk_get_rate(msm8916_wcd->mclk);
  945. switch (mclk_rate) {
  946. case 12288000:
  947. snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
  948. TOP_CTL_DIG_MCLK_FREQ_MASK,
  949. TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ);
  950. break;
  951. case 9600000:
  952. snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
  953. TOP_CTL_DIG_MCLK_FREQ_MASK,
  954. TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ);
  955. break;
  956. default:
  957. dev_err(component->dev, "Invalid mclk rate %ld\n", mclk_rate);
  958. break;
  959. }
  960. return 0;
  961. }
  962. static void msm8916_wcd_digital_shutdown(struct snd_pcm_substream *substream,
  963. struct snd_soc_dai *dai)
  964. {
  965. snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_PDM_CTL,
  966. LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK, 0);
  967. }
  968. static const struct snd_soc_dai_ops msm8916_wcd_digital_dai_ops = {
  969. .startup = msm8916_wcd_digital_startup,
  970. .shutdown = msm8916_wcd_digital_shutdown,
  971. .hw_params = msm8916_wcd_digital_hw_params,
  972. };
  973. static struct snd_soc_dai_driver msm8916_wcd_digital_dai[] = {
  974. [0] = {
  975. .name = "msm8916_wcd_digital_i2s_rx1",
  976. .id = 0,
  977. .playback = {
  978. .stream_name = "AIF1 Playback",
  979. .rates = MSM8916_WCD_DIGITAL_RATES,
  980. .formats = MSM8916_WCD_DIGITAL_FORMATS,
  981. .channels_min = 1,
  982. .channels_max = 3,
  983. },
  984. .ops = &msm8916_wcd_digital_dai_ops,
  985. },
  986. [1] = {
  987. .name = "msm8916_wcd_digital_i2s_tx1",
  988. .id = 1,
  989. .capture = {
  990. .stream_name = "AIF1 Capture",
  991. .rates = MSM8916_WCD_DIGITAL_RATES,
  992. .formats = MSM8916_WCD_DIGITAL_FORMATS,
  993. .channels_min = 1,
  994. .channels_max = 4,
  995. },
  996. .ops = &msm8916_wcd_digital_dai_ops,
  997. },
  998. };
  999. static const struct snd_soc_component_driver msm8916_wcd_digital = {
  1000. .probe = msm8916_wcd_digital_component_probe,
  1001. .set_sysclk = msm8916_wcd_digital_component_set_sysclk,
  1002. .controls = msm8916_wcd_digital_snd_controls,
  1003. .num_controls = ARRAY_SIZE(msm8916_wcd_digital_snd_controls),
  1004. .dapm_widgets = msm8916_wcd_digital_dapm_widgets,
  1005. .num_dapm_widgets = ARRAY_SIZE(msm8916_wcd_digital_dapm_widgets),
  1006. .dapm_routes = msm8916_wcd_digital_audio_map,
  1007. .num_dapm_routes = ARRAY_SIZE(msm8916_wcd_digital_audio_map),
  1008. .idle_bias_on = 1,
  1009. .use_pmdown_time = 1,
  1010. .endianness = 1,
  1011. .non_legacy_dai_naming = 1,
  1012. };
  1013. static const struct regmap_config msm8916_codec_regmap_config = {
  1014. .reg_bits = 32,
  1015. .reg_stride = 4,
  1016. .val_bits = 32,
  1017. .max_register = LPASS_CDC_TX2_DMIC_CTL,
  1018. .cache_type = REGCACHE_FLAT,
  1019. };
  1020. static int msm8916_wcd_digital_probe(struct platform_device *pdev)
  1021. {
  1022. struct msm8916_wcd_digital_priv *priv;
  1023. struct device *dev = &pdev->dev;
  1024. void __iomem *base;
  1025. struct regmap *digital_map;
  1026. int ret;
  1027. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  1028. if (!priv)
  1029. return -ENOMEM;
  1030. base = devm_platform_ioremap_resource(pdev, 0);
  1031. if (IS_ERR(base))
  1032. return PTR_ERR(base);
  1033. digital_map =
  1034. devm_regmap_init_mmio(&pdev->dev, base,
  1035. &msm8916_codec_regmap_config);
  1036. if (IS_ERR(digital_map))
  1037. return PTR_ERR(digital_map);
  1038. ret = msm8916_wcd_digital_get_clks(pdev, priv);
  1039. if (ret < 0)
  1040. return ret;
  1041. ret = clk_prepare_enable(priv->ahbclk);
  1042. if (ret < 0) {
  1043. dev_err(dev, "failed to enable ahbclk %d\n", ret);
  1044. return ret;
  1045. }
  1046. ret = clk_prepare_enable(priv->mclk);
  1047. if (ret < 0) {
  1048. dev_err(dev, "failed to enable mclk %d\n", ret);
  1049. goto err_clk;
  1050. }
  1051. dev_set_drvdata(dev, priv);
  1052. ret = devm_snd_soc_register_component(dev, &msm8916_wcd_digital,
  1053. msm8916_wcd_digital_dai,
  1054. ARRAY_SIZE(msm8916_wcd_digital_dai));
  1055. if (ret)
  1056. goto err_mclk;
  1057. return 0;
  1058. err_mclk:
  1059. clk_disable_unprepare(priv->mclk);
  1060. err_clk:
  1061. clk_disable_unprepare(priv->ahbclk);
  1062. return ret;
  1063. }
  1064. static int msm8916_wcd_digital_remove(struct platform_device *pdev)
  1065. {
  1066. struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(&pdev->dev);
  1067. clk_disable_unprepare(priv->mclk);
  1068. clk_disable_unprepare(priv->ahbclk);
  1069. return 0;
  1070. }
  1071. static const struct of_device_id msm8916_wcd_digital_match_table[] = {
  1072. { .compatible = "qcom,msm8916-wcd-digital-codec" },
  1073. { }
  1074. };
  1075. MODULE_DEVICE_TABLE(of, msm8916_wcd_digital_match_table);
  1076. static struct platform_driver msm8916_wcd_digital_driver = {
  1077. .driver = {
  1078. .name = "msm8916-wcd-digital-codec",
  1079. .of_match_table = msm8916_wcd_digital_match_table,
  1080. },
  1081. .probe = msm8916_wcd_digital_probe,
  1082. .remove = msm8916_wcd_digital_remove,
  1083. };
  1084. module_platform_driver(msm8916_wcd_digital_driver);
  1085. MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
  1086. MODULE_DESCRIPTION("MSM8916 WCD Digital Codec driver");
  1087. MODULE_LICENSE("GPL v2");