msm8916-wcd-analog.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2016, The Linux Foundation. All rights reserved.
  3. #include <linux/module.h>
  4. #include <linux/err.h>
  5. #include <linux/kernel.h>
  6. #include <linux/delay.h>
  7. #include <linux/regulator/consumer.h>
  8. #include <linux/types.h>
  9. #include <linux/clk.h>
  10. #include <linux/of.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/regmap.h>
  13. #include <sound/soc.h>
  14. #include <sound/pcm.h>
  15. #include <sound/pcm_params.h>
  16. #include <sound/tlv.h>
  17. #include <sound/jack.h>
  18. #define CDC_D_REVISION1 (0xf000)
  19. #define CDC_D_PERPH_SUBTYPE (0xf005)
  20. #define CDC_D_INT_EN_SET (0xf015)
  21. #define CDC_D_INT_EN_CLR (0xf016)
  22. #define MBHC_SWITCH_INT BIT(7)
  23. #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6)
  24. #define MBHC_BUTTON_PRESS_DET BIT(5)
  25. #define MBHC_BUTTON_RELEASE_DET BIT(4)
  26. #define CDC_D_CDC_RST_CTL (0xf046)
  27. #define RST_CTL_DIG_SW_RST_N_MASK BIT(7)
  28. #define RST_CTL_DIG_SW_RST_N_RESET 0
  29. #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7)
  30. #define CDC_D_CDC_TOP_CLK_CTL (0xf048)
  31. #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3))
  32. #define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2)
  33. #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3)
  34. #define CDC_D_CDC_ANA_CLK_CTL (0xf049)
  35. #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
  36. #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0)
  37. #define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1)
  38. #define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4)
  39. #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4)
  40. #define ANA_CLK_CTL_TXA_CLK25_EN BIT(5)
  41. #define CDC_D_CDC_DIG_CLK_CTL (0xf04A)
  42. #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0)
  43. #define DIG_CLK_CTL_RXD2_CLK_EN BIT(1)
  44. #define DIG_CLK_CTL_RXD3_CLK_EN BIT(2)
  45. #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3)
  46. #define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3)
  47. #define DIG_CLK_CTL_TXD_CLK_EN BIT(4)
  48. #define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6)
  49. #define DIG_CLK_CTL_NCP_CLK_EN BIT(6)
  50. #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7)
  51. #define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7)
  52. #define CDC_D_CDC_CONN_TX1_CTL (0xf050)
  53. #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0)
  54. #define CONN_TX1_SERIAL_TX1_ADC_1 0x0
  55. #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1
  56. #define CONN_TX1_SERIAL_TX1_ZERO 0x2
  57. #define CDC_D_CDC_CONN_TX2_CTL (0xf051)
  58. #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0)
  59. #define CONN_TX2_SERIAL_TX2_ADC_2 0x0
  60. #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1
  61. #define CONN_TX2_SERIAL_TX2_ZERO 0x2
  62. #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052)
  63. #define CDC_D_CDC_CONN_RX1_CTL (0xf053)
  64. #define CDC_D_CDC_CONN_RX2_CTL (0xf054)
  65. #define CDC_D_CDC_CONN_RX3_CTL (0xf055)
  66. #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056)
  67. #define CDC_D_SEC_ACCESS (0xf0D0)
  68. #define CDC_D_PERPH_RESET_CTL3 (0xf0DA)
  69. #define CDC_D_PERPH_RESET_CTL4 (0xf0DB)
  70. #define CDC_A_REVISION1 (0xf100)
  71. #define CDC_A_REVISION2 (0xf101)
  72. #define CDC_A_REVISION3 (0xf102)
  73. #define CDC_A_REVISION4 (0xf103)
  74. #define CDC_A_PERPH_TYPE (0xf104)
  75. #define CDC_A_PERPH_SUBTYPE (0xf105)
  76. #define CDC_A_INT_RT_STS (0xf110)
  77. #define CDC_A_INT_SET_TYPE (0xf111)
  78. #define CDC_A_INT_POLARITY_HIGH (0xf112)
  79. #define CDC_A_INT_POLARITY_LOW (0xf113)
  80. #define CDC_A_INT_LATCHED_CLR (0xf114)
  81. #define CDC_A_INT_EN_SET (0xf115)
  82. #define CDC_A_INT_EN_CLR (0xf116)
  83. #define CDC_A_INT_LATCHED_STS (0xf118)
  84. #define CDC_A_INT_PENDING_STS (0xf119)
  85. #define CDC_A_INT_MID_SEL (0xf11A)
  86. #define CDC_A_INT_PRIORITY (0xf11B)
  87. #define CDC_A_MICB_1_EN (0xf140)
  88. #define MICB_1_EN_MICB_ENABLE BIT(7)
  89. #define MICB_1_EN_BYP_CAP_MASK BIT(6)
  90. #define MICB_1_EN_NO_EXT_BYP_CAP BIT(6)
  91. #define MICB_1_EN_EXT_BYP_CAP 0
  92. #define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5)
  93. #define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5)
  94. #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)
  95. #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4)
  96. #define MICB_1_EN_PULL_UP_EN_MASK BIT(4)
  97. #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0)
  98. #define MICB_1_EN_TX3_GND_SEL_TX_GND 0
  99. #define CDC_A_MICB_1_VAL (0xf141)
  100. #define MICB_MIN_VAL 1600
  101. #define MICB_STEP_SIZE 50
  102. #define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3)
  103. #define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3)
  104. #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3)
  105. #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3)
  106. #define CDC_A_MICB_1_CTL (0xf142)
  107. #define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1)
  108. #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1)
  109. #define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5)
  110. #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5)
  111. #define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6)
  112. #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6)
  113. #define CDC_A_MICB_1_INT_RBIAS (0xf143)
  114. #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7)
  115. #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7)
  116. #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0
  117. #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6)
  118. #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6)
  119. #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0
  120. #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4)
  121. #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4)
  122. #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0
  123. #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3)
  124. #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3)
  125. #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0
  126. #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1)
  127. #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1)
  128. #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0
  129. #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0)
  130. #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
  131. #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0
  132. #define CDC_A_MICB_2_EN (0xf144)
  133. #define CDC_A_MICB_2_EN_ENABLE BIT(7)
  134. #define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5)
  135. #define CDC_A_MICB_2_PULL_DOWN_EN BIT(5)
  136. #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145)
  137. #define CDC_A_MASTER_BIAS_CTL (0xf146)
  138. #define CDC_A_MBHC_DET_CTL_1 (0xf147)
  139. #define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7)
  140. #define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6)
  141. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5)
  142. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0)
  143. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5)
  144. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5)
  145. #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4)
  146. #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3)
  147. #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3)
  148. #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2)
  149. #define CDC_A_MBHC_DET_CTL_2 (0xf150)
  150. #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6))
  151. #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5)
  152. #define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3)
  153. #define CDC_A_HPHL_PLUG_TYPE_NO BIT(4)
  154. #define CDC_A_GND_PLUG_TYPE_NO BIT(3)
  155. #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0)
  156. #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0)
  157. #define CDC_A_MBHC_FSM_CTL (0xf151)
  158. #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7)
  159. #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7)
  160. #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4)
  161. #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4)
  162. #define CDC_A_MBHC_DBNC_TIMER (0xf152)
  163. #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3)
  164. #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4)
  165. #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153)
  166. #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154)
  167. #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155)
  168. #define CDC_A_MBHC_BTN3_CTL (0xf156)
  169. #define CDC_A_MBHC_BTN4_CTL (0xf157)
  170. #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2)
  171. #define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2)
  172. #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5)
  173. #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5)
  174. #define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \
  175. CDC_A_MBHC_BTN_VREF_FINE_MASK)
  176. #define CDC_A_MBHC_RESULT_1 (0xf158)
  177. #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0)
  178. #define CDC_A_TX_1_EN (0xf160)
  179. #define CDC_A_TX_2_EN (0xf161)
  180. #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162)
  181. #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163)
  182. #define CDC_A_TX_1_2_ATEST_CTL (0xf164)
  183. #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165)
  184. #define CDC_A_TX_3_EN (0xf167)
  185. #define CDC_A_NCP_EN (0xf180)
  186. #define CDC_A_NCP_CLK (0xf181)
  187. #define CDC_A_NCP_FBCTRL (0xf183)
  188. #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5)
  189. #define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5)
  190. #define CDC_A_NCP_BIAS (0xf184)
  191. #define CDC_A_NCP_VCTRL (0xf185)
  192. #define CDC_A_NCP_TEST (0xf186)
  193. #define CDC_A_NCP_CLIM_ADDR (0xf187)
  194. #define CDC_A_RX_CLOCK_DIVIDER (0xf190)
  195. #define CDC_A_RX_COM_OCP_CTL (0xf191)
  196. #define CDC_A_RX_COM_OCP_COUNT (0xf192)
  197. #define CDC_A_RX_COM_BIAS_DAC (0xf193)
  198. #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7)
  199. #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7)
  200. #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0)
  201. #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0)
  202. #define CDC_A_RX_HPH_BIAS_PA (0xf194)
  203. #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195)
  204. #define CDC_A_RX_HPH_BIAS_CNP (0xf196)
  205. #define CDC_A_RX_HPH_CNP_EN (0xf197)
  206. #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B)
  207. #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
  208. #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1)
  209. #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D)
  210. #define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1)
  211. #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
  212. #define CDC_A_RX_EAR_CTL (0xf19E)
  213. #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0)
  214. #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0)
  215. #define RX_EAR_CTL_PA_EAR_PA_EN_MASK BIT(6)
  216. #define RX_EAR_CTL_PA_EAR_PA_EN_ENABLE BIT(6)
  217. #define RX_EAR_CTL_PA_SEL_MASK BIT(7)
  218. #define RX_EAR_CTL_PA_SEL BIT(7)
  219. #define CDC_A_SPKR_DAC_CTL (0xf1B0)
  220. #define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4)
  221. #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0
  222. #define CDC_A_SPKR_DRV_CTL (0xf1B2)
  223. #define SPKR_DRV_CTL_DEF_MASK 0xEF
  224. #define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7)
  225. #define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7)
  226. #define SPKR_DRV_CAL_EN BIT(6)
  227. #define SPKR_DRV_SETTLE_EN BIT(5)
  228. #define SPKR_DRV_FW_EN BIT(3)
  229. #define SPKR_DRV_BOOST_SET BIT(2)
  230. #define SPKR_DRV_CMFB_SET BIT(1)
  231. #define SPKR_DRV_GAIN_SET BIT(0)
  232. #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \
  233. SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
  234. SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
  235. SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET)
  236. #define CDC_A_SPKR_OCP_CTL (0xf1B4)
  237. #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5)
  238. #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0)
  239. #define SPKR_PWRSTG_CTL_DAC_EN BIT(0)
  240. #define SPKR_PWRSTG_CTL_MASK 0xE0
  241. #define SPKR_PWRSTG_CTL_BBM_MASK BIT(7)
  242. #define SPKR_PWRSTG_CTL_BBM_EN BIT(7)
  243. #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6)
  244. #define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6)
  245. #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5)
  246. #define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5)
  247. #define CDC_A_SPKR_DRV_DBG (0xf1B7)
  248. #define CDC_A_CURRENT_LIMIT (0xf1C0)
  249. #define CDC_A_BOOST_EN_CTL (0xf1C3)
  250. #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4)
  251. #define CDC_A_SEC_ACCESS (0xf1D0)
  252. #define CDC_A_PERPH_RESET_CTL3 (0xf1DA)
  253. #define CDC_A_PERPH_RESET_CTL4 (0xf1DB)
  254. #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  255. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
  256. #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  257. SNDRV_PCM_FMTBIT_S32_LE)
  258. static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  259. SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4;
  260. static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET;
  261. static const char * const supply_names[] = {
  262. "vdd-cdc-io",
  263. "vdd-cdc-tx-rx-cx",
  264. };
  265. #define MBHC_MAX_BUTTONS (5)
  266. struct pm8916_wcd_analog_priv {
  267. u16 pmic_rev;
  268. u16 codec_version;
  269. bool mbhc_btn_enabled;
  270. /* special event to detect accessory type */
  271. int mbhc_btn0_released;
  272. bool detect_accessory_type;
  273. struct clk *mclk;
  274. struct snd_soc_component *component;
  275. struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  276. struct snd_soc_jack *jack;
  277. bool hphl_jack_type_normally_open;
  278. bool gnd_jack_type_normally_open;
  279. /* Voltage threshold when internal current source of 100uA is used */
  280. u32 vref_btn_cs[MBHC_MAX_BUTTONS];
  281. /* Voltage threshold when microphone bias is ON */
  282. u32 vref_btn_micb[MBHC_MAX_BUTTONS];
  283. unsigned int micbias1_cap_mode;
  284. unsigned int micbias2_cap_mode;
  285. unsigned int micbias_mv;
  286. };
  287. static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
  288. static const char *const rdac2_mux_text[] = { "RX1", "RX2" };
  289. static const char *const hph_text[] = { "ZERO", "Switch", };
  290. static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT(
  291. ARRAY_SIZE(hph_text), hph_text);
  292. static const struct snd_kcontrol_new ear_mux = SOC_DAPM_ENUM("EAR_S", hph_enum);
  293. static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum);
  294. static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum);
  295. /* ADC2 MUX */
  296. static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT(
  297. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  298. /* RDAC2 MUX */
  299. static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE(
  300. CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text);
  301. static const struct snd_kcontrol_new spkr_switch[] = {
  302. SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
  303. };
  304. static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM(
  305. "RDAC2 MUX Mux", rdac2_mux_enum);
  306. static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM(
  307. "ADC2 MUX Mux", adc2_enum);
  308. /* Analog Gain control 0 dB to +24 dB in 6 dB steps */
  309. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
  310. static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = {
  311. SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
  312. SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
  313. SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
  314. };
  315. static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component)
  316. {
  317. struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
  318. snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
  319. MICB_1_CTL_EXT_PRECHARG_EN_MASK |
  320. MICB_1_CTL_INT_PRECHARG_BYP_MASK,
  321. MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL
  322. | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE);
  323. if (wcd->micbias_mv) {
  324. snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL,
  325. MICB_1_VAL_MICB_OUT_VAL_MASK,
  326. MICB_VOLTAGE_REGVAL(wcd->micbias_mv));
  327. /*
  328. * Special headset needs MICBIAS as 2.7V so wait for
  329. * 50 msec for the MICBIAS to reach 2.7 volts.
  330. */
  331. if (wcd->micbias_mv >= 2700)
  332. msleep(50);
  333. }
  334. snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
  335. MICB_1_CTL_EXT_PRECHARG_EN_MASK |
  336. MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0);
  337. }
  338. static int pm8916_wcd_analog_enable_micbias(struct snd_soc_component *component,
  339. int event, unsigned int cap_mode)
  340. {
  341. switch (event) {
  342. case SND_SOC_DAPM_POST_PMU:
  343. pm8916_wcd_analog_micbias_enable(component);
  344. snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
  345. MICB_1_EN_BYP_CAP_MASK, cap_mode);
  346. break;
  347. }
  348. return 0;
  349. }
  350. static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_dapm_widget *w,
  351. struct snd_kcontrol *kcontrol,
  352. int event)
  353. {
  354. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  355. switch (event) {
  356. case SND_SOC_DAPM_PRE_PMU:
  357. snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
  358. MICB_1_EN_OPA_STG2_TAIL_CURR_MASK,
  359. MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA);
  360. break;
  361. }
  362. return 0;
  363. }
  364. static int pm8916_wcd_analog_enable_micbias1(struct snd_soc_dapm_widget *w,
  365. struct snd_kcontrol *kcontrol,
  366. int event)
  367. {
  368. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  369. struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
  370. return pm8916_wcd_analog_enable_micbias(component, event,
  371. wcd->micbias1_cap_mode);
  372. }
  373. static int pm8916_wcd_analog_enable_micbias2(struct snd_soc_dapm_widget *w,
  374. struct snd_kcontrol *kcontrol,
  375. int event)
  376. {
  377. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  378. struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
  379. return pm8916_wcd_analog_enable_micbias(component, event,
  380. wcd->micbias2_cap_mode);
  381. }
  382. static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv,
  383. bool micbias2_enabled)
  384. {
  385. struct snd_soc_component *component = priv->component;
  386. u32 coarse, fine, reg_val, reg_addr;
  387. int *vrefs, i;
  388. if (!micbias2_enabled) { /* use internal 100uA Current source */
  389. /* Enable internal 2.2k Internal Rbias Resistor */
  390. snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
  391. MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
  392. MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
  393. /* Remove pull down on MIC BIAS2 */
  394. snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
  395. CDC_A_MICB_2_PULL_DOWN_EN_MASK,
  396. 0);
  397. /* enable 100uA internal current source */
  398. snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
  399. CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK,
  400. CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA);
  401. }
  402. snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
  403. CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK,
  404. CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN);
  405. if (micbias2_enabled)
  406. vrefs = &priv->vref_btn_micb[0];
  407. else
  408. vrefs = &priv->vref_btn_cs[0];
  409. /* program vref ranges for all the buttons */
  410. reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0;
  411. for (i = 0; i < MBHC_MAX_BUTTONS; i++) {
  412. /* split mv in to coarse parts of 100mv & fine parts of 12mv */
  413. coarse = (vrefs[i] / 100);
  414. fine = ((vrefs[i] % 100) / 12);
  415. reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) |
  416. (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT);
  417. snd_soc_component_update_bits(component, reg_addr,
  418. CDC_A_MBHC_BTN_VREF_MASK,
  419. reg_val);
  420. reg_addr++;
  421. }
  422. return 0;
  423. }
  424. static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd)
  425. {
  426. struct snd_soc_component *component = wcd->component;
  427. bool micbias_enabled = false;
  428. u32 plug_type = 0;
  429. u32 int_en_mask;
  430. snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1,
  431. CDC_A_MBHC_DET_CTL_L_DET_EN |
  432. CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION |
  433. CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO |
  434. CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN);
  435. if (wcd->hphl_jack_type_normally_open)
  436. plug_type |= CDC_A_HPHL_PLUG_TYPE_NO;
  437. if (wcd->gnd_jack_type_normally_open)
  438. plug_type |= CDC_A_GND_PLUG_TYPE_NO;
  439. snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2,
  440. CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 |
  441. CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD |
  442. plug_type |
  443. CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN);
  444. snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER,
  445. CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS |
  446. CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS);
  447. /* enable MBHC clock */
  448. snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL,
  449. DIG_CLK_CTL_D_MBHC_CLK_EN_MASK,
  450. DIG_CLK_CTL_D_MBHC_CLK_EN);
  451. if (snd_soc_component_read(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE)
  452. micbias_enabled = true;
  453. pm8916_mbhc_configure_bias(wcd, micbias_enabled);
  454. int_en_mask = MBHC_SWITCH_INT;
  455. if (wcd->mbhc_btn_enabled)
  456. int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET;
  457. snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0);
  458. snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask);
  459. wcd->mbhc_btn0_released = false;
  460. wcd->detect_accessory_type = true;
  461. }
  462. static int pm8916_wcd_analog_enable_micbias_int2(struct
  463. snd_soc_dapm_widget
  464. *w, struct snd_kcontrol
  465. *kcontrol, int event)
  466. {
  467. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  468. struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
  469. switch (event) {
  470. case SND_SOC_DAPM_PRE_PMU:
  471. snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
  472. CDC_A_MICB_2_PULL_DOWN_EN_MASK, 0);
  473. break;
  474. case SND_SOC_DAPM_POST_PMU:
  475. pm8916_mbhc_configure_bias(wcd, true);
  476. break;
  477. case SND_SOC_DAPM_POST_PMD:
  478. pm8916_mbhc_configure_bias(wcd, false);
  479. break;
  480. }
  481. return pm8916_wcd_analog_enable_micbias_int(w, kcontrol, event);
  482. }
  483. static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,
  484. struct snd_kcontrol *kcontrol,
  485. int event)
  486. {
  487. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  488. u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2;
  489. u8 init_bit_shift;
  490. if (w->reg == CDC_A_TX_1_EN)
  491. init_bit_shift = 5;
  492. else
  493. init_bit_shift = 4;
  494. switch (event) {
  495. case SND_SOC_DAPM_PRE_PMU:
  496. if (w->reg == CDC_A_TX_2_EN)
  497. snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
  498. MICB_1_CTL_CFILT_REF_SEL_MASK,
  499. MICB_1_CTL_CFILT_REF_SEL_HPF_REF);
  500. /*
  501. * Add delay of 10 ms to give sufficient time for the voltage
  502. * to shoot up and settle so that the txfe init does not
  503. * happen when the input voltage is changing too much.
  504. */
  505. usleep_range(10000, 10010);
  506. snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift,
  507. 1 << init_bit_shift);
  508. switch (w->reg) {
  509. case CDC_A_TX_1_EN:
  510. snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
  511. CONN_TX1_SERIAL_TX1_MUX,
  512. CONN_TX1_SERIAL_TX1_ADC_1);
  513. break;
  514. case CDC_A_TX_2_EN:
  515. case CDC_A_TX_3_EN:
  516. snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
  517. CONN_TX2_SERIAL_TX2_MUX,
  518. CONN_TX2_SERIAL_TX2_ADC_2);
  519. break;
  520. }
  521. break;
  522. case SND_SOC_DAPM_POST_PMU:
  523. /*
  524. * Add delay of 12 ms before deasserting the init
  525. * to reduce the tx pop
  526. */
  527. usleep_range(12000, 12010);
  528. snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00);
  529. break;
  530. case SND_SOC_DAPM_POST_PMD:
  531. switch (w->reg) {
  532. case CDC_A_TX_1_EN:
  533. snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
  534. CONN_TX1_SERIAL_TX1_MUX,
  535. CONN_TX1_SERIAL_TX1_ZERO);
  536. break;
  537. case CDC_A_TX_2_EN:
  538. snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
  539. MICB_1_CTL_CFILT_REF_SEL_MASK, 0);
  540. fallthrough;
  541. case CDC_A_TX_3_EN:
  542. snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
  543. CONN_TX2_SERIAL_TX2_MUX,
  544. CONN_TX2_SERIAL_TX2_ZERO);
  545. break;
  546. }
  547. break;
  548. }
  549. return 0;
  550. }
  551. static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,
  552. struct snd_kcontrol *kcontrol,
  553. int event)
  554. {
  555. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  556. switch (event) {
  557. case SND_SOC_DAPM_PRE_PMU:
  558. snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
  559. SPKR_PWRSTG_CTL_DAC_EN_MASK |
  560. SPKR_PWRSTG_CTL_BBM_MASK |
  561. SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
  562. SPKR_PWRSTG_CTL_CLAMP_EN_MASK,
  563. SPKR_PWRSTG_CTL_DAC_EN|
  564. SPKR_PWRSTG_CTL_BBM_EN |
  565. SPKR_PWRSTG_CTL_HBRDGE_EN |
  566. SPKR_PWRSTG_CTL_CLAMP_EN);
  567. snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
  568. RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK,
  569. RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE);
  570. break;
  571. case SND_SOC_DAPM_POST_PMU:
  572. snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL,
  573. SPKR_DRV_CTL_DEF_MASK,
  574. SPKR_DRV_CTL_DEF_VAL);
  575. snd_soc_component_update_bits(component, w->reg,
  576. SPKR_DRV_CLASSD_PA_EN_MASK,
  577. SPKR_DRV_CLASSD_PA_EN_ENABLE);
  578. break;
  579. case SND_SOC_DAPM_POST_PMD:
  580. snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
  581. SPKR_PWRSTG_CTL_DAC_EN_MASK|
  582. SPKR_PWRSTG_CTL_BBM_MASK |
  583. SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
  584. SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0);
  585. snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL,
  586. SPKR_DAC_CTL_DAC_RESET_MASK,
  587. SPKR_DAC_CTL_DAC_RESET_NORMAL);
  588. snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
  589. RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0);
  590. break;
  591. }
  592. return 0;
  593. }
  594. static int pm8916_wcd_analog_enable_ear_pa(struct snd_soc_dapm_widget *w,
  595. struct snd_kcontrol *kcontrol,
  596. int event)
  597. {
  598. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  599. switch (event) {
  600. case SND_SOC_DAPM_PRE_PMU:
  601. snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
  602. RX_EAR_CTL_PA_SEL_MASK, RX_EAR_CTL_PA_SEL);
  603. break;
  604. case SND_SOC_DAPM_POST_PMU:
  605. snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
  606. RX_EAR_CTL_PA_EAR_PA_EN_MASK,
  607. RX_EAR_CTL_PA_EAR_PA_EN_ENABLE);
  608. break;
  609. case SND_SOC_DAPM_POST_PMD:
  610. snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
  611. RX_EAR_CTL_PA_EAR_PA_EN_MASK, 0);
  612. /* Delay to reduce ear turn off pop */
  613. usleep_range(7000, 7100);
  614. snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
  615. RX_EAR_CTL_PA_SEL_MASK, 0);
  616. break;
  617. }
  618. return 0;
  619. }
  620. static const struct reg_default wcd_reg_defaults_2_0[] = {
  621. {CDC_A_RX_COM_OCP_CTL, 0xD1},
  622. {CDC_A_RX_COM_OCP_COUNT, 0xFF},
  623. {CDC_D_SEC_ACCESS, 0xA5},
  624. {CDC_D_PERPH_RESET_CTL3, 0x0F},
  625. {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
  626. {CDC_A_NCP_FBCTRL, 0x28},
  627. {CDC_A_SPKR_DRV_CTL, 0x69},
  628. {CDC_A_SPKR_DRV_DBG, 0x01},
  629. {CDC_A_BOOST_EN_CTL, 0x5F},
  630. {CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
  631. {CDC_A_SEC_ACCESS, 0xA5},
  632. {CDC_A_PERPH_RESET_CTL3, 0x0F},
  633. {CDC_A_CURRENT_LIMIT, 0x82},
  634. {CDC_A_SPKR_DAC_CTL, 0x03},
  635. {CDC_A_SPKR_OCP_CTL, 0xE1},
  636. {CDC_A_MASTER_BIAS_CTL, 0x30},
  637. };
  638. static int pm8916_wcd_analog_probe(struct snd_soc_component *component)
  639. {
  640. struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
  641. int err, reg;
  642. err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
  643. if (err != 0) {
  644. dev_err(component->dev, "failed to enable regulators (%d)\n", err);
  645. return err;
  646. }
  647. snd_soc_component_init_regmap(component,
  648. dev_get_regmap(component->dev->parent, NULL));
  649. snd_soc_component_set_drvdata(component, priv);
  650. priv->pmic_rev = snd_soc_component_read(component, CDC_D_REVISION1);
  651. priv->codec_version = snd_soc_component_read(component, CDC_D_PERPH_SUBTYPE);
  652. dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n",
  653. priv->pmic_rev, priv->codec_version);
  654. snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01);
  655. snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01);
  656. for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
  657. snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg,
  658. wcd_reg_defaults_2_0[reg].def);
  659. priv->component = component;
  660. snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
  661. RST_CTL_DIG_SW_RST_N_MASK,
  662. RST_CTL_DIG_SW_RST_N_REMOVE_RESET);
  663. pm8916_wcd_setup_mbhc(priv);
  664. return 0;
  665. }
  666. static void pm8916_wcd_analog_remove(struct snd_soc_component *component)
  667. {
  668. struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
  669. snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
  670. RST_CTL_DIG_SW_RST_N_MASK, 0);
  671. regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
  672. priv->supplies);
  673. }
  674. static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = {
  675. {"PDM_RX1", NULL, "PDM Playback"},
  676. {"PDM_RX2", NULL, "PDM Playback"},
  677. {"PDM_RX3", NULL, "PDM Playback"},
  678. {"PDM Capture", NULL, "PDM_TX"},
  679. /* ADC Connections */
  680. {"PDM_TX", NULL, "ADC2"},
  681. {"PDM_TX", NULL, "ADC3"},
  682. {"ADC2", NULL, "ADC2 MUX"},
  683. {"ADC3", NULL, "ADC2 MUX"},
  684. {"ADC2 MUX", "INP2", "ADC2_INP2"},
  685. {"ADC2 MUX", "INP3", "ADC2_INP3"},
  686. {"PDM_TX", NULL, "ADC1"},
  687. {"ADC1", NULL, "AMIC1"},
  688. {"ADC2_INP2", NULL, "AMIC2"},
  689. {"ADC2_INP3", NULL, "AMIC3"},
  690. /* RDAC Connections */
  691. {"HPHR DAC", NULL, "RDAC2 MUX"},
  692. {"RDAC2 MUX", "RX1", "PDM_RX1"},
  693. {"RDAC2 MUX", "RX2", "PDM_RX2"},
  694. {"HPHL DAC", NULL, "PDM_RX1"},
  695. {"PDM_RX1", NULL, "RXD1_CLK"},
  696. {"PDM_RX2", NULL, "RXD2_CLK"},
  697. {"PDM_RX3", NULL, "RXD3_CLK"},
  698. {"PDM_RX1", NULL, "RXD_PDM_CLK"},
  699. {"PDM_RX2", NULL, "RXD_PDM_CLK"},
  700. {"PDM_RX3", NULL, "RXD_PDM_CLK"},
  701. {"ADC1", NULL, "TXD_CLK"},
  702. {"ADC2", NULL, "TXD_CLK"},
  703. {"ADC3", NULL, "TXD_CLK"},
  704. {"ADC1", NULL, "TXA_CLK25"},
  705. {"ADC2", NULL, "TXA_CLK25"},
  706. {"ADC3", NULL, "TXA_CLK25"},
  707. {"PDM_RX1", NULL, "A_MCLK2"},
  708. {"PDM_RX2", NULL, "A_MCLK2"},
  709. {"PDM_RX3", NULL, "A_MCLK2"},
  710. {"PDM_TX", NULL, "A_MCLK2"},
  711. {"A_MCLK2", NULL, "A_MCLK"},
  712. /* Earpiece (RX MIX1) */
  713. {"EAR", NULL, "EAR_S"},
  714. {"EAR_S", "Switch", "EAR PA"},
  715. {"EAR PA", NULL, "RX_BIAS"},
  716. {"EAR PA", NULL, "HPHL DAC"},
  717. {"EAR PA", NULL, "HPHR DAC"},
  718. {"EAR PA", NULL, "EAR CP"},
  719. /* Headset (RX MIX1 and RX MIX2) */
  720. {"HEADPHONE", NULL, "HPHL PA"},
  721. {"HEADPHONE", NULL, "HPHR PA"},
  722. {"HPHL DAC", NULL, "EAR_HPHL_CLK"},
  723. {"HPHR DAC", NULL, "EAR_HPHR_CLK"},
  724. {"CP", NULL, "NCP_CLK"},
  725. {"HPHL PA", NULL, "HPHL"},
  726. {"HPHR PA", NULL, "HPHR"},
  727. {"HPHL PA", NULL, "CP"},
  728. {"HPHL PA", NULL, "RX_BIAS"},
  729. {"HPHR PA", NULL, "CP"},
  730. {"HPHR PA", NULL, "RX_BIAS"},
  731. {"HPHL", "Switch", "HPHL DAC"},
  732. {"HPHR", "Switch", "HPHR DAC"},
  733. {"RX_BIAS", NULL, "DAC_REF"},
  734. {"SPK_OUT", NULL, "SPK PA"},
  735. {"SPK PA", NULL, "RX_BIAS"},
  736. {"SPK PA", NULL, "SPKR_CLK"},
  737. {"SPK PA", NULL, "SPK DAC"},
  738. {"SPK DAC", "Switch", "PDM_RX3"},
  739. {"MIC_BIAS1", NULL, "INT_LDO_H"},
  740. {"MIC_BIAS2", NULL, "INT_LDO_H"},
  741. {"MIC_BIAS1", NULL, "vdd-micbias"},
  742. {"MIC_BIAS2", NULL, "vdd-micbias"},
  743. {"MIC BIAS External1", NULL, "MIC_BIAS1"},
  744. {"MIC BIAS Internal1", NULL, "MIC_BIAS1"},
  745. {"MIC BIAS External2", NULL, "MIC_BIAS2"},
  746. {"MIC BIAS Internal2", NULL, "MIC_BIAS2"},
  747. {"MIC BIAS Internal3", NULL, "MIC_BIAS1"},
  748. };
  749. static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = {
  750. SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
  751. SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
  752. SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
  753. SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
  754. SND_SOC_DAPM_INPUT("AMIC1"),
  755. SND_SOC_DAPM_INPUT("AMIC3"),
  756. SND_SOC_DAPM_INPUT("AMIC2"),
  757. SND_SOC_DAPM_OUTPUT("EAR"),
  758. SND_SOC_DAPM_OUTPUT("HEADPHONE"),
  759. /* RX stuff */
  760. SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
  761. SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM,
  762. 0, 0, NULL, 0,
  763. pm8916_wcd_analog_enable_ear_pa,
  764. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  765. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  766. SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, &ear_mux),
  767. SND_SOC_DAPM_SUPPLY("EAR CP", CDC_A_NCP_EN, 4, 0, NULL, 0),
  768. SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
  769. SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
  770. SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
  771. 0),
  772. SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
  773. SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
  774. SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
  775. 0),
  776. SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
  777. spkr_switch, ARRAY_SIZE(spkr_switch)),
  778. /* Speaker */
  779. SND_SOC_DAPM_OUTPUT("SPK_OUT"),
  780. SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL,
  781. 6, 0, NULL, 0,
  782. pm8916_wcd_analog_enable_spk_pa,
  783. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  784. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  785. SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
  786. SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
  787. SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
  788. SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
  789. /* TX */
  790. SND_SOC_DAPM_SUPPLY("MIC_BIAS1", CDC_A_MICB_1_EN, 7, 0,
  791. pm8916_wcd_analog_enable_micbias1,
  792. SND_SOC_DAPM_POST_PMU),
  793. SND_SOC_DAPM_SUPPLY("MIC_BIAS2", CDC_A_MICB_2_EN, 7, 0,
  794. pm8916_wcd_analog_enable_micbias2,
  795. SND_SOC_DAPM_POST_PMU),
  796. SND_SOC_DAPM_SUPPLY("MIC BIAS External1", SND_SOC_NOPM, 0, 0, NULL, 0),
  797. SND_SOC_DAPM_SUPPLY("MIC BIAS External2", SND_SOC_NOPM, 0, 0, NULL, 0),
  798. SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_INT_RBIAS, 7, 0,
  799. pm8916_wcd_analog_enable_micbias_int,
  800. SND_SOC_DAPM_PRE_PMU),
  801. SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_1_INT_RBIAS, 4, 0,
  802. pm8916_wcd_analog_enable_micbias_int2,
  803. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  804. SND_SOC_DAPM_POST_PMD),
  805. SND_SOC_DAPM_SUPPLY("MIC BIAS Internal3", CDC_A_MICB_1_INT_RBIAS, 1, 0,
  806. pm8916_wcd_analog_enable_micbias_int,
  807. SND_SOC_DAPM_PRE_PMU),
  808. SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
  809. pm8916_wcd_analog_enable_adc,
  810. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  811. SND_SOC_DAPM_POST_PMD),
  812. SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
  813. pm8916_wcd_analog_enable_adc,
  814. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  815. SND_SOC_DAPM_POST_PMD),
  816. SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
  817. pm8916_wcd_analog_enable_adc,
  818. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  819. SND_SOC_DAPM_POST_PMD),
  820. SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  821. SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  822. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
  823. SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
  824. /* Analog path clocks */
  825. SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
  826. 0),
  827. SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
  828. 0),
  829. SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
  830. SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
  831. /* Digital path clocks */
  832. SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
  833. SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
  834. SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
  835. SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
  836. SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
  837. SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
  838. 0),
  839. /* System Clock source */
  840. SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
  841. /* TX ADC and RX DAC Clock source. */
  842. SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
  843. };
  844. static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component,
  845. struct snd_soc_jack *jack,
  846. void *data)
  847. {
  848. struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
  849. wcd->jack = jack;
  850. return 0;
  851. }
  852. static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
  853. {
  854. struct pm8916_wcd_analog_priv *priv = arg;
  855. if (priv->detect_accessory_type) {
  856. struct snd_soc_component *component = priv->component;
  857. u32 val = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1);
  858. /* check if its BTN0 thats released */
  859. if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK))
  860. priv->mbhc_btn0_released = true;
  861. } else {
  862. snd_soc_jack_report(priv->jack, 0, btn_mask);
  863. }
  864. return IRQ_HANDLED;
  865. }
  866. static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg)
  867. {
  868. struct pm8916_wcd_analog_priv *priv = arg;
  869. struct snd_soc_component *component = priv->component;
  870. u32 btn_result;
  871. btn_result = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1) &
  872. CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK;
  873. switch (btn_result) {
  874. case 0xf:
  875. snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask);
  876. break;
  877. case 0x7:
  878. snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask);
  879. break;
  880. case 0x3:
  881. snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask);
  882. break;
  883. case 0x1:
  884. snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask);
  885. break;
  886. case 0x0:
  887. /* handle BTN_0 specially for type detection */
  888. if (!priv->detect_accessory_type)
  889. snd_soc_jack_report(priv->jack,
  890. SND_JACK_BTN_0, btn_mask);
  891. break;
  892. default:
  893. dev_err(component->dev,
  894. "Unexpected button press result (%x)", btn_result);
  895. break;
  896. }
  897. return IRQ_HANDLED;
  898. }
  899. static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg)
  900. {
  901. struct pm8916_wcd_analog_priv *priv = arg;
  902. struct snd_soc_component *component = priv->component;
  903. bool ins = false;
  904. if (snd_soc_component_read(component, CDC_A_MBHC_DET_CTL_1) &
  905. CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK)
  906. ins = true;
  907. /* Set the detection type appropriately */
  908. snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1,
  909. CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK,
  910. (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT));
  911. if (ins) { /* hs insertion */
  912. bool micbias_enabled = false;
  913. if (snd_soc_component_read(component, CDC_A_MICB_2_EN) &
  914. CDC_A_MICB_2_EN_ENABLE)
  915. micbias_enabled = true;
  916. pm8916_mbhc_configure_bias(priv, micbias_enabled);
  917. /*
  918. * if only a btn0 press event is receive just before
  919. * insert event then its a 3 pole headphone else if
  920. * both press and release event received then its
  921. * a headset.
  922. */
  923. if (priv->mbhc_btn0_released)
  924. snd_soc_jack_report(priv->jack,
  925. SND_JACK_HEADSET, hs_jack_mask);
  926. else
  927. snd_soc_jack_report(priv->jack,
  928. SND_JACK_HEADPHONE, hs_jack_mask);
  929. priv->detect_accessory_type = false;
  930. } else { /* removal */
  931. snd_soc_jack_report(priv->jack, 0, hs_jack_mask);
  932. priv->detect_accessory_type = true;
  933. priv->mbhc_btn0_released = false;
  934. }
  935. return IRQ_HANDLED;
  936. }
  937. static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = {
  938. [0] = {
  939. .name = "pm8916_wcd_analog_pdm_rx",
  940. .id = 0,
  941. .playback = {
  942. .stream_name = "PDM Playback",
  943. .rates = MSM8916_WCD_ANALOG_RATES,
  944. .formats = MSM8916_WCD_ANALOG_FORMATS,
  945. .channels_min = 1,
  946. .channels_max = 3,
  947. },
  948. },
  949. [1] = {
  950. .name = "pm8916_wcd_analog_pdm_tx",
  951. .id = 1,
  952. .capture = {
  953. .stream_name = "PDM Capture",
  954. .rates = MSM8916_WCD_ANALOG_RATES,
  955. .formats = MSM8916_WCD_ANALOG_FORMATS,
  956. .channels_min = 1,
  957. .channels_max = 4,
  958. },
  959. },
  960. };
  961. static const struct snd_soc_component_driver pm8916_wcd_analog = {
  962. .probe = pm8916_wcd_analog_probe,
  963. .remove = pm8916_wcd_analog_remove,
  964. .set_jack = pm8916_wcd_analog_set_jack,
  965. .controls = pm8916_wcd_analog_snd_controls,
  966. .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
  967. .dapm_widgets = pm8916_wcd_analog_dapm_widgets,
  968. .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets),
  969. .dapm_routes = pm8916_wcd_analog_audio_map,
  970. .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map),
  971. .idle_bias_on = 1,
  972. .use_pmdown_time = 1,
  973. .endianness = 1,
  974. .non_legacy_dai_naming = 1,
  975. };
  976. static int pm8916_wcd_analog_parse_dt(struct device *dev,
  977. struct pm8916_wcd_analog_priv *priv)
  978. {
  979. int rval;
  980. if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap"))
  981. priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP;
  982. else
  983. priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
  984. if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap"))
  985. priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP;
  986. else
  987. priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
  988. of_property_read_u32(dev->of_node, "qcom,micbias-lvl",
  989. &priv->micbias_mv);
  990. if (of_property_read_bool(dev->of_node,
  991. "qcom,hphl-jack-type-normally-open"))
  992. priv->hphl_jack_type_normally_open = true;
  993. else
  994. priv->hphl_jack_type_normally_open = false;
  995. if (of_property_read_bool(dev->of_node,
  996. "qcom,gnd-jack-type-normally-open"))
  997. priv->gnd_jack_type_normally_open = true;
  998. else
  999. priv->gnd_jack_type_normally_open = false;
  1000. priv->mbhc_btn_enabled = true;
  1001. rval = of_property_read_u32_array(dev->of_node,
  1002. "qcom,mbhc-vthreshold-low",
  1003. &priv->vref_btn_cs[0],
  1004. MBHC_MAX_BUTTONS);
  1005. if (rval < 0) {
  1006. priv->mbhc_btn_enabled = false;
  1007. } else {
  1008. rval = of_property_read_u32_array(dev->of_node,
  1009. "qcom,mbhc-vthreshold-high",
  1010. &priv->vref_btn_micb[0],
  1011. MBHC_MAX_BUTTONS);
  1012. if (rval < 0)
  1013. priv->mbhc_btn_enabled = false;
  1014. }
  1015. if (!priv->mbhc_btn_enabled)
  1016. dev_err(dev,
  1017. "DT property missing, MBHC btn detection disabled\n");
  1018. return 0;
  1019. }
  1020. static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)
  1021. {
  1022. struct pm8916_wcd_analog_priv *priv;
  1023. struct device *dev = &pdev->dev;
  1024. int ret, i, irq;
  1025. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  1026. if (!priv)
  1027. return -ENOMEM;
  1028. ret = pm8916_wcd_analog_parse_dt(dev, priv);
  1029. if (ret < 0)
  1030. return ret;
  1031. priv->mclk = devm_clk_get(dev, "mclk");
  1032. if (IS_ERR(priv->mclk)) {
  1033. dev_err(dev, "failed to get mclk\n");
  1034. return PTR_ERR(priv->mclk);
  1035. }
  1036. for (i = 0; i < ARRAY_SIZE(supply_names); i++)
  1037. priv->supplies[i].supply = supply_names[i];
  1038. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
  1039. priv->supplies);
  1040. if (ret) {
  1041. dev_err(dev, "Failed to get regulator supplies %d\n", ret);
  1042. return ret;
  1043. }
  1044. ret = clk_prepare_enable(priv->mclk);
  1045. if (ret < 0) {
  1046. dev_err(dev, "failed to enable mclk %d\n", ret);
  1047. return ret;
  1048. }
  1049. irq = platform_get_irq_byname(pdev, "mbhc_switch_int");
  1050. if (irq < 0) {
  1051. ret = irq;
  1052. goto err_disable_clk;
  1053. }
  1054. ret = devm_request_threaded_irq(dev, irq, NULL,
  1055. pm8916_mbhc_switch_irq_handler,
  1056. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
  1057. IRQF_ONESHOT,
  1058. "mbhc switch irq", priv);
  1059. if (ret)
  1060. dev_err(dev, "cannot request mbhc switch irq\n");
  1061. if (priv->mbhc_btn_enabled) {
  1062. irq = platform_get_irq_byname(pdev, "mbhc_but_press_det");
  1063. if (irq < 0) {
  1064. ret = irq;
  1065. goto err_disable_clk;
  1066. }
  1067. ret = devm_request_threaded_irq(dev, irq, NULL,
  1068. mbhc_btn_press_irq_handler,
  1069. IRQF_TRIGGER_RISING |
  1070. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  1071. "mbhc btn press irq", priv);
  1072. if (ret)
  1073. dev_err(dev, "cannot request mbhc button press irq\n");
  1074. irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det");
  1075. if (irq < 0) {
  1076. ret = irq;
  1077. goto err_disable_clk;
  1078. }
  1079. ret = devm_request_threaded_irq(dev, irq, NULL,
  1080. mbhc_btn_release_irq_handler,
  1081. IRQF_TRIGGER_RISING |
  1082. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  1083. "mbhc btn release irq", priv);
  1084. if (ret)
  1085. dev_err(dev, "cannot request mbhc button release irq\n");
  1086. }
  1087. dev_set_drvdata(dev, priv);
  1088. return devm_snd_soc_register_component(dev, &pm8916_wcd_analog,
  1089. pm8916_wcd_analog_dai,
  1090. ARRAY_SIZE(pm8916_wcd_analog_dai));
  1091. err_disable_clk:
  1092. clk_disable_unprepare(priv->mclk);
  1093. return ret;
  1094. }
  1095. static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev)
  1096. {
  1097. struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev);
  1098. clk_disable_unprepare(priv->mclk);
  1099. return 0;
  1100. }
  1101. static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = {
  1102. { .compatible = "qcom,pm8916-wcd-analog-codec", },
  1103. { }
  1104. };
  1105. MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table);
  1106. static struct platform_driver pm8916_wcd_analog_spmi_driver = {
  1107. .driver = {
  1108. .name = "qcom,pm8916-wcd-spmi-codec",
  1109. .of_match_table = pm8916_wcd_analog_spmi_match_table,
  1110. },
  1111. .probe = pm8916_wcd_analog_spmi_probe,
  1112. .remove = pm8916_wcd_analog_spmi_remove,
  1113. };
  1114. module_platform_driver(pm8916_wcd_analog_spmi_driver);
  1115. MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
  1116. MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver");
  1117. MODULE_LICENSE("GPL v2");