max98927.c 27 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * max98927.c -- MAX98927 ALSA Soc Audio driver
  4. *
  5. * Copyright (C) 2016-2017 Maxim Integrated Products
  6. * Author: Ryan Lee <ryans.lee@maximintegrated.com>
  7. */
  8. #include <linux/acpi.h>
  9. #include <linux/i2c.h>
  10. #include <linux/module.h>
  11. #include <linux/regmap.h>
  12. #include <linux/slab.h>
  13. #include <linux/cdev.h>
  14. #include <sound/pcm.h>
  15. #include <sound/pcm_params.h>
  16. #include <sound/soc.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <sound/tlv.h>
  20. #include "max98927.h"
  21. static struct reg_default max98927_reg[] = {
  22. {MAX98927_R0001_INT_RAW1, 0x00},
  23. {MAX98927_R0002_INT_RAW2, 0x00},
  24. {MAX98927_R0003_INT_RAW3, 0x00},
  25. {MAX98927_R0004_INT_STATE1, 0x00},
  26. {MAX98927_R0005_INT_STATE2, 0x00},
  27. {MAX98927_R0006_INT_STATE3, 0x00},
  28. {MAX98927_R0007_INT_FLAG1, 0x00},
  29. {MAX98927_R0008_INT_FLAG2, 0x00},
  30. {MAX98927_R0009_INT_FLAG3, 0x00},
  31. {MAX98927_R000A_INT_EN1, 0x00},
  32. {MAX98927_R000B_INT_EN2, 0x00},
  33. {MAX98927_R000C_INT_EN3, 0x00},
  34. {MAX98927_R000D_INT_FLAG_CLR1, 0x00},
  35. {MAX98927_R000E_INT_FLAG_CLR2, 0x00},
  36. {MAX98927_R000F_INT_FLAG_CLR3, 0x00},
  37. {MAX98927_R0010_IRQ_CTRL, 0x00},
  38. {MAX98927_R0011_CLK_MON, 0x00},
  39. {MAX98927_R0012_WDOG_CTRL, 0x00},
  40. {MAX98927_R0013_WDOG_RST, 0x00},
  41. {MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH, 0x75},
  42. {MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH, 0x8c},
  43. {MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS, 0x08},
  44. {MAX98927_R0017_PIN_CFG, 0x55},
  45. {MAX98927_R0018_PCM_RX_EN_A, 0x00},
  46. {MAX98927_R0019_PCM_RX_EN_B, 0x00},
  47. {MAX98927_R001A_PCM_TX_EN_A, 0x00},
  48. {MAX98927_R001B_PCM_TX_EN_B, 0x00},
  49. {MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0x00},
  50. {MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0x00},
  51. {MAX98927_R001E_PCM_TX_CH_SRC_A, 0x00},
  52. {MAX98927_R001F_PCM_TX_CH_SRC_B, 0x00},
  53. {MAX98927_R0020_PCM_MODE_CFG, 0x40},
  54. {MAX98927_R0021_PCM_MASTER_MODE, 0x00},
  55. {MAX98927_R0022_PCM_CLK_SETUP, 0x22},
  56. {MAX98927_R0023_PCM_SR_SETUP1, 0x00},
  57. {MAX98927_R0024_PCM_SR_SETUP2, 0x00},
  58. {MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 0x00},
  59. {MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 0x00},
  60. {MAX98927_R0027_ICC_RX_EN_A, 0x00},
  61. {MAX98927_R0028_ICC_RX_EN_B, 0x00},
  62. {MAX98927_R002B_ICC_TX_EN_A, 0x00},
  63. {MAX98927_R002C_ICC_TX_EN_B, 0x00},
  64. {MAX98927_R002E_ICC_HIZ_MANUAL_MODE, 0x00},
  65. {MAX98927_R002F_ICC_TX_HIZ_EN_A, 0x00},
  66. {MAX98927_R0030_ICC_TX_HIZ_EN_B, 0x00},
  67. {MAX98927_R0031_ICC_LNK_EN, 0x00},
  68. {MAX98927_R0032_PDM_TX_EN, 0x00},
  69. {MAX98927_R0033_PDM_TX_HIZ_CTRL, 0x00},
  70. {MAX98927_R0034_PDM_TX_CTRL, 0x00},
  71. {MAX98927_R0035_PDM_RX_CTRL, 0x00},
  72. {MAX98927_R0036_AMP_VOL_CTRL, 0x00},
  73. {MAX98927_R0037_AMP_DSP_CFG, 0x02},
  74. {MAX98927_R0038_TONE_GEN_DC_CFG, 0x00},
  75. {MAX98927_R0039_DRE_CTRL, 0x01},
  76. {MAX98927_R003A_AMP_EN, 0x00},
  77. {MAX98927_R003B_SPK_SRC_SEL, 0x00},
  78. {MAX98927_R003C_SPK_GAIN, 0x00},
  79. {MAX98927_R003D_SSM_CFG, 0x04},
  80. {MAX98927_R003E_MEAS_EN, 0x00},
  81. {MAX98927_R003F_MEAS_DSP_CFG, 0x04},
  82. {MAX98927_R0040_BOOST_CTRL0, 0x00},
  83. {MAX98927_R0041_BOOST_CTRL3, 0x00},
  84. {MAX98927_R0042_BOOST_CTRL1, 0x00},
  85. {MAX98927_R0043_MEAS_ADC_CFG, 0x00},
  86. {MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x01},
  87. {MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x00},
  88. {MAX98927_R0046_ADC_CH0_DIVIDE, 0x00},
  89. {MAX98927_R0047_ADC_CH1_DIVIDE, 0x00},
  90. {MAX98927_R0048_ADC_CH2_DIVIDE, 0x00},
  91. {MAX98927_R0049_ADC_CH0_FILT_CFG, 0x00},
  92. {MAX98927_R004A_ADC_CH1_FILT_CFG, 0x00},
  93. {MAX98927_R004B_ADC_CH2_FILT_CFG, 0x00},
  94. {MAX98927_R004C_MEAS_ADC_CH0_READ, 0x00},
  95. {MAX98927_R004D_MEAS_ADC_CH1_READ, 0x00},
  96. {MAX98927_R004E_MEAS_ADC_CH2_READ, 0x00},
  97. {MAX98927_R0051_BROWNOUT_STATUS, 0x00},
  98. {MAX98927_R0052_BROWNOUT_EN, 0x00},
  99. {MAX98927_R0053_BROWNOUT_INFINITE_HOLD, 0x00},
  100. {MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
  101. {MAX98927_R0055_BROWNOUT_LVL_HOLD, 0x00},
  102. {MAX98927_R005A_BROWNOUT_LVL1_THRESH, 0x00},
  103. {MAX98927_R005B_BROWNOUT_LVL2_THRESH, 0x00},
  104. {MAX98927_R005C_BROWNOUT_LVL3_THRESH, 0x00},
  105. {MAX98927_R005D_BROWNOUT_LVL4_THRESH, 0x00},
  106. {MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
  107. {MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL, 0x00},
  108. {MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
  109. {MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE, 0x00},
  110. {MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
  111. {MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
  112. {MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
  113. {MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
  114. {MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
  115. {MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
  116. {MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
  117. {MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
  118. {MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
  119. {MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
  120. {MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
  121. {MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
  122. {MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
  123. {MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
  124. {MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
  125. {MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
  126. {MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 0x00},
  127. {MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY, 0x00},
  128. {MAX98927_R0084_ENV_TRACK_REL_RATE, 0x00},
  129. {MAX98927_R0085_ENV_TRACK_HOLD_RATE, 0x00},
  130. {MAX98927_R0086_ENV_TRACK_CTRL, 0x00},
  131. {MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 0x00},
  132. {MAX98927_R00FF_GLOBAL_SHDN, 0x00},
  133. {MAX98927_R0100_SOFT_RESET, 0x00},
  134. {MAX98927_R01FF_REV_ID, 0x40},
  135. };
  136. static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  137. {
  138. struct snd_soc_component *component = codec_dai->component;
  139. struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
  140. unsigned int mode = 0;
  141. unsigned int format = 0;
  142. bool use_pdm = false;
  143. unsigned int invert = 0;
  144. dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
  145. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  146. case SND_SOC_DAIFMT_CBS_CFS:
  147. mode = MAX98927_PCM_MASTER_MODE_SLAVE;
  148. break;
  149. case SND_SOC_DAIFMT_CBM_CFM:
  150. max98927->master = true;
  151. mode = MAX98927_PCM_MASTER_MODE_MASTER;
  152. break;
  153. default:
  154. dev_err(component->dev, "DAI clock mode unsupported\n");
  155. return -EINVAL;
  156. }
  157. regmap_update_bits(max98927->regmap,
  158. MAX98927_R0021_PCM_MASTER_MODE,
  159. MAX98927_PCM_MASTER_MODE_MASK,
  160. mode);
  161. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  162. case SND_SOC_DAIFMT_NB_NF:
  163. break;
  164. case SND_SOC_DAIFMT_IB_NF:
  165. invert = MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE;
  166. break;
  167. default:
  168. dev_err(component->dev, "DAI invert mode unsupported\n");
  169. return -EINVAL;
  170. }
  171. regmap_update_bits(max98927->regmap,
  172. MAX98927_R0020_PCM_MODE_CFG,
  173. MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE,
  174. invert);
  175. /* interface format */
  176. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  177. case SND_SOC_DAIFMT_I2S:
  178. format = MAX98927_PCM_FORMAT_I2S;
  179. break;
  180. case SND_SOC_DAIFMT_LEFT_J:
  181. format = MAX98927_PCM_FORMAT_LJ;
  182. break;
  183. case SND_SOC_DAIFMT_DSP_A:
  184. format = MAX98927_PCM_FORMAT_TDM_MODE1;
  185. break;
  186. case SND_SOC_DAIFMT_DSP_B:
  187. format = MAX98927_PCM_FORMAT_TDM_MODE0;
  188. break;
  189. case SND_SOC_DAIFMT_PDM:
  190. use_pdm = true;
  191. break;
  192. default:
  193. return -EINVAL;
  194. }
  195. max98927->iface = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  196. if (!use_pdm) {
  197. /* pcm channel configuration */
  198. regmap_update_bits(max98927->regmap,
  199. MAX98927_R0018_PCM_RX_EN_A,
  200. MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
  201. MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN);
  202. regmap_update_bits(max98927->regmap,
  203. MAX98927_R0020_PCM_MODE_CFG,
  204. MAX98927_PCM_MODE_CFG_FORMAT_MASK,
  205. format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT);
  206. regmap_update_bits(max98927->regmap,
  207. MAX98927_R003B_SPK_SRC_SEL,
  208. MAX98927_SPK_SRC_MASK, 0);
  209. regmap_update_bits(max98927->regmap,
  210. MAX98927_R0035_PDM_RX_CTRL,
  211. MAX98927_PDM_RX_EN_MASK, 0);
  212. } else {
  213. /* pdm channel configuration */
  214. regmap_update_bits(max98927->regmap,
  215. MAX98927_R0035_PDM_RX_CTRL,
  216. MAX98927_PDM_RX_EN_MASK, 1);
  217. regmap_update_bits(max98927->regmap,
  218. MAX98927_R003B_SPK_SRC_SEL,
  219. MAX98927_SPK_SRC_MASK, 3);
  220. regmap_update_bits(max98927->regmap,
  221. MAX98927_R0018_PCM_RX_EN_A,
  222. MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN, 0);
  223. }
  224. return 0;
  225. }
  226. /* codec MCLK rate in master mode */
  227. static const int rate_table[] = {
  228. 5644800, 6000000, 6144000, 6500000,
  229. 9600000, 11289600, 12000000, 12288000,
  230. 13000000, 19200000,
  231. };
  232. /* BCLKs per LRCLK */
  233. static const int bclk_sel_table[] = {
  234. 32, 48, 64, 96, 128, 192, 256, 384, 512,
  235. };
  236. static int max98927_get_bclk_sel(int bclk)
  237. {
  238. int i;
  239. /* match BCLKs per LRCLK */
  240. for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
  241. if (bclk_sel_table[i] == bclk)
  242. return i + 2;
  243. }
  244. return 0;
  245. }
  246. static int max98927_set_clock(struct max98927_priv *max98927,
  247. struct snd_pcm_hw_params *params)
  248. {
  249. struct snd_soc_component *component = max98927->component;
  250. /* BCLK/LRCLK ratio calculation */
  251. int blr_clk_ratio = params_channels(params) * max98927->ch_size;
  252. int value;
  253. if (max98927->master) {
  254. int i;
  255. /* match rate to closest value */
  256. for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
  257. if (rate_table[i] >= max98927->sysclk)
  258. break;
  259. }
  260. if (i == ARRAY_SIZE(rate_table)) {
  261. dev_err(component->dev, "failed to find proper clock rate.\n");
  262. return -EINVAL;
  263. }
  264. regmap_update_bits(max98927->regmap,
  265. MAX98927_R0021_PCM_MASTER_MODE,
  266. MAX98927_PCM_MASTER_MODE_MCLK_MASK,
  267. i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
  268. }
  269. if (!max98927->tdm_mode) {
  270. /* BCLK configuration */
  271. value = max98927_get_bclk_sel(blr_clk_ratio);
  272. if (!value) {
  273. dev_err(component->dev, "format unsupported %d\n",
  274. params_format(params));
  275. return -EINVAL;
  276. }
  277. regmap_update_bits(max98927->regmap,
  278. MAX98927_R0022_PCM_CLK_SETUP,
  279. MAX98927_PCM_CLK_SETUP_BSEL_MASK,
  280. value);
  281. }
  282. return 0;
  283. }
  284. static int max98927_dai_hw_params(struct snd_pcm_substream *substream,
  285. struct snd_pcm_hw_params *params,
  286. struct snd_soc_dai *dai)
  287. {
  288. struct snd_soc_component *component = dai->component;
  289. struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
  290. unsigned int sampling_rate = 0;
  291. unsigned int chan_sz = 0;
  292. /* pcm mode configuration */
  293. switch (snd_pcm_format_width(params_format(params))) {
  294. case 16:
  295. chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
  296. break;
  297. case 24:
  298. chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
  299. break;
  300. case 32:
  301. chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
  302. break;
  303. default:
  304. dev_err(component->dev, "format unsupported %d\n",
  305. params_format(params));
  306. goto err;
  307. }
  308. max98927->ch_size = snd_pcm_format_width(params_format(params));
  309. regmap_update_bits(max98927->regmap,
  310. MAX98927_R0020_PCM_MODE_CFG,
  311. MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
  312. dev_dbg(component->dev, "format supported %d",
  313. params_format(params));
  314. /* sampling rate configuration */
  315. switch (params_rate(params)) {
  316. case 8000:
  317. sampling_rate = MAX98927_PCM_SR_SET1_SR_8000;
  318. break;
  319. case 11025:
  320. sampling_rate = MAX98927_PCM_SR_SET1_SR_11025;
  321. break;
  322. case 12000:
  323. sampling_rate = MAX98927_PCM_SR_SET1_SR_12000;
  324. break;
  325. case 16000:
  326. sampling_rate = MAX98927_PCM_SR_SET1_SR_16000;
  327. break;
  328. case 22050:
  329. sampling_rate = MAX98927_PCM_SR_SET1_SR_22050;
  330. break;
  331. case 24000:
  332. sampling_rate = MAX98927_PCM_SR_SET1_SR_24000;
  333. break;
  334. case 32000:
  335. sampling_rate = MAX98927_PCM_SR_SET1_SR_32000;
  336. break;
  337. case 44100:
  338. sampling_rate = MAX98927_PCM_SR_SET1_SR_44100;
  339. break;
  340. case 48000:
  341. sampling_rate = MAX98927_PCM_SR_SET1_SR_48000;
  342. break;
  343. default:
  344. dev_err(component->dev, "rate %d not supported\n",
  345. params_rate(params));
  346. goto err;
  347. }
  348. /* set DAI_SR to correct LRCLK frequency */
  349. regmap_update_bits(max98927->regmap,
  350. MAX98927_R0023_PCM_SR_SETUP1,
  351. MAX98927_PCM_SR_SET1_SR_MASK,
  352. sampling_rate);
  353. regmap_update_bits(max98927->regmap,
  354. MAX98927_R0024_PCM_SR_SETUP2,
  355. MAX98927_PCM_SR_SET2_SR_MASK,
  356. sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT);
  357. /* set sampling rate of IV */
  358. if (max98927->interleave_mode &&
  359. sampling_rate > MAX98927_PCM_SR_SET1_SR_16000)
  360. regmap_update_bits(max98927->regmap,
  361. MAX98927_R0024_PCM_SR_SETUP2,
  362. MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
  363. sampling_rate - 3);
  364. else
  365. regmap_update_bits(max98927->regmap,
  366. MAX98927_R0024_PCM_SR_SETUP2,
  367. MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
  368. sampling_rate);
  369. return max98927_set_clock(max98927, params);
  370. err:
  371. return -EINVAL;
  372. }
  373. static int max98927_dai_tdm_slot(struct snd_soc_dai *dai,
  374. unsigned int tx_mask, unsigned int rx_mask,
  375. int slots, int slot_width)
  376. {
  377. struct snd_soc_component *component = dai->component;
  378. struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
  379. int bsel = 0;
  380. unsigned int chan_sz = 0;
  381. max98927->tdm_mode = true;
  382. /* BCLK configuration */
  383. bsel = max98927_get_bclk_sel(slots * slot_width);
  384. if (bsel == 0) {
  385. dev_err(component->dev, "BCLK %d not supported\n",
  386. slots * slot_width);
  387. return -EINVAL;
  388. }
  389. regmap_update_bits(max98927->regmap,
  390. MAX98927_R0022_PCM_CLK_SETUP,
  391. MAX98927_PCM_CLK_SETUP_BSEL_MASK,
  392. bsel);
  393. /* Channel size configuration */
  394. switch (slot_width) {
  395. case 16:
  396. chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
  397. break;
  398. case 24:
  399. chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
  400. break;
  401. case 32:
  402. chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
  403. break;
  404. default:
  405. dev_err(component->dev, "format unsupported %d\n",
  406. slot_width);
  407. return -EINVAL;
  408. }
  409. regmap_update_bits(max98927->regmap,
  410. MAX98927_R0020_PCM_MODE_CFG,
  411. MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
  412. /* Rx slot configuration */
  413. regmap_write(max98927->regmap,
  414. MAX98927_R0018_PCM_RX_EN_A,
  415. rx_mask & 0xFF);
  416. regmap_write(max98927->regmap,
  417. MAX98927_R0019_PCM_RX_EN_B,
  418. (rx_mask & 0xFF00) >> 8);
  419. /* Tx slot configuration */
  420. regmap_write(max98927->regmap,
  421. MAX98927_R001A_PCM_TX_EN_A,
  422. tx_mask & 0xFF);
  423. regmap_write(max98927->regmap,
  424. MAX98927_R001B_PCM_TX_EN_B,
  425. (tx_mask & 0xFF00) >> 8);
  426. /* Tx slot Hi-Z configuration */
  427. regmap_write(max98927->regmap,
  428. MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
  429. ~tx_mask & 0xFF);
  430. regmap_write(max98927->regmap,
  431. MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
  432. (~tx_mask & 0xFF00) >> 8);
  433. return 0;
  434. }
  435. #define MAX98927_RATES SNDRV_PCM_RATE_8000_48000
  436. #define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  437. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  438. static int max98927_dai_set_sysclk(struct snd_soc_dai *dai,
  439. int clk_id, unsigned int freq, int dir)
  440. {
  441. struct snd_soc_component *component = dai->component;
  442. struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
  443. max98927->sysclk = freq;
  444. return 0;
  445. }
  446. static const struct snd_soc_dai_ops max98927_dai_ops = {
  447. .set_sysclk = max98927_dai_set_sysclk,
  448. .set_fmt = max98927_dai_set_fmt,
  449. .hw_params = max98927_dai_hw_params,
  450. .set_tdm_slot = max98927_dai_tdm_slot,
  451. };
  452. static int max98927_dac_event(struct snd_soc_dapm_widget *w,
  453. struct snd_kcontrol *kcontrol, int event)
  454. {
  455. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  456. struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
  457. switch (event) {
  458. case SND_SOC_DAPM_PRE_PMU:
  459. max98927->tdm_mode = false;
  460. break;
  461. case SND_SOC_DAPM_POST_PMU:
  462. regmap_update_bits(max98927->regmap,
  463. MAX98927_R003A_AMP_EN,
  464. MAX98927_AMP_EN_MASK, 1);
  465. regmap_update_bits(max98927->regmap,
  466. MAX98927_R00FF_GLOBAL_SHDN,
  467. MAX98927_GLOBAL_EN_MASK, 1);
  468. break;
  469. case SND_SOC_DAPM_POST_PMD:
  470. regmap_update_bits(max98927->regmap,
  471. MAX98927_R00FF_GLOBAL_SHDN,
  472. MAX98927_GLOBAL_EN_MASK, 0);
  473. regmap_update_bits(max98927->regmap,
  474. MAX98927_R003A_AMP_EN,
  475. MAX98927_AMP_EN_MASK, 0);
  476. break;
  477. default:
  478. return 0;
  479. }
  480. return 0;
  481. }
  482. static const char * const max98927_switch_text[] = {
  483. "Left", "Right", "LeftRight"};
  484. static const struct soc_enum dai_sel_enum =
  485. SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
  486. MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
  487. 3, max98927_switch_text);
  488. static const struct snd_kcontrol_new max98927_dai_controls =
  489. SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
  490. static const struct snd_kcontrol_new max98927_vi_control =
  491. SOC_DAPM_SINGLE("Switch", MAX98927_R003F_MEAS_DSP_CFG, 2, 1, 0);
  492. static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
  493. SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN,
  494. 0, 0, max98927_dac_event,
  495. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  496. SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
  497. &max98927_dai_controls),
  498. SND_SOC_DAPM_OUTPUT("BE_OUT"),
  499. SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
  500. MAX98927_R003E_MEAS_EN, 0, 0),
  501. SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
  502. MAX98927_R003E_MEAS_EN, 1, 0),
  503. SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
  504. &max98927_vi_control),
  505. SND_SOC_DAPM_SIGGEN("VMON"),
  506. SND_SOC_DAPM_SIGGEN("IMON"),
  507. };
  508. static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0);
  509. static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0);
  510. static bool max98927_readable_register(struct device *dev, unsigned int reg)
  511. {
  512. switch (reg) {
  513. case MAX98927_R0001_INT_RAW1 ... MAX98927_R0028_ICC_RX_EN_B:
  514. case MAX98927_R002B_ICC_TX_EN_A ... MAX98927_R002C_ICC_TX_EN_B:
  515. case MAX98927_R002E_ICC_HIZ_MANUAL_MODE
  516. ... MAX98927_R004E_MEAS_ADC_CH2_READ:
  517. case MAX98927_R0051_BROWNOUT_STATUS
  518. ... MAX98927_R0055_BROWNOUT_LVL_HOLD:
  519. case MAX98927_R005A_BROWNOUT_LVL1_THRESH
  520. ... MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE:
  521. case MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT
  522. ... MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
  523. case MAX98927_R00FF_GLOBAL_SHDN:
  524. case MAX98927_R0100_SOFT_RESET:
  525. case MAX98927_R01FF_REV_ID:
  526. return true;
  527. default:
  528. return false;
  529. }
  530. };
  531. static bool max98927_volatile_reg(struct device *dev, unsigned int reg)
  532. {
  533. switch (reg) {
  534. case MAX98927_R0001_INT_RAW1 ... MAX98927_R0009_INT_FLAG3:
  535. case MAX98927_R004C_MEAS_ADC_CH0_READ:
  536. case MAX98927_R004D_MEAS_ADC_CH1_READ:
  537. case MAX98927_R004E_MEAS_ADC_CH2_READ:
  538. case MAX98927_R0051_BROWNOUT_STATUS:
  539. case MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
  540. case MAX98927_R01FF_REV_ID:
  541. case MAX98927_R0100_SOFT_RESET:
  542. return true;
  543. default:
  544. return false;
  545. }
  546. }
  547. static const char * const max98927_boost_voltage_text[] = {
  548. "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
  549. "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
  550. "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
  551. "9.5V", "9.625V", "9.75V", "9.875V", "10V"
  552. };
  553. static SOC_ENUM_SINGLE_DECL(max98927_boost_voltage,
  554. MAX98927_R0040_BOOST_CTRL0, 0,
  555. max98927_boost_voltage_text);
  556. static const char * const max98927_current_limit_text[] = {
  557. "1.00A", "1.10A", "1.20A", "1.30A", "1.40A", "1.50A", "1.60A", "1.70A",
  558. "1.80A", "1.90A", "2.00A", "2.10A", "2.20A", "2.30A", "2.40A", "2.50A",
  559. "2.60A", "2.70A", "2.80A", "2.90A", "3.00A", "3.10A", "3.20A", "3.30A",
  560. "3.40A", "3.50A", "3.60A", "3.70A", "3.80A", "3.90A", "4.00A", "4.10A"
  561. };
  562. static SOC_ENUM_SINGLE_DECL(max98927_current_limit,
  563. MAX98927_R0042_BOOST_CTRL1, 1,
  564. max98927_current_limit_text);
  565. static const struct snd_kcontrol_new max98927_snd_controls[] = {
  566. SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN,
  567. 0, 6, 0,
  568. max98927_spk_tlv),
  569. SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL,
  570. 0, (1<<MAX98927_AMP_VOL_WIDTH)-1, 0,
  571. max98927_digital_tlv),
  572. SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN,
  573. MAX98927_BROWNOUT_DSP_SHIFT, 1, 0),
  574. SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG,
  575. MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0),
  576. SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL,
  577. MAX98927_DRE_EN_SHIFT, 1, 0),
  578. SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL,
  579. MAX98927_AMP_VOL_SEL_SHIFT, 1, 0),
  580. SOC_ENUM("Boost Output Voltage", max98927_boost_voltage),
  581. SOC_ENUM("Current Limit", max98927_current_limit),
  582. };
  583. static const struct snd_soc_dapm_route max98927_audio_map[] = {
  584. /* Plabyack */
  585. {"DAI Sel Mux", "Left", "Amp Enable"},
  586. {"DAI Sel Mux", "Right", "Amp Enable"},
  587. {"DAI Sel Mux", "LeftRight", "Amp Enable"},
  588. {"BE_OUT", NULL, "DAI Sel Mux"},
  589. /* Capture */
  590. { "VI Sense", "Switch", "VMON" },
  591. { "VI Sense", "Switch", "IMON" },
  592. { "Voltage Sense", NULL, "VI Sense" },
  593. { "Current Sense", NULL, "VI Sense" },
  594. };
  595. static struct snd_soc_dai_driver max98927_dai[] = {
  596. {
  597. .name = "max98927-aif1",
  598. .playback = {
  599. .stream_name = "HiFi Playback",
  600. .channels_min = 1,
  601. .channels_max = 2,
  602. .rates = MAX98927_RATES,
  603. .formats = MAX98927_FORMATS,
  604. },
  605. .capture = {
  606. .stream_name = "HiFi Capture",
  607. .channels_min = 1,
  608. .channels_max = 2,
  609. .rates = MAX98927_RATES,
  610. .formats = MAX98927_FORMATS,
  611. },
  612. .ops = &max98927_dai_ops,
  613. }
  614. };
  615. static int max98927_probe(struct snd_soc_component *component)
  616. {
  617. struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
  618. max98927->component = component;
  619. /* Software Reset */
  620. regmap_write(max98927->regmap,
  621. MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
  622. /* IV default slot configuration */
  623. regmap_write(max98927->regmap,
  624. MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
  625. 0xFF);
  626. regmap_write(max98927->regmap,
  627. MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
  628. 0xFF);
  629. regmap_write(max98927->regmap,
  630. MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
  631. 0x80);
  632. regmap_write(max98927->regmap,
  633. MAX98927_R0026_PCM_TO_SPK_MONOMIX_B,
  634. 0x1);
  635. /* Set inital volume (+13dB) */
  636. regmap_write(max98927->regmap,
  637. MAX98927_R0036_AMP_VOL_CTRL,
  638. 0x38);
  639. regmap_write(max98927->regmap,
  640. MAX98927_R003C_SPK_GAIN,
  641. 0x05);
  642. /* Enable DC blocker */
  643. regmap_write(max98927->regmap,
  644. MAX98927_R0037_AMP_DSP_CFG,
  645. 0x03);
  646. /* Enable IMON VMON DC blocker */
  647. regmap_write(max98927->regmap,
  648. MAX98927_R003F_MEAS_DSP_CFG,
  649. 0xF7);
  650. /* Boost Output Voltage & Current limit */
  651. regmap_write(max98927->regmap,
  652. MAX98927_R0040_BOOST_CTRL0,
  653. 0x1C);
  654. regmap_write(max98927->regmap,
  655. MAX98927_R0042_BOOST_CTRL1,
  656. 0x3E);
  657. /* Measurement ADC config */
  658. regmap_write(max98927->regmap,
  659. MAX98927_R0043_MEAS_ADC_CFG,
  660. 0x04);
  661. regmap_write(max98927->regmap,
  662. MAX98927_R0044_MEAS_ADC_BASE_MSB,
  663. 0x00);
  664. regmap_write(max98927->regmap,
  665. MAX98927_R0045_MEAS_ADC_BASE_LSB,
  666. 0x24);
  667. /* Brownout Level */
  668. regmap_write(max98927->regmap,
  669. MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1,
  670. 0x06);
  671. /* Envelope Tracking configuration */
  672. regmap_write(max98927->regmap,
  673. MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM,
  674. 0x08);
  675. regmap_write(max98927->regmap,
  676. MAX98927_R0086_ENV_TRACK_CTRL,
  677. 0x01);
  678. regmap_write(max98927->regmap,
  679. MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ,
  680. 0x10);
  681. /* voltage, current slot configuration */
  682. regmap_write(max98927->regmap,
  683. MAX98927_R001E_PCM_TX_CH_SRC_A,
  684. (max98927->i_l_slot<<MAX98927_PCM_TX_CH_SRC_A_I_SHIFT|
  685. max98927->v_l_slot)&0xFF);
  686. if (max98927->v_l_slot < 8) {
  687. regmap_update_bits(max98927->regmap,
  688. MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
  689. 1 << max98927->v_l_slot, 0);
  690. regmap_update_bits(max98927->regmap,
  691. MAX98927_R001A_PCM_TX_EN_A,
  692. 1 << max98927->v_l_slot,
  693. 1 << max98927->v_l_slot);
  694. } else {
  695. regmap_update_bits(max98927->regmap,
  696. MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
  697. 1 << (max98927->v_l_slot - 8), 0);
  698. regmap_update_bits(max98927->regmap,
  699. MAX98927_R001B_PCM_TX_EN_B,
  700. 1 << (max98927->v_l_slot - 8),
  701. 1 << (max98927->v_l_slot - 8));
  702. }
  703. if (max98927->i_l_slot < 8) {
  704. regmap_update_bits(max98927->regmap,
  705. MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
  706. 1 << max98927->i_l_slot, 0);
  707. regmap_update_bits(max98927->regmap,
  708. MAX98927_R001A_PCM_TX_EN_A,
  709. 1 << max98927->i_l_slot,
  710. 1 << max98927->i_l_slot);
  711. } else {
  712. regmap_update_bits(max98927->regmap,
  713. MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
  714. 1 << (max98927->i_l_slot - 8), 0);
  715. regmap_update_bits(max98927->regmap,
  716. MAX98927_R001B_PCM_TX_EN_B,
  717. 1 << (max98927->i_l_slot - 8),
  718. 1 << (max98927->i_l_slot - 8));
  719. }
  720. /* Set interleave mode */
  721. if (max98927->interleave_mode)
  722. regmap_update_bits(max98927->regmap,
  723. MAX98927_R001F_PCM_TX_CH_SRC_B,
  724. MAX98927_PCM_TX_CH_INTERLEAVE_MASK,
  725. MAX98927_PCM_TX_CH_INTERLEAVE_MASK);
  726. return 0;
  727. }
  728. #ifdef CONFIG_PM_SLEEP
  729. static int max98927_suspend(struct device *dev)
  730. {
  731. struct max98927_priv *max98927 = dev_get_drvdata(dev);
  732. regcache_cache_only(max98927->regmap, true);
  733. regcache_mark_dirty(max98927->regmap);
  734. return 0;
  735. }
  736. static int max98927_resume(struct device *dev)
  737. {
  738. struct max98927_priv *max98927 = dev_get_drvdata(dev);
  739. regmap_write(max98927->regmap,
  740. MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
  741. regcache_cache_only(max98927->regmap, false);
  742. regcache_sync(max98927->regmap);
  743. return 0;
  744. }
  745. #endif
  746. static const struct dev_pm_ops max98927_pm = {
  747. SET_SYSTEM_SLEEP_PM_OPS(max98927_suspend, max98927_resume)
  748. };
  749. static const struct snd_soc_component_driver soc_component_dev_max98927 = {
  750. .probe = max98927_probe,
  751. .controls = max98927_snd_controls,
  752. .num_controls = ARRAY_SIZE(max98927_snd_controls),
  753. .dapm_widgets = max98927_dapm_widgets,
  754. .num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets),
  755. .dapm_routes = max98927_audio_map,
  756. .num_dapm_routes = ARRAY_SIZE(max98927_audio_map),
  757. .idle_bias_on = 1,
  758. .use_pmdown_time = 1,
  759. .endianness = 1,
  760. .non_legacy_dai_naming = 1,
  761. };
  762. static const struct regmap_config max98927_regmap = {
  763. .reg_bits = 16,
  764. .val_bits = 8,
  765. .max_register = MAX98927_R01FF_REV_ID,
  766. .reg_defaults = max98927_reg,
  767. .num_reg_defaults = ARRAY_SIZE(max98927_reg),
  768. .readable_reg = max98927_readable_register,
  769. .volatile_reg = max98927_volatile_reg,
  770. .cache_type = REGCACHE_RBTREE,
  771. };
  772. static void max98927_slot_config(struct i2c_client *i2c,
  773. struct max98927_priv *max98927)
  774. {
  775. int value;
  776. struct device *dev = &i2c->dev;
  777. if (!device_property_read_u32(dev, "vmon-slot-no", &value))
  778. max98927->v_l_slot = value & 0xF;
  779. else
  780. max98927->v_l_slot = 0;
  781. if (!device_property_read_u32(dev, "imon-slot-no", &value))
  782. max98927->i_l_slot = value & 0xF;
  783. else
  784. max98927->i_l_slot = 1;
  785. }
  786. static int max98927_i2c_probe(struct i2c_client *i2c,
  787. const struct i2c_device_id *id)
  788. {
  789. int ret = 0, value;
  790. int reg = 0;
  791. struct max98927_priv *max98927 = NULL;
  792. max98927 = devm_kzalloc(&i2c->dev,
  793. sizeof(*max98927), GFP_KERNEL);
  794. if (!max98927) {
  795. ret = -ENOMEM;
  796. return ret;
  797. }
  798. i2c_set_clientdata(i2c, max98927);
  799. /* update interleave mode info */
  800. if (!of_property_read_u32(i2c->dev.of_node,
  801. "interleave_mode", &value)) {
  802. if (value > 0)
  803. max98927->interleave_mode = true;
  804. else
  805. max98927->interleave_mode = false;
  806. } else
  807. max98927->interleave_mode = false;
  808. /* regmap initialization */
  809. max98927->regmap
  810. = devm_regmap_init_i2c(i2c, &max98927_regmap);
  811. if (IS_ERR(max98927->regmap)) {
  812. ret = PTR_ERR(max98927->regmap);
  813. dev_err(&i2c->dev,
  814. "Failed to allocate regmap: %d\n", ret);
  815. return ret;
  816. }
  817. /* Check Revision ID */
  818. ret = regmap_read(max98927->regmap,
  819. MAX98927_R01FF_REV_ID, &reg);
  820. if (ret < 0) {
  821. dev_err(&i2c->dev,
  822. "Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID);
  823. return ret;
  824. }
  825. dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg);
  826. /* voltage/current slot configuration */
  827. max98927_slot_config(i2c, max98927);
  828. /* codec registeration */
  829. ret = devm_snd_soc_register_component(&i2c->dev,
  830. &soc_component_dev_max98927,
  831. max98927_dai, ARRAY_SIZE(max98927_dai));
  832. if (ret < 0)
  833. dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
  834. return ret;
  835. }
  836. static const struct i2c_device_id max98927_i2c_id[] = {
  837. { "max98927", 0},
  838. { },
  839. };
  840. MODULE_DEVICE_TABLE(i2c, max98927_i2c_id);
  841. #if defined(CONFIG_OF)
  842. static const struct of_device_id max98927_of_match[] = {
  843. { .compatible = "maxim,max98927", },
  844. { }
  845. };
  846. MODULE_DEVICE_TABLE(of, max98927_of_match);
  847. #endif
  848. #ifdef CONFIG_ACPI
  849. static const struct acpi_device_id max98927_acpi_match[] = {
  850. { "MX98927", 0 },
  851. {},
  852. };
  853. MODULE_DEVICE_TABLE(acpi, max98927_acpi_match);
  854. #endif
  855. static struct i2c_driver max98927_i2c_driver = {
  856. .driver = {
  857. .name = "max98927",
  858. .of_match_table = of_match_ptr(max98927_of_match),
  859. .acpi_match_table = ACPI_PTR(max98927_acpi_match),
  860. .pm = &max98927_pm,
  861. },
  862. .probe = max98927_i2c_probe,
  863. .id_table = max98927_i2c_id,
  864. };
  865. module_i2c_driver(max98927_i2c_driver)
  866. MODULE_DESCRIPTION("ALSA SoC MAX98927 driver");
  867. MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
  868. MODULE_LICENSE("GPL");