max98926.h 36 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * max98926.h -- MAX98926 ALSA SoC Audio driver
  4. * Copyright 2013-2015 Maxim Integrated Products
  5. */
  6. #ifndef _MAX98926_H
  7. #define _MAX98926_H
  8. #define MAX98926_CHIP_VERSION 0x40
  9. #define MAX98926_CHIP_VERSION1 0x50
  10. #define MAX98926_VBAT_DATA 0x00
  11. #define MAX98926_VBST_DATA 0x01
  12. #define MAX98926_LIVE_STATUS0 0x02
  13. #define MAX98926_LIVE_STATUS1 0x03
  14. #define MAX98926_LIVE_STATUS2 0x04
  15. #define MAX98926_STATE0 0x05
  16. #define MAX98926_STATE1 0x06
  17. #define MAX98926_STATE2 0x07
  18. #define MAX98926_FLAG0 0x08
  19. #define MAX98926_FLAG1 0x09
  20. #define MAX98926_FLAG2 0x0A
  21. #define MAX98926_IRQ_ENABLE0 0x0B
  22. #define MAX98926_IRQ_ENABLE1 0x0C
  23. #define MAX98926_IRQ_ENABLE2 0x0D
  24. #define MAX98926_IRQ_CLEAR0 0x0E
  25. #define MAX98926_IRQ_CLEAR1 0x0F
  26. #define MAX98926_IRQ_CLEAR2 0x10
  27. #define MAX98926_MAP0 0x11
  28. #define MAX98926_MAP1 0x12
  29. #define MAX98926_MAP2 0x13
  30. #define MAX98926_MAP3 0x14
  31. #define MAX98926_MAP4 0x15
  32. #define MAX98926_MAP5 0x16
  33. #define MAX98926_MAP6 0x17
  34. #define MAX98926_MAP7 0x18
  35. #define MAX98926_MAP8 0x19
  36. #define MAX98926_DAI_CLK_MODE1 0x1A
  37. #define MAX98926_DAI_CLK_MODE2 0x1B
  38. #define MAX98926_DAI_CLK_DIV_M_MSBS 0x1C
  39. #define MAX98926_DAI_CLK_DIV_M_LSBS 0x1D
  40. #define MAX98926_DAI_CLK_DIV_N_MSBS 0x1E
  41. #define MAX98926_DAI_CLK_DIV_N_LSBS 0x1F
  42. #define MAX98926_FORMAT 0x20
  43. #define MAX98926_TDM_SLOT_SELECT 0x21
  44. #define MAX98926_DOUT_CFG_VMON 0x22
  45. #define MAX98926_DOUT_CFG_IMON 0x23
  46. #define MAX98926_DOUT_CFG_VBAT 0x24
  47. #define MAX98926_DOUT_CFG_VBST 0x25
  48. #define MAX98926_DOUT_CFG_FLAG 0x26
  49. #define MAX98926_DOUT_HIZ_CFG1 0x27
  50. #define MAX98926_DOUT_HIZ_CFG2 0x28
  51. #define MAX98926_DOUT_HIZ_CFG3 0x29
  52. #define MAX98926_DOUT_HIZ_CFG4 0x2A
  53. #define MAX98926_DOUT_DRV_STRENGTH 0x2B
  54. #define MAX98926_FILTERS 0x2C
  55. #define MAX98926_GAIN 0x2D
  56. #define MAX98926_GAIN_RAMPING 0x2E
  57. #define MAX98926_SPK_AMP 0x2F
  58. #define MAX98926_THRESHOLD 0x30
  59. #define MAX98926_ALC_ATTACK 0x31
  60. #define MAX98926_ALC_ATTEN_RLS 0x32
  61. #define MAX98926_ALC_HOLD_RLS 0x33
  62. #define MAX98926_ALC_CONFIGURATION 0x34
  63. #define MAX98926_BOOST_CONVERTER 0x35
  64. #define MAX98926_BLOCK_ENABLE 0x36
  65. #define MAX98926_CONFIGURATION 0x37
  66. #define MAX98926_GLOBAL_ENABLE 0x38
  67. #define MAX98926_BOOST_LIMITER 0x3A
  68. #define MAX98926_VERSION 0xFF
  69. #define MAX98926_REG_CNT (MAX98926_R03A_BOOST_LIMITER+1)
  70. #define MAX98926_PDM_CURRENT_MASK (1<<7)
  71. #define MAX98926_PDM_CURRENT_SHIFT 7
  72. #define MAX98926_PDM_VOLTAGE_MASK (1<<3)
  73. #define MAX98926_PDM_VOLTAGE_SHIFT 3
  74. #define MAX98926_PDM_CHANNEL_0_MASK (1<<2)
  75. #define MAX98926_PDM_CHANNEL_0_SHIFT 2
  76. #define MAX98926_PDM_CHANNEL_1_MASK (1<<6)
  77. #define MAX98926_PDM_CHANNEL_1_SHIFT 6
  78. #define MAX98926_PDM_CHANNEL_1_HIZ 5
  79. #define MAX98926_PDM_CHANNEL_0_HIZ 1
  80. #define MAX98926_PDM_SOURCE_0_SHIFT 0
  81. #define MAX98926_PDM_SOURCE_0_MASK (1<<0)
  82. #define MAX98926_PDM_SOURCE_1_MASK (1<<4)
  83. #define MAX98926_PDM_SOURCE_1_SHIFT 4
  84. /* MAX98926 Register Bit Fields */
  85. /* MAX98926_R002_LIVE_STATUS0 */
  86. #define MAX98926_THERMWARN_STATUS_MASK (1<<3)
  87. #define MAX98926_THERMWARN_STATUS_SHIFT 3
  88. #define MAX98926_THERMWARN_STATUS_WIDTH 1
  89. #define MAX98926_THERMSHDN_STATUS_MASK (1<<1)
  90. #define MAX98926_THERMSHDN_STATUS_SHIFT 1
  91. #define MAX98926_THERMSHDN_STATUS_WIDTH 1
  92. /* MAX98926_R003_LIVE_STATUS1 */
  93. #define MAX98926_SPKCURNT_STATUS_MASK (1<<5)
  94. #define MAX98926_SPKCURNT_STATUS_SHIFT 5
  95. #define MAX98926_SPKCURNT_STATUS_WIDTH 1
  96. #define MAX98926_WATCHFAIL_STATUS_MASK (1<<4)
  97. #define MAX98926_WATCHFAIL_STATUS_SHIFT 4
  98. #define MAX98926_WATCHFAIL_STATUS_WIDTH 1
  99. #define MAX98926_ALCINFH_STATUS_MASK (1<<3)
  100. #define MAX98926_ALCINFH_STATUS_SHIFT 3
  101. #define MAX98926_ALCINFH_STATUS_WIDTH 1
  102. #define MAX98926_ALCACT_STATUS_MASK (1<<2)
  103. #define MAX98926_ALCACT_STATUS_SHIFT 2
  104. #define MAX98926_ALCACT_STATUS_WIDTH 1
  105. #define MAX98926_ALCMUT_STATUS_MASK (1<<1)
  106. #define MAX98926_ALCMUT_STATUS_SHIFT 1
  107. #define MAX98926_ALCMUT_STATUS_WIDTH 1
  108. #define MAX98926_ACLP_STATUS_MASK (1<<0)
  109. #define MAX98926_ACLP_STATUS_SHIFT 0
  110. #define MAX98926_ACLP_STATUS_WIDTH 1
  111. /* MAX98926_R004_LIVE_STATUS2 */
  112. #define MAX98926_SLOTOVRN_STATUS_MASK (1<<6)
  113. #define MAX98926_SLOTOVRN_STATUS_SHIFT 6
  114. #define MAX98926_SLOTOVRN_STATUS_WIDTH 1
  115. #define MAX98926_INVALSLOT_STATUS_MASK (1<<5)
  116. #define MAX98926_INVALSLOT_STATUS_SHIFT 5
  117. #define MAX98926_INVALSLOT_STATUS_WIDTH 1
  118. #define MAX98926_SLOTCNFLT_STATUS_MASK (1<<4)
  119. #define MAX98926_SLOTCNFLT_STATUS_SHIFT 4
  120. #define MAX98926_SLOTCNFLT_STATUS_WIDTH 1
  121. #define MAX98926_VBSTOVFL_STATUS_MASK (1<<3)
  122. #define MAX98926_VBSTOVFL_STATUS_SHIFT 3
  123. #define MAX98926_VBSTOVFL_STATUS_WIDTH 1
  124. #define MAX98926_VBATOVFL_STATUS_MASK (1<<2)
  125. #define MAX98926_VBATOVFL_STATUS_SHIFT 2
  126. #define MAX98926_VBATOVFL_STATUS_WIDTH 1
  127. #define MAX98926_IMONOVFL_STATUS_MASK (1<<1)
  128. #define MAX98926_IMONOVFL_STATUS_SHIFT 1
  129. #define MAX98926_IMONOVFL_STATUS_WIDTH 1
  130. #define MAX98926_VMONOVFL_STATUS_MASK (1<<0)
  131. #define MAX98926_VMONOVFL_STATUS_SHIFT 0
  132. #define MAX98926_VMONOVFL_STATUS_WIDTH 1
  133. /* MAX98926_R005_STATE0 */
  134. #define MAX98926_THERMWARN_END_STATE_MASK (1<<3)
  135. #define MAX98926_THERMWARN_END_STATE_SHIFT 3
  136. #define MAX98926_THERMWARN_END_STATE_WIDTH 1
  137. #define MAX98926_THERMWARN_BGN_STATE_MASK (1<<2)
  138. #define MAX98926_THERMWARN_BGN_STATE_SHIFT 1
  139. #define MAX98926_THERMWARN_BGN_STATE_WIDTH 1
  140. #define MAX98926_THERMSHDN_END_STATE_MASK (1<<1)
  141. #define MAX98926_THERMSHDN_END_STATE_SHIFT 1
  142. #define MAX98926_THERMSHDN_END_STATE_WIDTH 1
  143. #define MAX98926_THERMSHDN_BGN_STATE_MASK (1<<0)
  144. #define MAX98926_THERMSHDN_BGN_STATE_SHIFT 0
  145. #define MAX98926_THERMSHDN_BGN_STATE_WIDTH 1
  146. /* MAX98926_R006_STATE1 */
  147. #define MAX98926_SPRCURNT_STATE_MASK (1<<5)
  148. #define MAX98926_SPRCURNT_STATE_SHIFT 5
  149. #define MAX98926_SPRCURNT_STATE_WIDTH 1
  150. #define MAX98926_WATCHFAIL_STATE_MASK (1<<4)
  151. #define MAX98926_WATCHFAIL_STATE_SHIFT 4
  152. #define MAX98926_WATCHFAIL_STATE_WIDTH 1
  153. #define MAX98926_ALCINFH_STATE_MASK (1<<3)
  154. #define MAX98926_ALCINFH_STATE_SHIFT 3
  155. #define MAX98926_ALCINFH_STATE_WIDTH 1
  156. #define MAX98926_ALCACT_STATE_MASK (1<<2)
  157. #define MAX98926_ALCACT_STATE_SHIFT 2
  158. #define MAX98926_ALCACT_STATE_WIDTH 1
  159. #define MAX98926_ALCMUT_STATE_MASK (1<<1)
  160. #define MAX98926_ALCMUT_STATE_SHIFT 1
  161. #define MAX98926_ALCMUT_STATE_WIDTH 1
  162. #define MAX98926_ALCP_STATE_MASK (1<<0)
  163. #define MAX98926_ALCP_STATE_SHIFT 0
  164. #define MAX98926_ALCP_STATE_WIDTH 1
  165. /* MAX98926_R007_STATE2 */
  166. #define MAX98926_SLOTOVRN_STATE_MASK (1<<6)
  167. #define MAX98926_SLOTOVRN_STATE_SHIFT 6
  168. #define MAX98926_SLOTOVRN_STATE_WIDTH 1
  169. #define MAX98926_INVALSLOT_STATE_MASK (1<<5)
  170. #define MAX98926_INVALSLOT_STATE_SHIFT 5
  171. #define MAX98926_INVALSLOT_STATE_WIDTH 1
  172. #define MAX98926_SLOTCNFLT_STATE_MASK (1<<4)
  173. #define MAX98926_SLOTCNFLT_STATE_SHIFT 4
  174. #define MAX98926_SLOTCNFLT_STATE_WIDTH 1
  175. #define MAX98926_VBSTOVFL_STATE_MASK (1<<3)
  176. #define MAX98926_VBSTOVFL_STATE_SHIFT 3
  177. #define MAX98926_VBSTOVFL_STATE_WIDTH 1
  178. #define MAX98926_VBATOVFL_STATE_MASK (1<<2)
  179. #define MAX98926_VBATOVFL_STATE_SHIFT 2
  180. #define MAX98926_VBATOVFL_STATE_WIDTH 1
  181. #define MAX98926_IMONOVFL_STATE_MASK (1<<1)
  182. #define MAX98926_IMONOVFL_STATE_SHIFT 1
  183. #define MAX98926_IMONOVFL_STATE_WIDTH 1
  184. #define MAX98926_VMONOVFL_STATE_MASK (1<<0)
  185. #define MAX98926_VMONOVFL_STATE_SHIFT 0
  186. #define MAX98926_VMONOVFL_STATE_WIDTH 1
  187. /* MAX98926_R008_FLAG0 */
  188. #define MAX98926_THERMWARN_END_FLAG_MASK (1<<3)
  189. #define MAX98926_THERMWARN_END_FLAG_SHIFT 3
  190. #define MAX98926_THERMWARN_END_FLAG_WIDTH 1
  191. #define MAX98926_THERMWARN_BGN_FLAG_MASK (1<<2)
  192. #define MAX98926_THERMWARN_BGN_FLAG_SHIFT 2
  193. #define MAX98926_THERMWARN_BGN_FLAG_WIDTH 1
  194. #define MAX98926_THERMSHDN_END_FLAG_MASK (1<<1)
  195. #define MAX98926_THERMSHDN_END_FLAG_SHIFT 1
  196. #define MAX98926_THERMSHDN_END_FLAG_WIDTH 1
  197. #define MAX98926_THERMSHDN_BGN_FLAG_MASK (1<<0)
  198. #define MAX98926_THERMSHDN_BGN_FLAG_SHIFT 0
  199. #define MAX98926_THERMSHDN_BGN_FLAG_WIDTH 1
  200. /* MAX98926_R009_FLAG1 */
  201. #define MAX98926_SPKCURNT_FLAG_MASK (1<<5)
  202. #define MAX98926_SPKCURNT_FLAG_SHIFT 5
  203. #define MAX98926_SPKCURNT_FLAG_WIDTH 1
  204. #define MAX98926_WATCHFAIL_FLAG_MASK (1<<4)
  205. #define MAX98926_WATCHFAIL_FLAG_SHIFT 4
  206. #define MAX98926_WATCHFAIL_FLAG_WIDTH 1
  207. #define MAX98926_ALCINFH_FLAG_MASK (1<<3)
  208. #define MAX98926_ALCINFH_FLAG_SHIFT 3
  209. #define MAX98926_ALCINFH_FLAG_WIDTH 1
  210. #define MAX98926_ALCACT_FLAG_MASK (1<<2)
  211. #define MAX98926_ALCACT_FLAG_SHIFT 2
  212. #define MAX98926_ALCACT_FLAG_WIDTH 1
  213. #define MAX98926_ALCMUT_FLAG_MASK (1<<1)
  214. #define MAX98926_ALCMUT_FLAG_SHIFT 1
  215. #define MAX98926_ALCMUT_FLAG_WIDTH 1
  216. #define MAX98926_ALCP_FLAG_MASK (1<<0)
  217. #define MAX98926_ALCP_FLAG_SHIFT 0
  218. #define MAX98926_ALCP_FLAG_WIDTH 1
  219. /* MAX98926_R00A_FLAG2 */
  220. #define MAX98926_SLOTOVRN_FLAG_MASK (1<<6)
  221. #define MAX98926_SLOTOVRN_FLAG_SHIFT 6
  222. #define MAX98926_SLOTOVRN_FLAG_WIDTH 1
  223. #define MAX98926_INVALSLOT_FLAG_MASK (1<<5)
  224. #define MAX98926_INVALSLOT_FLAG_SHIFT 5
  225. #define MAX98926_INVALSLOT_FLAG_WIDTH 1
  226. #define MAX98926_SLOTCNFLT_FLAG_MASK (1<<4)
  227. #define MAX98926_SLOTCNFLT_FLAG_SHIFT 4
  228. #define MAX98926_SLOTCNFLT_FLAG_WIDTH 1
  229. #define MAX98926_VBSTOVFL_FLAG_MASK (1<<3)
  230. #define MAX98926_VBSTOVFL_FLAG_SHIFT 3
  231. #define MAX98926_VBSTOVFL_FLAG_WIDTH 1
  232. #define MAX98926_VBATOVFL_FLAG_MASK (1<<2)
  233. #define MAX98926_VBATOVFL_FLAG_SHIFT 2
  234. #define MAX98926_VBATOVFL_FLAG_WIDTH 1
  235. #define MAX98926_IMONOVFL_FLAG_MASK (1<<1)
  236. #define MAX98926_IMONOVFL_FLAG_SHIFT 1
  237. #define MAX98926_IMONOVFL_FLAG_WIDTH 1
  238. #define MAX98926_VMONOVFL_FLAG_MASK (1<<0)
  239. #define MAX98926_VMONOVFL_FLAG_SHIFT 0
  240. #define MAX98926_VMONOVFL_FLAG_WIDTH 1
  241. /* MAX98926_R00B_IRQ_ENABLE0 */
  242. #define MAX98926_THERMWARN_END_EN_MASK (1<<3)
  243. #define MAX98926_THERMWARN_END_EN_SHIFT 3
  244. #define MAX98926_THERMWARN_END_EN_WIDTH 1
  245. #define MAX98926_THERMWARN_BGN_EN_MASK (1<<2)
  246. #define MAX98926_THERMWARN_BGN_EN_SHIFT 2
  247. #define MAX98926_THERMWARN_BGN_EN_WIDTH 1
  248. #define MAX98926_THERMSHDN_END_EN_MASK (1<<1)
  249. #define MAX98926_THERMSHDN_END_EN_SHIFT 1
  250. #define MAX98926_THERMSHDN_END_EN_WIDTH 1
  251. #define MAX98926_THERMSHDN_BGN_EN_MASK (1<<0)
  252. #define MAX98926_THERMSHDN_BGN_EN_SHIFT 0
  253. #define MAX98926_THERMSHDN_BGN_EN_WIDTH 1
  254. /* MAX98926_R00C_IRQ_ENABLE1 */
  255. #define MAX98926_SPKCURNT_EN_MASK (1<<5)
  256. #define MAX98926_SPKCURNT_EN_SHIFT 5
  257. #define MAX98926_SPKCURNT_EN_WIDTH 1
  258. #define MAX98926_WATCHFAIL_EN_MASK (1<<4)
  259. #define MAX98926_WATCHFAIL_EN_SHIFT 4
  260. #define MAX98926_WATCHFAIL_EN_WIDTH 1
  261. #define MAX98926_ALCINFH_EN_MASK (1<<3)
  262. #define MAX98926_ALCINFH_EN_SHIFT 3
  263. #define MAX98926_ALCINFH_EN_WIDTH 1
  264. #define MAX98926_ALCACT_EN_MASK (1<<2)
  265. #define MAX98926_ALCACT_EN_SHIFT 2
  266. #define MAX98926_ALCACT_EN_WIDTH 1
  267. #define MAX98926_ALCMUT_EN_MASK (1<<1)
  268. #define MAX98926_ALCMUT_EN_SHIFT 1
  269. #define MAX98926_ALCMUT_EN_WIDTH 1
  270. #define MAX98926_ALCP_EN_MASK (1<<0)
  271. #define MAX98926_ALCP_EN_SHIFT 0
  272. #define MAX98926_ALCP_EN_WIDTH 1
  273. /* MAX98926_R00D_IRQ_ENABLE2 */
  274. #define MAX98926_SLOTOVRN_EN_MASK (1<<6)
  275. #define MAX98926_SLOTOVRN_EN_SHIFT 6
  276. #define MAX98926_SLOTOVRN_EN_WIDTH 1
  277. #define MAX98926_INVALSLOT_EN_MASK (1<<5)
  278. #define MAX98926_INVALSLOT_EN_SHIFT 5
  279. #define MAX98926_INVALSLOT_EN_WIDTH 1
  280. #define MAX98926_SLOTCNFLT_EN_MASK (1<<4)
  281. #define MAX98926_SLOTCNFLT_EN_SHIFT 4
  282. #define MAX98926_SLOTCNFLT_EN_WIDTH 1
  283. #define MAX98926_VBSTOVFL_EN_MASK (1<<3)
  284. #define MAX98926_VBSTOVFL_EN_SHIFT 3
  285. #define MAX98926_VBSTOVFL_EN_WIDTH 1
  286. #define MAX98926_VBATOVFL_EN_MASK (1<<2)
  287. #define MAX98926_VBATOVFL_EN_SHIFT 2
  288. #define MAX98926_VBATOVFL_EN_WIDTH 1
  289. #define MAX98926_IMONOVFL_EN_MASK (1<<1)
  290. #define MAX98926_IMONOVFL_EN_SHIFT 1
  291. #define MAX98926_IMONOVFL_EN_WIDTH 1
  292. #define MAX98926_VMONOVFL_EN_MASK (1<<0)
  293. #define MAX98926_VMONOVFL_EN_SHIFT 0
  294. #define MAX98926_VMONOVFL_EN_WIDTH 1
  295. /* MAX98926_R00E_IRQ_CLEAR0 */
  296. #define MAX98926_THERMWARN_END_CLR_MASK (1<<3)
  297. #define MAX98926_THERMWARN_END_CLR_SHIFT 3
  298. #define MAX98926_THERMWARN_END_CLR_WIDTH 1
  299. #define MAX98926_THERMWARN_BGN_CLR_MASK (1<<2)
  300. #define MAX98926_THERMWARN_BGN_CLR_SHIFT 2
  301. #define MAX98926_THERMWARN_BGN_CLR_WIDTH 1
  302. #define MAX98926_THERMSHDN_END_CLR_MASK (1<<1)
  303. #define MAX98926_THERMSHDN_END_CLR_SHIFT 1
  304. #define MAX98926_THERMSHDN_END_CLR_WIDTH 1
  305. #define MAX98926_THERMSHDN_BGN_CLR_MASK (1<<0)
  306. #define MAX98926_THERMSHDN_BGN_CLR_SHIFT 0
  307. #define MAX98926_THERMSHDN_BGN_CLR_WIDTH 1
  308. /* MAX98926_R00F_IRQ_CLEAR1 */
  309. #define MAX98926_SPKCURNT_CLR_MASK (1<<5)
  310. #define MAX98926_SPKCURNT_CLR_SHIFT 5
  311. #define MAX98926_SPKCURNT_CLR_WIDTH 1
  312. #define MAX98926_WATCHFAIL_CLR_MASK (1<<4)
  313. #define MAX98926_WATCHFAIL_CLR_SHIFT 4
  314. #define MAX98926_WATCHFAIL_CLR_WIDTH 1
  315. #define MAX98926_ALCINFH_CLR_MASK (1<<3)
  316. #define MAX98926_ALCINFH_CLR_SHIFT 3
  317. #define MAX98926_ALCINFH_CLR_WIDTH 1
  318. #define MAX98926_ALCACT_CLR_MASK (1<<2)
  319. #define MAX98926_ALCACT_CLR_SHIFT 2
  320. #define MAX98926_ALCACT_CLR_WIDTH 1
  321. #define MAX98926_ALCMUT_CLR_MASK (1<<1)
  322. #define MAX98926_ALCMUT_CLR_SHIFT 1
  323. #define MAX98926_ALCMUT_CLR_WIDTH 1
  324. #define MAX98926_ALCP_CLR_MASK (1<<0)
  325. #define MAX98926_ALCP_CLR_SHIFT 0
  326. #define MAX98926_ALCP_CLR_WIDTH 1
  327. /* MAX98926_R010_IRQ_CLEAR2 */
  328. #define MAX98926_SLOTOVRN_CLR_MASK (1<<6)
  329. #define MAX98926_SLOTOVRN_CLR_SHIFT 6
  330. #define MAX98926_SLOTOVRN_CLR_WIDTH 1
  331. #define MAX98926_INVALSLOT_CLR_MASK (1<<5)
  332. #define MAX98926_INVALSLOT_CLR_SHIFT 5
  333. #define MAX98926_INVALSLOT_CLR_WIDTH 1
  334. #define MAX98926_SLOTCNFLT_CLR_MASK (1<<4)
  335. #define MAX98926_SLOTCNFLT_CLR_SHIFT 4
  336. #define MAX98926_SLOTCNFLT_CLR_WIDTH 1
  337. #define MAX98926_VBSTOVFL_CLR_MASK (1<<3)
  338. #define MAX98926_VBSTOVFL_CLR_SHIFT 3
  339. #define MAX98926_VBSTOVFL_CLR_WIDTH 1
  340. #define MAX98926_VBATOVFL_CLR_MASK (1<<2)
  341. #define MAX98926_VBATOVFL_CLR_SHIFT 2
  342. #define MAX98926_VBATOVFL_CLR_WIDTH 1
  343. #define MAX98926_IMONOVFL_CLR_MASK (1<<1)
  344. #define MAX98926_IMONOVFL_CLR_SHIFT 1
  345. #define MAX98926_IMONOVFL_CLR_WIDTH 1
  346. #define MAX98926_VMONOVFL_CLR_MASK (1<<0)
  347. #define MAX98926_VMONOVFL_CLR_SHIFT 0
  348. #define MAX98926_VMONOVFL_CLR_WIDTH 1
  349. /* MAX98926_R011_MAP0 */
  350. #define MAX98926_ER_THERMWARN_EN_MASK (1<<7)
  351. #define MAX98926_ER_THERMWARN_EN_SHIFT 7
  352. #define MAX98926_ER_THERMWARN_EN_WIDTH 1
  353. #define MAX98926_ER_THERMWARN_MAP_MASK (0x07<<4)
  354. #define MAX98926_ER_THERMWARN_MAP_SHIFT 4
  355. #define MAX98926_ER_THERMWARN_MAP_WIDTH 3
  356. /* MAX98926_R012_MAP1 */
  357. #define MAX98926_ER_ALCMUT_EN_MASK (1<<7)
  358. #define MAX98926_ER_ALCMUT_EN_SHIFT 7
  359. #define MAX98926_ER_ALCMUT_EN_WIDTH 1
  360. #define MAX98926_ER_ALCMUT_MAP_MASK (0x07<<4)
  361. #define MAX98926_ER_ALCMUT_MAP_SHIFT 4
  362. #define MAX98926_ER_ALCMUT_MAP_WIDTH 3
  363. #define MAX98926_ER_ALCP_EN_MASK (1<<3)
  364. #define MAX98926_ER_ALCP_EN_SHIFT 3
  365. #define MAX98926_ER_ALCP_EN_WIDTH 1
  366. #define MAX98926_ER_ALCP_MAP_MASK (0x07<<0)
  367. #define MAX98926_ER_ALCP_MAP_SHIFT 0
  368. #define MAX98926_ER_ALCP_MAP_WIDTH 3
  369. /* MAX98926_R013_MAP2 */
  370. #define MAX98926_ER_ALCINFH_EN_MASK (1<<7)
  371. #define MAX98926_ER_ALCINFH_EN_SHIFT 7
  372. #define MAX98926_ER_ALCINFH_EN_WIDTH 1
  373. #define MAX98926_ER_ALCINFH_MAP_MASK (0x07<<4)
  374. #define MAX98926_ER_ALCINFH_MAP_SHIFT 4
  375. #define MAX98926_ER_ALCINFH_MAP_WIDTH 3
  376. #define MAX98926_ER_ALCACT_EN_MASK (1<<3)
  377. #define MAX98926_ER_ALCACT_EN_SHIFT 3
  378. #define MAX98926_ER_ALCACT_EN_WIDTH 1
  379. #define MAX98926_ER_ALCACT_MAP_MASK (0x07<<0)
  380. #define MAX98926_ER_ALCACT_MAP_SHIFT 0
  381. #define MAX98926_ER_ALCACT_MAP_WIDTH 3
  382. /* MAX98926_R014_MAP3 */
  383. #define MAX98926_ER_SPKCURNT_EN_MASK (1<<7)
  384. #define MAX98926_ER_SPKCURNT_EN_SHIFT 7
  385. #define MAX98926_ER_SPKCURNT_EN_WIDTH 1
  386. #define MAX98926_ER_SPKCURNT_MAP_MASK (0x07<<4)
  387. #define MAX98926_ER_SPKCURNT_MAP_SHIFT 4
  388. #define MAX98926_ER_SPKCURNT_MAP_WIDTH 3
  389. /* MAX98926_R015_MAP4 */
  390. /* RESERVED */
  391. /* MAX98926_R016_MAP5 */
  392. #define MAX98926_ER_IMONOVFL_EN_MASK (1<<7)
  393. #define MAX98926_ER_IMONOVFL_EN_SHIFT 7
  394. #define MAX98926_ER_IMONOVFL_EN_WIDTH 1
  395. #define MAX98926_ER_IMONOVFL_MAP_MASK (0x07<<4)
  396. #define MAX98926_ER_IMONOVFL_MAP_SHIFT 4
  397. #define MAX98926_ER_IMONOVFL_MAP_WIDTH 3
  398. #define MAX98926_ER_VMONOVFL_EN_MASK (1<<3)
  399. #define MAX98926_ER_VMONOVFL_EN_SHIFT 3
  400. #define MAX98926_ER_VMONOVFL_EN_WIDTH 1
  401. #define MAX98926_ER_VMONOVFL_MAP_MASK (0x07<<0)
  402. #define MAX98926_ER_VMONOVFL_MAP_SHIFT 0
  403. #define MAX98926_ER_VMONOVFL_MAP_WIDTH 3
  404. /* MAX98926_R017_MAP6 */
  405. #define MAX98926_ER_VBSTOVFL_EN_MASK (1<<7)
  406. #define MAX98926_ER_VBSTOVFL_EN_SHIFT 7
  407. #define MAX98926_ER_VBSTOVFL_EN_WIDTH 1
  408. #define MAX98926_ER_VBSTOVFL_MAP_MASK (0x07<<4)
  409. #define MAX98926_ER_VBSTOVFL_MAP_SHIFT 4
  410. #define MAX98926_ER_VBSTOVFL_MAP_WIDTH 3
  411. #define MAX98926_ER_VBATOVFL_EN_MASK (1<<3)
  412. #define MAX98926_ER_VBATOVFL_EN_SHIFT 3
  413. #define MAX98926_ER_VBATOVFL_EN_WIDTH 1
  414. #define MAX98926_ER_VBATOVFL_MAP_MASK (0x07<<0)
  415. #define MAX98926_ER_VBATOVFL_MAP_SHIFT 0
  416. #define MAX98926_ER_VBATOVFL_MAP_WIDTH 3
  417. /* MAX98926_R018_MAP7 */
  418. #define MAX98926_ER_INVALSLOT_EN_MASK (1<<7)
  419. #define MAX98926_ER_INVALSLOT_EN_SHIFT 7
  420. #define MAX98926_ER_INVALSLOT_EN_WIDTH 1
  421. #define MAX98926_ER_INVALSLOT_MAP_MASK (0x07<<4)
  422. #define MAX98926_ER_INVALSLOT_MAP_SHIFT 4
  423. #define MAX98926_ER_INVALSLOT_MAP_WIDTH 3
  424. #define MAX98926_ER_SLOTCNFLT_EN_MASK (1<<3)
  425. #define MAX98926_ER_SLOTCNFLT_EN_SHIFT 3
  426. #define MAX98926_ER_SLOTCNFLT_EN_WIDTH 1
  427. #define MAX98926_ER_SLOTCNFLT_MAP_MASK (0x07<<0)
  428. #define MAX98926_ER_SLOTCNFLT_MAP_SHIFT 0
  429. #define MAX98926_ER_SLOTCNFLT_MAP_WIDTH 3
  430. /* MAX98926_R019_MAP8 */
  431. #define MAX98926_ER_SLOTOVRN_EN_MASK (1<<3)
  432. #define MAX98926_ER_SLOTOVRN_EN_SHIFT 3
  433. #define MAX98926_ER_SLOTOVRN_EN_WIDTH 1
  434. #define MAX98926_ER_SLOTOVRN_MAP_MASK (0x07<<0)
  435. #define MAX98926_ER_SLOTOVRN_MAP_SHIFT 0
  436. #define MAX98926_ER_SLOTOVRN_MAP_WIDTH 3
  437. /* MAX98926_R01A_DAI_CLK_MODE1 */
  438. #define MAX98926_DAI_CLK_SOURCE_MASK (1<<6)
  439. #define MAX98926_DAI_CLK_SOURCE_SHIFT 6
  440. #define MAX98926_DAI_CLK_SOURCE_WIDTH 1
  441. #define MAX98926_MDLL_MULT_MASK (0x0F<<0)
  442. #define MAX98926_MDLL_MULT_SHIFT 0
  443. #define MAX98926_MDLL_MULT_WIDTH 4
  444. #define MAX98926_MDLL_MULT_MCLKx8 6
  445. #define MAX98926_MDLL_MULT_MCLKx16 8
  446. /* MAX98926_R01B_DAI_CLK_MODE2 */
  447. #define MAX98926_DAI_SR_MASK (0x0F<<4)
  448. #define MAX98926_DAI_SR_SHIFT 4
  449. #define MAX98926_DAI_SR_WIDTH 4
  450. #define MAX98926_DAI_MAS_MASK (1<<3)
  451. #define MAX98926_DAI_MAS_SHIFT 3
  452. #define MAX98926_DAI_MAS_WIDTH 1
  453. #define MAX98926_DAI_BSEL_MASK (0x07<<0)
  454. #define MAX98926_DAI_BSEL_SHIFT 0
  455. #define MAX98926_DAI_BSEL_WIDTH 3
  456. #define MAX98926_DAI_BSEL_32 (0 << MAX98926_DAI_BSEL_SHIFT)
  457. #define MAX98926_DAI_BSEL_48 (1 << MAX98926_DAI_BSEL_SHIFT)
  458. #define MAX98926_DAI_BSEL_64 (2 << MAX98926_DAI_BSEL_SHIFT)
  459. #define MAX98926_DAI_BSEL_256 (6 << MAX98926_DAI_BSEL_SHIFT)
  460. /* MAX98926_R01C_DAI_CLK_DIV_M_MSBS */
  461. #define MAX98926_DAI_M_MSBS_MASK (0xFF<<0)
  462. #define MAX98926_DAI_M_MSBS_SHIFT 0
  463. #define MAX98926_DAI_M_MSBS_WIDTH 8
  464. /* MAX98926_R01D_DAI_CLK_DIV_M_LSBS */
  465. #define MAX98926_DAI_M_LSBS_MASK (0xFF<<0)
  466. #define MAX98926_DAI_M_LSBS_SHIFT 0
  467. #define MAX98926_DAI_M_LSBS_WIDTH 8
  468. /* MAX98926_R01E_DAI_CLK_DIV_N_MSBS */
  469. #define MAX98926_DAI_N_MSBS_MASK (0x7F<<0)
  470. #define MAX98926_DAI_N_MSBS_SHIFT 0
  471. #define MAX98926_DAI_N_MSBS_WIDTH 7
  472. /* MAX98926_R01F_DAI_CLK_DIV_N_LSBS */
  473. #define MAX98926_DAI_N_LSBS_MASK (0xFF<<0)
  474. #define MAX98926_DAI_N_LSBS_SHIFT 0
  475. #define MAX98926_DAI_N_LSBS_WIDTH 8
  476. /* MAX98926_R020_FORMAT */
  477. #define MAX98926_DAI_CHANSZ_MASK (0x03<<6)
  478. #define MAX98926_DAI_CHANSZ_SHIFT 6
  479. #define MAX98926_DAI_CHANSZ_WIDTH 2
  480. #define MAX98926_DAI_INTERLEAVE_MASK (1<<5)
  481. #define MAX98926_DAI_INTERLEAVE_SHIFT 5
  482. #define MAX98926_DAI_INTERLEAVE_WIDTH 1
  483. #define MAX98926_DAI_EXTBCLK_HIZ_MASK (1<<4)
  484. #define MAX98926_DAI_EXTBCLK_HIZ_SHIFT 4
  485. #define MAX98926_DAI_EXTBCLK_HIZ_WIDTH 1
  486. #define MAX98926_DAI_WCI_MASK (1<<3)
  487. #define MAX98926_DAI_WCI_SHIFT 3
  488. #define MAX98926_DAI_WCI_WIDTH 1
  489. #define MAX98926_DAI_BCI_MASK (1<<2)
  490. #define MAX98926_DAI_BCI_SHIFT 2
  491. #define MAX98926_DAI_BCI_WIDTH 1
  492. #define MAX98926_DAI_DLY_MASK (1<<1)
  493. #define MAX98926_DAI_DLY_SHIFT 1
  494. #define MAX98926_DAI_DLY_WIDTH 1
  495. #define MAX98926_DAI_TDM_MASK (1<<0)
  496. #define MAX98926_DAI_TDM_SHIFT 0
  497. #define MAX98926_DAI_TDM_WIDTH 1
  498. #define MAX98926_DAI_CHANSZ_16 (1 << MAX98926_DAI_CHANSZ_SHIFT)
  499. #define MAX98926_DAI_CHANSZ_24 (2 << MAX98926_DAI_CHANSZ_SHIFT)
  500. #define MAX98926_DAI_CHANSZ_32 (3 << MAX98926_DAI_CHANSZ_SHIFT)
  501. /* MAX98926_R021_TDM_SLOT_SELECT */
  502. #define MAX98926_DAI_DO_EN_MASK (1<<7)
  503. #define MAX98926_DAI_DO_EN_SHIFT 7
  504. #define MAX98926_DAI_DO_EN_WIDTH 1
  505. #define MAX98926_DAI_DIN_EN_MASK (1<<6)
  506. #define MAX98926_DAI_DIN_EN_SHIFT 6
  507. #define MAX98926_DAI_DIN_EN_WIDTH 1
  508. #define MAX98926_DAI_INR_SOURCE_MASK (0x07<<3)
  509. #define MAX98926_DAI_INR_SOURCE_SHIFT 3
  510. #define MAX98926_DAI_INR_SOURCE_WIDTH 3
  511. #define MAX98926_DAI_INL_SOURCE_MASK (0x07<<0)
  512. #define MAX98926_DAI_INL_SOURCE_SHIFT 0
  513. #define MAX98926_DAI_INL_SOURCE_WIDTH 3
  514. /* MAX98926_R022_DOUT_CFG_VMON */
  515. #define MAX98926_DAI_VMON_EN_MASK (1<<5)
  516. #define MAX98926_DAI_VMON_EN_SHIFT 5
  517. #define MAX98926_DAI_VMON_EN_WIDTH 1
  518. #define MAX98926_DAI_VMON_SLOT_MASK (0x1F<<0)
  519. #define MAX98926_DAI_VMON_SLOT_SHIFT 0
  520. #define MAX98926_DAI_VMON_SLOT_WIDTH 5
  521. #define MAX98926_DAI_VMON_SLOT_00_01 (0 << MAX98926_DAI_VMON_SLOT_SHIFT)
  522. #define MAX98926_DAI_VMON_SLOT_01_02 (1 << MAX98926_DAI_VMON_SLOT_SHIFT)
  523. #define MAX98926_DAI_VMON_SLOT_02_03 (2 << MAX98926_DAI_VMON_SLOT_SHIFT)
  524. #define MAX98926_DAI_VMON_SLOT_03_04 (3 << MAX98926_DAI_VMON_SLOT_SHIFT)
  525. #define MAX98926_DAI_VMON_SLOT_04_05 (4 << MAX98926_DAI_VMON_SLOT_SHIFT)
  526. #define MAX98926_DAI_VMON_SLOT_05_06 (5 << MAX98926_DAI_VMON_SLOT_SHIFT)
  527. #define MAX98926_DAI_VMON_SLOT_06_07 (6 << MAX98926_DAI_VMON_SLOT_SHIFT)
  528. #define MAX98926_DAI_VMON_SLOT_07_08 (7 << MAX98926_DAI_VMON_SLOT_SHIFT)
  529. #define MAX98926_DAI_VMON_SLOT_08_09 (8 << MAX98926_DAI_VMON_SLOT_SHIFT)
  530. #define MAX98926_DAI_VMON_SLOT_09_0A (9 << MAX98926_DAI_VMON_SLOT_SHIFT)
  531. #define MAX98926_DAI_VMON_SLOT_0A_0B (10 << MAX98926_DAI_VMON_SLOT_SHIFT)
  532. #define MAX98926_DAI_VMON_SLOT_0B_0C (11 << MAX98926_DAI_VMON_SLOT_SHIFT)
  533. #define MAX98926_DAI_VMON_SLOT_0C_0D (12 << MAX98926_DAI_VMON_SLOT_SHIFT)
  534. #define MAX98926_DAI_VMON_SLOT_0D_0E (13 << MAX98926_DAI_VMON_SLOT_SHIFT)
  535. #define MAX98926_DAI_VMON_SLOT_0E_0F (14 << MAX98926_DAI_VMON_SLOT_SHIFT)
  536. #define MAX98926_DAI_VMON_SLOT_0F_10 (15 << MAX98926_DAI_VMON_SLOT_SHIFT)
  537. #define MAX98926_DAI_VMON_SLOT_10_11 (16 << MAX98926_DAI_VMON_SLOT_SHIFT)
  538. #define MAX98926_DAI_VMON_SLOT_11_12 (17 << MAX98926_DAI_VMON_SLOT_SHIFT)
  539. #define MAX98926_DAI_VMON_SLOT_12_13 (18 << MAX98926_DAI_VMON_SLOT_SHIFT)
  540. #define MAX98926_DAI_VMON_SLOT_13_14 (19 << MAX98926_DAI_VMON_SLOT_SHIFT)
  541. #define MAX98926_DAI_VMON_SLOT_14_15 (20 << MAX98926_DAI_VMON_SLOT_SHIFT)
  542. #define MAX98926_DAI_VMON_SLOT_15_16 (21 << MAX98926_DAI_VMON_SLOT_SHIFT)
  543. #define MAX98926_DAI_VMON_SLOT_16_17 (22 << MAX98926_DAI_VMON_SLOT_SHIFT)
  544. #define MAX98926_DAI_VMON_SLOT_17_18 (23 << MAX98926_DAI_VMON_SLOT_SHIFT)
  545. #define MAX98926_DAI_VMON_SLOT_18_19 (24 << MAX98926_DAI_VMON_SLOT_SHIFT)
  546. #define MAX98926_DAI_VMON_SLOT_19_1A (25 << MAX98926_DAI_VMON_SLOT_SHIFT)
  547. #define MAX98926_DAI_VMON_SLOT_1A_1B (26 << MAX98926_DAI_VMON_SLOT_SHIFT)
  548. #define MAX98926_DAI_VMON_SLOT_1B_1C (27 << MAX98926_DAI_VMON_SLOT_SHIFT)
  549. #define MAX98926_DAI_VMON_SLOT_1C_1D (28 << MAX98926_DAI_VMON_SLOT_SHIFT)
  550. #define MAX98926_DAI_VMON_SLOT_1D_1E (29 << MAX98926_DAI_VMON_SLOT_SHIFT)
  551. #define MAX98926_DAI_VMON_SLOT_1E_1F (30 << MAX98926_DAI_VMON_SLOT_SHIFT)
  552. /* MAX98926_R023_DOUT_CFG_IMON */
  553. #define MAX98926_DAI_IMON_EN_MASK (1<<5)
  554. #define MAX98926_DAI_IMON_EN_SHIFT 5
  555. #define MAX98926_DAI_IMON_EN_WIDTH 1
  556. #define MAX98926_DAI_IMON_SLOT_MASK (0x1F<<0)
  557. #define MAX98926_DAI_IMON_SLOT_SHIFT 0
  558. #define MAX98926_DAI_IMON_SLOT_WIDTH 5
  559. #define MAX98926_DAI_IMON_SLOT_00_01 (0 << MAX98926_DAI_IMON_SLOT_SHIFT)
  560. #define MAX98926_DAI_IMON_SLOT_01_02 (1 << MAX98926_DAI_IMON_SLOT_SHIFT)
  561. #define MAX98926_DAI_IMON_SLOT_02_03 (2 << MAX98926_DAI_IMON_SLOT_SHIFT)
  562. #define MAX98926_DAI_IMON_SLOT_03_04 (3 << MAX98926_DAI_IMON_SLOT_SHIFT)
  563. #define MAX98926_DAI_IMON_SLOT_04_05 (4 << MAX98926_DAI_IMON_SLOT_SHIFT)
  564. #define MAX98926_DAI_IMON_SLOT_05_06 (5 << MAX98926_DAI_IMON_SLOT_SHIFT)
  565. #define MAX98926_DAI_IMON_SLOT_06_07 (6 << MAX98926_DAI_IMON_SLOT_SHIFT)
  566. #define MAX98926_DAI_IMON_SLOT_07_08 (7 << MAX98926_DAI_IMON_SLOT_SHIFT)
  567. #define MAX98926_DAI_IMON_SLOT_08_09 (8 << MAX98926_DAI_IMON_SLOT_SHIFT)
  568. #define MAX98926_DAI_IMON_SLOT_09_0A (9 << MAX98926_DAI_IMON_SLOT_SHIFT)
  569. #define MAX98926_DAI_IMON_SLOT_0A_0B (10 << MAX98926_DAI_IMON_SLOT_SHIFT)
  570. #define MAX98926_DAI_IMON_SLOT_0B_0C (11 << MAX98926_DAI_IMON_SLOT_SHIFT)
  571. #define MAX98926_DAI_IMON_SLOT_0C_0D (12 << MAX98926_DAI_IMON_SLOT_SHIFT)
  572. #define MAX98926_DAI_IMON_SLOT_0D_0E (13 << MAX98926_DAI_IMON_SLOT_SHIFT)
  573. #define MAX98926_DAI_IMON_SLOT_0E_0F (14 << MAX98926_DAI_IMON_SLOT_SHIFT)
  574. #define MAX98926_DAI_IMON_SLOT_0F_10 (15 << MAX98926_DAI_IMON_SLOT_SHIFT)
  575. #define MAX98926_DAI_IMON_SLOT_10_11 (16 << MAX98926_DAI_IMON_SLOT_SHIFT)
  576. #define MAX98926_DAI_IMON_SLOT_11_12 (17 << MAX98926_DAI_IMON_SLOT_SHIFT)
  577. #define MAX98926_DAI_IMON_SLOT_12_13 (18 << MAX98926_DAI_IMON_SLOT_SHIFT)
  578. #define MAX98926_DAI_IMON_SLOT_13_14 (19 << MAX98926_DAI_IMON_SLOT_SHIFT)
  579. #define MAX98926_DAI_IMON_SLOT_14_15 (20 << MAX98926_DAI_IMON_SLOT_SHIFT)
  580. #define MAX98926_DAI_IMON_SLOT_15_16 (21 << MAX98926_DAI_IMON_SLOT_SHIFT)
  581. #define MAX98926_DAI_IMON_SLOT_16_17 (22 << MAX98926_DAI_IMON_SLOT_SHIFT)
  582. #define MAX98926_DAI_IMON_SLOT_17_18 (23 << MAX98926_DAI_IMON_SLOT_SHIFT)
  583. #define MAX98926_DAI_IMON_SLOT_18_19 (24 << MAX98926_DAI_IMON_SLOT_SHIFT)
  584. #define MAX98926_DAI_IMON_SLOT_19_1A (25 << MAX98926_DAI_IMON_SLOT_SHIFT)
  585. #define MAX98926_DAI_IMON_SLOT_1A_1B (26 << MAX98926_DAI_IMON_SLOT_SHIFT)
  586. #define MAX98926_DAI_IMON_SLOT_1B_1C (27 << MAX98926_DAI_IMON_SLOT_SHIFT)
  587. #define MAX98926_DAI_IMON_SLOT_1C_1D (28 << MAX98926_DAI_IMON_SLOT_SHIFT)
  588. #define MAX98926_DAI_IMON_SLOT_1D_1E (29 << MAX98926_DAI_IMON_SLOT_SHIFT)
  589. #define MAX98926_DAI_IMON_SLOT_1E_1F (30 << MAX98926_DAI_IMON_SLOT_SHIFT)
  590. /* MAX98926_R024_DOUT_CFG_VBAT */
  591. #define MAX98926_DAI_INTERLEAVE_SLOT_MASK (0x1F<<0)
  592. #define MAX98926_DAI_INTERLEAVE_SLOT_SHIFT 0
  593. #define MAX98926_DAI_INTERLEAVE_SLOT_WIDTH 5
  594. /* MAX98926_R025_DOUT_CFG_VBST */
  595. #define MAX98926_DAI_VBST_EN_MASK (1<<5)
  596. #define MAX98926_DAI_VBST_EN_SHIFT 5
  597. #define MAX98926_DAI_VBST_EN_WIDTH 1
  598. #define MAX98926_DAI_VBST_SLOT_MASK (0x1F<<0)
  599. #define MAX98926_DAI_VBST_SLOT_SHIFT 0
  600. #define MAX98926_DAI_VBST_SLOT_WIDTH 5
  601. /* MAX98926_R026_DOUT_CFG_FLAG */
  602. #define MAX98926_DAI_FLAG_EN_MASK (1<<5)
  603. #define MAX98926_DAI_FLAG_EN_SHIFT 5
  604. #define MAX98926_DAI_FLAG_EN_WIDTH 1
  605. #define MAX98926_DAI_FLAG_SLOT_MASK (0x1F<<0)
  606. #define MAX98926_DAI_FLAG_SLOT_SHIFT 0
  607. #define MAX98926_DAI_FLAG_SLOT_WIDTH 5
  608. /* MAX98926_R027_DOUT_HIZ_CFG1 */
  609. #define MAX98926_DAI_SLOT_HIZ_CFG1_MASK (0xFF<<0)
  610. #define MAX98926_DAI_SLOT_HIZ_CFG1_SHIFT 0
  611. #define MAX98926_DAI_SLOT_HIZ_CFG1_WIDTH 8
  612. /* MAX98926_R028_DOUT_HIZ_CFG2 */
  613. #define MAX98926_DAI_SLOT_HIZ_CFG2_MASK (0xFF<<0)
  614. #define MAX98926_DAI_SLOT_HIZ_CFG2_SHIFT 0
  615. #define MAX98926_DAI_SLOT_HIZ_CFG2_WIDTH 8
  616. /* MAX98926_R029_DOUT_HIZ_CFG3 */
  617. #define MAX98926_DAI_SLOT_HIZ_CFG3_MASK (0xFF<<0)
  618. #define MAX98926_DAI_SLOT_HIZ_CFG3_SHIFT 0
  619. #define MAX98926_DAI_SLOT_HIZ_CFG3_WIDTH 8
  620. /* MAX98926_R02A_DOUT_HIZ_CFG4 */
  621. #define MAX98926_DAI_SLOT_HIZ_CFG4_MASK (0xFF<<0)
  622. #define MAX98926_DAI_SLOT_HIZ_CFG4_SHIFT 0
  623. #define MAX98926_DAI_SLOT_HIZ_CFG4_WIDTH 8
  624. /* MAX98926_R02B_DOUT_DRV_STRENGTH */
  625. #define MAX98926_DAI_OUT_DRIVE_MASK (0x03<<0)
  626. #define MAX98926_DAI_OUT_DRIVE_SHIFT 0
  627. #define MAX98926_DAI_OUT_DRIVE_WIDTH 2
  628. /* MAX98926_R02C_FILTERS */
  629. #define MAX98926_ADC_DITHER_EN_MASK (1<<7)
  630. #define MAX98926_ADC_DITHER_EN_SHIFT 7
  631. #define MAX98926_ADC_DITHER_EN_WIDTH 1
  632. #define MAX98926_IV_DCB_EN_MASK (1<<6)
  633. #define MAX98926_IV_DCB_EN_SHIFT 6
  634. #define MAX98926_IV_DCB_EN_WIDTH 1
  635. #define MAX98926_DAC_DITHER_EN_MASK (1<<4)
  636. #define MAX98926_DAC_DITHER_EN_SHIFT 4
  637. #define MAX98926_DAC_DITHER_EN_WIDTH 1
  638. #define MAX98926_DAC_FILTER_MODE_MASK (1<<3)
  639. #define MAX98926_DAC_FILTER_MODE_SHIFT 3
  640. #define MAX98926_DAC_FILTER_MODE_WIDTH 1
  641. #define MAX98926_DAC_HPF_MASK (0x07<<0)
  642. #define MAX98926_DAC_HPF_SHIFT 0
  643. #define MAX98926_DAC_HPF_WIDTH 3
  644. #define MAX98926_DAC_HPF_DISABLE (0 << MAX98926_DAC_HPF_SHIFT)
  645. #define MAX98926_DAC_HPF_DC_BLOCK (1 << MAX98926_DAC_HPF_SHIFT)
  646. #define MAX98926_DAC_HPF_EN_100 (2 << MAX98926_DAC_HPF_SHIFT)
  647. #define MAX98926_DAC_HPF_EN_200 (3 << MAX98926_DAC_HPF_SHIFT)
  648. #define MAX98926_DAC_HPF_EN_400 (4 << MAX98926_DAC_HPF_SHIFT)
  649. #define MAX98926_DAC_HPF_EN_800 (5 << MAX98926_DAC_HPF_SHIFT)
  650. /* MAX98926_R02D_GAIN */
  651. #define MAX98926_DAC_IN_SEL_MASK (0x03<<5)
  652. #define MAX98926_DAC_IN_SEL_SHIFT 5
  653. #define MAX98926_DAC_IN_SEL_WIDTH 2
  654. #define MAX98926_SPK_GAIN_MASK (0x1F<<0)
  655. #define MAX98926_SPK_GAIN_SHIFT 0
  656. #define MAX98926_SPK_GAIN_WIDTH 5
  657. #define MAX98926_DAC_IN_SEL_LEFT_DAI (0 << MAX98926_DAC_IN_SEL_SHIFT)
  658. #define MAX98926_DAC_IN_SEL_RIGHT_DAI (1 << MAX98926_DAC_IN_SEL_SHIFT)
  659. #define MAX98926_DAC_IN_SEL_SUMMED_DAI (2 << MAX98926_DAC_IN_SEL_SHIFT)
  660. #define MAX98926_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << MAX98926_DAC_IN_SEL_SHIFT)
  661. /* MAX98926_R02E_GAIN_RAMPING */
  662. #define MAX98926_SPK_RMP_EN_MASK (1<<1)
  663. #define MAX98926_SPK_RMP_EN_SHIFT 1
  664. #define MAX98926_SPK_RMP_EN_WIDTH 1
  665. #define MAX98926_SPK_ZCD_EN_MASK (1<<0)
  666. #define MAX98926_SPK_ZCD_EN_SHIFT 0
  667. #define MAX98926_SPK_ZCD_EN_WIDTH 1
  668. /* MAX98926_R02F_SPK_AMP */
  669. #define MAX98926_SPK_MODE_MASK (1<<0)
  670. #define MAX98926_SPK_MODE_SHIFT 0
  671. #define MAX98926_SPK_MODE_WIDTH 1
  672. #define MAX98926_INSELECT_MODE_MASK (1<<1)
  673. #define MAX98926_INSELECT_MODE_SHIFT 1
  674. #define MAX98926_INSELECT_MODE_WIDTH 1
  675. /* MAX98926_R030_THRESHOLD */
  676. #define MAX98926_ALC_EN_MASK (1<<5)
  677. #define MAX98926_ALC_EN_SHIFT 5
  678. #define MAX98926_ALC_EN_WIDTH 1
  679. #define MAX98926_ALC_TH_MASK (0x1F<<0)
  680. #define MAX98926_ALC_TH_SHIFT 0
  681. #define MAX98926_ALC_TH_WIDTH 5
  682. /* MAX98926_R031_ALC_ATTACK */
  683. #define MAX98926_ALC_ATK_STEP_MASK (0x0F<<4)
  684. #define MAX98926_ALC_ATK_STEP_SHIFT 4
  685. #define MAX98926_ALC_ATK_STEP_WIDTH 4
  686. #define MAX98926_ALC_ATK_RATE_MASK (0x7<<0)
  687. #define MAX98926_ALC_ATK_RATE_SHIFT 0
  688. #define MAX98926_ALC_ATK_RATE_WIDTH 3
  689. /* MAX98926_R032_ALC_ATTEN_RLS */
  690. #define MAX98926_ALC_MAX_ATTEN_MASK (0x0F<<4)
  691. #define MAX98926_ALC_MAX_ATTEN_SHIFT 4
  692. #define MAX98926_ALC_MAX_ATTEN_WIDTH 4
  693. #define MAX98926_ALC_RLS_RATE_MASK (0x7<<0)
  694. #define MAX98926_ALC_RLS_RATE_SHIFT 0
  695. #define MAX98926_ALC_RLS_RATE_WIDTH 3
  696. /* MAX98926_R033_ALC_HOLD_RLS */
  697. #define MAX98926_ALC_RLS_TGR_MASK (1<<0)
  698. #define MAX98926_ALC_RLS_TGR_SHIFT 0
  699. #define MAX98926_ALC_RLS_TGR_WIDTH 1
  700. /* MAX98926_R034_ALC_CONFIGURATION */
  701. #define MAX98926_ALC_MUTE_EN_MASK (1<<7)
  702. #define MAX98926_ALC_MUTE_EN_SHIFT 7
  703. #define MAX98926_ALC_MUTE_EN_WIDTH 1
  704. #define MAX98926_ALC_MUTE_DLY_MASK (0x07<<4)
  705. #define MAX98926_ALC_MUTE_DLY_SHIFT 4
  706. #define MAX98926_ALC_MUTE_DLY_WIDTH 3
  707. #define MAX98926_ALC_RLS_DBT_MASK (0x07<<0)
  708. #define MAX98926_ALC_RLS_DBT_SHIFT 0
  709. #define MAX98926_ALC_RLS_DBT_WIDTH 3
  710. /* MAX98926_R035_BOOST_CONVERTER */
  711. #define MAX98926_BST_SYNC_MASK (1<<7)
  712. #define MAX98926_BST_SYNC_SHIFT 7
  713. #define MAX98926_BST_SYNC_WIDTH 1
  714. #define MAX98926_BST_PHASE_MASK (0x03<<4)
  715. #define MAX98926_BST_PHASE_SHIFT 4
  716. #define MAX98926_BST_PHASE_WIDTH 2
  717. #define MAX98926_BST_SKIP_MODE_MASK (0x03<<0)
  718. #define MAX98926_BST_SKIP_MODE_SHIFT 0
  719. #define MAX98926_BST_SKIP_MODE_WIDTH 2
  720. /* MAX98926_R036_BLOCK_ENABLE */
  721. #define MAX98926_BST_EN_MASK (1<<7)
  722. #define MAX98926_BST_EN_SHIFT 7
  723. #define MAX98926_BST_EN_WIDTH 1
  724. #define MAX98926_WATCH_EN_MASK (1<<6)
  725. #define MAX98926_WATCH_EN_SHIFT 6
  726. #define MAX98926_WATCH_EN_WIDTH 1
  727. #define MAX98926_CLKMON_EN_MASK (1<<5)
  728. #define MAX98926_CLKMON_EN_SHIFT 5
  729. #define MAX98926_CLKMON_EN_WIDTH 1
  730. #define MAX98926_SPK_EN_MASK (1<<4)
  731. #define MAX98926_SPK_EN_SHIFT 4
  732. #define MAX98926_SPK_EN_WIDTH 1
  733. #define MAX98926_ADC_VBST_EN_MASK (1<<3)
  734. #define MAX98926_ADC_VBST_EN_SHIFT 3
  735. #define MAX98926_ADC_VBST_EN_WIDTH 1
  736. #define MAX98926_ADC_VBAT_EN_MASK (1<<2)
  737. #define MAX98926_ADC_VBAT_EN_SHIFT 2
  738. #define MAX98926_ADC_VBAT_EN_WIDTH 1
  739. #define MAX98926_ADC_IMON_EN_MASK (1<<1)
  740. #define MAX98926_ADC_IMON_EN_SHIFT 1
  741. #define MAX98926_ADC_IMON_EN_WIDTH 1
  742. #define MAX98926_ADC_VMON_EN_MASK (1<<0)
  743. #define MAX98926_ADC_VMON_EN_SHIFT 0
  744. #define MAX98926_ADC_VMON_EN_WIDTH 1
  745. /* MAX98926_R037_CONFIGURATION */
  746. #define MAX98926_BST_VOUT_MASK (0x0F<<4)
  747. #define MAX98926_BST_VOUT_SHIFT 4
  748. #define MAX98926_BST_VOUT_WIDTH 4
  749. #define MAX98926_THERMWARN_LEVEL_MASK (0x03<<2)
  750. #define MAX98926_THERMWARN_LEVEL_SHIFT 2
  751. #define MAX98926_THERMWARN_LEVEL_WIDTH 2
  752. #define MAX98926_WATCH_TIME_MASK (0x03<<0)
  753. #define MAX98926_WATCH_TIME_SHIFT 0
  754. #define MAX98926_WATCH_TIME_WIDTH 2
  755. /* MAX98926_R038_GLOBAL_ENABLE */
  756. #define MAX98926_EN_MASK (1<<7)
  757. #define MAX98926_EN_SHIFT 7
  758. #define MAX98926_EN_WIDTH 1
  759. /* MAX98926_R03A_BOOST_LIMITER */
  760. #define MAX98926_BST_ILIM_MASK (0xF<<4)
  761. #define MAX98926_BST_ILIM_SHIFT 4
  762. #define MAX98926_BST_ILIM_WIDTH 4
  763. /* MAX98926_R0FF_VERSION */
  764. #define MAX98926_REV_ID_MASK (0xFF<<0)
  765. #define MAX98926_REV_ID_SHIFT 0
  766. #define MAX98926_REV_ID_WIDTH 8
  767. struct max98926_priv {
  768. struct regmap *regmap;
  769. struct snd_soc_component *component;
  770. unsigned int sysclk;
  771. unsigned int v_slot;
  772. unsigned int i_slot;
  773. unsigned int ch_size;
  774. unsigned int interleave_mode;
  775. };
  776. #endif