max98925.h 31 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * max98925.h -- MAX98925 ALSA SoC Audio driver
  4. *
  5. * Copyright 2013-2015 Maxim Integrated Products
  6. */
  7. #ifndef _MAX98925_H
  8. #define _MAX98925_H
  9. #define MAX98925_VERSION 0x51
  10. #define MAX98925_VERSION1 0x80
  11. #define MAX98925_VBAT_DATA 0x00
  12. #define MAX98925_VBST_DATA 0x01
  13. #define MAX98925_LIVE_STATUS0 0x02
  14. #define MAX98925_LIVE_STATUS1 0x03
  15. #define MAX98925_LIVE_STATUS2 0x04
  16. #define MAX98925_STATE0 0x05
  17. #define MAX98925_STATE1 0x06
  18. #define MAX98925_STATE2 0x07
  19. #define MAX98925_FLAG0 0x08
  20. #define MAX98925_FLAG1 0x09
  21. #define MAX98925_FLAG2 0x0A
  22. #define MAX98925_IRQ_ENABLE0 0x0B
  23. #define MAX98925_IRQ_ENABLE1 0x0C
  24. #define MAX98925_IRQ_ENABLE2 0x0D
  25. #define MAX98925_IRQ_CLEAR0 0x0E
  26. #define MAX98925_IRQ_CLEAR1 0x0F
  27. #define MAX98925_IRQ_CLEAR2 0x10
  28. #define MAX98925_MAP0 0x11
  29. #define MAX98925_MAP1 0x12
  30. #define MAX98925_MAP2 0x13
  31. #define MAX98925_MAP3 0x14
  32. #define MAX98925_MAP4 0x15
  33. #define MAX98925_MAP5 0x16
  34. #define MAX98925_MAP6 0x17
  35. #define MAX98925_MAP7 0x18
  36. #define MAX98925_MAP8 0x19
  37. #define MAX98925_DAI_CLK_MODE1 0x1A
  38. #define MAX98925_DAI_CLK_MODE2 0x1B
  39. #define MAX98925_DAI_CLK_DIV_M_MSBS 0x1C
  40. #define MAX98925_DAI_CLK_DIV_M_LSBS 0x1D
  41. #define MAX98925_DAI_CLK_DIV_N_MSBS 0x1E
  42. #define MAX98925_DAI_CLK_DIV_N_LSBS 0x1F
  43. #define MAX98925_FORMAT 0x20
  44. #define MAX98925_TDM_SLOT_SELECT 0x21
  45. #define MAX98925_DOUT_CFG_VMON 0x22
  46. #define MAX98925_DOUT_CFG_IMON 0x23
  47. #define MAX98925_DOUT_CFG_VBAT 0x24
  48. #define MAX98925_DOUT_CFG_VBST 0x25
  49. #define MAX98925_DOUT_CFG_FLAG 0x26
  50. #define MAX98925_DOUT_HIZ_CFG1 0x27
  51. #define MAX98925_DOUT_HIZ_CFG2 0x28
  52. #define MAX98925_DOUT_HIZ_CFG3 0x29
  53. #define MAX98925_DOUT_HIZ_CFG4 0x2A
  54. #define MAX98925_DOUT_DRV_STRENGTH 0x2B
  55. #define MAX98925_FILTERS 0x2C
  56. #define MAX98925_GAIN 0x2D
  57. #define MAX98925_GAIN_RAMPING 0x2E
  58. #define MAX98925_SPK_AMP 0x2F
  59. #define MAX98925_THRESHOLD 0x30
  60. #define MAX98925_ALC_ATTACK 0x31
  61. #define MAX98925_ALC_ATTEN_RLS 0x32
  62. #define MAX98925_ALC_HOLD_RLS 0x33
  63. #define MAX98925_ALC_CONFIGURATION 0x34
  64. #define MAX98925_BOOST_CONVERTER 0x35
  65. #define MAX98925_BLOCK_ENABLE 0x36
  66. #define MAX98925_CONFIGURATION 0x37
  67. #define MAX98925_GLOBAL_ENABLE 0x38
  68. #define MAX98925_BOOST_LIMITER 0x3A
  69. #define MAX98925_REV_VERSION 0xFF
  70. #define MAX98925_REG_CNT (MAX98925_R03A_BOOST_LIMITER+1)
  71. /* MAX98925 Register Bit Fields */
  72. /* MAX98925_R002_LIVE_STATUS0 */
  73. #define M98925_THERMWARN_STATUS_MASK (1<<3)
  74. #define M98925_THERMWARN_STATUS_SHIFT 3
  75. #define M98925_THERMWARN_STATUS_WIDTH 1
  76. #define M98925_THERMSHDN_STATUS_MASK (1<<1)
  77. #define M98925_THERMSHDN_STATUS_SHIFT 1
  78. #define M98925_THERMSHDN_STATUS_WIDTH 1
  79. /* MAX98925_R003_LIVE_STATUS1 */
  80. #define M98925_SPKCURNT_STATUS_MASK (1<<5)
  81. #define M98925_SPKCURNT_STATUS_SHIFT 5
  82. #define M98925_SPKCURNT_STATUS_WIDTH 1
  83. #define M98925_WATCHFAIL_STATUS_MASK (1<<4)
  84. #define M98925_WATCHFAIL_STATUS_SHIFT 4
  85. #define M98925_WATCHFAIL_STATUS_WIDTH 1
  86. #define M98925_ALCINFH_STATUS_MASK (1<<3)
  87. #define M98925_ALCINFH_STATUS_SHIFT 3
  88. #define M98925_ALCINFH_STATUS_WIDTH 1
  89. #define M98925_ALCACT_STATUS_MASK (1<<2)
  90. #define M98925_ALCACT_STATUS_SHIFT 2
  91. #define M98925_ALCACT_STATUS_WIDTH 1
  92. #define M98925_ALCMUT_STATUS_MASK (1<<1)
  93. #define M98925_ALCMUT_STATUS_SHIFT 1
  94. #define M98925_ALCMUT_STATUS_WIDTH 1
  95. #define M98925_ACLP_STATUS_MASK (1<<0)
  96. #define M98925_ACLP_STATUS_SHIFT 0
  97. #define M98925_ACLP_STATUS_WIDTH 1
  98. /* MAX98925_R004_LIVE_STATUS2 */
  99. #define M98925_SLOTOVRN_STATUS_MASK (1<<6)
  100. #define M98925_SLOTOVRN_STATUS_SHIFT 6
  101. #define M98925_SLOTOVRN_STATUS_WIDTH 1
  102. #define M98925_INVALSLOT_STATUS_MASK (1<<5)
  103. #define M98925_INVALSLOT_STATUS_SHIFT 5
  104. #define M98925_INVALSLOT_STATUS_WIDTH 1
  105. #define M98925_SLOTCNFLT_STATUS_MASK (1<<4)
  106. #define M98925_SLOTCNFLT_STATUS_SHIFT 4
  107. #define M98925_SLOTCNFLT_STATUS_WIDTH 1
  108. #define M98925_VBSTOVFL_STATUS_MASK (1<<3)
  109. #define M98925_VBSTOVFL_STATUS_SHIFT 3
  110. #define M98925_VBSTOVFL_STATUS_WIDTH 1
  111. #define M98925_VBATOVFL_STATUS_MASK (1<<2)
  112. #define M98925_VBATOVFL_STATUS_SHIFT 2
  113. #define M98925_VBATOVFL_STATUS_WIDTH 1
  114. #define M98925_IMONOVFL_STATUS_MASK (1<<1)
  115. #define M98925_IMONOVFL_STATUS_SHIFT 1
  116. #define M98925_IMONOVFL_STATUS_WIDTH 1
  117. #define M98925_VMONOVFL_STATUS_MASK (1<<0)
  118. #define M98925_VMONOVFL_STATUS_SHIFT 0
  119. #define M98925_VMONOVFL_STATUS_WIDTH 1
  120. /* MAX98925_R005_STATE0 */
  121. #define M98925_THERMWARN_END_STATE_MASK (1<<3)
  122. #define M98925_THERMWARN_END_STATE_SHIFT 3
  123. #define M98925_THERMWARN_END_STATE_WIDTH 1
  124. #define M98925_THERMWARN_BGN_STATE_MASK (1<<2)
  125. #define M98925_THERMWARN_BGN_STATE_SHIFT 1
  126. #define M98925_THERMWARN_BGN_STATE_WIDTH 1
  127. #define M98925_THERMSHDN_END_STATE_MASK (1<<1)
  128. #define M98925_THERMSHDN_END_STATE_SHIFT 1
  129. #define M98925_THERMSHDN_END_STATE_WIDTH 1
  130. #define M98925_THERMSHDN_BGN_STATE_MASK (1<<0)
  131. #define M98925_THERMSHDN_BGN_STATE_SHIFT 0
  132. #define M98925_THERMSHDN_BGN_STATE_WIDTH 1
  133. /* MAX98925_R006_STATE1 */
  134. #define M98925_SPRCURNT_STATE_MASK (1<<5)
  135. #define M98925_SPRCURNT_STATE_SHIFT 5
  136. #define M98925_SPRCURNT_STATE_WIDTH 1
  137. #define M98925_WATCHFAIL_STATE_MASK (1<<4)
  138. #define M98925_WATCHFAIL_STATE_SHIFT 4
  139. #define M98925_WATCHFAIL_STATE_WIDTH 1
  140. #define M98925_ALCINFH_STATE_MASK (1<<3)
  141. #define M98925_ALCINFH_STATE_SHIFT 3
  142. #define M98925_ALCINFH_STATE_WIDTH 1
  143. #define M98925_ALCACT_STATE_MASK (1<<2)
  144. #define M98925_ALCACT_STATE_SHIFT 2
  145. #define M98925_ALCACT_STATE_WIDTH 1
  146. #define M98925_ALCMUT_STATE_MASK (1<<1)
  147. #define M98925_ALCMUT_STATE_SHIFT 1
  148. #define M98925_ALCMUT_STATE_WIDTH 1
  149. #define M98925_ALCP_STATE_MASK (1<<0)
  150. #define M98925_ALCP_STATE_SHIFT 0
  151. #define M98925_ALCP_STATE_WIDTH 1
  152. /* MAX98925_R007_STATE2 */
  153. #define M98925_SLOTOVRN_STATE_MASK (1<<6)
  154. #define M98925_SLOTOVRN_STATE_SHIFT 6
  155. #define M98925_SLOTOVRN_STATE_WIDTH 1
  156. #define M98925_INVALSLOT_STATE_MASK (1<<5)
  157. #define M98925_INVALSLOT_STATE_SHIFT 5
  158. #define M98925_INVALSLOT_STATE_WIDTH 1
  159. #define M98925_SLOTCNFLT_STATE_MASK (1<<4)
  160. #define M98925_SLOTCNFLT_STATE_SHIFT 4
  161. #define M98925_SLOTCNFLT_STATE_WIDTH 1
  162. #define M98925_VBSTOVFL_STATE_MASK (1<<3)
  163. #define M98925_VBSTOVFL_STATE_SHIFT 3
  164. #define M98925_VBSTOVFL_STATE_WIDTH 1
  165. #define M98925_VBATOVFL_STATE_MASK (1<<2)
  166. #define M98925_VBATOVFL_STATE_SHIFT 2
  167. #define M98925_VBATOVFL_STATE_WIDTH 1
  168. #define M98925_IMONOVFL_STATE_MASK (1<<1)
  169. #define M98925_IMONOVFL_STATE_SHIFT 1
  170. #define M98925_IMONOVFL_STATE_WIDTH 1
  171. #define M98925_VMONOVFL_STATE_MASK (1<<0)
  172. #define M98925_VMONOVFL_STATE_SHIFT 0
  173. #define M98925_VMONOVFL_STATE_WIDTH 1
  174. /* MAX98925_R008_FLAG0 */
  175. #define M98925_THERMWARN_END_FLAG_MASK (1<<3)
  176. #define M98925_THERMWARN_END_FLAG_SHIFT 3
  177. #define M98925_THERMWARN_END_FLAG_WIDTH 1
  178. #define M98925_THERMWARN_BGN_FLAG_MASK (1<<2)
  179. #define M98925_THERMWARN_BGN_FLAG_SHIFT 2
  180. #define M98925_THERMWARN_BGN_FLAG_WIDTH 1
  181. #define M98925_THERMSHDN_END_FLAG_MASK (1<<1)
  182. #define M98925_THERMSHDN_END_FLAG_SHIFT 1
  183. #define M98925_THERMSHDN_END_FLAG_WIDTH 1
  184. #define M98925_THERMSHDN_BGN_FLAG_MASK (1<<0)
  185. #define M98925_THERMSHDN_BGN_FLAG_SHIFT 0
  186. #define M98925_THERMSHDN_BGN_FLAG_WIDTH 1
  187. /* MAX98925_R009_FLAG1 */
  188. #define M98925_SPKCURNT_FLAG_MASK (1<<5)
  189. #define M98925_SPKCURNT_FLAG_SHIFT 5
  190. #define M98925_SPKCURNT_FLAG_WIDTH 1
  191. #define M98925_WATCHFAIL_FLAG_MASK (1<<4)
  192. #define M98925_WATCHFAIL_FLAG_SHIFT 4
  193. #define M98925_WATCHFAIL_FLAG_WIDTH 1
  194. #define M98925_ALCINFH_FLAG_MASK (1<<3)
  195. #define M98925_ALCINFH_FLAG_SHIFT 3
  196. #define M98925_ALCINFH_FLAG_WIDTH 1
  197. #define M98925_ALCACT_FLAG_MASK (1<<2)
  198. #define M98925_ALCACT_FLAG_SHIFT 2
  199. #define M98925_ALCACT_FLAG_WIDTH 1
  200. #define M98925_ALCMUT_FLAG_MASK (1<<1)
  201. #define M98925_ALCMUT_FLAG_SHIFT 1
  202. #define M98925_ALCMUT_FLAG_WIDTH 1
  203. #define M98925_ALCP_FLAG_MASK (1<<0)
  204. #define M98925_ALCP_FLAG_SHIFT 0
  205. #define M98925_ALCP_FLAG_WIDTH 1
  206. /* MAX98925_R00A_FLAG2 */
  207. #define M98925_SLOTOVRN_FLAG_MASK (1<<6)
  208. #define M98925_SLOTOVRN_FLAG_SHIFT 6
  209. #define M98925_SLOTOVRN_FLAG_WIDTH 1
  210. #define M98925_INVALSLOT_FLAG_MASK (1<<5)
  211. #define M98925_INVALSLOT_FLAG_SHIFT 5
  212. #define M98925_INVALSLOT_FLAG_WIDTH 1
  213. #define M98925_SLOTCNFLT_FLAG_MASK (1<<4)
  214. #define M98925_SLOTCNFLT_FLAG_SHIFT 4
  215. #define M98925_SLOTCNFLT_FLAG_WIDTH 1
  216. #define M98925_VBSTOVFL_FLAG_MASK (1<<3)
  217. #define M98925_VBSTOVFL_FLAG_SHIFT 3
  218. #define M98925_VBSTOVFL_FLAG_WIDTH 1
  219. #define M98925_VBATOVFL_FLAG_MASK (1<<2)
  220. #define M98925_VBATOVFL_FLAG_SHIFT 2
  221. #define M98925_VBATOVFL_FLAG_WIDTH 1
  222. #define M98925_IMONOVFL_FLAG_MASK (1<<1)
  223. #define M98925_IMONOVFL_FLAG_SHIFT 1
  224. #define M98925_IMONOVFL_FLAG_WIDTH 1
  225. #define M98925_VMONOVFL_FLAG_MASK (1<<0)
  226. #define M98925_VMONOVFL_FLAG_SHIFT 0
  227. #define M98925_VMONOVFL_FLAG_WIDTH 1
  228. /* MAX98925_R00B_IRQ_ENABLE0 */
  229. #define M98925_THERMWARN_END_EN_MASK (1<<3)
  230. #define M98925_THERMWARN_END_EN_SHIFT 3
  231. #define M98925_THERMWARN_END_EN_WIDTH 1
  232. #define M98925_THERMWARN_BGN_EN_MASK (1<<2)
  233. #define M98925_THERMWARN_BGN_EN_SHIFT 2
  234. #define M98925_THERMWARN_BGN_EN_WIDTH 1
  235. #define M98925_THERMSHDN_END_EN_MASK (1<<1)
  236. #define M98925_THERMSHDN_END_EN_SHIFT 1
  237. #define M98925_THERMSHDN_END_EN_WIDTH 1
  238. #define M98925_THERMSHDN_BGN_EN_MASK (1<<0)
  239. #define M98925_THERMSHDN_BGN_EN_SHIFT 0
  240. #define M98925_THERMSHDN_BGN_EN_WIDTH 1
  241. /* MAX98925_R00C_IRQ_ENABLE1 */
  242. #define M98925_SPKCURNT_EN_MASK (1<<5)
  243. #define M98925_SPKCURNT_EN_SHIFT 5
  244. #define M98925_SPKCURNT_EN_WIDTH 1
  245. #define M98925_WATCHFAIL_EN_MASK (1<<4)
  246. #define M98925_WATCHFAIL_EN_SHIFT 4
  247. #define M98925_WATCHFAIL_EN_WIDTH 1
  248. #define M98925_ALCINFH_EN_MASK (1<<3)
  249. #define M98925_ALCINFH_EN_SHIFT 3
  250. #define M98925_ALCINFH_EN_WIDTH 1
  251. #define M98925_ALCACT_EN_MASK (1<<2)
  252. #define M98925_ALCACT_EN_SHIFT 2
  253. #define M98925_ALCACT_EN_WIDTH 1
  254. #define M98925_ALCMUT_EN_MASK (1<<1)
  255. #define M98925_ALCMUT_EN_SHIFT 1
  256. #define M98925_ALCMUT_EN_WIDTH 1
  257. #define M98925_ALCP_EN_MASK (1<<0)
  258. #define M98925_ALCP_EN_SHIFT 0
  259. #define M98925_ALCP_EN_WIDTH 1
  260. /* MAX98925_R00D_IRQ_ENABLE2 */
  261. #define M98925_SLOTOVRN_EN_MASK (1<<6)
  262. #define M98925_SLOTOVRN_EN_SHIFT 6
  263. #define M98925_SLOTOVRN_EN_WIDTH 1
  264. #define M98925_INVALSLOT_EN_MASK (1<<5)
  265. #define M98925_INVALSLOT_EN_SHIFT 5
  266. #define M98925_INVALSLOT_EN_WIDTH 1
  267. #define M98925_SLOTCNFLT_EN_MASK (1<<4)
  268. #define M98925_SLOTCNFLT_EN_SHIFT 4
  269. #define M98925_SLOTCNFLT_EN_WIDTH 1
  270. #define M98925_VBSTOVFL_EN_MASK (1<<3)
  271. #define M98925_VBSTOVFL_EN_SHIFT 3
  272. #define M98925_VBSTOVFL_EN_WIDTH 1
  273. #define M98925_VBATOVFL_EN_MASK (1<<2)
  274. #define M98925_VBATOVFL_EN_SHIFT 2
  275. #define M98925_VBATOVFL_EN_WIDTH 1
  276. #define M98925_IMONOVFL_EN_MASK (1<<1)
  277. #define M98925_IMONOVFL_EN_SHIFT 1
  278. #define M98925_IMONOVFL_EN_WIDTH 1
  279. #define M98925_VMONOVFL_EN_MASK (1<<0)
  280. #define M98925_VMONOVFL_EN_SHIFT 0
  281. #define M98925_VMONOVFL_EN_WIDTH 1
  282. /* MAX98925_R00E_IRQ_CLEAR0 */
  283. #define M98925_THERMWARN_END_CLR_MASK (1<<3)
  284. #define M98925_THERMWARN_END_CLR_SHIFT 3
  285. #define M98925_THERMWARN_END_CLR_WIDTH 1
  286. #define M98925_THERMWARN_BGN_CLR_MASK (1<<2)
  287. #define M98925_THERMWARN_BGN_CLR_SHIFT 2
  288. #define M98925_THERMWARN_BGN_CLR_WIDTH 1
  289. #define M98925_THERMSHDN_END_CLR_MASK (1<<1)
  290. #define M98925_THERMSHDN_END_CLR_SHIFT 1
  291. #define M98925_THERMSHDN_END_CLR_WIDTH 1
  292. #define M98925_THERMSHDN_BGN_CLR_MASK (1<<0)
  293. #define M98925_THERMSHDN_BGN_CLR_SHIFT 0
  294. #define M98925_THERMSHDN_BGN_CLR_WIDTH 1
  295. /* MAX98925_R00F_IRQ_CLEAR1 */
  296. #define M98925_SPKCURNT_CLR_MASK (1<<5)
  297. #define M98925_SPKCURNT_CLR_SHIFT 5
  298. #define M98925_SPKCURNT_CLR_WIDTH 1
  299. #define M98925_WATCHFAIL_CLR_MASK (1<<4)
  300. #define M98925_WATCHFAIL_CLR_SHIFT 4
  301. #define M98925_WATCHFAIL_CLR_WIDTH 1
  302. #define M98925_ALCINFH_CLR_MASK (1<<3)
  303. #define M98925_ALCINFH_CLR_SHIFT 3
  304. #define M98925_ALCINFH_CLR_WIDTH 1
  305. #define M98925_ALCACT_CLR_MASK (1<<2)
  306. #define M98925_ALCACT_CLR_SHIFT 2
  307. #define M98925_ALCACT_CLR_WIDTH 1
  308. #define M98925_ALCMUT_CLR_MASK (1<<1)
  309. #define M98925_ALCMUT_CLR_SHIFT 1
  310. #define M98925_ALCMUT_CLR_WIDTH 1
  311. #define M98925_ALCP_CLR_MASK (1<<0)
  312. #define M98925_ALCP_CLR_SHIFT 0
  313. #define M98925_ALCP_CLR_WIDTH 1
  314. /* MAX98925_R010_IRQ_CLEAR2 */
  315. #define M98925_SLOTOVRN_CLR_MASK (1<<6)
  316. #define M98925_SLOTOVRN_CLR_SHIFT 6
  317. #define M98925_SLOTOVRN_CLR_WIDTH 1
  318. #define M98925_INVALSLOT_CLR_MASK (1<<5)
  319. #define M98925_INVALSLOT_CLR_SHIFT 5
  320. #define M98925_INVALSLOT_CLR_WIDTH 1
  321. #define M98925_SLOTCNFLT_CLR_MASK (1<<4)
  322. #define M98925_SLOTCNFLT_CLR_SHIFT 4
  323. #define M98925_SLOTCNFLT_CLR_WIDTH 1
  324. #define M98925_VBSTOVFL_CLR_MASK (1<<3)
  325. #define M98925_VBSTOVFL_CLR_SHIFT 3
  326. #define M98925_VBSTOVFL_CLR_WIDTH 1
  327. #define M98925_VBATOVFL_CLR_MASK (1<<2)
  328. #define M98925_VBATOVFL_CLR_SHIFT 2
  329. #define M98925_VBATOVFL_CLR_WIDTH 1
  330. #define M98925_IMONOVFL_CLR_MASK (1<<1)
  331. #define M98925_IMONOVFL_CLR_SHIFT 1
  332. #define M98925_IMONOVFL_CLR_WIDTH 1
  333. #define M98925_VMONOVFL_CLR_MASK (1<<0)
  334. #define M98925_VMONOVFL_CLR_SHIFT 0
  335. #define M98925_VMONOVFL_CLR_WIDTH 1
  336. /* MAX98925_R011_MAP0 */
  337. #define M98925_ER_THERMWARN_EN_MASK (1<<7)
  338. #define M98925_ER_THERMWARN_EN_SHIFT 7
  339. #define M98925_ER_THERMWARN_EN_WIDTH 1
  340. #define M98925_ER_THERMWARN_MAP_MASK (0x07<<4)
  341. #define M98925_ER_THERMWARN_MAP_SHIFT 4
  342. #define M98925_ER_THERMWARN_MAP_WIDTH 3
  343. /* MAX98925_R012_MAP1 */
  344. #define M98925_ER_ALCMUT_EN_MASK (1<<7)
  345. #define M98925_ER_ALCMUT_EN_SHIFT 7
  346. #define M98925_ER_ALCMUT_EN_WIDTH 1
  347. #define M98925_ER_ALCMUT_MAP_MASK (0x07<<4)
  348. #define M98925_ER_ALCMUT_MAP_SHIFT 4
  349. #define M98925_ER_ALCMUT_MAP_WIDTH 3
  350. #define M98925_ER_ALCP_EN_MASK (1<<3)
  351. #define M98925_ER_ALCP_EN_SHIFT 3
  352. #define M98925_ER_ALCP_EN_WIDTH 1
  353. #define M98925_ER_ALCP_MAP_MASK (0x07<<0)
  354. #define M98925_ER_ALCP_MAP_SHIFT 0
  355. #define M98925_ER_ALCP_MAP_WIDTH 3
  356. /* MAX98925_R013_MAP2 */
  357. #define M98925_ER_ALCINFH_EN_MASK (1<<7)
  358. #define M98925_ER_ALCINFH_EN_SHIFT 7
  359. #define M98925_ER_ALCINFH_EN_WIDTH 1
  360. #define M98925_ER_ALCINFH_MAP_MASK (0x07<<4)
  361. #define M98925_ER_ALCINFH_MAP_SHIFT 4
  362. #define M98925_ER_ALCINFH_MAP_WIDTH 3
  363. #define M98925_ER_ALCACT_EN_MASK (1<<3)
  364. #define M98925_ER_ALCACT_EN_SHIFT 3
  365. #define M98925_ER_ALCACT_EN_WIDTH 1
  366. #define M98925_ER_ALCACT_MAP_MASK (0x07<<0)
  367. #define M98925_ER_ALCACT_MAP_SHIFT 0
  368. #define M98925_ER_ALCACT_MAP_WIDTH 3
  369. /* MAX98925_R014_MAP3 */
  370. #define M98925_ER_SPKCURNT_EN_MASK (1<<7)
  371. #define M98925_ER_SPKCURNT_EN_SHIFT 7
  372. #define M98925_ER_SPKCURNT_EN_WIDTH 1
  373. #define M98925_ER_SPKCURNT_MAP_MASK (0x07<<4)
  374. #define M98925_ER_SPKCURNT_MAP_SHIFT 4
  375. #define M98925_ER_SPKCURNT_MAP_WIDTH 3
  376. /* MAX98925_R015_MAP4 */
  377. /* RESERVED */
  378. /* MAX98925_R016_MAP5 */
  379. #define M98925_ER_IMONOVFL_EN_MASK (1<<7)
  380. #define M98925_ER_IMONOVFL_EN_SHIFT 7
  381. #define M98925_ER_IMONOVFL_EN_WIDTH 1
  382. #define M98925_ER_IMONOVFL_MAP_MASK (0x07<<4)
  383. #define M98925_ER_IMONOVFL_MAP_SHIFT 4
  384. #define M98925_ER_IMONOVFL_MAP_WIDTH 3
  385. #define M98925_ER_VMONOVFL_EN_MASK (1<<3)
  386. #define M98925_ER_VMONOVFL_EN_SHIFT 3
  387. #define M98925_ER_VMONOVFL_EN_WIDTH 1
  388. #define M98925_ER_VMONOVFL_MAP_MASK (0x07<<0)
  389. #define M98925_ER_VMONOVFL_MAP_SHIFT 0
  390. #define M98925_ER_VMONOVFL_MAP_WIDTH 3
  391. /* MAX98925_R017_MAP6 */
  392. #define M98925_ER_VBSTOVFL_EN_MASK (1<<7)
  393. #define M98925_ER_VBSTOVFL_EN_SHIFT 7
  394. #define M98925_ER_VBSTOVFL_EN_WIDTH 1
  395. #define M98925_ER_VBSTOVFL_MAP_MASK (0x07<<4)
  396. #define M98925_ER_VBSTOVFL_MAP_SHIFT 4
  397. #define M98925_ER_VBSTOVFL_MAP_WIDTH 3
  398. #define M98925_ER_VBATOVFL_EN_MASK (1<<3)
  399. #define M98925_ER_VBATOVFL_EN_SHIFT 3
  400. #define M98925_ER_VBATOVFL_EN_WIDTH 1
  401. #define M98925_ER_VBATOVFL_MAP_MASK (0x07<<0)
  402. #define M98925_ER_VBATOVFL_MAP_SHIFT 0
  403. #define M98925_ER_VBATOVFL_MAP_WIDTH 3
  404. /* MAX98925_R018_MAP7 */
  405. #define M98925_ER_INVALSLOT_EN_MASK (1<<7)
  406. #define M98925_ER_INVALSLOT_EN_SHIFT 7
  407. #define M98925_ER_INVALSLOT_EN_WIDTH 1
  408. #define M98925_ER_INVALSLOT_MAP_MASK (0x07<<4)
  409. #define M98925_ER_INVALSLOT_MAP_SHIFT 4
  410. #define M98925_ER_INVALSLOT_MAP_WIDTH 3
  411. #define M98925_ER_SLOTCNFLT_EN_MASK (1<<3)
  412. #define M98925_ER_SLOTCNFLT_EN_SHIFT 3
  413. #define M98925_ER_SLOTCNFLT_EN_WIDTH 1
  414. #define M98925_ER_SLOTCNFLT_MAP_MASK (0x07<<0)
  415. #define M98925_ER_SLOTCNFLT_MAP_SHIFT 0
  416. #define M98925_ER_SLOTCNFLT_MAP_WIDTH 3
  417. /* MAX98925_R019_MAP8 */
  418. #define M98925_ER_SLOTOVRN_EN_MASK (1<<3)
  419. #define M98925_ER_SLOTOVRN_EN_SHIFT 3
  420. #define M98925_ER_SLOTOVRN_EN_WIDTH 1
  421. #define M98925_ER_SLOTOVRN_MAP_MASK (0x07<<0)
  422. #define M98925_ER_SLOTOVRN_MAP_SHIFT 0
  423. #define M98925_ER_SLOTOVRN_MAP_WIDTH 3
  424. /* MAX98925_R01A_DAI_CLK_MODE1 */
  425. #define M98925_DAI_CLK_SOURCE_MASK (1<<6)
  426. #define M98925_DAI_CLK_SOURCE_SHIFT 6
  427. #define M98925_DAI_CLK_SOURCE_WIDTH 1
  428. #define M98925_MDLL_MULT_MASK (0x0F<<0)
  429. #define M98925_MDLL_MULT_SHIFT 0
  430. #define M98925_MDLL_MULT_WIDTH 4
  431. #define M98925_MDLL_MULT_MCLKx8 6
  432. #define M98925_MDLL_MULT_MCLKx16 8
  433. /* MAX98925_R01B_DAI_CLK_MODE2 */
  434. #define M98925_DAI_SR_MASK (0x0F<<4)
  435. #define M98925_DAI_SR_SHIFT 4
  436. #define M98925_DAI_SR_WIDTH 4
  437. #define M98925_DAI_MAS_MASK (1<<3)
  438. #define M98925_DAI_MAS_SHIFT 3
  439. #define M98925_DAI_MAS_WIDTH 1
  440. #define M98925_DAI_BSEL_MASK (0x07<<0)
  441. #define M98925_DAI_BSEL_SHIFT 0
  442. #define M98925_DAI_BSEL_WIDTH 3
  443. #define M98925_DAI_BSEL_32 (0 << M98925_DAI_BSEL_SHIFT)
  444. #define M98925_DAI_BSEL_48 (1 << M98925_DAI_BSEL_SHIFT)
  445. #define M98925_DAI_BSEL_64 (2 << M98925_DAI_BSEL_SHIFT)
  446. #define M98925_DAI_BSEL_256 (6 << M98925_DAI_BSEL_SHIFT)
  447. /* MAX98925_R01C_DAI_CLK_DIV_M_MSBS */
  448. #define M98925_DAI_M_MSBS_MASK (0xFF<<0)
  449. #define M98925_DAI_M_MSBS_SHIFT 0
  450. #define M98925_DAI_M_MSBS_WIDTH 8
  451. /* MAX98925_R01D_DAI_CLK_DIV_M_LSBS */
  452. #define M98925_DAI_M_LSBS_MASK (0xFF<<0)
  453. #define M98925_DAI_M_LSBS_SHIFT 0
  454. #define M98925_DAI_M_LSBS_WIDTH 8
  455. /* MAX98925_R01E_DAI_CLK_DIV_N_MSBS */
  456. #define M98925_DAI_N_MSBS_MASK (0x7F<<0)
  457. #define M98925_DAI_N_MSBS_SHIFT 0
  458. #define M98925_DAI_N_MSBS_WIDTH 7
  459. /* MAX98925_R01F_DAI_CLK_DIV_N_LSBS */
  460. #define M98925_DAI_N_LSBS_MASK (0xFF<<0)
  461. #define M98925_DAI_N_LSBS_SHIFT 0
  462. #define M98925_DAI_N_LSBS_WIDTH 8
  463. /* MAX98925_R020_FORMAT */
  464. #define M98925_DAI_CHANSZ_MASK (0x03<<6)
  465. #define M98925_DAI_CHANSZ_SHIFT 6
  466. #define M98925_DAI_CHANSZ_WIDTH 2
  467. #define M98925_DAI_EXTBCLK_HIZ_MASK (1<<4)
  468. #define M98925_DAI_EXTBCLK_HIZ_SHIFT 4
  469. #define M98925_DAI_EXTBCLK_HIZ_WIDTH 1
  470. #define M98925_DAI_WCI_MASK (1<<3)
  471. #define M98925_DAI_WCI_SHIFT 3
  472. #define M98925_DAI_WCI_WIDTH 1
  473. #define M98925_DAI_BCI_MASK (1<<2)
  474. #define M98925_DAI_BCI_SHIFT 2
  475. #define M98925_DAI_BCI_WIDTH 1
  476. #define M98925_DAI_DLY_MASK (1<<1)
  477. #define M98925_DAI_DLY_SHIFT 1
  478. #define M98925_DAI_DLY_WIDTH 1
  479. #define M98925_DAI_TDM_MASK (1<<0)
  480. #define M98925_DAI_TDM_SHIFT 0
  481. #define M98925_DAI_TDM_WIDTH 1
  482. #define M98925_DAI_CHANSZ_16 (1 << M98925_DAI_CHANSZ_SHIFT)
  483. #define M98925_DAI_CHANSZ_24 (2 << M98925_DAI_CHANSZ_SHIFT)
  484. #define M98925_DAI_CHANSZ_32 (3 << M98925_DAI_CHANSZ_SHIFT)
  485. /* MAX98925_R021_TDM_SLOT_SELECT */
  486. #define M98925_DAI_DO_EN_MASK (1<<7)
  487. #define M98925_DAI_DO_EN_SHIFT 7
  488. #define M98925_DAI_DO_EN_WIDTH 1
  489. #define M98925_DAI_DIN_EN_MASK (1<<6)
  490. #define M98925_DAI_DIN_EN_SHIFT 6
  491. #define M98925_DAI_DIN_EN_WIDTH 1
  492. #define M98925_DAI_INR_SOURCE_MASK (0x07<<3)
  493. #define M98925_DAI_INR_SOURCE_SHIFT 3
  494. #define M98925_DAI_INR_SOURCE_WIDTH 3
  495. #define M98925_DAI_INL_SOURCE_MASK (0x07<<0)
  496. #define M98925_DAI_INL_SOURCE_SHIFT 0
  497. #define M98925_DAI_INL_SOURCE_WIDTH 3
  498. /* MAX98925_R022_DOUT_CFG_VMON */
  499. #define M98925_DAI_VMON_EN_MASK (1<<5)
  500. #define M98925_DAI_VMON_EN_SHIFT 5
  501. #define M98925_DAI_VMON_EN_WIDTH 1
  502. #define M98925_DAI_VMON_SLOT_MASK (0x1F<<0)
  503. #define M98925_DAI_VMON_SLOT_SHIFT 0
  504. #define M98925_DAI_VMON_SLOT_WIDTH 5
  505. #define M98925_DAI_VMON_SLOT_00_01 (0 << M98925_DAI_VMON_SLOT_SHIFT)
  506. #define M98925_DAI_VMON_SLOT_01_02 (1 << M98925_DAI_VMON_SLOT_SHIFT)
  507. #define M98925_DAI_VMON_SLOT_02_03 (2 << M98925_DAI_VMON_SLOT_SHIFT)
  508. #define M98925_DAI_VMON_SLOT_03_04 (3 << M98925_DAI_VMON_SLOT_SHIFT)
  509. #define M98925_DAI_VMON_SLOT_04_05 (4 << M98925_DAI_VMON_SLOT_SHIFT)
  510. #define M98925_DAI_VMON_SLOT_05_06 (5 << M98925_DAI_VMON_SLOT_SHIFT)
  511. #define M98925_DAI_VMON_SLOT_06_07 (6 << M98925_DAI_VMON_SLOT_SHIFT)
  512. #define M98925_DAI_VMON_SLOT_07_08 (7 << M98925_DAI_VMON_SLOT_SHIFT)
  513. #define M98925_DAI_VMON_SLOT_08_09 (8 << M98925_DAI_VMON_SLOT_SHIFT)
  514. #define M98925_DAI_VMON_SLOT_09_0A (9 << M98925_DAI_VMON_SLOT_SHIFT)
  515. #define M98925_DAI_VMON_SLOT_0A_0B (10 << M98925_DAI_VMON_SLOT_SHIFT)
  516. #define M98925_DAI_VMON_SLOT_0B_0C (11 << M98925_DAI_VMON_SLOT_SHIFT)
  517. #define M98925_DAI_VMON_SLOT_0C_0D (12 << M98925_DAI_VMON_SLOT_SHIFT)
  518. #define M98925_DAI_VMON_SLOT_0D_0E (13 << M98925_DAI_VMON_SLOT_SHIFT)
  519. #define M98925_DAI_VMON_SLOT_0E_0F (14 << M98925_DAI_VMON_SLOT_SHIFT)
  520. #define M98925_DAI_VMON_SLOT_0F_10 (15 << M98925_DAI_VMON_SLOT_SHIFT)
  521. #define M98925_DAI_VMON_SLOT_10_11 (16 << M98925_DAI_VMON_SLOT_SHIFT)
  522. #define M98925_DAI_VMON_SLOT_11_12 (17 << M98925_DAI_VMON_SLOT_SHIFT)
  523. #define M98925_DAI_VMON_SLOT_12_13 (18 << M98925_DAI_VMON_SLOT_SHIFT)
  524. #define M98925_DAI_VMON_SLOT_13_14 (19 << M98925_DAI_VMON_SLOT_SHIFT)
  525. #define M98925_DAI_VMON_SLOT_14_15 (20 << M98925_DAI_VMON_SLOT_SHIFT)
  526. #define M98925_DAI_VMON_SLOT_15_16 (21 << M98925_DAI_VMON_SLOT_SHIFT)
  527. #define M98925_DAI_VMON_SLOT_16_17 (22 << M98925_DAI_VMON_SLOT_SHIFT)
  528. #define M98925_DAI_VMON_SLOT_17_18 (23 << M98925_DAI_VMON_SLOT_SHIFT)
  529. #define M98925_DAI_VMON_SLOT_18_19 (24 << M98925_DAI_VMON_SLOT_SHIFT)
  530. #define M98925_DAI_VMON_SLOT_19_1A (25 << M98925_DAI_VMON_SLOT_SHIFT)
  531. #define M98925_DAI_VMON_SLOT_1A_1B (26 << M98925_DAI_VMON_SLOT_SHIFT)
  532. #define M98925_DAI_VMON_SLOT_1B_1C (27 << M98925_DAI_VMON_SLOT_SHIFT)
  533. #define M98925_DAI_VMON_SLOT_1C_1D (28 << M98925_DAI_VMON_SLOT_SHIFT)
  534. #define M98925_DAI_VMON_SLOT_1D_1E (29 << M98925_DAI_VMON_SLOT_SHIFT)
  535. #define M98925_DAI_VMON_SLOT_1E_1F (30 << M98925_DAI_VMON_SLOT_SHIFT)
  536. /* MAX98925_R023_DOUT_CFG_IMON */
  537. #define M98925_DAI_IMON_EN_MASK (1<<5)
  538. #define M98925_DAI_IMON_EN_SHIFT 5
  539. #define M98925_DAI_IMON_EN_WIDTH 1
  540. #define M98925_DAI_IMON_SLOT_MASK (0x1F<<0)
  541. #define M98925_DAI_IMON_SLOT_SHIFT 0
  542. #define M98925_DAI_IMON_SLOT_WIDTH 5
  543. #define M98925_DAI_IMON_SLOT_00_01 (0 << M98925_DAI_IMON_SLOT_SHIFT)
  544. #define M98925_DAI_IMON_SLOT_01_02 (1 << M98925_DAI_IMON_SLOT_SHIFT)
  545. #define M98925_DAI_IMON_SLOT_02_03 (2 << M98925_DAI_IMON_SLOT_SHIFT)
  546. #define M98925_DAI_IMON_SLOT_03_04 (3 << M98925_DAI_IMON_SLOT_SHIFT)
  547. #define M98925_DAI_IMON_SLOT_04_05 (4 << M98925_DAI_IMON_SLOT_SHIFT)
  548. #define M98925_DAI_IMON_SLOT_05_06 (5 << M98925_DAI_IMON_SLOT_SHIFT)
  549. #define M98925_DAI_IMON_SLOT_06_07 (6 << M98925_DAI_IMON_SLOT_SHIFT)
  550. #define M98925_DAI_IMON_SLOT_07_08 (7 << M98925_DAI_IMON_SLOT_SHIFT)
  551. #define M98925_DAI_IMON_SLOT_08_09 (8 << M98925_DAI_IMON_SLOT_SHIFT)
  552. #define M98925_DAI_IMON_SLOT_09_0A (9 << M98925_DAI_IMON_SLOT_SHIFT)
  553. #define M98925_DAI_IMON_SLOT_0A_0B (10 << M98925_DAI_IMON_SLOT_SHIFT)
  554. #define M98925_DAI_IMON_SLOT_0B_0C (11 << M98925_DAI_IMON_SLOT_SHIFT)
  555. #define M98925_DAI_IMON_SLOT_0C_0D (12 << M98925_DAI_IMON_SLOT_SHIFT)
  556. #define M98925_DAI_IMON_SLOT_0D_0E (13 << M98925_DAI_IMON_SLOT_SHIFT)
  557. #define M98925_DAI_IMON_SLOT_0E_0F (14 << M98925_DAI_IMON_SLOT_SHIFT)
  558. #define M98925_DAI_IMON_SLOT_0F_10 (15 << M98925_DAI_IMON_SLOT_SHIFT)
  559. #define M98925_DAI_IMON_SLOT_10_11 (16 << M98925_DAI_IMON_SLOT_SHIFT)
  560. #define M98925_DAI_IMON_SLOT_11_12 (17 << M98925_DAI_IMON_SLOT_SHIFT)
  561. #define M98925_DAI_IMON_SLOT_12_13 (18 << M98925_DAI_IMON_SLOT_SHIFT)
  562. #define M98925_DAI_IMON_SLOT_13_14 (19 << M98925_DAI_IMON_SLOT_SHIFT)
  563. #define M98925_DAI_IMON_SLOT_14_15 (20 << M98925_DAI_IMON_SLOT_SHIFT)
  564. #define M98925_DAI_IMON_SLOT_15_16 (21 << M98925_DAI_IMON_SLOT_SHIFT)
  565. #define M98925_DAI_IMON_SLOT_16_17 (22 << M98925_DAI_IMON_SLOT_SHIFT)
  566. #define M98925_DAI_IMON_SLOT_17_18 (23 << M98925_DAI_IMON_SLOT_SHIFT)
  567. #define M98925_DAI_IMON_SLOT_18_19 (24 << M98925_DAI_IMON_SLOT_SHIFT)
  568. #define M98925_DAI_IMON_SLOT_19_1A (25 << M98925_DAI_IMON_SLOT_SHIFT)
  569. #define M98925_DAI_IMON_SLOT_1A_1B (26 << M98925_DAI_IMON_SLOT_SHIFT)
  570. #define M98925_DAI_IMON_SLOT_1B_1C (27 << M98925_DAI_IMON_SLOT_SHIFT)
  571. #define M98925_DAI_IMON_SLOT_1C_1D (28 << M98925_DAI_IMON_SLOT_SHIFT)
  572. #define M98925_DAI_IMON_SLOT_1D_1E (29 << M98925_DAI_IMON_SLOT_SHIFT)
  573. #define M98925_DAI_IMON_SLOT_1E_1F (30 << M98925_DAI_IMON_SLOT_SHIFT)
  574. /* MAX98925_R024_DOUT_CFG_VBAT */
  575. #define M98925_DAI_VBAT_EN_MASK (1<<5)
  576. #define M98925_DAI_VBAT_EN_SHIFT 5
  577. #define M98925_DAI_VBAT_EN_WIDTH 1
  578. #define M98925_DAI_VBAT_SLOT_MASK (0x1F<<0)
  579. #define M98925_DAI_VBAT_SLOT_SHIFT 0
  580. #define M98925_DAI_VBAT_SLOT_WIDTH 5
  581. /* MAX98925_R025_DOUT_CFG_VBST */
  582. #define M98925_DAI_VBST_EN_MASK (1<<5)
  583. #define M98925_DAI_VBST_EN_SHIFT 5
  584. #define M98925_DAI_VBST_EN_WIDTH 1
  585. #define M98925_DAI_VBST_SLOT_MASK (0x1F<<0)
  586. #define M98925_DAI_VBST_SLOT_SHIFT 0
  587. #define M98925_DAI_VBST_SLOT_WIDTH 5
  588. /* MAX98925_R026_DOUT_CFG_FLAG */
  589. #define M98925_DAI_FLAG_EN_MASK (1<<5)
  590. #define M98925_DAI_FLAG_EN_SHIFT 5
  591. #define M98925_DAI_FLAG_EN_WIDTH 1
  592. #define M98925_DAI_FLAG_SLOT_MASK (0x1F<<0)
  593. #define M98925_DAI_FLAG_SLOT_SHIFT 0
  594. #define M98925_DAI_FLAG_SLOT_WIDTH 5
  595. /* MAX98925_R027_DOUT_HIZ_CFG1 */
  596. #define M98925_DAI_SLOT_HIZ_CFG1_MASK (0xFF<<0)
  597. #define M98925_DAI_SLOT_HIZ_CFG1_SHIFT 0
  598. #define M98925_DAI_SLOT_HIZ_CFG1_WIDTH 8
  599. /* MAX98925_R028_DOUT_HIZ_CFG2 */
  600. #define M98925_DAI_SLOT_HIZ_CFG2_MASK (0xFF<<0)
  601. #define M98925_DAI_SLOT_HIZ_CFG2_SHIFT 0
  602. #define M98925_DAI_SLOT_HIZ_CFG2_WIDTH 8
  603. /* MAX98925_R029_DOUT_HIZ_CFG3 */
  604. #define M98925_DAI_SLOT_HIZ_CFG3_MASK (0xFF<<0)
  605. #define M98925_DAI_SLOT_HIZ_CFG3_SHIFT 0
  606. #define M98925_DAI_SLOT_HIZ_CFG3_WIDTH 8
  607. /* MAX98925_R02A_DOUT_HIZ_CFG4 */
  608. #define M98925_DAI_SLOT_HIZ_CFG4_MASK (0xFF<<0)
  609. #define M98925_DAI_SLOT_HIZ_CFG4_SHIFT 0
  610. #define M98925_DAI_SLOT_HIZ_CFG4_WIDTH 8
  611. /* MAX98925_R02B_DOUT_DRV_STRENGTH */
  612. #define M98925_DAI_OUT_DRIVE_MASK (0x03<<0)
  613. #define M98925_DAI_OUT_DRIVE_SHIFT 0
  614. #define M98925_DAI_OUT_DRIVE_WIDTH 2
  615. /* MAX98925_R02C_FILTERS */
  616. #define M98925_ADC_DITHER_EN_MASK (1<<7)
  617. #define M98925_ADC_DITHER_EN_SHIFT 7
  618. #define M98925_ADC_DITHER_EN_WIDTH 1
  619. #define M98925_IV_DCB_EN_MASK (1<<6)
  620. #define M98925_IV_DCB_EN_SHIFT 6
  621. #define M98925_IV_DCB_EN_WIDTH 1
  622. #define M98925_DAC_DITHER_EN_MASK (1<<4)
  623. #define M98925_DAC_DITHER_EN_SHIFT 4
  624. #define M98925_DAC_DITHER_EN_WIDTH 1
  625. #define M98925_DAC_FILTER_MODE_MASK (1<<3)
  626. #define M98925_DAC_FILTER_MODE_SHIFT 3
  627. #define M98925_DAC_FILTER_MODE_WIDTH 1
  628. #define M98925_DAC_HPF_MASK (0x07<<0)
  629. #define M98925_DAC_HPF_SHIFT 0
  630. #define M98925_DAC_HPF_WIDTH 3
  631. #define M98925_DAC_HPF_DISABLE (0 << M98925_DAC_HPF_SHIFT)
  632. #define M98925_DAC_HPF_DC_BLOCK (1 << M98925_DAC_HPF_SHIFT)
  633. #define M98925_DAC_HPF_EN_100 (2 << M98925_DAC_HPF_SHIFT)
  634. #define M98925_DAC_HPF_EN_200 (3 << M98925_DAC_HPF_SHIFT)
  635. #define M98925_DAC_HPF_EN_400 (4 << M98925_DAC_HPF_SHIFT)
  636. #define M98925_DAC_HPF_EN_800 (5 << M98925_DAC_HPF_SHIFT)
  637. /* MAX98925_R02D_GAIN */
  638. #define M98925_DAC_IN_SEL_MASK (0x03<<5)
  639. #define M98925_DAC_IN_SEL_SHIFT 5
  640. #define M98925_DAC_IN_SEL_WIDTH 2
  641. #define M98925_SPK_GAIN_MASK (0x1F<<0)
  642. #define M98925_SPK_GAIN_SHIFT 0
  643. #define M98925_SPK_GAIN_WIDTH 5
  644. #define M98925_DAC_IN_SEL_LEFT_DAI (0 << M98925_DAC_IN_SEL_SHIFT)
  645. #define M98925_DAC_IN_SEL_RIGHT_DAI (1 << M98925_DAC_IN_SEL_SHIFT)
  646. #define M98925_DAC_IN_SEL_SUMMED_DAI (2 << M98925_DAC_IN_SEL_SHIFT)
  647. #define M98925_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << M98925_DAC_IN_SEL_SHIFT)
  648. /* MAX98925_R02E_GAIN_RAMPING */
  649. #define M98925_SPK_RMP_EN_MASK (1<<1)
  650. #define M98925_SPK_RMP_EN_SHIFT 1
  651. #define M98925_SPK_RMP_EN_WIDTH 1
  652. #define M98925_SPK_ZCD_EN_MASK (1<<0)
  653. #define M98925_SPK_ZCD_EN_SHIFT 0
  654. #define M98925_SPK_ZCD_EN_WIDTH 1
  655. /* MAX98925_R02F_SPK_AMP */
  656. #define M98925_SPK_MODE_MASK (1<<0)
  657. #define M98925_SPK_MODE_SHIFT 0
  658. #define M98925_SPK_MODE_WIDTH 1
  659. /* MAX98925_R030_THRESHOLD */
  660. #define M98925_ALC_EN_MASK (1<<5)
  661. #define M98925_ALC_EN_SHIFT 5
  662. #define M98925_ALC_EN_WIDTH 1
  663. #define M98925_ALC_TH_MASK (0x1F<<0)
  664. #define M98925_ALC_TH_SHIFT 0
  665. #define M98925_ALC_TH_WIDTH 5
  666. /* MAX98925_R031_ALC_ATTACK */
  667. #define M98925_ALC_ATK_STEP_MASK (0x0F<<4)
  668. #define M98925_ALC_ATK_STEP_SHIFT 4
  669. #define M98925_ALC_ATK_STEP_WIDTH 4
  670. #define M98925_ALC_ATK_RATE_MASK (0x7<<0)
  671. #define M98925_ALC_ATK_RATE_SHIFT 0
  672. #define M98925_ALC_ATK_RATE_WIDTH 3
  673. /* MAX98925_R032_ALC_ATTEN_RLS */
  674. #define M98925_ALC_MAX_ATTEN_MASK (0x0F<<4)
  675. #define M98925_ALC_MAX_ATTEN_SHIFT 4
  676. #define M98925_ALC_MAX_ATTEN_WIDTH 4
  677. #define M98925_ALC_RLS_RATE_MASK (0x7<<0)
  678. #define M98925_ALC_RLS_RATE_SHIFT 0
  679. #define M98925_ALC_RLS_RATE_WIDTH 3
  680. /* MAX98925_R033_ALC_HOLD_RLS */
  681. #define M98925_ALC_RLS_TGR_MASK (1<<0)
  682. #define M98925_ALC_RLS_TGR_SHIFT 0
  683. #define M98925_ALC_RLS_TGR_WIDTH 1
  684. /* MAX98925_R034_ALC_CONFIGURATION */
  685. #define M98925_ALC_MUTE_EN_MASK (1<<7)
  686. #define M98925_ALC_MUTE_EN_SHIFT 7
  687. #define M98925_ALC_MUTE_EN_WIDTH 1
  688. #define M98925_ALC_MUTE_DLY_MASK (0x07<<4)
  689. #define M98925_ALC_MUTE_DLY_SHIFT 4
  690. #define M98925_ALC_MUTE_DLY_WIDTH 3
  691. #define M98925_ALC_RLS_DBT_MASK (0x07<<0)
  692. #define M98925_ALC_RLS_DBT_SHIFT 0
  693. #define M98925_ALC_RLS_DBT_WIDTH 3
  694. /* MAX98925_R035_BOOST_CONVERTER */
  695. #define M98925_BST_SYNC_MASK (1<<7)
  696. #define M98925_BST_SYNC_SHIFT 7
  697. #define M98925_BST_SYNC_WIDTH 1
  698. #define M98925_BST_PHASE_MASK (0x03<<4)
  699. #define M98925_BST_PHASE_SHIFT 4
  700. #define M98925_BST_PHASE_WIDTH 2
  701. #define M98925_BST_SKIP_MODE_MASK (0x03<<0)
  702. #define M98925_BST_SKIP_MODE_SHIFT 0
  703. #define M98925_BST_SKIP_MODE_WIDTH 2
  704. /* MAX98925_R036_BLOCK_ENABLE */
  705. #define M98925_BST_EN_MASK (1<<7)
  706. #define M98925_BST_EN_SHIFT 7
  707. #define M98925_BST_EN_WIDTH 1
  708. #define M98925_WATCH_EN_MASK (1<<6)
  709. #define M98925_WATCH_EN_SHIFT 6
  710. #define M98925_WATCH_EN_WIDTH 1
  711. #define M98925_CLKMON_EN_MASK (1<<5)
  712. #define M98925_CLKMON_EN_SHIFT 5
  713. #define M98925_CLKMON_EN_WIDTH 1
  714. #define M98925_SPK_EN_MASK (1<<4)
  715. #define M98925_SPK_EN_SHIFT 4
  716. #define M98925_SPK_EN_WIDTH 1
  717. #define M98925_ADC_VBST_EN_MASK (1<<3)
  718. #define M98925_ADC_VBST_EN_SHIFT 3
  719. #define M98925_ADC_VBST_EN_WIDTH 1
  720. #define M98925_ADC_VBAT_EN_MASK (1<<2)
  721. #define M98925_ADC_VBAT_EN_SHIFT 2
  722. #define M98925_ADC_VBAT_EN_WIDTH 1
  723. #define M98925_ADC_IMON_EN_MASK (1<<1)
  724. #define M98925_ADC_IMON_EN_SHIFT 1
  725. #define M98925_ADC_IMON_EN_WIDTH 1
  726. #define M98925_ADC_VMON_EN_MASK (1<<0)
  727. #define M98925_ADC_VMON_EN_SHIFT 0
  728. #define M98925_ADC_VMON_EN_WIDTH 1
  729. /* MAX98925_R037_CONFIGURATION */
  730. #define M98925_BST_VOUT_MASK (0x0F<<4)
  731. #define M98925_BST_VOUT_SHIFT 4
  732. #define M98925_BST_VOUT_WIDTH 4
  733. #define M98925_THERMWARN_LEVEL_MASK (0x03<<2)
  734. #define M98925_THERMWARN_LEVEL_SHIFT 2
  735. #define M98925_THERMWARN_LEVEL_WIDTH 2
  736. #define M98925_WATCH_TIME_MASK (0x03<<0)
  737. #define M98925_WATCH_TIME_SHIFT 0
  738. #define M98925_WATCH_TIME_WIDTH 2
  739. /* MAX98925_R038_GLOBAL_ENABLE */
  740. #define M98925_EN_MASK (1<<7)
  741. #define M98925_EN_SHIFT 7
  742. #define M98925_EN_WIDTH 1
  743. /* MAX98925_R03A_BOOST_LIMITER */
  744. #define M98925_BST_ILIM_MASK (0x1F<<3)
  745. #define M98925_BST_ILIM_SHIFT 3
  746. #define M98925_BST_ILIM_WIDTH 5
  747. /* MAX98925_R0FF_VERSION */
  748. #define M98925_REV_ID_MASK (0xFF<<0)
  749. #define M98925_REV_ID_SHIFT 0
  750. #define M98925_REV_ID_WIDTH 8
  751. struct max98925_priv {
  752. struct regmap *regmap;
  753. struct snd_soc_component *component;
  754. struct max98925_pdata *pdata;
  755. unsigned int sysclk;
  756. unsigned int v_slot;
  757. unsigned int i_slot;
  758. unsigned int spk_gain;
  759. unsigned int ch_size;
  760. };
  761. #endif