max98925.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * max98925.c -- ALSA SoC Stereo MAX98925 driver
  4. * Copyright 2013-15 Maxim Integrated Products
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/i2c.h>
  8. #include <linux/module.h>
  9. #include <linux/regmap.h>
  10. #include <linux/slab.h>
  11. #include <linux/cdev.h>
  12. #include <sound/pcm.h>
  13. #include <sound/pcm_params.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include "max98925.h"
  17. static const char *const dai_text[] = {
  18. "Left", "Right", "LeftRight", "LeftRightDiv2",
  19. };
  20. static const char * const max98925_boost_voltage_text[] = {
  21. "8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
  22. "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V"
  23. };
  24. static SOC_ENUM_SINGLE_DECL(max98925_boost_voltage,
  25. MAX98925_CONFIGURATION, M98925_BST_VOUT_SHIFT,
  26. max98925_boost_voltage_text);
  27. static const char *const hpf_text[] = {
  28. "Disable", "DC Block", "100Hz", "200Hz", "400Hz", "800Hz",
  29. };
  30. static const struct reg_default max98925_reg[] = {
  31. { 0x0B, 0x00 }, /* IRQ Enable0 */
  32. { 0x0C, 0x00 }, /* IRQ Enable1 */
  33. { 0x0D, 0x00 }, /* IRQ Enable2 */
  34. { 0x0E, 0x00 }, /* IRQ Clear0 */
  35. { 0x0F, 0x00 }, /* IRQ Clear1 */
  36. { 0x10, 0x00 }, /* IRQ Clear2 */
  37. { 0x11, 0xC0 }, /* Map0 */
  38. { 0x12, 0x00 }, /* Map1 */
  39. { 0x13, 0x00 }, /* Map2 */
  40. { 0x14, 0xF0 }, /* Map3 */
  41. { 0x15, 0x00 }, /* Map4 */
  42. { 0x16, 0xAB }, /* Map5 */
  43. { 0x17, 0x89 }, /* Map6 */
  44. { 0x18, 0x00 }, /* Map7 */
  45. { 0x19, 0x00 }, /* Map8 */
  46. { 0x1A, 0x06 }, /* DAI Clock Mode 1 */
  47. { 0x1B, 0xC0 }, /* DAI Clock Mode 2 */
  48. { 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
  49. { 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
  50. { 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
  51. { 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
  52. { 0x20, 0x50 }, /* Format */
  53. { 0x21, 0x00 }, /* TDM Slot Select */
  54. { 0x22, 0x00 }, /* DOUT Configuration VMON */
  55. { 0x23, 0x00 }, /* DOUT Configuration IMON */
  56. { 0x24, 0x00 }, /* DOUT Configuration VBAT */
  57. { 0x25, 0x00 }, /* DOUT Configuration VBST */
  58. { 0x26, 0x00 }, /* DOUT Configuration FLAG */
  59. { 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
  60. { 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
  61. { 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
  62. { 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
  63. { 0x2B, 0x02 }, /* DOUT Drive Strength */
  64. { 0x2C, 0x90 }, /* Filters */
  65. { 0x2D, 0x00 }, /* Gain */
  66. { 0x2E, 0x02 }, /* Gain Ramping */
  67. { 0x2F, 0x00 }, /* Speaker Amplifier */
  68. { 0x30, 0x0A }, /* Threshold */
  69. { 0x31, 0x00 }, /* ALC Attack */
  70. { 0x32, 0x80 }, /* ALC Atten and Release */
  71. { 0x33, 0x00 }, /* ALC Infinite Hold Release */
  72. { 0x34, 0x92 }, /* ALC Configuration */
  73. { 0x35, 0x01 }, /* Boost Converter */
  74. { 0x36, 0x00 }, /* Block Enable */
  75. { 0x37, 0x00 }, /* Configuration */
  76. { 0x38, 0x00 }, /* Global Enable */
  77. { 0x3A, 0x00 }, /* Boost Limiter */
  78. };
  79. static const struct soc_enum max98925_dai_enum =
  80. SOC_ENUM_SINGLE(MAX98925_GAIN, 5, ARRAY_SIZE(dai_text), dai_text);
  81. static const struct soc_enum max98925_hpf_enum =
  82. SOC_ENUM_SINGLE(MAX98925_FILTERS, 0, ARRAY_SIZE(hpf_text), hpf_text);
  83. static const struct snd_kcontrol_new max98925_hpf_sel_mux =
  84. SOC_DAPM_ENUM("Rc Filter MUX Mux", max98925_hpf_enum);
  85. static const struct snd_kcontrol_new max98925_dai_sel_mux =
  86. SOC_DAPM_ENUM("DAI IN MUX Mux", max98925_dai_enum);
  87. static int max98925_dac_event(struct snd_soc_dapm_widget *w,
  88. struct snd_kcontrol *kcontrol, int event)
  89. {
  90. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  91. struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
  92. switch (event) {
  93. case SND_SOC_DAPM_PRE_PMU:
  94. regmap_update_bits(max98925->regmap,
  95. MAX98925_BLOCK_ENABLE,
  96. M98925_BST_EN_MASK |
  97. M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK,
  98. M98925_BST_EN_MASK |
  99. M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK);
  100. break;
  101. case SND_SOC_DAPM_POST_PMD:
  102. regmap_update_bits(max98925->regmap,
  103. MAX98925_BLOCK_ENABLE, M98925_BST_EN_MASK |
  104. M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK, 0);
  105. break;
  106. default:
  107. return 0;
  108. }
  109. return 0;
  110. }
  111. static const struct snd_soc_dapm_widget max98925_dapm_widgets[] = {
  112. SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
  113. SND_SOC_DAPM_MUX("DAI IN MUX", SND_SOC_NOPM, 0, 0,
  114. &max98925_dai_sel_mux),
  115. SND_SOC_DAPM_MUX("Rc Filter MUX", SND_SOC_NOPM, 0, 0,
  116. &max98925_hpf_sel_mux),
  117. SND_SOC_DAPM_DAC_E("Amp Enable", NULL, MAX98925_BLOCK_ENABLE,
  118. M98925_SPK_EN_SHIFT, 0, max98925_dac_event,
  119. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  120. SND_SOC_DAPM_SUPPLY("Global Enable", MAX98925_GLOBAL_ENABLE,
  121. M98925_EN_SHIFT, 0, NULL, 0),
  122. SND_SOC_DAPM_OUTPUT("BE_OUT"),
  123. };
  124. static const struct snd_soc_dapm_route max98925_audio_map[] = {
  125. {"DAI IN MUX", "Left", "DAI_OUT"},
  126. {"DAI IN MUX", "Right", "DAI_OUT"},
  127. {"DAI IN MUX", "LeftRight", "DAI_OUT"},
  128. {"DAI IN MUX", "LeftRightDiv2", "DAI_OUT"},
  129. {"Rc Filter MUX", "Disable", "DAI IN MUX"},
  130. {"Rc Filter MUX", "DC Block", "DAI IN MUX"},
  131. {"Rc Filter MUX", "100Hz", "DAI IN MUX"},
  132. {"Rc Filter MUX", "200Hz", "DAI IN MUX"},
  133. {"Rc Filter MUX", "400Hz", "DAI IN MUX"},
  134. {"Rc Filter MUX", "800Hz", "DAI IN MUX"},
  135. {"Amp Enable", NULL, "Rc Filter MUX"},
  136. {"BE_OUT", NULL, "Amp Enable"},
  137. {"BE_OUT", NULL, "Global Enable"},
  138. };
  139. static bool max98925_volatile_register(struct device *dev, unsigned int reg)
  140. {
  141. switch (reg) {
  142. case MAX98925_VBAT_DATA:
  143. case MAX98925_VBST_DATA:
  144. case MAX98925_LIVE_STATUS0:
  145. case MAX98925_LIVE_STATUS1:
  146. case MAX98925_LIVE_STATUS2:
  147. case MAX98925_STATE0:
  148. case MAX98925_STATE1:
  149. case MAX98925_STATE2:
  150. case MAX98925_FLAG0:
  151. case MAX98925_FLAG1:
  152. case MAX98925_FLAG2:
  153. case MAX98925_REV_VERSION:
  154. return true;
  155. default:
  156. return false;
  157. }
  158. }
  159. static bool max98925_readable_register(struct device *dev, unsigned int reg)
  160. {
  161. switch (reg) {
  162. case MAX98925_IRQ_CLEAR0:
  163. case MAX98925_IRQ_CLEAR1:
  164. case MAX98925_IRQ_CLEAR2:
  165. case MAX98925_ALC_HOLD_RLS:
  166. return false;
  167. default:
  168. return true;
  169. }
  170. }
  171. static DECLARE_TLV_DB_SCALE(max98925_spk_tlv, -600, 100, 0);
  172. static const struct snd_kcontrol_new max98925_snd_controls[] = {
  173. SOC_SINGLE_TLV("Speaker Volume", MAX98925_GAIN,
  174. M98925_SPK_GAIN_SHIFT, (1<<M98925_SPK_GAIN_WIDTH)-1, 0,
  175. max98925_spk_tlv),
  176. SOC_SINGLE("Ramp Switch", MAX98925_GAIN_RAMPING,
  177. M98925_SPK_RMP_EN_SHIFT, 1, 0),
  178. SOC_SINGLE("ZCD Switch", MAX98925_GAIN_RAMPING,
  179. M98925_SPK_ZCD_EN_SHIFT, 1, 0),
  180. SOC_SINGLE("ALC Switch", MAX98925_THRESHOLD,
  181. M98925_ALC_EN_SHIFT, 1, 0),
  182. SOC_SINGLE("ALC Threshold", MAX98925_THRESHOLD, M98925_ALC_TH_SHIFT,
  183. (1<<M98925_ALC_TH_WIDTH)-1, 0),
  184. SOC_ENUM("Boost Output Voltage", max98925_boost_voltage),
  185. };
  186. /* codec sample rate and n/m dividers parameter table */
  187. static const struct {
  188. int rate;
  189. int sr;
  190. int divisors[3][2];
  191. } rate_table[] = {
  192. {
  193. .rate = 8000,
  194. .sr = 0,
  195. .divisors = { {1, 375}, {5, 1764}, {1, 384} }
  196. },
  197. {
  198. .rate = 11025,
  199. .sr = 1,
  200. .divisors = { {147, 40000}, {1, 256}, {147, 40960} }
  201. },
  202. {
  203. .rate = 12000,
  204. .sr = 2,
  205. .divisors = { {1, 250}, {5, 1176}, {1, 256} }
  206. },
  207. {
  208. .rate = 16000,
  209. .sr = 3,
  210. .divisors = { {2, 375}, {5, 882}, {1, 192} }
  211. },
  212. {
  213. .rate = 22050,
  214. .sr = 4,
  215. .divisors = { {147, 20000}, {1, 128}, {147, 20480} }
  216. },
  217. {
  218. .rate = 24000,
  219. .sr = 5,
  220. .divisors = { {1, 125}, {5, 588}, {1, 128} }
  221. },
  222. {
  223. .rate = 32000,
  224. .sr = 6,
  225. .divisors = { {4, 375}, {5, 441}, {1, 96} }
  226. },
  227. {
  228. .rate = 44100,
  229. .sr = 7,
  230. .divisors = { {147, 10000}, {1, 64}, {147, 10240} }
  231. },
  232. {
  233. .rate = 48000,
  234. .sr = 8,
  235. .divisors = { {2, 125}, {5, 294}, {1, 64} }
  236. },
  237. };
  238. static inline int max98925_rate_value(struct snd_soc_component *component,
  239. int rate, int clock, int *value, int *n, int *m)
  240. {
  241. int ret = -EINVAL;
  242. int i;
  243. for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
  244. if (rate_table[i].rate >= rate) {
  245. *value = rate_table[i].sr;
  246. *n = rate_table[i].divisors[clock][0];
  247. *m = rate_table[i].divisors[clock][1];
  248. ret = 0;
  249. break;
  250. }
  251. }
  252. return ret;
  253. }
  254. static void max98925_set_sense_data(struct max98925_priv *max98925)
  255. {
  256. /* set VMON slots */
  257. regmap_update_bits(max98925->regmap,
  258. MAX98925_DOUT_CFG_VMON,
  259. M98925_DAI_VMON_EN_MASK, M98925_DAI_VMON_EN_MASK);
  260. regmap_update_bits(max98925->regmap,
  261. MAX98925_DOUT_CFG_VMON,
  262. M98925_DAI_VMON_SLOT_MASK,
  263. max98925->v_slot << M98925_DAI_VMON_SLOT_SHIFT);
  264. /* set IMON slots */
  265. regmap_update_bits(max98925->regmap,
  266. MAX98925_DOUT_CFG_IMON,
  267. M98925_DAI_IMON_EN_MASK, M98925_DAI_IMON_EN_MASK);
  268. regmap_update_bits(max98925->regmap,
  269. MAX98925_DOUT_CFG_IMON,
  270. M98925_DAI_IMON_SLOT_MASK,
  271. max98925->i_slot << M98925_DAI_IMON_SLOT_SHIFT);
  272. }
  273. static int max98925_dai_set_fmt(struct snd_soc_dai *codec_dai,
  274. unsigned int fmt)
  275. {
  276. struct snd_soc_component *component = codec_dai->component;
  277. struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
  278. unsigned int invert = 0;
  279. dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
  280. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  281. case SND_SOC_DAIFMT_CBS_CFS:
  282. /* set DAI to slave mode */
  283. regmap_update_bits(max98925->regmap,
  284. MAX98925_DAI_CLK_MODE2,
  285. M98925_DAI_MAS_MASK, 0);
  286. max98925_set_sense_data(max98925);
  287. break;
  288. case SND_SOC_DAIFMT_CBM_CFM:
  289. /*
  290. * set left channel DAI to master mode,
  291. * right channel always slave
  292. */
  293. regmap_update_bits(max98925->regmap,
  294. MAX98925_DAI_CLK_MODE2,
  295. M98925_DAI_MAS_MASK, M98925_DAI_MAS_MASK);
  296. break;
  297. case SND_SOC_DAIFMT_CBS_CFM:
  298. case SND_SOC_DAIFMT_CBM_CFS:
  299. default:
  300. dev_err(component->dev, "DAI clock mode unsupported");
  301. return -EINVAL;
  302. }
  303. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  304. case SND_SOC_DAIFMT_NB_NF:
  305. break;
  306. case SND_SOC_DAIFMT_NB_IF:
  307. invert = M98925_DAI_WCI_MASK;
  308. break;
  309. case SND_SOC_DAIFMT_IB_NF:
  310. invert = M98925_DAI_BCI_MASK;
  311. break;
  312. case SND_SOC_DAIFMT_IB_IF:
  313. invert = M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK;
  314. break;
  315. default:
  316. dev_err(component->dev, "DAI invert mode unsupported");
  317. return -EINVAL;
  318. }
  319. regmap_update_bits(max98925->regmap, MAX98925_FORMAT,
  320. M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK, invert);
  321. return 0;
  322. }
  323. static int max98925_set_clock(struct max98925_priv *max98925,
  324. struct snd_pcm_hw_params *params)
  325. {
  326. unsigned int dai_sr = 0, clock, mdll, n, m;
  327. struct snd_soc_component *component = max98925->component;
  328. int rate = params_rate(params);
  329. /* BCLK/LRCLK ratio calculation */
  330. int blr_clk_ratio = params_channels(params) * max98925->ch_size;
  331. switch (blr_clk_ratio) {
  332. case 32:
  333. regmap_update_bits(max98925->regmap,
  334. MAX98925_DAI_CLK_MODE2,
  335. M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_32);
  336. break;
  337. case 48:
  338. regmap_update_bits(max98925->regmap,
  339. MAX98925_DAI_CLK_MODE2,
  340. M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_48);
  341. break;
  342. case 64:
  343. regmap_update_bits(max98925->regmap,
  344. MAX98925_DAI_CLK_MODE2,
  345. M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_64);
  346. break;
  347. default:
  348. return -EINVAL;
  349. }
  350. switch (max98925->sysclk) {
  351. case 6000000:
  352. clock = 0;
  353. mdll = M98925_MDLL_MULT_MCLKx16;
  354. break;
  355. case 11289600:
  356. clock = 1;
  357. mdll = M98925_MDLL_MULT_MCLKx8;
  358. break;
  359. case 12000000:
  360. clock = 0;
  361. mdll = M98925_MDLL_MULT_MCLKx8;
  362. break;
  363. case 12288000:
  364. clock = 2;
  365. mdll = M98925_MDLL_MULT_MCLKx8;
  366. break;
  367. default:
  368. dev_info(max98925->component->dev, "unsupported sysclk %d\n",
  369. max98925->sysclk);
  370. return -EINVAL;
  371. }
  372. if (max98925_rate_value(component, rate, clock, &dai_sr, &n, &m))
  373. return -EINVAL;
  374. /* set DAI_SR to correct LRCLK frequency */
  375. regmap_update_bits(max98925->regmap,
  376. MAX98925_DAI_CLK_MODE2,
  377. M98925_DAI_SR_MASK, dai_sr << M98925_DAI_SR_SHIFT);
  378. /* set DAI m divider */
  379. regmap_write(max98925->regmap,
  380. MAX98925_DAI_CLK_DIV_M_MSBS, m >> 8);
  381. regmap_write(max98925->regmap,
  382. MAX98925_DAI_CLK_DIV_M_LSBS, m & 0xFF);
  383. /* set DAI n divider */
  384. regmap_write(max98925->regmap,
  385. MAX98925_DAI_CLK_DIV_N_MSBS, n >> 8);
  386. regmap_write(max98925->regmap,
  387. MAX98925_DAI_CLK_DIV_N_LSBS, n & 0xFF);
  388. /* set MDLL */
  389. regmap_update_bits(max98925->regmap, MAX98925_DAI_CLK_MODE1,
  390. M98925_MDLL_MULT_MASK, mdll << M98925_MDLL_MULT_SHIFT);
  391. return 0;
  392. }
  393. static int max98925_dai_hw_params(struct snd_pcm_substream *substream,
  394. struct snd_pcm_hw_params *params,
  395. struct snd_soc_dai *dai)
  396. {
  397. struct snd_soc_component *component = dai->component;
  398. struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
  399. switch (params_width(params)) {
  400. case 16:
  401. regmap_update_bits(max98925->regmap,
  402. MAX98925_FORMAT,
  403. M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_16);
  404. max98925->ch_size = 16;
  405. break;
  406. case 24:
  407. regmap_update_bits(max98925->regmap,
  408. MAX98925_FORMAT,
  409. M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_24);
  410. max98925->ch_size = 24;
  411. break;
  412. case 32:
  413. regmap_update_bits(max98925->regmap,
  414. MAX98925_FORMAT,
  415. M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_32);
  416. max98925->ch_size = 32;
  417. break;
  418. default:
  419. pr_err("%s: format unsupported %d",
  420. __func__, params_format(params));
  421. return -EINVAL;
  422. }
  423. dev_dbg(component->dev, "%s: format supported %d",
  424. __func__, params_format(params));
  425. return max98925_set_clock(max98925, params);
  426. }
  427. static int max98925_dai_set_sysclk(struct snd_soc_dai *dai,
  428. int clk_id, unsigned int freq, int dir)
  429. {
  430. struct snd_soc_component *component = dai->component;
  431. struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
  432. switch (clk_id) {
  433. case 0:
  434. /* use MCLK for Left channel, right channel always BCLK */
  435. regmap_update_bits(max98925->regmap,
  436. MAX98925_DAI_CLK_MODE1,
  437. M98925_DAI_CLK_SOURCE_MASK, 0);
  438. break;
  439. case 1:
  440. /* configure dai clock source to BCLK instead of MCLK */
  441. regmap_update_bits(max98925->regmap,
  442. MAX98925_DAI_CLK_MODE1,
  443. M98925_DAI_CLK_SOURCE_MASK,
  444. M98925_DAI_CLK_SOURCE_MASK);
  445. break;
  446. default:
  447. return -EINVAL;
  448. }
  449. max98925->sysclk = freq;
  450. return 0;
  451. }
  452. #define MAX98925_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  453. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  454. static const struct snd_soc_dai_ops max98925_dai_ops = {
  455. .set_sysclk = max98925_dai_set_sysclk,
  456. .set_fmt = max98925_dai_set_fmt,
  457. .hw_params = max98925_dai_hw_params,
  458. };
  459. static struct snd_soc_dai_driver max98925_dai[] = {
  460. {
  461. .name = "max98925-aif1",
  462. .playback = {
  463. .stream_name = "HiFi Playback",
  464. .channels_min = 1,
  465. .channels_max = 2,
  466. .rates = SNDRV_PCM_RATE_8000_48000,
  467. .formats = MAX98925_FORMATS,
  468. },
  469. .capture = {
  470. .stream_name = "HiFi Capture",
  471. .channels_min = 1,
  472. .channels_max = 2,
  473. .rates = SNDRV_PCM_RATE_8000_48000,
  474. .formats = MAX98925_FORMATS,
  475. },
  476. .ops = &max98925_dai_ops,
  477. }
  478. };
  479. static int max98925_probe(struct snd_soc_component *component)
  480. {
  481. struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
  482. max98925->component = component;
  483. regmap_write(max98925->regmap, MAX98925_GLOBAL_ENABLE, 0x00);
  484. /* It's not the default but we need to set DAI_DLY */
  485. regmap_write(max98925->regmap,
  486. MAX98925_FORMAT, M98925_DAI_DLY_MASK);
  487. regmap_write(max98925->regmap, MAX98925_TDM_SLOT_SELECT, 0xC8);
  488. regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG1, 0xFF);
  489. regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG2, 0xFF);
  490. regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG3, 0xFF);
  491. regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG4, 0xF0);
  492. regmap_write(max98925->regmap, MAX98925_FILTERS, 0xD8);
  493. regmap_write(max98925->regmap, MAX98925_ALC_CONFIGURATION, 0xF8);
  494. regmap_write(max98925->regmap, MAX98925_CONFIGURATION, 0xF0);
  495. /* Disable ALC muting */
  496. regmap_write(max98925->regmap, MAX98925_BOOST_LIMITER, 0xF8);
  497. return 0;
  498. }
  499. static const struct snd_soc_component_driver soc_component_dev_max98925 = {
  500. .probe = max98925_probe,
  501. .controls = max98925_snd_controls,
  502. .num_controls = ARRAY_SIZE(max98925_snd_controls),
  503. .dapm_routes = max98925_audio_map,
  504. .num_dapm_routes = ARRAY_SIZE(max98925_audio_map),
  505. .dapm_widgets = max98925_dapm_widgets,
  506. .num_dapm_widgets = ARRAY_SIZE(max98925_dapm_widgets),
  507. .idle_bias_on = 1,
  508. .use_pmdown_time = 1,
  509. .endianness = 1,
  510. .non_legacy_dai_naming = 1,
  511. };
  512. static const struct regmap_config max98925_regmap = {
  513. .reg_bits = 8,
  514. .val_bits = 8,
  515. .max_register = MAX98925_REV_VERSION,
  516. .reg_defaults = max98925_reg,
  517. .num_reg_defaults = ARRAY_SIZE(max98925_reg),
  518. .volatile_reg = max98925_volatile_register,
  519. .readable_reg = max98925_readable_register,
  520. .cache_type = REGCACHE_RBTREE,
  521. };
  522. static int max98925_i2c_probe(struct i2c_client *i2c,
  523. const struct i2c_device_id *id)
  524. {
  525. int ret, reg;
  526. u32 value;
  527. struct max98925_priv *max98925;
  528. max98925 = devm_kzalloc(&i2c->dev,
  529. sizeof(*max98925), GFP_KERNEL);
  530. if (!max98925)
  531. return -ENOMEM;
  532. i2c_set_clientdata(i2c, max98925);
  533. max98925->regmap = devm_regmap_init_i2c(i2c, &max98925_regmap);
  534. if (IS_ERR(max98925->regmap)) {
  535. ret = PTR_ERR(max98925->regmap);
  536. dev_err(&i2c->dev,
  537. "Failed to allocate regmap: %d\n", ret);
  538. return ret;
  539. }
  540. if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
  541. if (value > M98925_DAI_VMON_SLOT_1E_1F) {
  542. dev_err(&i2c->dev, "vmon slot number is wrong:\n");
  543. return -EINVAL;
  544. }
  545. max98925->v_slot = value;
  546. }
  547. if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
  548. if (value > M98925_DAI_IMON_SLOT_1E_1F) {
  549. dev_err(&i2c->dev, "imon slot number is wrong:\n");
  550. return -EINVAL;
  551. }
  552. max98925->i_slot = value;
  553. }
  554. ret = regmap_read(max98925->regmap, MAX98925_REV_VERSION, &reg);
  555. if (ret < 0) {
  556. dev_err(&i2c->dev, "Read revision failed\n");
  557. return ret;
  558. }
  559. if ((reg != MAX98925_VERSION) && (reg != MAX98925_VERSION1)) {
  560. ret = -ENODEV;
  561. dev_err(&i2c->dev, "Invalid revision (%d 0x%02X)\n",
  562. ret, reg);
  563. return ret;
  564. }
  565. dev_info(&i2c->dev, "device version 0x%02X\n", reg);
  566. ret = devm_snd_soc_register_component(&i2c->dev,
  567. &soc_component_dev_max98925,
  568. max98925_dai, ARRAY_SIZE(max98925_dai));
  569. if (ret < 0)
  570. dev_err(&i2c->dev,
  571. "Failed to register component: %d\n", ret);
  572. return ret;
  573. }
  574. static const struct i2c_device_id max98925_i2c_id[] = {
  575. { "max98925", 0 },
  576. { }
  577. };
  578. MODULE_DEVICE_TABLE(i2c, max98925_i2c_id);
  579. static const struct of_device_id max98925_of_match[] = {
  580. { .compatible = "maxim,max98925", },
  581. { }
  582. };
  583. MODULE_DEVICE_TABLE(of, max98925_of_match);
  584. static struct i2c_driver max98925_i2c_driver = {
  585. .driver = {
  586. .name = "max98925",
  587. .of_match_table = of_match_ptr(max98925_of_match),
  588. .pm = NULL,
  589. },
  590. .probe = max98925_i2c_probe,
  591. .id_table = max98925_i2c_id,
  592. };
  593. module_i2c_driver(max98925_i2c_driver)
  594. MODULE_DESCRIPTION("ALSA SoC MAX98925 driver");
  595. MODULE_AUTHOR("Ralph Birt <rdbirt@gmail.com>, Anish kumar <anish.kumar@maximintegrated.com>");
  596. MODULE_LICENSE("GPL");