max98390.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * max98390.c -- MAX98390 ALSA Soc Audio driver
  4. *
  5. * Copyright (C) 2020 Maxim Integrated Products
  6. *
  7. */
  8. #include <linux/acpi.h>
  9. #include <linux/cdev.h>
  10. #include <linux/dmi.h>
  11. #include <linux/firmware.h>
  12. #include <linux/gpio.h>
  13. #include <linux/i2c.h>
  14. #include <linux/module.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <linux/time.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/tlv.h>
  23. #include "max98390.h"
  24. static struct reg_default max98390_reg_defaults[] = {
  25. {MAX98390_INT_EN1, 0xf0},
  26. {MAX98390_INT_EN2, 0x00},
  27. {MAX98390_INT_EN3, 0x00},
  28. {MAX98390_INT_FLAG_CLR1, 0x00},
  29. {MAX98390_INT_FLAG_CLR2, 0x00},
  30. {MAX98390_INT_FLAG_CLR3, 0x00},
  31. {MAX98390_IRQ_CTRL, 0x01},
  32. {MAX98390_CLK_MON, 0x6d},
  33. {MAX98390_DAT_MON, 0x03},
  34. {MAX98390_WDOG_CTRL, 0x00},
  35. {MAX98390_WDOG_RST, 0x00},
  36. {MAX98390_MEAS_ADC_THERM_WARN_THRESH, 0x75},
  37. {MAX98390_MEAS_ADC_THERM_SHDN_THRESH, 0x8c},
  38. {MAX98390_MEAS_ADC_THERM_HYSTERESIS, 0x08},
  39. {MAX98390_PIN_CFG, 0x55},
  40. {MAX98390_PCM_RX_EN_A, 0x00},
  41. {MAX98390_PCM_RX_EN_B, 0x00},
  42. {MAX98390_PCM_TX_EN_A, 0x00},
  43. {MAX98390_PCM_TX_EN_B, 0x00},
  44. {MAX98390_PCM_TX_HIZ_CTRL_A, 0xff},
  45. {MAX98390_PCM_TX_HIZ_CTRL_B, 0xff},
  46. {MAX98390_PCM_CH_SRC_1, 0x00},
  47. {MAX98390_PCM_CH_SRC_2, 0x00},
  48. {MAX98390_PCM_CH_SRC_3, 0x00},
  49. {MAX98390_PCM_MODE_CFG, 0xc0},
  50. {MAX98390_PCM_MASTER_MODE, 0x1c},
  51. {MAX98390_PCM_CLK_SETUP, 0x44},
  52. {MAX98390_PCM_SR_SETUP, 0x08},
  53. {MAX98390_ICC_RX_EN_A, 0x00},
  54. {MAX98390_ICC_RX_EN_B, 0x00},
  55. {MAX98390_ICC_TX_EN_A, 0x00},
  56. {MAX98390_ICC_TX_EN_B, 0x00},
  57. {MAX98390_ICC_HIZ_MANUAL_MODE, 0x00},
  58. {MAX98390_ICC_TX_HIZ_EN_A, 0x00},
  59. {MAX98390_ICC_TX_HIZ_EN_B, 0x00},
  60. {MAX98390_ICC_LNK_EN, 0x00},
  61. {MAX98390_R2039_AMP_DSP_CFG, 0x0f},
  62. {MAX98390_R203A_AMP_EN, 0x81},
  63. {MAX98390_TONE_GEN_DC_CFG, 0x00},
  64. {MAX98390_SPK_SRC_SEL, 0x00},
  65. {MAX98390_SSM_CFG, 0x85},
  66. {MAX98390_MEAS_EN, 0x03},
  67. {MAX98390_MEAS_DSP_CFG, 0x0f},
  68. {MAX98390_BOOST_CTRL0, 0x1c},
  69. {MAX98390_BOOST_CTRL3, 0x01},
  70. {MAX98390_BOOST_CTRL1, 0x40},
  71. {MAX98390_MEAS_ADC_CFG, 0x07},
  72. {MAX98390_MEAS_ADC_BASE_MSB, 0x00},
  73. {MAX98390_MEAS_ADC_BASE_LSB, 0x23},
  74. {MAX98390_ADC_CH0_DIVIDE, 0x00},
  75. {MAX98390_ADC_CH1_DIVIDE, 0x00},
  76. {MAX98390_ADC_CH2_DIVIDE, 0x00},
  77. {MAX98390_ADC_CH0_FILT_CFG, 0x00},
  78. {MAX98390_ADC_CH1_FILT_CFG, 0x00},
  79. {MAX98390_ADC_CH2_FILT_CFG, 0x00},
  80. {MAX98390_PWR_GATE_CTL, 0x2c},
  81. {MAX98390_BROWNOUT_EN, 0x00},
  82. {MAX98390_BROWNOUT_INFINITE_HOLD, 0x00},
  83. {MAX98390_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
  84. {MAX98390_BROWNOUT_LVL_HOLD, 0x00},
  85. {MAX98390_BROWNOUT_LVL1_THRESH, 0x00},
  86. {MAX98390_BROWNOUT_LVL2_THRESH, 0x00},
  87. {MAX98390_BROWNOUT_LVL3_THRESH, 0x00},
  88. {MAX98390_BROWNOUT_LVL4_THRESH, 0x00},
  89. {MAX98390_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
  90. {MAX98390_BROWNOUT_AMP_LIMITER_ATK_REL, 0x1f},
  91. {MAX98390_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
  92. {MAX98390_BROWNOUT_AMP1_CLIP_MODE, 0x00},
  93. {MAX98390_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
  94. {MAX98390_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
  95. {MAX98390_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
  96. {MAX98390_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
  97. {MAX98390_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
  98. {MAX98390_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
  99. {MAX98390_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
  100. {MAX98390_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
  101. {MAX98390_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
  102. {MAX98390_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
  103. {MAX98390_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
  104. {MAX98390_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
  105. {MAX98390_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
  106. {MAX98390_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
  107. {MAX98390_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
  108. {MAX98390_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
  109. {MAX98390_BROWNOUT_ILIM_HLD, 0x00},
  110. {MAX98390_BROWNOUT_LIM_HLD, 0x00},
  111. {MAX98390_BROWNOUT_CLIP_HLD, 0x00},
  112. {MAX98390_BROWNOUT_GAIN_HLD, 0x00},
  113. {MAX98390_ENV_TRACK_VOUT_HEADROOM, 0x0f},
  114. {MAX98390_ENV_TRACK_BOOST_VOUT_DELAY, 0x80},
  115. {MAX98390_ENV_TRACK_REL_RATE, 0x07},
  116. {MAX98390_ENV_TRACK_HOLD_RATE, 0x07},
  117. {MAX98390_ENV_TRACK_CTRL, 0x01},
  118. {MAX98390_BOOST_BYPASS1, 0x49},
  119. {MAX98390_BOOST_BYPASS2, 0x2b},
  120. {MAX98390_BOOST_BYPASS3, 0x08},
  121. {MAX98390_FET_SCALING1, 0x00},
  122. {MAX98390_FET_SCALING2, 0x03},
  123. {MAX98390_FET_SCALING3, 0x00},
  124. {MAX98390_FET_SCALING4, 0x07},
  125. {MAX98390_SPK_SPEEDUP, 0x00},
  126. {DSMIG_WB_DRC_RELEASE_TIME_1, 0x00},
  127. {DSMIG_WB_DRC_RELEASE_TIME_2, 0x00},
  128. {DSMIG_WB_DRC_ATTACK_TIME_1, 0x00},
  129. {DSMIG_WB_DRC_ATTACK_TIME_2, 0x00},
  130. {DSMIG_WB_DRC_COMPRESSION_RATIO, 0x00},
  131. {DSMIG_WB_DRC_COMPRESSION_THRESHOLD, 0x00},
  132. {DSMIG_WB_DRC_MAKEUPGAIN, 0x00},
  133. {DSMIG_WB_DRC_NOISE_GATE_THRESHOLD, 0x00},
  134. {DSMIG_WBDRC_HPF_ENABLE, 0x00},
  135. {DSMIG_WB_DRC_TEST_SMOOTHER_OUT_EN, 0x00},
  136. {DSMIG_PPR_THRESHOLD, 0x00},
  137. {DSM_STEREO_BASS_CHANNEL_SELECT, 0x00},
  138. {DSM_TPROT_THRESHOLD_BYTE0, 0x00},
  139. {DSM_TPROT_THRESHOLD_BYTE1, 0x00},
  140. {DSM_TPROT_ROOM_TEMPERATURE_BYTE0, 0x00},
  141. {DSM_TPROT_ROOM_TEMPERATURE_BYTE1, 0x00},
  142. {DSM_TPROT_RECIP_RDC_ROOM_BYTE0, 0x00},
  143. {DSM_TPROT_RECIP_RDC_ROOM_BYTE1, 0x00},
  144. {DSM_TPROT_RECIP_RDC_ROOM_BYTE2, 0x00},
  145. {DSM_TPROT_RECIP_TCONST_BYTE0, 0x00},
  146. {DSM_TPROT_RECIP_TCONST_BYTE1, 0x00},
  147. {DSM_TPROT_RECIP_TCONST_BYTE2, 0x00},
  148. {DSM_THERMAL_ATTENUATION_SETTINGS, 0x00},
  149. {DSM_THERMAL_PILOT_TONE_ATTENUATION, 0x00},
  150. {DSM_TPROT_PG_TEMP_THRESH_BYTE0, 0x00},
  151. {DSM_TPROT_PG_TEMP_THRESH_BYTE1, 0x00},
  152. {DSMIG_DEBUZZER_THRESHOLD, 0x00},
  153. {DSMIG_DEBUZZER_ALPHA_COEF_TEST_ONLY, 0x08},
  154. {DSM_VOL_ENA, 0x20},
  155. {DSM_VOL_CTRL, 0xa0},
  156. {DSMIG_EN, 0x00},
  157. {MAX98390_R23E1_DSP_GLOBAL_EN, 0x00},
  158. {MAX98390_R23FF_GLOBAL_EN, 0x00},
  159. };
  160. static int max98390_dsm_calibrate(struct snd_soc_component *component);
  161. static int max98390_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  162. {
  163. struct snd_soc_component *component = codec_dai->component;
  164. struct max98390_priv *max98390 =
  165. snd_soc_component_get_drvdata(component);
  166. unsigned int mode;
  167. unsigned int format;
  168. unsigned int invert = 0;
  169. dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
  170. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  171. case SND_SOC_DAIFMT_CBS_CFS:
  172. mode = MAX98390_PCM_MASTER_MODE_SLAVE;
  173. break;
  174. case SND_SOC_DAIFMT_CBM_CFM:
  175. max98390->master = true;
  176. mode = MAX98390_PCM_MASTER_MODE_MASTER;
  177. break;
  178. default:
  179. dev_err(component->dev, "DAI clock mode unsupported\n");
  180. return -EINVAL;
  181. }
  182. regmap_update_bits(max98390->regmap,
  183. MAX98390_PCM_MASTER_MODE,
  184. MAX98390_PCM_MASTER_MODE_MASK,
  185. mode);
  186. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  187. case SND_SOC_DAIFMT_NB_NF:
  188. break;
  189. case SND_SOC_DAIFMT_IB_NF:
  190. invert = MAX98390_PCM_MODE_CFG_PCM_BCLKEDGE;
  191. break;
  192. default:
  193. dev_err(component->dev, "DAI invert mode unsupported\n");
  194. return -EINVAL;
  195. }
  196. regmap_update_bits(max98390->regmap,
  197. MAX98390_PCM_MODE_CFG,
  198. MAX98390_PCM_MODE_CFG_PCM_BCLKEDGE,
  199. invert);
  200. /* interface format */
  201. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  202. case SND_SOC_DAIFMT_I2S:
  203. format = MAX98390_PCM_FORMAT_I2S;
  204. break;
  205. case SND_SOC_DAIFMT_LEFT_J:
  206. format = MAX98390_PCM_FORMAT_LJ;
  207. break;
  208. case SND_SOC_DAIFMT_DSP_A:
  209. format = MAX98390_PCM_FORMAT_TDM_MODE1;
  210. break;
  211. case SND_SOC_DAIFMT_DSP_B:
  212. format = MAX98390_PCM_FORMAT_TDM_MODE0;
  213. break;
  214. default:
  215. return -EINVAL;
  216. }
  217. regmap_update_bits(max98390->regmap,
  218. MAX98390_PCM_MODE_CFG,
  219. MAX98390_PCM_MODE_CFG_FORMAT_MASK,
  220. format << MAX98390_PCM_MODE_CFG_FORMAT_SHIFT);
  221. return 0;
  222. }
  223. static int max98390_get_bclk_sel(int bclk)
  224. {
  225. int i;
  226. /* BCLKs per LRCLK */
  227. static int bclk_sel_table[] = {
  228. 32, 48, 64, 96, 128, 192, 256, 320, 384, 512,
  229. };
  230. /* match BCLKs per LRCLK */
  231. for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
  232. if (bclk_sel_table[i] == bclk)
  233. return i + 2;
  234. }
  235. return 0;
  236. }
  237. static int max98390_set_clock(struct snd_soc_component *component,
  238. struct snd_pcm_hw_params *params)
  239. {
  240. struct max98390_priv *max98390 =
  241. snd_soc_component_get_drvdata(component);
  242. /* codec MCLK rate in master mode */
  243. static int rate_table[] = {
  244. 5644800, 6000000, 6144000, 6500000,
  245. 9600000, 11289600, 12000000, 12288000,
  246. 13000000, 19200000,
  247. };
  248. /* BCLK/LRCLK ratio calculation */
  249. int blr_clk_ratio = params_channels(params)
  250. * snd_pcm_format_width(params_format(params));
  251. int value;
  252. if (max98390->master) {
  253. int i;
  254. /* match rate to closest value */
  255. for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
  256. if (rate_table[i] >= max98390->sysclk)
  257. break;
  258. }
  259. if (i == ARRAY_SIZE(rate_table)) {
  260. dev_err(component->dev, "failed to find proper clock rate.\n");
  261. return -EINVAL;
  262. }
  263. regmap_update_bits(max98390->regmap,
  264. MAX98390_PCM_MASTER_MODE,
  265. MAX98390_PCM_MASTER_MODE_MCLK_MASK,
  266. i << MAX98390_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
  267. }
  268. if (!max98390->tdm_mode) {
  269. /* BCLK configuration */
  270. value = max98390_get_bclk_sel(blr_clk_ratio);
  271. if (!value) {
  272. dev_err(component->dev, "format unsupported %d\n",
  273. params_format(params));
  274. return -EINVAL;
  275. }
  276. regmap_update_bits(max98390->regmap,
  277. MAX98390_PCM_CLK_SETUP,
  278. MAX98390_PCM_CLK_SETUP_BSEL_MASK,
  279. value);
  280. }
  281. return 0;
  282. }
  283. static int max98390_dai_hw_params(struct snd_pcm_substream *substream,
  284. struct snd_pcm_hw_params *params,
  285. struct snd_soc_dai *dai)
  286. {
  287. struct snd_soc_component *component =
  288. dai->component;
  289. struct max98390_priv *max98390 =
  290. snd_soc_component_get_drvdata(component);
  291. unsigned int sampling_rate;
  292. unsigned int chan_sz;
  293. /* pcm mode configuration */
  294. switch (snd_pcm_format_width(params_format(params))) {
  295. case 16:
  296. chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_16;
  297. break;
  298. case 24:
  299. chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_24;
  300. break;
  301. case 32:
  302. chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_32;
  303. break;
  304. default:
  305. dev_err(component->dev, "format unsupported %d\n",
  306. params_format(params));
  307. goto err;
  308. }
  309. regmap_update_bits(max98390->regmap,
  310. MAX98390_PCM_MODE_CFG,
  311. MAX98390_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
  312. dev_dbg(component->dev, "format supported %d",
  313. params_format(params));
  314. /* sampling rate configuration */
  315. switch (params_rate(params)) {
  316. case 8000:
  317. sampling_rate = MAX98390_PCM_SR_SET1_SR_8000;
  318. break;
  319. case 11025:
  320. sampling_rate = MAX98390_PCM_SR_SET1_SR_11025;
  321. break;
  322. case 12000:
  323. sampling_rate = MAX98390_PCM_SR_SET1_SR_12000;
  324. break;
  325. case 16000:
  326. sampling_rate = MAX98390_PCM_SR_SET1_SR_16000;
  327. break;
  328. case 22050:
  329. sampling_rate = MAX98390_PCM_SR_SET1_SR_22050;
  330. break;
  331. case 24000:
  332. sampling_rate = MAX98390_PCM_SR_SET1_SR_24000;
  333. break;
  334. case 32000:
  335. sampling_rate = MAX98390_PCM_SR_SET1_SR_32000;
  336. break;
  337. case 44100:
  338. sampling_rate = MAX98390_PCM_SR_SET1_SR_44100;
  339. break;
  340. case 48000:
  341. sampling_rate = MAX98390_PCM_SR_SET1_SR_48000;
  342. break;
  343. default:
  344. dev_err(component->dev, "rate %d not supported\n",
  345. params_rate(params));
  346. goto err;
  347. }
  348. /* set DAI_SR to correct LRCLK frequency */
  349. regmap_update_bits(max98390->regmap,
  350. MAX98390_PCM_SR_SETUP,
  351. MAX98390_PCM_SR_SET1_SR_MASK,
  352. sampling_rate);
  353. return max98390_set_clock(component, params);
  354. err:
  355. return -EINVAL;
  356. }
  357. static int max98390_dai_tdm_slot(struct snd_soc_dai *dai,
  358. unsigned int tx_mask, unsigned int rx_mask,
  359. int slots, int slot_width)
  360. {
  361. struct snd_soc_component *component = dai->component;
  362. struct max98390_priv *max98390 =
  363. snd_soc_component_get_drvdata(component);
  364. int bsel;
  365. unsigned int chan_sz;
  366. if (!tx_mask && !rx_mask && !slots && !slot_width)
  367. max98390->tdm_mode = false;
  368. else
  369. max98390->tdm_mode = true;
  370. dev_dbg(component->dev,
  371. "Tdm mode : %d\n", max98390->tdm_mode);
  372. /* BCLK configuration */
  373. bsel = max98390_get_bclk_sel(slots * slot_width);
  374. if (!bsel) {
  375. dev_err(component->dev, "BCLK %d not supported\n",
  376. slots * slot_width);
  377. return -EINVAL;
  378. }
  379. regmap_update_bits(max98390->regmap,
  380. MAX98390_PCM_CLK_SETUP,
  381. MAX98390_PCM_CLK_SETUP_BSEL_MASK,
  382. bsel);
  383. /* Channel size configuration */
  384. switch (slot_width) {
  385. case 16:
  386. chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_16;
  387. break;
  388. case 24:
  389. chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_24;
  390. break;
  391. case 32:
  392. chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_32;
  393. break;
  394. default:
  395. dev_err(component->dev, "format unsupported %d\n",
  396. slot_width);
  397. return -EINVAL;
  398. }
  399. regmap_update_bits(max98390->regmap,
  400. MAX98390_PCM_MODE_CFG,
  401. MAX98390_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
  402. /* Rx slot configuration */
  403. regmap_write(max98390->regmap,
  404. MAX98390_PCM_RX_EN_A,
  405. rx_mask & 0xFF);
  406. regmap_write(max98390->regmap,
  407. MAX98390_PCM_RX_EN_B,
  408. (rx_mask & 0xFF00) >> 8);
  409. /* Tx slot Hi-Z configuration */
  410. regmap_write(max98390->regmap,
  411. MAX98390_PCM_TX_HIZ_CTRL_A,
  412. ~tx_mask & 0xFF);
  413. regmap_write(max98390->regmap,
  414. MAX98390_PCM_TX_HIZ_CTRL_B,
  415. (~tx_mask & 0xFF00) >> 8);
  416. return 0;
  417. }
  418. static int max98390_dai_set_sysclk(struct snd_soc_dai *dai,
  419. int clk_id, unsigned int freq, int dir)
  420. {
  421. struct snd_soc_component *component = dai->component;
  422. struct max98390_priv *max98390 =
  423. snd_soc_component_get_drvdata(component);
  424. max98390->sysclk = freq;
  425. return 0;
  426. }
  427. static const struct snd_soc_dai_ops max98390_dai_ops = {
  428. .set_sysclk = max98390_dai_set_sysclk,
  429. .set_fmt = max98390_dai_set_fmt,
  430. .hw_params = max98390_dai_hw_params,
  431. .set_tdm_slot = max98390_dai_tdm_slot,
  432. };
  433. static int max98390_dac_event(struct snd_soc_dapm_widget *w,
  434. struct snd_kcontrol *kcontrol, int event)
  435. {
  436. struct snd_soc_component *component =
  437. snd_soc_dapm_to_component(w->dapm);
  438. struct max98390_priv *max98390 =
  439. snd_soc_component_get_drvdata(component);
  440. switch (event) {
  441. case SND_SOC_DAPM_POST_PMU:
  442. regmap_update_bits(max98390->regmap,
  443. MAX98390_R203A_AMP_EN,
  444. MAX98390_AMP_EN_MASK, 1);
  445. regmap_update_bits(max98390->regmap,
  446. MAX98390_R23FF_GLOBAL_EN,
  447. MAX98390_GLOBAL_EN_MASK, 1);
  448. break;
  449. case SND_SOC_DAPM_POST_PMD:
  450. regmap_update_bits(max98390->regmap,
  451. MAX98390_R23FF_GLOBAL_EN,
  452. MAX98390_GLOBAL_EN_MASK, 0);
  453. regmap_update_bits(max98390->regmap,
  454. MAX98390_R203A_AMP_EN,
  455. MAX98390_AMP_EN_MASK, 0);
  456. break;
  457. }
  458. return 0;
  459. }
  460. static const char * const max98390_switch_text[] = {
  461. "Left", "Right", "LeftRight"};
  462. static const char * const max98390_boost_voltage_text[] = {
  463. "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
  464. "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
  465. "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
  466. "9.5V", "9.625V", "9.75V", "9.875V", "10V"
  467. };
  468. static SOC_ENUM_SINGLE_DECL(max98390_boost_voltage,
  469. MAX98390_BOOST_CTRL0, 0,
  470. max98390_boost_voltage_text);
  471. static DECLARE_TLV_DB_SCALE(max98390_spk_tlv, 300, 300, 0);
  472. static DECLARE_TLV_DB_SCALE(max98390_digital_tlv, -8000, 50, 0);
  473. static const char * const max98390_current_limit_text[] = {
  474. "0.00A", "0.50A", "1.00A", "1.05A", "1.10A", "1.15A", "1.20A", "1.25A",
  475. "1.30A", "1.35A", "1.40A", "1.45A", "1.50A", "1.55A", "1.60A", "1.65A",
  476. "1.70A", "1.75A", "1.80A", "1.85A", "1.90A", "1.95A", "2.00A", "2.05A",
  477. "2.10A", "2.15A", "2.20A", "2.25A", "2.30A", "2.35A", "2.40A", "2.45A",
  478. "2.50A", "2.55A", "2.60A", "2.65A", "2.70A", "2.75A", "2.80A", "2.85A",
  479. "2.90A", "2.95A", "3.00A", "3.05A", "3.10A", "3.15A", "3.20A", "3.25A",
  480. "3.30A", "3.35A", "3.40A", "3.45A", "3.50A", "3.55A", "3.60A", "3.65A",
  481. "3.70A", "3.75A", "3.80A", "3.85A", "3.90A", "3.95A", "4.00A", "4.05A",
  482. "4.10A"
  483. };
  484. static SOC_ENUM_SINGLE_DECL(max98390_current_limit,
  485. MAX98390_BOOST_CTRL1, 0,
  486. max98390_current_limit_text);
  487. static int max98390_ref_rdc_put(struct snd_kcontrol *kcontrol,
  488. struct snd_ctl_elem_value *ucontrol)
  489. {
  490. struct snd_soc_component *component =
  491. snd_soc_kcontrol_component(kcontrol);
  492. struct max98390_priv *max98390 =
  493. snd_soc_component_get_drvdata(component);
  494. max98390->ref_rdc_value = ucontrol->value.integer.value[0];
  495. regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE0,
  496. max98390->ref_rdc_value & 0x000000ff);
  497. regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE1,
  498. (max98390->ref_rdc_value >> 8) & 0x000000ff);
  499. regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE2,
  500. (max98390->ref_rdc_value >> 16) & 0x000000ff);
  501. return 0;
  502. }
  503. static int max98390_ref_rdc_get(struct snd_kcontrol *kcontrol,
  504. struct snd_ctl_elem_value *ucontrol)
  505. {
  506. struct snd_soc_component *component =
  507. snd_soc_kcontrol_component(kcontrol);
  508. struct max98390_priv *max98390 =
  509. snd_soc_component_get_drvdata(component);
  510. ucontrol->value.integer.value[0] = max98390->ref_rdc_value;
  511. return 0;
  512. }
  513. static int max98390_ambient_temp_put(struct snd_kcontrol *kcontrol,
  514. struct snd_ctl_elem_value *ucontrol)
  515. {
  516. struct snd_soc_component *component =
  517. snd_soc_kcontrol_component(kcontrol);
  518. struct max98390_priv *max98390 =
  519. snd_soc_component_get_drvdata(component);
  520. max98390->ambient_temp_value = ucontrol->value.integer.value[0];
  521. regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE1,
  522. (max98390->ambient_temp_value >> 8) & 0x000000ff);
  523. regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE0,
  524. (max98390->ambient_temp_value) & 0x000000ff);
  525. return 0;
  526. }
  527. static int max98390_ambient_temp_get(struct snd_kcontrol *kcontrol,
  528. struct snd_ctl_elem_value *ucontrol)
  529. {
  530. struct snd_soc_component *component =
  531. snd_soc_kcontrol_component(kcontrol);
  532. struct max98390_priv *max98390 =
  533. snd_soc_component_get_drvdata(component);
  534. ucontrol->value.integer.value[0] = max98390->ambient_temp_value;
  535. return 0;
  536. }
  537. static int max98390_adaptive_rdc_put(struct snd_kcontrol *kcontrol,
  538. struct snd_ctl_elem_value *ucontrol)
  539. {
  540. struct snd_soc_component *component =
  541. snd_soc_kcontrol_component(kcontrol);
  542. dev_warn(component->dev, "Put adaptive rdc not supported\n");
  543. return 0;
  544. }
  545. static int max98390_adaptive_rdc_get(struct snd_kcontrol *kcontrol,
  546. struct snd_ctl_elem_value *ucontrol)
  547. {
  548. int rdc, rdc0;
  549. struct snd_soc_component *component =
  550. snd_soc_kcontrol_component(kcontrol);
  551. struct max98390_priv *max98390 =
  552. snd_soc_component_get_drvdata(component);
  553. regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE1, &rdc);
  554. regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE0, &rdc0);
  555. ucontrol->value.integer.value[0] = rdc0 | rdc << 8;
  556. return 0;
  557. }
  558. static int max98390_dsm_calib_get(struct snd_kcontrol *kcontrol,
  559. struct snd_ctl_elem_value *ucontrol)
  560. {
  561. /* Do nothing */
  562. return 0;
  563. }
  564. static int max98390_dsm_calib_put(struct snd_kcontrol *kcontrol,
  565. struct snd_ctl_elem_value *ucontrol)
  566. {
  567. struct snd_soc_component *component =
  568. snd_soc_kcontrol_component(kcontrol);
  569. max98390_dsm_calibrate(component);
  570. return 0;
  571. }
  572. static const struct snd_kcontrol_new max98390_snd_controls[] = {
  573. SOC_SINGLE_TLV("Digital Volume", DSM_VOL_CTRL,
  574. 0, 184, 0,
  575. max98390_digital_tlv),
  576. SOC_SINGLE_TLV("Speaker Volume", MAX98390_R203D_SPK_GAIN,
  577. 0, 6, 0,
  578. max98390_spk_tlv),
  579. SOC_SINGLE("Ramp Up Bypass Switch", MAX98390_R2039_AMP_DSP_CFG,
  580. MAX98390_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
  581. SOC_SINGLE("Ramp Down Bypass Switch", MAX98390_R2039_AMP_DSP_CFG,
  582. MAX98390_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
  583. SOC_SINGLE("Boost Clock Phase", MAX98390_BOOST_CTRL3,
  584. MAX98390_BOOST_CLK_PHASE_CFG_SHIFT, 3, 0),
  585. SOC_ENUM("Boost Output Voltage", max98390_boost_voltage),
  586. SOC_ENUM("Current Limit", max98390_current_limit),
  587. SOC_SINGLE_EXT("DSM Rdc", SND_SOC_NOPM, 0, 0xffffff, 0,
  588. max98390_ref_rdc_get, max98390_ref_rdc_put),
  589. SOC_SINGLE_EXT("DSM Ambient Temp", SND_SOC_NOPM, 0, 0xffff, 0,
  590. max98390_ambient_temp_get, max98390_ambient_temp_put),
  591. SOC_SINGLE_EXT("DSM Adaptive Rdc", SND_SOC_NOPM, 0, 0xffff, 0,
  592. max98390_adaptive_rdc_get, max98390_adaptive_rdc_put),
  593. SOC_SINGLE_EXT("DSM Calibration", SND_SOC_NOPM, 0, 1, 0,
  594. max98390_dsm_calib_get, max98390_dsm_calib_put),
  595. };
  596. static const struct soc_enum dai_sel_enum =
  597. SOC_ENUM_SINGLE(MAX98390_PCM_CH_SRC_1,
  598. MAX98390_PCM_RX_CH_SRC_SHIFT,
  599. 3, max98390_switch_text);
  600. static const struct snd_kcontrol_new max98390_dai_controls =
  601. SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
  602. static const struct snd_soc_dapm_widget max98390_dapm_widgets[] = {
  603. SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
  604. SND_SOC_NOPM, 0, 0, max98390_dac_event,
  605. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  606. SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
  607. &max98390_dai_controls),
  608. SND_SOC_DAPM_OUTPUT("BE_OUT"),
  609. };
  610. static const struct snd_soc_dapm_route max98390_audio_map[] = {
  611. /* Plabyack */
  612. {"DAI Sel Mux", "Left", "Amp Enable"},
  613. {"DAI Sel Mux", "Right", "Amp Enable"},
  614. {"DAI Sel Mux", "LeftRight", "Amp Enable"},
  615. {"BE_OUT", NULL, "DAI Sel Mux"},
  616. };
  617. static bool max98390_readable_register(struct device *dev, unsigned int reg)
  618. {
  619. switch (reg) {
  620. case MAX98390_SOFTWARE_RESET ... MAX98390_INT_EN3:
  621. case MAX98390_IRQ_CTRL ... MAX98390_WDOG_CTRL:
  622. case MAX98390_MEAS_ADC_THERM_WARN_THRESH
  623. ... MAX98390_BROWNOUT_INFINITE_HOLD:
  624. case MAX98390_BROWNOUT_LVL_HOLD ... DSMIG_DEBUZZER_THRESHOLD:
  625. case DSM_VOL_ENA ... MAX98390_R24FF_REV_ID:
  626. return true;
  627. default:
  628. return false;
  629. }
  630. };
  631. static bool max98390_volatile_reg(struct device *dev, unsigned int reg)
  632. {
  633. switch (reg) {
  634. case MAX98390_SOFTWARE_RESET ... MAX98390_INT_EN3:
  635. case MAX98390_MEAS_ADC_CH0_READ ... MAX98390_MEAS_ADC_CH2_READ:
  636. case MAX98390_PWR_GATE_STATUS ... MAX98390_BROWNOUT_STATUS:
  637. case MAX98390_BROWNOUT_LOWEST_STATUS:
  638. case MAX98390_ENV_TRACK_BOOST_VOUT_READ:
  639. case DSM_STBASS_HPF_B0_BYTE0 ... DSM_DEBUZZER_ATTACK_TIME_BYTE2:
  640. case THERMAL_RDC_RD_BACK_BYTE1 ... DSMIG_DEBUZZER_THRESHOLD:
  641. case DSM_THERMAL_GAIN ... DSM_WBDRC_GAIN:
  642. return true;
  643. default:
  644. return false;
  645. }
  646. }
  647. #define MAX98390_RATES SNDRV_PCM_RATE_8000_48000
  648. #define MAX98390_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  649. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  650. static struct snd_soc_dai_driver max98390_dai[] = {
  651. {
  652. .name = "max98390-aif1",
  653. .playback = {
  654. .stream_name = "HiFi Playback",
  655. .channels_min = 1,
  656. .channels_max = 2,
  657. .rates = MAX98390_RATES,
  658. .formats = MAX98390_FORMATS,
  659. },
  660. .capture = {
  661. .stream_name = "HiFi Capture",
  662. .channels_min = 1,
  663. .channels_max = 2,
  664. .rates = MAX98390_RATES,
  665. .formats = MAX98390_FORMATS,
  666. },
  667. .ops = &max98390_dai_ops,
  668. }
  669. };
  670. static int max98390_dsm_init(struct snd_soc_component *component)
  671. {
  672. int ret;
  673. int param_size, param_start_addr;
  674. char filename[128];
  675. const char *vendor, *product;
  676. struct max98390_priv *max98390 =
  677. snd_soc_component_get_drvdata(component);
  678. const struct firmware *fw;
  679. char *dsm_param;
  680. vendor = dmi_get_system_info(DMI_SYS_VENDOR);
  681. product = dmi_get_system_info(DMI_PRODUCT_NAME);
  682. if (vendor && product) {
  683. snprintf(filename, sizeof(filename), "dsm_param_%s_%s.bin",
  684. vendor, product);
  685. } else {
  686. sprintf(filename, "dsm_param.bin");
  687. }
  688. ret = request_firmware(&fw, filename, component->dev);
  689. if (ret) {
  690. ret = request_firmware(&fw, "dsm_param.bin", component->dev);
  691. if (ret)
  692. goto err;
  693. }
  694. dev_dbg(component->dev,
  695. "max98390: param fw size %zd\n",
  696. fw->size);
  697. if (fw->size < MAX98390_DSM_PARAM_MIN_SIZE) {
  698. dev_err(component->dev,
  699. "param fw is invalid.\n");
  700. ret = -EINVAL;
  701. goto err_alloc;
  702. }
  703. dsm_param = (char *)fw->data;
  704. param_start_addr = (dsm_param[0] & 0xff) | (dsm_param[1] & 0xff) << 8;
  705. param_size = (dsm_param[2] & 0xff) | (dsm_param[3] & 0xff) << 8;
  706. if (param_size > MAX98390_DSM_PARAM_MAX_SIZE ||
  707. param_start_addr < MAX98390_IRQ_CTRL ||
  708. fw->size < param_size + MAX98390_DSM_PAYLOAD_OFFSET) {
  709. dev_err(component->dev,
  710. "param fw is invalid.\n");
  711. ret = -EINVAL;
  712. goto err_alloc;
  713. }
  714. regmap_write(max98390->regmap, MAX98390_R203A_AMP_EN, 0x80);
  715. dsm_param += MAX98390_DSM_PAYLOAD_OFFSET;
  716. regmap_bulk_write(max98390->regmap, param_start_addr,
  717. dsm_param, param_size);
  718. regmap_write(max98390->regmap, MAX98390_R23E1_DSP_GLOBAL_EN, 0x01);
  719. err_alloc:
  720. release_firmware(fw);
  721. err:
  722. return ret;
  723. }
  724. static int max98390_dsm_calibrate(struct snd_soc_component *component)
  725. {
  726. unsigned int rdc, rdc_cal_result, temp;
  727. unsigned int rdc_integer, rdc_factor;
  728. struct max98390_priv *max98390 =
  729. snd_soc_component_get_drvdata(component);
  730. regmap_write(max98390->regmap, MAX98390_R203A_AMP_EN, 0x81);
  731. regmap_write(max98390->regmap, MAX98390_R23FF_GLOBAL_EN, 0x01);
  732. regmap_read(max98390->regmap,
  733. THERMAL_RDC_RD_BACK_BYTE1, &rdc);
  734. regmap_read(max98390->regmap,
  735. THERMAL_RDC_RD_BACK_BYTE0, &rdc_cal_result);
  736. rdc_cal_result |= (rdc << 8) & 0x0000FFFF;
  737. if (rdc_cal_result)
  738. max98390->ref_rdc_value = 268435456U / rdc_cal_result;
  739. regmap_read(max98390->regmap, MAX98390_MEAS_ADC_CH2_READ, &temp);
  740. max98390->ambient_temp_value = temp * 52 - 1188;
  741. rdc_integer = rdc_cal_result * 937 / 65536;
  742. rdc_factor = ((rdc_cal_result * 937 * 100) / 65536)
  743. - (rdc_integer * 100);
  744. dev_info(component->dev, "rdc resistance about %d.%02d ohm, reg=0x%X temp reg=0x%X\n",
  745. rdc_integer, rdc_factor, rdc_cal_result, temp);
  746. regmap_write(max98390->regmap, MAX98390_R23FF_GLOBAL_EN, 0x00);
  747. regmap_write(max98390->regmap, MAX98390_R203A_AMP_EN, 0x80);
  748. return 0;
  749. }
  750. static void max98390_init_regs(struct snd_soc_component *component)
  751. {
  752. struct max98390_priv *max98390 =
  753. snd_soc_component_get_drvdata(component);
  754. regmap_write(max98390->regmap, MAX98390_CLK_MON, 0x6f);
  755. regmap_write(max98390->regmap, MAX98390_DAT_MON, 0x00);
  756. regmap_write(max98390->regmap, MAX98390_PWR_GATE_CTL, 0x00);
  757. regmap_write(max98390->regmap, MAX98390_PCM_RX_EN_A, 0x03);
  758. regmap_write(max98390->regmap, MAX98390_ENV_TRACK_VOUT_HEADROOM, 0x0e);
  759. regmap_write(max98390->regmap, MAX98390_BOOST_BYPASS1, 0x46);
  760. regmap_write(max98390->regmap, MAX98390_FET_SCALING3, 0x03);
  761. }
  762. static int max98390_probe(struct snd_soc_component *component)
  763. {
  764. struct max98390_priv *max98390 =
  765. snd_soc_component_get_drvdata(component);
  766. regmap_write(max98390->regmap, MAX98390_SOFTWARE_RESET, 0x01);
  767. /* Sleep reset settle time */
  768. msleep(20);
  769. /* Amp init setting */
  770. max98390_init_regs(component);
  771. /* Update dsm bin param */
  772. max98390_dsm_init(component);
  773. /* Dsm Setting */
  774. if (max98390->ref_rdc_value) {
  775. regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE0,
  776. max98390->ref_rdc_value & 0x000000ff);
  777. regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE1,
  778. (max98390->ref_rdc_value >> 8) & 0x000000ff);
  779. regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE2,
  780. (max98390->ref_rdc_value >> 16) & 0x000000ff);
  781. }
  782. if (max98390->ambient_temp_value) {
  783. regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE1,
  784. (max98390->ambient_temp_value >> 8) & 0x000000ff);
  785. regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE0,
  786. (max98390->ambient_temp_value) & 0x000000ff);
  787. }
  788. return 0;
  789. }
  790. #ifdef CONFIG_PM_SLEEP
  791. static int max98390_suspend(struct device *dev)
  792. {
  793. struct max98390_priv *max98390 = dev_get_drvdata(dev);
  794. dev_dbg(dev, "%s:Enter\n", __func__);
  795. regcache_cache_only(max98390->regmap, true);
  796. regcache_mark_dirty(max98390->regmap);
  797. return 0;
  798. }
  799. static int max98390_resume(struct device *dev)
  800. {
  801. struct max98390_priv *max98390 = dev_get_drvdata(dev);
  802. dev_dbg(dev, "%s:Enter\n", __func__);
  803. regcache_cache_only(max98390->regmap, false);
  804. regcache_sync(max98390->regmap);
  805. return 0;
  806. }
  807. #endif
  808. static const struct dev_pm_ops max98390_pm = {
  809. SET_SYSTEM_SLEEP_PM_OPS(max98390_suspend, max98390_resume)
  810. };
  811. static const struct snd_soc_component_driver soc_codec_dev_max98390 = {
  812. .probe = max98390_probe,
  813. .controls = max98390_snd_controls,
  814. .num_controls = ARRAY_SIZE(max98390_snd_controls),
  815. .dapm_widgets = max98390_dapm_widgets,
  816. .num_dapm_widgets = ARRAY_SIZE(max98390_dapm_widgets),
  817. .dapm_routes = max98390_audio_map,
  818. .num_dapm_routes = ARRAY_SIZE(max98390_audio_map),
  819. .idle_bias_on = 1,
  820. .use_pmdown_time = 1,
  821. .endianness = 1,
  822. .non_legacy_dai_naming = 1,
  823. };
  824. static const struct regmap_config max98390_regmap = {
  825. .reg_bits = 16,
  826. .val_bits = 8,
  827. .max_register = MAX98390_R24FF_REV_ID,
  828. .reg_defaults = max98390_reg_defaults,
  829. .num_reg_defaults = ARRAY_SIZE(max98390_reg_defaults),
  830. .readable_reg = max98390_readable_register,
  831. .volatile_reg = max98390_volatile_reg,
  832. .cache_type = REGCACHE_RBTREE,
  833. };
  834. static int max98390_i2c_probe(struct i2c_client *i2c,
  835. const struct i2c_device_id *id)
  836. {
  837. int ret = 0;
  838. int reg = 0;
  839. struct max98390_priv *max98390 = NULL;
  840. struct i2c_adapter *adapter = to_i2c_adapter(i2c->dev.parent);
  841. ret = i2c_check_functionality(adapter,
  842. I2C_FUNC_SMBUS_BYTE
  843. | I2C_FUNC_SMBUS_BYTE_DATA);
  844. if (!ret) {
  845. dev_err(&i2c->dev, "I2C check functionality failed\n");
  846. return -ENXIO;
  847. }
  848. max98390 = devm_kzalloc(&i2c->dev, sizeof(*max98390), GFP_KERNEL);
  849. if (!max98390) {
  850. ret = -ENOMEM;
  851. return ret;
  852. }
  853. i2c_set_clientdata(i2c, max98390);
  854. ret = device_property_read_u32(&i2c->dev, "maxim,temperature_calib",
  855. &max98390->ambient_temp_value);
  856. if (ret) {
  857. dev_info(&i2c->dev,
  858. "no optional property 'temperature_calib' found, default:\n");
  859. }
  860. ret = device_property_read_u32(&i2c->dev, "maxim,r0_calib",
  861. &max98390->ref_rdc_value);
  862. if (ret) {
  863. dev_info(&i2c->dev,
  864. "no optional property 'r0_calib' found, default:\n");
  865. }
  866. dev_info(&i2c->dev,
  867. "%s: r0_calib: 0x%x,temperature_calib: 0x%x",
  868. __func__, max98390->ref_rdc_value,
  869. max98390->ambient_temp_value);
  870. /* regmap initialization */
  871. max98390->regmap = devm_regmap_init_i2c(i2c, &max98390_regmap);
  872. if (IS_ERR(max98390->regmap)) {
  873. ret = PTR_ERR(max98390->regmap);
  874. dev_err(&i2c->dev,
  875. "Failed to allocate regmap: %d\n", ret);
  876. return ret;
  877. }
  878. /* Check Revision ID */
  879. ret = regmap_read(max98390->regmap,
  880. MAX98390_R24FF_REV_ID, &reg);
  881. if (ret) {
  882. dev_err(&i2c->dev,
  883. "ret=%d, Failed to read: 0x%02X\n",
  884. ret, MAX98390_R24FF_REV_ID);
  885. return ret;
  886. }
  887. dev_info(&i2c->dev, "MAX98390 revisionID: 0x%02X\n", reg);
  888. ret = devm_snd_soc_register_component(&i2c->dev,
  889. &soc_codec_dev_max98390,
  890. max98390_dai, ARRAY_SIZE(max98390_dai));
  891. return ret;
  892. }
  893. static const struct i2c_device_id max98390_i2c_id[] = {
  894. { "max98390", 0},
  895. {},
  896. };
  897. MODULE_DEVICE_TABLE(i2c, max98390_i2c_id);
  898. #if defined(CONFIG_OF)
  899. static const struct of_device_id max98390_of_match[] = {
  900. { .compatible = "maxim,max98390", },
  901. {}
  902. };
  903. MODULE_DEVICE_TABLE(of, max98390_of_match);
  904. #endif
  905. #ifdef CONFIG_ACPI
  906. static const struct acpi_device_id max98390_acpi_match[] = {
  907. { "MX98390", 0 },
  908. {},
  909. };
  910. MODULE_DEVICE_TABLE(acpi, max98390_acpi_match);
  911. #endif
  912. static struct i2c_driver max98390_i2c_driver = {
  913. .driver = {
  914. .name = "max98390",
  915. .of_match_table = of_match_ptr(max98390_of_match),
  916. .acpi_match_table = ACPI_PTR(max98390_acpi_match),
  917. .pm = &max98390_pm,
  918. },
  919. .probe = max98390_i2c_probe,
  920. .id_table = max98390_i2c_id,
  921. };
  922. module_i2c_driver(max98390_i2c_driver)
  923. MODULE_DESCRIPTION("ALSA SoC MAX98390 driver");
  924. MODULE_AUTHOR("Steve Lee <steves.lee@maximintegrated.com>");
  925. MODULE_LICENSE("GPL");