max98373.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2017, Maxim Integrated
  3. #include <linux/acpi.h>
  4. #include <linux/delay.h>
  5. #include <linux/i2c.h>
  6. #include <linux/module.h>
  7. #include <linux/regmap.h>
  8. #include <linux/slab.h>
  9. #include <linux/cdev.h>
  10. #include <sound/pcm.h>
  11. #include <sound/pcm_params.h>
  12. #include <sound/soc.h>
  13. #include <linux/gpio.h>
  14. #include <linux/of.h>
  15. #include <linux/of_gpio.h>
  16. #include <sound/tlv.h>
  17. #include "max98373.h"
  18. static int max98373_dac_event(struct snd_soc_dapm_widget *w,
  19. struct snd_kcontrol *kcontrol, int event)
  20. {
  21. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  22. struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
  23. switch (event) {
  24. case SND_SOC_DAPM_POST_PMU:
  25. regmap_update_bits(max98373->regmap,
  26. MAX98373_R20FF_GLOBAL_SHDN,
  27. MAX98373_GLOBAL_EN_MASK, 1);
  28. usleep_range(30000, 31000);
  29. break;
  30. case SND_SOC_DAPM_POST_PMD:
  31. regmap_update_bits(max98373->regmap,
  32. MAX98373_R20FF_GLOBAL_SHDN,
  33. MAX98373_GLOBAL_EN_MASK, 0);
  34. usleep_range(30000, 31000);
  35. max98373->tdm_mode = false;
  36. break;
  37. default:
  38. return 0;
  39. }
  40. return 0;
  41. }
  42. static const char * const max98373_switch_text[] = {
  43. "Left", "Right", "LeftRight"};
  44. static const struct soc_enum dai_sel_enum =
  45. SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
  46. MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
  47. 3, max98373_switch_text);
  48. static const struct snd_kcontrol_new max98373_dai_controls =
  49. SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
  50. static const struct snd_kcontrol_new max98373_vi_control =
  51. SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
  52. static const struct snd_kcontrol_new max98373_spkfb_control =
  53. SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
  54. static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
  55. SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
  56. MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
  57. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  58. SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
  59. &max98373_dai_controls),
  60. SND_SOC_DAPM_OUTPUT("BE_OUT"),
  61. SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
  62. MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
  63. SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
  64. MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
  65. SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
  66. SND_SOC_NOPM, 0, 0),
  67. SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
  68. &max98373_vi_control),
  69. SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
  70. &max98373_spkfb_control),
  71. SND_SOC_DAPM_SIGGEN("VMON"),
  72. SND_SOC_DAPM_SIGGEN("IMON"),
  73. SND_SOC_DAPM_SIGGEN("FBMON"),
  74. };
  75. static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
  76. static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
  77. 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
  78. 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
  79. );
  80. static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
  81. 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
  82. );
  83. static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
  84. 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
  85. 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
  86. );
  87. static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
  88. 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
  89. );
  90. static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
  91. 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
  92. 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
  93. 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
  94. 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
  95. 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
  96. 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
  97. );
  98. static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
  99. 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
  100. );
  101. static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
  102. 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0),
  103. );
  104. static const char * const max98373_output_voltage_lvl_text[] = {
  105. "5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
  106. "9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
  107. };
  108. static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
  109. MAX98373_R203E_AMP_PATH_GAIN, 0,
  110. max98373_output_voltage_lvl_text);
  111. static const char * const max98373_dht_attack_rate_text[] = {
  112. "17.5us", "35us", "70us", "140us",
  113. "280us", "560us", "1120us", "2240us"
  114. };
  115. static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
  116. MAX98373_R20D2_DHT_ATTACK_CFG, 0,
  117. max98373_dht_attack_rate_text);
  118. static const char * const max98373_dht_release_rate_text[] = {
  119. "45ms", "225ms", "450ms", "1150ms",
  120. "2250ms", "3100ms", "4500ms", "6750ms"
  121. };
  122. static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
  123. MAX98373_R20D3_DHT_RELEASE_CFG, 0,
  124. max98373_dht_release_rate_text);
  125. static const char * const max98373_limiter_attack_rate_text[] = {
  126. "10us", "20us", "40us", "80us",
  127. "160us", "320us", "640us", "1.28ms",
  128. "2.56ms", "5.12ms", "10.24ms", "20.48ms",
  129. "40.96ms", "81.92ms", "16.384ms", "32.768ms"
  130. };
  131. static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
  132. MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
  133. max98373_limiter_attack_rate_text);
  134. static const char * const max98373_limiter_release_rate_text[] = {
  135. "40us", "80us", "160us", "320us",
  136. "640us", "1.28ms", "2.56ms", "5.120ms",
  137. "10.24ms", "20.48ms", "40.96ms", "81.92ms",
  138. "163.84ms", "327.68ms", "655.36ms", "1310.72ms"
  139. };
  140. static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
  141. MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
  142. max98373_limiter_release_rate_text);
  143. static const char * const max98373_ADC_samplerate_text[] = {
  144. "333kHz", "192kHz", "64kHz", "48kHz"
  145. };
  146. static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
  147. MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
  148. max98373_ADC_samplerate_text);
  149. static const struct snd_kcontrol_new max98373_snd_controls[] = {
  150. SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
  151. MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
  152. SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
  153. MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
  154. SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
  155. MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
  156. SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
  157. MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
  158. SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
  159. MAX98373_CLOCK_MON_SHIFT, 1, 0),
  160. SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
  161. MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
  162. SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
  163. MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
  164. SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
  165. 0, 0x7F, 1, max98373_digital_tlv),
  166. SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
  167. MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
  168. SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
  169. MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
  170. SOC_ENUM("Output Voltage", max98373_out_volt_enum),
  171. /* Dynamic Headroom Tracking */
  172. SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
  173. MAX98373_DHT_EN_SHIFT, 1, 0),
  174. SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
  175. MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
  176. SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
  177. MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv),
  178. SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
  179. MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
  180. SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
  181. MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
  182. SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
  183. SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
  184. /* ADC configuration */
  185. SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
  186. SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
  187. MAX98373_FLT_EN_SHIFT, 1, 0),
  188. SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
  189. MAX98373_FLT_EN_SHIFT, 1, 0),
  190. SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0),
  191. SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0),
  192. SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
  193. 0, 0x3, 0),
  194. SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
  195. 0, 0x3, 0),
  196. SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
  197. /* Brownout Detection Engine */
  198. SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
  199. SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
  200. MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
  201. SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
  202. MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
  203. SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
  204. SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
  205. SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
  206. SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
  207. SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0),
  208. SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
  209. SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
  210. SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
  211. SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
  212. SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
  213. SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
  214. 0, 0x3C, 1, max98373_bde_gain_tlv),
  215. SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
  216. 0, 0x3C, 1, max98373_bde_gain_tlv),
  217. SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
  218. 0, 0x3C, 1, max98373_bde_gain_tlv),
  219. SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
  220. 0, 0x3C, 1, max98373_bde_gain_tlv),
  221. SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
  222. 0, 0x3C, 1, max98373_bde_gain_tlv),
  223. SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
  224. 0, 0x3C, 1, max98373_bde_gain_tlv),
  225. SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
  226. 0, 0x3C, 1, max98373_bde_gain_tlv),
  227. SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
  228. 0, 0x3C, 1, max98373_bde_gain_tlv),
  229. SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
  230. 0, 0xF, 1, max98373_limiter_thresh_tlv),
  231. SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
  232. 0, 0xF, 1, max98373_limiter_thresh_tlv),
  233. SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
  234. 0, 0xF, 1, max98373_limiter_thresh_tlv),
  235. SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
  236. 0, 0xF, 1, max98373_limiter_thresh_tlv),
  237. /* Limiter */
  238. SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
  239. MAX98373_LIMITER_EN_SHIFT, 1, 0),
  240. SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
  241. MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
  242. SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
  243. MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
  244. SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
  245. SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
  246. };
  247. static const struct snd_soc_dapm_route max98373_audio_map[] = {
  248. /* Plabyack */
  249. {"DAI Sel Mux", "Left", "Amp Enable"},
  250. {"DAI Sel Mux", "Right", "Amp Enable"},
  251. {"DAI Sel Mux", "LeftRight", "Amp Enable"},
  252. {"BE_OUT", NULL, "DAI Sel Mux"},
  253. /* Capture */
  254. { "VI Sense", "Switch", "VMON" },
  255. { "VI Sense", "Switch", "IMON" },
  256. { "SpkFB Sense", "Switch", "FBMON" },
  257. { "Voltage Sense", NULL, "VI Sense" },
  258. { "Current Sense", NULL, "VI Sense" },
  259. { "Speaker FB Sense", NULL, "SpkFB Sense" },
  260. };
  261. void max98373_reset(struct max98373_priv *max98373, struct device *dev)
  262. {
  263. int ret, reg, count;
  264. /* Software Reset */
  265. ret = regmap_update_bits(max98373->regmap,
  266. MAX98373_R2000_SW_RESET,
  267. MAX98373_SOFT_RESET,
  268. MAX98373_SOFT_RESET);
  269. if (ret)
  270. dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
  271. count = 0;
  272. while (count < 3) {
  273. usleep_range(10000, 11000);
  274. /* Software Reset Verification */
  275. ret = regmap_read(max98373->regmap,
  276. MAX98373_R21FF_REV_ID, &reg);
  277. if (!ret) {
  278. dev_info(dev, "Reset completed (retry:%d)\n", count);
  279. return;
  280. }
  281. count++;
  282. }
  283. dev_err(dev, "Reset failed. (ret:%d)\n", ret);
  284. }
  285. EXPORT_SYMBOL_GPL(max98373_reset);
  286. static int max98373_probe(struct snd_soc_component *component)
  287. {
  288. struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
  289. /* Software Reset */
  290. max98373_reset(max98373, component->dev);
  291. /* IV default slot configuration */
  292. regmap_write(max98373->regmap,
  293. MAX98373_R2020_PCM_TX_HIZ_EN_1,
  294. 0xFF);
  295. regmap_write(max98373->regmap,
  296. MAX98373_R2021_PCM_TX_HIZ_EN_2,
  297. 0xFF);
  298. /* L/R mix configuration */
  299. regmap_write(max98373->regmap,
  300. MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
  301. 0x80);
  302. regmap_write(max98373->regmap,
  303. MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
  304. 0x1);
  305. /* Enable DC blocker */
  306. regmap_write(max98373->regmap,
  307. MAX98373_R203F_AMP_DSP_CFG,
  308. 0x3);
  309. /* Enable IMON VMON DC blocker */
  310. regmap_write(max98373->regmap,
  311. MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
  312. 0x7);
  313. /* voltage, current slot configuration */
  314. regmap_write(max98373->regmap,
  315. MAX98373_R2022_PCM_TX_SRC_1,
  316. (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
  317. max98373->v_slot) & 0xFF);
  318. if (max98373->v_slot < 8)
  319. regmap_update_bits(max98373->regmap,
  320. MAX98373_R2020_PCM_TX_HIZ_EN_1,
  321. 1 << max98373->v_slot, 0);
  322. else
  323. regmap_update_bits(max98373->regmap,
  324. MAX98373_R2021_PCM_TX_HIZ_EN_2,
  325. 1 << (max98373->v_slot - 8), 0);
  326. if (max98373->i_slot < 8)
  327. regmap_update_bits(max98373->regmap,
  328. MAX98373_R2020_PCM_TX_HIZ_EN_1,
  329. 1 << max98373->i_slot, 0);
  330. else
  331. regmap_update_bits(max98373->regmap,
  332. MAX98373_R2021_PCM_TX_HIZ_EN_2,
  333. 1 << (max98373->i_slot - 8), 0);
  334. /* speaker feedback slot configuration */
  335. regmap_write(max98373->regmap,
  336. MAX98373_R2023_PCM_TX_SRC_2,
  337. max98373->spkfb_slot & 0xFF);
  338. /* Set interleave mode */
  339. if (max98373->interleave_mode)
  340. regmap_update_bits(max98373->regmap,
  341. MAX98373_R2024_PCM_DATA_FMT_CFG,
  342. MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
  343. MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
  344. /* Speaker enable */
  345. regmap_update_bits(max98373->regmap,
  346. MAX98373_R2043_AMP_EN,
  347. MAX98373_SPK_EN_MASK, 1);
  348. return 0;
  349. }
  350. const struct snd_soc_component_driver soc_codec_dev_max98373 = {
  351. .probe = max98373_probe,
  352. .controls = max98373_snd_controls,
  353. .num_controls = ARRAY_SIZE(max98373_snd_controls),
  354. .dapm_widgets = max98373_dapm_widgets,
  355. .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
  356. .dapm_routes = max98373_audio_map,
  357. .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
  358. .use_pmdown_time = 1,
  359. .endianness = 1,
  360. .non_legacy_dai_naming = 1,
  361. };
  362. EXPORT_SYMBOL_GPL(soc_codec_dev_max98373);
  363. const struct snd_soc_component_driver soc_codec_dev_max98373_sdw = {
  364. .probe = NULL,
  365. .controls = max98373_snd_controls,
  366. .num_controls = ARRAY_SIZE(max98373_snd_controls),
  367. .dapm_widgets = max98373_dapm_widgets,
  368. .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
  369. .dapm_routes = max98373_audio_map,
  370. .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
  371. .use_pmdown_time = 1,
  372. .endianness = 1,
  373. .non_legacy_dai_naming = 1,
  374. };
  375. EXPORT_SYMBOL_GPL(soc_codec_dev_max98373_sdw);
  376. void max98373_slot_config(struct device *dev,
  377. struct max98373_priv *max98373)
  378. {
  379. int value;
  380. if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
  381. max98373->v_slot = value & 0xF;
  382. else
  383. max98373->v_slot = 0;
  384. if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
  385. max98373->i_slot = value & 0xF;
  386. else
  387. max98373->i_slot = 1;
  388. if (dev->of_node) {
  389. max98373->reset_gpio = of_get_named_gpio(dev->of_node,
  390. "maxim,reset-gpio", 0);
  391. if (!gpio_is_valid(max98373->reset_gpio)) {
  392. dev_err(dev, "Looking up %s property in node %s failed %d\n",
  393. "maxim,reset-gpio", dev->of_node->full_name,
  394. max98373->reset_gpio);
  395. } else {
  396. dev_dbg(dev, "maxim,reset-gpio=%d",
  397. max98373->reset_gpio);
  398. }
  399. } else {
  400. /* this makes reset_gpio as invalid */
  401. max98373->reset_gpio = -1;
  402. }
  403. if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
  404. max98373->spkfb_slot = value & 0xF;
  405. else
  406. max98373->spkfb_slot = 2;
  407. }
  408. EXPORT_SYMBOL_GPL(max98373_slot_config);
  409. MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
  410. MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
  411. MODULE_LICENSE("GPL");