max98373-sdw.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. // Copyright (c) 2020, Maxim Integrated
  3. #include <linux/acpi.h>
  4. #include <linux/delay.h>
  5. #include <linux/module.h>
  6. #include <linux/mod_devicetable.h>
  7. #include <linux/pm_runtime.h>
  8. #include <linux/regmap.h>
  9. #include <linux/slab.h>
  10. #include <sound/pcm.h>
  11. #include <sound/pcm_params.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <linux/of.h>
  15. #include <linux/soundwire/sdw.h>
  16. #include <linux/soundwire/sdw_type.h>
  17. #include <linux/soundwire/sdw_registers.h>
  18. #include "max98373.h"
  19. #include "max98373-sdw.h"
  20. struct sdw_stream_data {
  21. struct sdw_stream_runtime *sdw_stream;
  22. };
  23. static struct reg_default max98373_reg[] = {
  24. {MAX98373_R0040_SCP_INIT_STAT_1, 0x00},
  25. {MAX98373_R0041_SCP_INIT_MASK_1, 0x00},
  26. {MAX98373_R0042_SCP_INIT_STAT_2, 0x00},
  27. {MAX98373_R0044_SCP_CTRL, 0x00},
  28. {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00},
  29. {MAX98373_R0046_SCP_DEV_NUMBER, 0x00},
  30. {MAX98373_R0050_SCP_DEV_ID_0, 0x21},
  31. {MAX98373_R0051_SCP_DEV_ID_1, 0x01},
  32. {MAX98373_R0052_SCP_DEV_ID_2, 0x9F},
  33. {MAX98373_R0053_SCP_DEV_ID_3, 0x87},
  34. {MAX98373_R0054_SCP_DEV_ID_4, 0x08},
  35. {MAX98373_R0055_SCP_DEV_ID_5, 0x00},
  36. {MAX98373_R0060_SCP_FRAME_CTLR, 0x00},
  37. {MAX98373_R0070_SCP_FRAME_CTLR, 0x00},
  38. {MAX98373_R0100_DP1_INIT_STAT, 0x00},
  39. {MAX98373_R0101_DP1_INIT_MASK, 0x00},
  40. {MAX98373_R0102_DP1_PORT_CTRL, 0x00},
  41. {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00},
  42. {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00},
  43. {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00},
  44. {MAX98373_R0120_DP1_CHANNEL_EN, 0x00},
  45. {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00},
  46. {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00},
  47. {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00},
  48. {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00},
  49. {MAX98373_R0126_DP1_HCTRL, 0x00},
  50. {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00},
  51. {MAX98373_R0130_DP1_CHANNEL_EN, 0x00},
  52. {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00},
  53. {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00},
  54. {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00},
  55. {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00},
  56. {MAX98373_R0136_DP1_HCTRL, 0x0136},
  57. {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00},
  58. {MAX98373_R0300_DP3_INIT_STAT, 0x00},
  59. {MAX98373_R0301_DP3_INIT_MASK, 0x00},
  60. {MAX98373_R0302_DP3_PORT_CTRL, 0x00},
  61. {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00},
  62. {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00},
  63. {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00},
  64. {MAX98373_R0320_DP3_CHANNEL_EN, 0x00},
  65. {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00},
  66. {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00},
  67. {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00},
  68. {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00},
  69. {MAX98373_R0326_DP3_HCTRL, 0x00},
  70. {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00},
  71. {MAX98373_R0330_DP3_CHANNEL_EN, 0x00},
  72. {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00},
  73. {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00},
  74. {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00},
  75. {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00},
  76. {MAX98373_R0336_DP3_HCTRL, 0x00},
  77. {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00},
  78. {MAX98373_R2000_SW_RESET, 0x00},
  79. {MAX98373_R2001_INT_RAW1, 0x00},
  80. {MAX98373_R2002_INT_RAW2, 0x00},
  81. {MAX98373_R2003_INT_RAW3, 0x00},
  82. {MAX98373_R2004_INT_STATE1, 0x00},
  83. {MAX98373_R2005_INT_STATE2, 0x00},
  84. {MAX98373_R2006_INT_STATE3, 0x00},
  85. {MAX98373_R2007_INT_FLAG1, 0x00},
  86. {MAX98373_R2008_INT_FLAG2, 0x00},
  87. {MAX98373_R2009_INT_FLAG3, 0x00},
  88. {MAX98373_R200A_INT_EN1, 0x00},
  89. {MAX98373_R200B_INT_EN2, 0x00},
  90. {MAX98373_R200C_INT_EN3, 0x00},
  91. {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
  92. {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
  93. {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
  94. {MAX98373_R2010_IRQ_CTRL, 0x00},
  95. {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
  96. {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
  97. {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
  98. {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
  99. {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
  100. {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
  101. {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
  102. {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
  103. {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
  104. {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
  105. {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
  106. {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
  107. {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
  108. {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
  109. {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
  110. {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
  111. {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
  112. {MAX98373_R202B_PCM_RX_EN, 0x00},
  113. {MAX98373_R202C_PCM_TX_EN, 0x00},
  114. {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
  115. {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
  116. {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
  117. {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
  118. {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
  119. {MAX98373_R2034_ICC_TX_CNTL, 0x00},
  120. {MAX98373_R2035_ICC_TX_EN, 0x00},
  121. {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
  122. {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
  123. {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
  124. {MAX98373_R203F_AMP_DSP_CFG, 0x02},
  125. {MAX98373_R2040_TONE_GEN_CFG, 0x00},
  126. {MAX98373_R2041_AMP_CFG, 0x03},
  127. {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
  128. {MAX98373_R2043_AMP_EN, 0x00},
  129. {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
  130. {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
  131. {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
  132. {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
  133. {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
  134. {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
  135. {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
  136. {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
  137. {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
  138. {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
  139. {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
  140. {MAX98373_R2097_BDE_L1_THRESH, 0x00},
  141. {MAX98373_R2098_BDE_L2_THRESH, 0x00},
  142. {MAX98373_R2099_BDE_L3_THRESH, 0x00},
  143. {MAX98373_R209A_BDE_L4_THRESH, 0x00},
  144. {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
  145. {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
  146. {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
  147. {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
  148. {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
  149. {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
  150. {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
  151. {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
  152. {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
  153. {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
  154. {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
  155. {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
  156. {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
  157. {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
  158. {MAX98373_R20B5_BDE_EN, 0x00},
  159. {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
  160. {MAX98373_R20D1_DHT_CFG, 0x01},
  161. {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
  162. {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
  163. {MAX98373_R20D4_DHT_EN, 0x00},
  164. {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
  165. {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
  166. {MAX98373_R20E2_LIMITER_EN, 0x00},
  167. {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
  168. {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
  169. {MAX98373_R21FF_REV_ID, 0x42},
  170. };
  171. static bool max98373_readable_register(struct device *dev, unsigned int reg)
  172. {
  173. switch (reg) {
  174. case MAX98373_R21FF_REV_ID:
  175. case MAX98373_R2010_IRQ_CTRL:
  176. /* SoundWire Control Port Registers */
  177. case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
  178. /* Soundwire Data Port 1 Registers */
  179. case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
  180. /* Soundwire Data Port 3 Registers */
  181. case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
  182. case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3:
  183. case MAX98373_R2014_THERM_WARN_THRESH
  184. ... MAX98373_R2018_THERM_FOLDBACK_EN:
  185. case MAX98373_R201E_PIN_DRIVE_STRENGTH
  186. ... MAX98373_R2036_SOUNDWIRE_CTRL:
  187. case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
  188. case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
  189. ... MAX98373_R2047_IV_SENSE_ADC_EN:
  190. case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
  191. ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
  192. case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
  193. case MAX98373_R2097_BDE_L1_THRESH
  194. ... MAX98373_R209B_BDE_THRESH_HYST:
  195. case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
  196. case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
  197. case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
  198. case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
  199. case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
  200. ... MAX98373_R20FF_GLOBAL_SHDN:
  201. return true;
  202. default:
  203. return false;
  204. }
  205. };
  206. static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
  207. {
  208. switch (reg) {
  209. case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
  210. case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
  211. case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
  212. case MAX98373_R20FF_GLOBAL_SHDN:
  213. case MAX98373_R21FF_REV_ID:
  214. /* SoundWire Control Port Registers */
  215. case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
  216. /* Soundwire Data Port 1 Registers */
  217. case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
  218. /* Soundwire Data Port 3 Registers */
  219. case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
  220. case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
  221. return true;
  222. default:
  223. return false;
  224. }
  225. }
  226. static const struct regmap_config max98373_sdw_regmap = {
  227. .reg_bits = 32,
  228. .val_bits = 8,
  229. .max_register = MAX98373_R21FF_REV_ID,
  230. .reg_defaults = max98373_reg,
  231. .num_reg_defaults = ARRAY_SIZE(max98373_reg),
  232. .readable_reg = max98373_readable_register,
  233. .volatile_reg = max98373_volatile_reg,
  234. .cache_type = REGCACHE_RBTREE,
  235. .use_single_read = true,
  236. .use_single_write = true,
  237. };
  238. /* Power management functions and structure */
  239. static __maybe_unused int max98373_suspend(struct device *dev)
  240. {
  241. struct max98373_priv *max98373 = dev_get_drvdata(dev);
  242. regcache_cache_only(max98373->regmap, true);
  243. regcache_mark_dirty(max98373->regmap);
  244. return 0;
  245. }
  246. static __maybe_unused int max98373_resume(struct device *dev)
  247. {
  248. struct sdw_slave *slave = dev_to_sdw_dev(dev);
  249. struct max98373_priv *max98373 = dev_get_drvdata(dev);
  250. unsigned long time;
  251. if (!max98373->first_hw_init)
  252. return 0;
  253. if (!slave->unattach_request)
  254. goto regmap_sync;
  255. time = wait_for_completion_timeout(&slave->initialization_complete,
  256. msecs_to_jiffies(2000));
  257. if (!time) {
  258. dev_err(dev, "Initialization not complete, timed out\n");
  259. return -ETIMEDOUT;
  260. }
  261. regmap_sync:
  262. slave->unattach_request = 0;
  263. regcache_cache_only(max98373->regmap, false);
  264. regcache_sync(max98373->regmap);
  265. return 0;
  266. }
  267. static const struct dev_pm_ops max98373_pm = {
  268. SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
  269. SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL)
  270. };
  271. static int max98373_read_prop(struct sdw_slave *slave)
  272. {
  273. struct sdw_slave_prop *prop = &slave->prop;
  274. int nval, i;
  275. u32 bit;
  276. unsigned long addr;
  277. struct sdw_dpn_prop *dpn;
  278. prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
  279. /* BITMAP: 00001000 Dataport 3 is active */
  280. prop->source_ports = BIT(3);
  281. /* BITMAP: 00000010 Dataport 1 is active */
  282. prop->sink_ports = BIT(1);
  283. prop->paging_support = true;
  284. prop->clk_stop_timeout = 20;
  285. nval = hweight32(prop->source_ports);
  286. prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
  287. sizeof(*prop->src_dpn_prop),
  288. GFP_KERNEL);
  289. if (!prop->src_dpn_prop)
  290. return -ENOMEM;
  291. i = 0;
  292. dpn = prop->src_dpn_prop;
  293. addr = prop->source_ports;
  294. for_each_set_bit(bit, &addr, 32) {
  295. dpn[i].num = bit;
  296. dpn[i].type = SDW_DPN_FULL;
  297. dpn[i].simple_ch_prep_sm = true;
  298. dpn[i].ch_prep_timeout = 10;
  299. i++;
  300. }
  301. /* do this again for sink now */
  302. nval = hweight32(prop->sink_ports);
  303. prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
  304. sizeof(*prop->sink_dpn_prop),
  305. GFP_KERNEL);
  306. if (!prop->sink_dpn_prop)
  307. return -ENOMEM;
  308. i = 0;
  309. dpn = prop->sink_dpn_prop;
  310. addr = prop->sink_ports;
  311. for_each_set_bit(bit, &addr, 32) {
  312. dpn[i].num = bit;
  313. dpn[i].type = SDW_DPN_FULL;
  314. dpn[i].simple_ch_prep_sm = true;
  315. dpn[i].ch_prep_timeout = 10;
  316. i++;
  317. }
  318. /* set the timeout values */
  319. prop->clk_stop_timeout = 20;
  320. return 0;
  321. }
  322. static int max98373_io_init(struct sdw_slave *slave)
  323. {
  324. struct device *dev = &slave->dev;
  325. struct max98373_priv *max98373 = dev_get_drvdata(dev);
  326. if (max98373->first_hw_init) {
  327. regcache_cache_only(max98373->regmap, false);
  328. regcache_cache_bypass(max98373->regmap, true);
  329. }
  330. /*
  331. * PM runtime is only enabled when a Slave reports as Attached
  332. */
  333. if (!max98373->first_hw_init) {
  334. /* set autosuspend parameters */
  335. pm_runtime_set_autosuspend_delay(dev, 3000);
  336. pm_runtime_use_autosuspend(dev);
  337. /* update count of parent 'active' children */
  338. pm_runtime_set_active(dev);
  339. /* make sure the device does not suspend immediately */
  340. pm_runtime_mark_last_busy(dev);
  341. pm_runtime_enable(dev);
  342. }
  343. pm_runtime_get_noresume(dev);
  344. /* Software Reset */
  345. max98373_reset(max98373, dev);
  346. /* Set soundwire mode */
  347. regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3);
  348. /* Enable ADC */
  349. regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3);
  350. /* Set default Soundwire clock */
  351. regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5);
  352. /* Set default sampling rate for speaker and IVDAC */
  353. regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
  354. /* IV default slot configuration */
  355. regmap_write(max98373->regmap,
  356. MAX98373_R2020_PCM_TX_HIZ_EN_1,
  357. 0xFF);
  358. regmap_write(max98373->regmap,
  359. MAX98373_R2021_PCM_TX_HIZ_EN_2,
  360. 0xFF);
  361. /* L/R mix configuration */
  362. regmap_write(max98373->regmap,
  363. MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
  364. 0x80);
  365. regmap_write(max98373->regmap,
  366. MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
  367. 0x1);
  368. /* Enable DC blocker */
  369. regmap_write(max98373->regmap,
  370. MAX98373_R203F_AMP_DSP_CFG,
  371. 0x3);
  372. /* Enable IMON VMON DC blocker */
  373. regmap_write(max98373->regmap,
  374. MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
  375. 0x7);
  376. /* voltage, current slot configuration */
  377. regmap_write(max98373->regmap,
  378. MAX98373_R2022_PCM_TX_SRC_1,
  379. (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
  380. max98373->v_slot) & 0xFF);
  381. if (max98373->v_slot < 8)
  382. regmap_update_bits(max98373->regmap,
  383. MAX98373_R2020_PCM_TX_HIZ_EN_1,
  384. 1 << max98373->v_slot, 0);
  385. else
  386. regmap_update_bits(max98373->regmap,
  387. MAX98373_R2021_PCM_TX_HIZ_EN_2,
  388. 1 << (max98373->v_slot - 8), 0);
  389. if (max98373->i_slot < 8)
  390. regmap_update_bits(max98373->regmap,
  391. MAX98373_R2020_PCM_TX_HIZ_EN_1,
  392. 1 << max98373->i_slot, 0);
  393. else
  394. regmap_update_bits(max98373->regmap,
  395. MAX98373_R2021_PCM_TX_HIZ_EN_2,
  396. 1 << (max98373->i_slot - 8), 0);
  397. /* speaker feedback slot configuration */
  398. regmap_write(max98373->regmap,
  399. MAX98373_R2023_PCM_TX_SRC_2,
  400. max98373->spkfb_slot & 0xFF);
  401. /* Set interleave mode */
  402. if (max98373->interleave_mode)
  403. regmap_update_bits(max98373->regmap,
  404. MAX98373_R2024_PCM_DATA_FMT_CFG,
  405. MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
  406. MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
  407. /* Speaker enable */
  408. regmap_update_bits(max98373->regmap,
  409. MAX98373_R2043_AMP_EN,
  410. MAX98373_SPK_EN_MASK, 1);
  411. regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1);
  412. regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1);
  413. if (max98373->first_hw_init) {
  414. regcache_cache_bypass(max98373->regmap, false);
  415. regcache_mark_dirty(max98373->regmap);
  416. }
  417. max98373->first_hw_init = true;
  418. max98373->hw_init = true;
  419. pm_runtime_mark_last_busy(dev);
  420. pm_runtime_put_autosuspend(dev);
  421. return 0;
  422. }
  423. static int max98373_clock_calculate(struct sdw_slave *slave,
  424. unsigned int clk_freq)
  425. {
  426. int x, y;
  427. static const int max98373_clk_family[] = {
  428. 7680000, 8400000, 9600000, 11289600,
  429. 12000000, 12288000, 13000000
  430. };
  431. for (x = 0; x < 4; x++)
  432. for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++)
  433. if (clk_freq == (max98373_clk_family[y] >> x))
  434. return (x << 3) + y;
  435. /* Set default clock (12.288 Mhz) if the value is not in the list */
  436. dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n",
  437. clk_freq);
  438. return 0x5;
  439. }
  440. static int max98373_clock_config(struct sdw_slave *slave,
  441. struct sdw_bus_params *params)
  442. {
  443. struct device *dev = &slave->dev;
  444. struct max98373_priv *max98373 = dev_get_drvdata(dev);
  445. unsigned int clk_freq, value;
  446. clk_freq = (params->curr_dr_freq >> 1);
  447. /*
  448. * Select the proper value for the register based on the
  449. * requested clock. If the value is not in the list,
  450. * use reasonable default - 12.288 Mhz
  451. */
  452. value = max98373_clock_calculate(slave, clk_freq);
  453. /* SWCLK */
  454. regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value);
  455. /* The default Sampling Rate value for IV is 48KHz*/
  456. regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
  457. return 0;
  458. }
  459. #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
  460. #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
  461. static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream,
  462. struct snd_pcm_hw_params *params,
  463. struct snd_soc_dai *dai)
  464. {
  465. struct snd_soc_component *component = dai->component;
  466. struct max98373_priv *max98373 =
  467. snd_soc_component_get_drvdata(component);
  468. struct sdw_stream_config stream_config;
  469. struct sdw_port_config port_config;
  470. enum sdw_data_direction direction;
  471. struct sdw_stream_data *stream;
  472. int ret, chan_sz, sampling_rate;
  473. stream = snd_soc_dai_get_dma_data(dai, substream);
  474. if (!stream)
  475. return -EINVAL;
  476. if (!max98373->slave)
  477. return -EINVAL;
  478. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  479. direction = SDW_DATA_DIR_RX;
  480. port_config.num = 1;
  481. } else {
  482. direction = SDW_DATA_DIR_TX;
  483. port_config.num = 3;
  484. }
  485. stream_config.frame_rate = params_rate(params);
  486. stream_config.bps = snd_pcm_format_width(params_format(params));
  487. stream_config.direction = direction;
  488. if (max98373->slot && direction == SDW_DATA_DIR_RX) {
  489. stream_config.ch_count = max98373->slot;
  490. port_config.ch_mask = max98373->rx_mask;
  491. } else {
  492. /* only IV are supported by capture */
  493. if (direction == SDW_DATA_DIR_TX)
  494. stream_config.ch_count = 2;
  495. else
  496. stream_config.ch_count = params_channels(params);
  497. port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);
  498. }
  499. ret = sdw_stream_add_slave(max98373->slave, &stream_config,
  500. &port_config, 1, stream->sdw_stream);
  501. if (ret) {
  502. dev_err(dai->dev, "Unable to configure port\n");
  503. return ret;
  504. }
  505. if (params_channels(params) > 16) {
  506. dev_err(component->dev, "Unsupported channels %d\n",
  507. params_channels(params));
  508. return -EINVAL;
  509. }
  510. /* Channel size configuration */
  511. switch (snd_pcm_format_width(params_format(params))) {
  512. case 16:
  513. chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
  514. break;
  515. case 24:
  516. chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
  517. break;
  518. case 32:
  519. chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
  520. break;
  521. default:
  522. dev_err(component->dev, "Channel size unsupported %d\n",
  523. params_format(params));
  524. return -EINVAL;
  525. }
  526. max98373->ch_size = snd_pcm_format_width(params_format(params));
  527. regmap_update_bits(max98373->regmap,
  528. MAX98373_R2024_PCM_DATA_FMT_CFG,
  529. MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
  530. dev_dbg(component->dev, "Format supported %d", params_format(params));
  531. /* Sampling rate configuration */
  532. switch (params_rate(params)) {
  533. case 8000:
  534. sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
  535. break;
  536. case 11025:
  537. sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
  538. break;
  539. case 12000:
  540. sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
  541. break;
  542. case 16000:
  543. sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
  544. break;
  545. case 22050:
  546. sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
  547. break;
  548. case 24000:
  549. sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
  550. break;
  551. case 32000:
  552. sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
  553. break;
  554. case 44100:
  555. sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
  556. break;
  557. case 48000:
  558. sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
  559. break;
  560. case 88200:
  561. sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
  562. break;
  563. case 96000:
  564. sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
  565. break;
  566. default:
  567. dev_err(component->dev, "Rate %d is not supported\n",
  568. params_rate(params));
  569. return -EINVAL;
  570. }
  571. /* set correct sampling frequency */
  572. regmap_update_bits(max98373->regmap,
  573. MAX98373_R2028_PCM_SR_SETUP_2,
  574. MAX98373_PCM_SR_SET2_SR_MASK,
  575. sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
  576. /* set sampling rate of IV */
  577. regmap_update_bits(max98373->regmap,
  578. MAX98373_R2028_PCM_SR_SETUP_2,
  579. MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
  580. sampling_rate);
  581. return 0;
  582. }
  583. static int max98373_pcm_hw_free(struct snd_pcm_substream *substream,
  584. struct snd_soc_dai *dai)
  585. {
  586. struct snd_soc_component *component = dai->component;
  587. struct max98373_priv *max98373 =
  588. snd_soc_component_get_drvdata(component);
  589. struct sdw_stream_data *stream =
  590. snd_soc_dai_get_dma_data(dai, substream);
  591. if (!max98373->slave)
  592. return -EINVAL;
  593. sdw_stream_remove_slave(max98373->slave, stream->sdw_stream);
  594. return 0;
  595. }
  596. static int max98373_set_sdw_stream(struct snd_soc_dai *dai,
  597. void *sdw_stream, int direction)
  598. {
  599. struct sdw_stream_data *stream;
  600. if (!sdw_stream)
  601. return 0;
  602. stream = kzalloc(sizeof(*stream), GFP_KERNEL);
  603. if (!stream)
  604. return -ENOMEM;
  605. stream->sdw_stream = sdw_stream;
  606. /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
  607. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  608. dai->playback_dma_data = stream;
  609. else
  610. dai->capture_dma_data = stream;
  611. return 0;
  612. }
  613. static void max98373_shutdown(struct snd_pcm_substream *substream,
  614. struct snd_soc_dai *dai)
  615. {
  616. struct sdw_stream_data *stream;
  617. stream = snd_soc_dai_get_dma_data(dai, substream);
  618. snd_soc_dai_set_dma_data(dai, substream, NULL);
  619. kfree(stream);
  620. }
  621. static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai,
  622. unsigned int tx_mask,
  623. unsigned int rx_mask,
  624. int slots, int slot_width)
  625. {
  626. struct snd_soc_component *component = dai->component;
  627. struct max98373_priv *max98373 =
  628. snd_soc_component_get_drvdata(component);
  629. /* tx_mask is unused since it's irrelevant for I/V feedback */
  630. if (tx_mask)
  631. return -EINVAL;
  632. if (!rx_mask && !slots && !slot_width)
  633. max98373->tdm_mode = false;
  634. else
  635. max98373->tdm_mode = true;
  636. max98373->rx_mask = rx_mask;
  637. max98373->slot = slots;
  638. return 0;
  639. }
  640. static const struct snd_soc_dai_ops max98373_dai_sdw_ops = {
  641. .hw_params = max98373_sdw_dai_hw_params,
  642. .hw_free = max98373_pcm_hw_free,
  643. .set_sdw_stream = max98373_set_sdw_stream,
  644. .shutdown = max98373_shutdown,
  645. .set_tdm_slot = max98373_sdw_set_tdm_slot,
  646. };
  647. static struct snd_soc_dai_driver max98373_sdw_dai[] = {
  648. {
  649. .name = "max98373-aif1",
  650. .playback = {
  651. .stream_name = "HiFi Playback",
  652. .channels_min = 1,
  653. .channels_max = 2,
  654. .rates = MAX98373_RATES,
  655. .formats = MAX98373_FORMATS,
  656. },
  657. .capture = {
  658. .stream_name = "HiFi Capture",
  659. .channels_min = 1,
  660. .channels_max = 2,
  661. .rates = MAX98373_RATES,
  662. .formats = MAX98373_FORMATS,
  663. },
  664. .ops = &max98373_dai_sdw_ops,
  665. }
  666. };
  667. static int max98373_init(struct sdw_slave *slave, struct regmap *regmap)
  668. {
  669. struct max98373_priv *max98373;
  670. int ret;
  671. struct device *dev = &slave->dev;
  672. /* Allocate and assign private driver data structure */
  673. max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL);
  674. if (!max98373)
  675. return -ENOMEM;
  676. dev_set_drvdata(dev, max98373);
  677. max98373->regmap = regmap;
  678. max98373->slave = slave;
  679. /* Read voltage and slot configuration */
  680. max98373_slot_config(dev, max98373);
  681. max98373->hw_init = false;
  682. max98373->first_hw_init = false;
  683. /* codec registration */
  684. ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw,
  685. max98373_sdw_dai,
  686. ARRAY_SIZE(max98373_sdw_dai));
  687. if (ret < 0)
  688. dev_err(dev, "Failed to register codec: %d\n", ret);
  689. return ret;
  690. }
  691. static int max98373_update_status(struct sdw_slave *slave,
  692. enum sdw_slave_status status)
  693. {
  694. struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
  695. if (status == SDW_SLAVE_UNATTACHED)
  696. max98373->hw_init = false;
  697. /*
  698. * Perform initialization only if slave status is SDW_SLAVE_ATTACHED
  699. */
  700. if (max98373->hw_init || status != SDW_SLAVE_ATTACHED)
  701. return 0;
  702. /* perform I/O transfers required for Slave initialization */
  703. return max98373_io_init(slave);
  704. }
  705. static int max98373_bus_config(struct sdw_slave *slave,
  706. struct sdw_bus_params *params)
  707. {
  708. int ret;
  709. ret = max98373_clock_config(slave, params);
  710. if (ret < 0)
  711. dev_err(&slave->dev, "Invalid clk config");
  712. return ret;
  713. }
  714. /*
  715. * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
  716. * port_prep are not defined for now
  717. */
  718. static struct sdw_slave_ops max98373_slave_ops = {
  719. .read_prop = max98373_read_prop,
  720. .update_status = max98373_update_status,
  721. .bus_config = max98373_bus_config,
  722. };
  723. static int max98373_sdw_probe(struct sdw_slave *slave,
  724. const struct sdw_device_id *id)
  725. {
  726. struct regmap *regmap;
  727. /* Regmap Initialization */
  728. regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap);
  729. if (IS_ERR(regmap))
  730. return PTR_ERR(regmap);
  731. return max98373_init(slave, regmap);
  732. }
  733. #if defined(CONFIG_OF)
  734. static const struct of_device_id max98373_of_match[] = {
  735. { .compatible = "maxim,max98373", },
  736. {},
  737. };
  738. MODULE_DEVICE_TABLE(of, max98373_of_match);
  739. #endif
  740. #ifdef CONFIG_ACPI
  741. static const struct acpi_device_id max98373_acpi_match[] = {
  742. { "MX98373", 0 },
  743. {},
  744. };
  745. MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
  746. #endif
  747. static const struct sdw_device_id max98373_id[] = {
  748. SDW_SLAVE_ENTRY(0x019F, 0x8373, 0),
  749. {},
  750. };
  751. MODULE_DEVICE_TABLE(sdw, max98373_id);
  752. static struct sdw_driver max98373_sdw_driver = {
  753. .driver = {
  754. .name = "max98373",
  755. .owner = THIS_MODULE,
  756. .of_match_table = of_match_ptr(max98373_of_match),
  757. .acpi_match_table = ACPI_PTR(max98373_acpi_match),
  758. .pm = &max98373_pm,
  759. },
  760. .probe = max98373_sdw_probe,
  761. .remove = NULL,
  762. .ops = &max98373_slave_ops,
  763. .id_table = max98373_id,
  764. };
  765. module_sdw_driver(max98373_sdw_driver);
  766. MODULE_DESCRIPTION("ASoC MAX98373 driver SDW");
  767. MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>");
  768. MODULE_LICENSE("GPL v2");