max98373-i2c.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2017, Maxim Integrated
  3. #include <linux/acpi.h>
  4. #include <linux/delay.h>
  5. #include <linux/gpio.h>
  6. #include <linux/i2c.h>
  7. #include <linux/module.h>
  8. #include <linux/mod_devicetable.h>
  9. #include <linux/of.h>
  10. #include <linux/of_gpio.h>
  11. #include <linux/pm_runtime.h>
  12. #include <linux/regmap.h>
  13. #include <linux/slab.h>
  14. #include <linux/cdev.h>
  15. #include <sound/pcm.h>
  16. #include <sound/pcm_params.h>
  17. #include <sound/soc.h>
  18. #include <sound/tlv.h>
  19. #include "max98373.h"
  20. static struct reg_default max98373_reg[] = {
  21. {MAX98373_R2000_SW_RESET, 0x00},
  22. {MAX98373_R2001_INT_RAW1, 0x00},
  23. {MAX98373_R2002_INT_RAW2, 0x00},
  24. {MAX98373_R2003_INT_RAW3, 0x00},
  25. {MAX98373_R2004_INT_STATE1, 0x00},
  26. {MAX98373_R2005_INT_STATE2, 0x00},
  27. {MAX98373_R2006_INT_STATE3, 0x00},
  28. {MAX98373_R2007_INT_FLAG1, 0x00},
  29. {MAX98373_R2008_INT_FLAG2, 0x00},
  30. {MAX98373_R2009_INT_FLAG3, 0x00},
  31. {MAX98373_R200A_INT_EN1, 0x00},
  32. {MAX98373_R200B_INT_EN2, 0x00},
  33. {MAX98373_R200C_INT_EN3, 0x00},
  34. {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
  35. {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
  36. {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
  37. {MAX98373_R2010_IRQ_CTRL, 0x00},
  38. {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
  39. {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
  40. {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
  41. {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
  42. {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
  43. {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
  44. {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
  45. {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
  46. {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
  47. {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
  48. {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
  49. {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
  50. {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
  51. {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
  52. {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
  53. {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
  54. {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
  55. {MAX98373_R202B_PCM_RX_EN, 0x00},
  56. {MAX98373_R202C_PCM_TX_EN, 0x00},
  57. {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
  58. {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
  59. {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
  60. {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
  61. {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
  62. {MAX98373_R2034_ICC_TX_CNTL, 0x00},
  63. {MAX98373_R2035_ICC_TX_EN, 0x00},
  64. {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
  65. {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
  66. {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
  67. {MAX98373_R203F_AMP_DSP_CFG, 0x02},
  68. {MAX98373_R2040_TONE_GEN_CFG, 0x00},
  69. {MAX98373_R2041_AMP_CFG, 0x03},
  70. {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
  71. {MAX98373_R2043_AMP_EN, 0x00},
  72. {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
  73. {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
  74. {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
  75. {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
  76. {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
  77. {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
  78. {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
  79. {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
  80. {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
  81. {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
  82. {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
  83. {MAX98373_R2097_BDE_L1_THRESH, 0x00},
  84. {MAX98373_R2098_BDE_L2_THRESH, 0x00},
  85. {MAX98373_R2099_BDE_L3_THRESH, 0x00},
  86. {MAX98373_R209A_BDE_L4_THRESH, 0x00},
  87. {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
  88. {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
  89. {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
  90. {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
  91. {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
  92. {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
  93. {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
  94. {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
  95. {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
  96. {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
  97. {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
  98. {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
  99. {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
  100. {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
  101. {MAX98373_R20B5_BDE_EN, 0x00},
  102. {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
  103. {MAX98373_R20D1_DHT_CFG, 0x01},
  104. {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
  105. {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
  106. {MAX98373_R20D4_DHT_EN, 0x00},
  107. {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
  108. {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
  109. {MAX98373_R20E2_LIMITER_EN, 0x00},
  110. {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
  111. {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
  112. {MAX98373_R21FF_REV_ID, 0x42},
  113. };
  114. static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  115. {
  116. struct snd_soc_component *component = codec_dai->component;
  117. struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
  118. unsigned int format = 0;
  119. unsigned int invert = 0;
  120. dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
  121. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  122. case SND_SOC_DAIFMT_NB_NF:
  123. break;
  124. case SND_SOC_DAIFMT_IB_NF:
  125. invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE;
  126. break;
  127. default:
  128. dev_err(component->dev, "DAI invert mode unsupported\n");
  129. return -EINVAL;
  130. }
  131. regmap_update_bits(max98373->regmap,
  132. MAX98373_R2026_PCM_CLOCK_RATIO,
  133. MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE,
  134. invert);
  135. /* interface format */
  136. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  137. case SND_SOC_DAIFMT_I2S:
  138. format = MAX98373_PCM_FORMAT_I2S;
  139. break;
  140. case SND_SOC_DAIFMT_LEFT_J:
  141. format = MAX98373_PCM_FORMAT_LJ;
  142. break;
  143. case SND_SOC_DAIFMT_DSP_A:
  144. format = MAX98373_PCM_FORMAT_TDM_MODE1;
  145. break;
  146. case SND_SOC_DAIFMT_DSP_B:
  147. format = MAX98373_PCM_FORMAT_TDM_MODE0;
  148. break;
  149. default:
  150. return -EINVAL;
  151. }
  152. regmap_update_bits(max98373->regmap,
  153. MAX98373_R2024_PCM_DATA_FMT_CFG,
  154. MAX98373_PCM_MODE_CFG_FORMAT_MASK,
  155. format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT);
  156. return 0;
  157. }
  158. /* BCLKs per LRCLK */
  159. static const int bclk_sel_table[] = {
  160. 32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
  161. };
  162. static int max98373_get_bclk_sel(int bclk)
  163. {
  164. int i;
  165. /* match BCLKs per LRCLK */
  166. for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
  167. if (bclk_sel_table[i] == bclk)
  168. return i + 2;
  169. }
  170. return 0;
  171. }
  172. static int max98373_set_clock(struct snd_soc_component *component,
  173. struct snd_pcm_hw_params *params)
  174. {
  175. struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
  176. /* BCLK/LRCLK ratio calculation */
  177. int blr_clk_ratio = params_channels(params) * max98373->ch_size;
  178. int value;
  179. if (!max98373->tdm_mode) {
  180. /* BCLK configuration */
  181. value = max98373_get_bclk_sel(blr_clk_ratio);
  182. if (!value) {
  183. dev_err(component->dev, "format unsupported %d\n",
  184. params_format(params));
  185. return -EINVAL;
  186. }
  187. regmap_update_bits(max98373->regmap,
  188. MAX98373_R2026_PCM_CLOCK_RATIO,
  189. MAX98373_PCM_CLK_SETUP_BSEL_MASK,
  190. value);
  191. }
  192. return 0;
  193. }
  194. static int max98373_dai_hw_params(struct snd_pcm_substream *substream,
  195. struct snd_pcm_hw_params *params,
  196. struct snd_soc_dai *dai)
  197. {
  198. struct snd_soc_component *component = dai->component;
  199. struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
  200. unsigned int sampling_rate = 0;
  201. unsigned int chan_sz = 0;
  202. /* pcm mode configuration */
  203. switch (snd_pcm_format_width(params_format(params))) {
  204. case 16:
  205. chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
  206. break;
  207. case 24:
  208. chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
  209. break;
  210. case 32:
  211. chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
  212. break;
  213. default:
  214. dev_err(component->dev, "format unsupported %d\n",
  215. params_format(params));
  216. goto err;
  217. }
  218. max98373->ch_size = snd_pcm_format_width(params_format(params));
  219. regmap_update_bits(max98373->regmap,
  220. MAX98373_R2024_PCM_DATA_FMT_CFG,
  221. MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
  222. dev_dbg(component->dev, "format supported %d",
  223. params_format(params));
  224. /* sampling rate configuration */
  225. switch (params_rate(params)) {
  226. case 8000:
  227. sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
  228. break;
  229. case 11025:
  230. sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
  231. break;
  232. case 12000:
  233. sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
  234. break;
  235. case 16000:
  236. sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
  237. break;
  238. case 22050:
  239. sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
  240. break;
  241. case 24000:
  242. sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
  243. break;
  244. case 32000:
  245. sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
  246. break;
  247. case 44100:
  248. sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
  249. break;
  250. case 48000:
  251. sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
  252. break;
  253. case 88200:
  254. sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
  255. break;
  256. case 96000:
  257. sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
  258. break;
  259. default:
  260. dev_err(component->dev, "rate %d not supported\n",
  261. params_rate(params));
  262. goto err;
  263. }
  264. /* set DAI_SR to correct LRCLK frequency */
  265. regmap_update_bits(max98373->regmap,
  266. MAX98373_R2027_PCM_SR_SETUP_1,
  267. MAX98373_PCM_SR_SET1_SR_MASK,
  268. sampling_rate);
  269. regmap_update_bits(max98373->regmap,
  270. MAX98373_R2028_PCM_SR_SETUP_2,
  271. MAX98373_PCM_SR_SET2_SR_MASK,
  272. sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
  273. /* set sampling rate of IV */
  274. if (max98373->interleave_mode &&
  275. sampling_rate > MAX98373_PCM_SR_SET1_SR_16000)
  276. regmap_update_bits(max98373->regmap,
  277. MAX98373_R2028_PCM_SR_SETUP_2,
  278. MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
  279. sampling_rate - 3);
  280. else
  281. regmap_update_bits(max98373->regmap,
  282. MAX98373_R2028_PCM_SR_SETUP_2,
  283. MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
  284. sampling_rate);
  285. return max98373_set_clock(component, params);
  286. err:
  287. return -EINVAL;
  288. }
  289. static int max98373_dai_tdm_slot(struct snd_soc_dai *dai,
  290. unsigned int tx_mask, unsigned int rx_mask,
  291. int slots, int slot_width)
  292. {
  293. struct snd_soc_component *component = dai->component;
  294. struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
  295. int bsel = 0;
  296. unsigned int chan_sz = 0;
  297. unsigned int mask;
  298. int x, slot_found;
  299. if (!tx_mask && !rx_mask && !slots && !slot_width)
  300. max98373->tdm_mode = false;
  301. else
  302. max98373->tdm_mode = true;
  303. /* BCLK configuration */
  304. bsel = max98373_get_bclk_sel(slots * slot_width);
  305. if (bsel == 0) {
  306. dev_err(component->dev, "BCLK %d not supported\n",
  307. slots * slot_width);
  308. return -EINVAL;
  309. }
  310. regmap_update_bits(max98373->regmap,
  311. MAX98373_R2026_PCM_CLOCK_RATIO,
  312. MAX98373_PCM_CLK_SETUP_BSEL_MASK,
  313. bsel);
  314. /* Channel size configuration */
  315. switch (slot_width) {
  316. case 16:
  317. chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
  318. break;
  319. case 24:
  320. chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
  321. break;
  322. case 32:
  323. chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
  324. break;
  325. default:
  326. dev_err(component->dev, "format unsupported %d\n",
  327. slot_width);
  328. return -EINVAL;
  329. }
  330. regmap_update_bits(max98373->regmap,
  331. MAX98373_R2024_PCM_DATA_FMT_CFG,
  332. MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
  333. /* Rx slot configuration */
  334. slot_found = 0;
  335. mask = rx_mask;
  336. for (x = 0 ; x < 16 ; x++, mask >>= 1) {
  337. if (mask & 0x1) {
  338. if (slot_found == 0)
  339. regmap_update_bits(max98373->regmap,
  340. MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
  341. MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x);
  342. else
  343. regmap_write(max98373->regmap,
  344. MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
  345. x);
  346. slot_found++;
  347. if (slot_found > 1)
  348. break;
  349. }
  350. }
  351. /* Tx slot Hi-Z configuration */
  352. regmap_write(max98373->regmap,
  353. MAX98373_R2020_PCM_TX_HIZ_EN_1,
  354. ~tx_mask & 0xFF);
  355. regmap_write(max98373->regmap,
  356. MAX98373_R2021_PCM_TX_HIZ_EN_2,
  357. (~tx_mask & 0xFF00) >> 8);
  358. return 0;
  359. }
  360. #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
  361. #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  362. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  363. static const struct snd_soc_dai_ops max98373_dai_ops = {
  364. .set_fmt = max98373_dai_set_fmt,
  365. .hw_params = max98373_dai_hw_params,
  366. .set_tdm_slot = max98373_dai_tdm_slot,
  367. };
  368. static bool max98373_readable_register(struct device *dev, unsigned int reg)
  369. {
  370. switch (reg) {
  371. case MAX98373_R2000_SW_RESET:
  372. case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3:
  373. case MAX98373_R2010_IRQ_CTRL:
  374. case MAX98373_R2014_THERM_WARN_THRESH
  375. ... MAX98373_R2018_THERM_FOLDBACK_EN:
  376. case MAX98373_R201E_PIN_DRIVE_STRENGTH
  377. ... MAX98373_R2036_SOUNDWIRE_CTRL:
  378. case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
  379. case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
  380. ... MAX98373_R2047_IV_SENSE_ADC_EN:
  381. case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
  382. ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
  383. case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
  384. case MAX98373_R2097_BDE_L1_THRESH
  385. ... MAX98373_R209B_BDE_THRESH_HYST:
  386. case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
  387. case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
  388. case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
  389. case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
  390. case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
  391. ... MAX98373_R20FF_GLOBAL_SHDN:
  392. case MAX98373_R21FF_REV_ID:
  393. return true;
  394. default:
  395. return false;
  396. }
  397. };
  398. static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
  399. {
  400. switch (reg) {
  401. case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
  402. case MAX98373_R203E_AMP_PATH_GAIN:
  403. case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
  404. case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
  405. case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
  406. case MAX98373_R20FF_GLOBAL_SHDN:
  407. case MAX98373_R21FF_REV_ID:
  408. return true;
  409. default:
  410. return false;
  411. }
  412. }
  413. static struct snd_soc_dai_driver max98373_dai[] = {
  414. {
  415. .name = "max98373-aif1",
  416. .playback = {
  417. .stream_name = "HiFi Playback",
  418. .channels_min = 1,
  419. .channels_max = 2,
  420. .rates = MAX98373_RATES,
  421. .formats = MAX98373_FORMATS,
  422. },
  423. .capture = {
  424. .stream_name = "HiFi Capture",
  425. .channels_min = 1,
  426. .channels_max = 2,
  427. .rates = MAX98373_RATES,
  428. .formats = MAX98373_FORMATS,
  429. },
  430. .ops = &max98373_dai_ops,
  431. }
  432. };
  433. #ifdef CONFIG_PM_SLEEP
  434. static int max98373_suspend(struct device *dev)
  435. {
  436. struct max98373_priv *max98373 = dev_get_drvdata(dev);
  437. regcache_cache_only(max98373->regmap, true);
  438. regcache_mark_dirty(max98373->regmap);
  439. return 0;
  440. }
  441. static int max98373_resume(struct device *dev)
  442. {
  443. struct max98373_priv *max98373 = dev_get_drvdata(dev);
  444. regcache_cache_only(max98373->regmap, false);
  445. max98373_reset(max98373, dev);
  446. regcache_sync(max98373->regmap);
  447. return 0;
  448. }
  449. #endif
  450. static const struct dev_pm_ops max98373_pm = {
  451. SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
  452. };
  453. static const struct regmap_config max98373_regmap = {
  454. .reg_bits = 16,
  455. .val_bits = 8,
  456. .max_register = MAX98373_R21FF_REV_ID,
  457. .reg_defaults = max98373_reg,
  458. .num_reg_defaults = ARRAY_SIZE(max98373_reg),
  459. .readable_reg = max98373_readable_register,
  460. .volatile_reg = max98373_volatile_reg,
  461. .cache_type = REGCACHE_RBTREE,
  462. };
  463. static int max98373_i2c_probe(struct i2c_client *i2c,
  464. const struct i2c_device_id *id)
  465. {
  466. int ret = 0;
  467. int reg = 0;
  468. struct max98373_priv *max98373 = NULL;
  469. max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL);
  470. if (!max98373) {
  471. ret = -ENOMEM;
  472. return ret;
  473. }
  474. i2c_set_clientdata(i2c, max98373);
  475. /* update interleave mode info */
  476. if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode"))
  477. max98373->interleave_mode = true;
  478. else
  479. max98373->interleave_mode = false;
  480. /* regmap initialization */
  481. max98373->regmap = devm_regmap_init_i2c(i2c, &max98373_regmap);
  482. if (IS_ERR(max98373->regmap)) {
  483. ret = PTR_ERR(max98373->regmap);
  484. dev_err(&i2c->dev,
  485. "Failed to allocate regmap: %d\n", ret);
  486. return ret;
  487. }
  488. /* voltage/current slot & gpio configuration */
  489. max98373_slot_config(&i2c->dev, max98373);
  490. /* Power on device */
  491. if (gpio_is_valid(max98373->reset_gpio)) {
  492. ret = devm_gpio_request(&i2c->dev, max98373->reset_gpio,
  493. "MAX98373_RESET");
  494. if (ret) {
  495. dev_err(&i2c->dev, "%s: Failed to request gpio %d\n",
  496. __func__, max98373->reset_gpio);
  497. return -EINVAL;
  498. }
  499. gpio_direction_output(max98373->reset_gpio, 0);
  500. msleep(50);
  501. gpio_direction_output(max98373->reset_gpio, 1);
  502. msleep(20);
  503. }
  504. /* Check Revision ID */
  505. ret = regmap_read(max98373->regmap,
  506. MAX98373_R21FF_REV_ID, &reg);
  507. if (ret < 0) {
  508. dev_err(&i2c->dev,
  509. "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID);
  510. return ret;
  511. }
  512. dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg);
  513. /* codec registration */
  514. ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373,
  515. max98373_dai, ARRAY_SIZE(max98373_dai));
  516. if (ret < 0)
  517. dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
  518. return ret;
  519. }
  520. static const struct i2c_device_id max98373_i2c_id[] = {
  521. { "max98373", 0},
  522. { },
  523. };
  524. MODULE_DEVICE_TABLE(i2c, max98373_i2c_id);
  525. #if defined(CONFIG_OF)
  526. static const struct of_device_id max98373_of_match[] = {
  527. { .compatible = "maxim,max98373", },
  528. { }
  529. };
  530. MODULE_DEVICE_TABLE(of, max98373_of_match);
  531. #endif
  532. #ifdef CONFIG_ACPI
  533. static const struct acpi_device_id max98373_acpi_match[] = {
  534. { "MX98373", 0 },
  535. {},
  536. };
  537. MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
  538. #endif
  539. static struct i2c_driver max98373_i2c_driver = {
  540. .driver = {
  541. .name = "max98373",
  542. .of_match_table = of_match_ptr(max98373_of_match),
  543. .acpi_match_table = ACPI_PTR(max98373_acpi_match),
  544. .pm = &max98373_pm,
  545. },
  546. .probe = max98373_i2c_probe,
  547. .id_table = max98373_i2c_id,
  548. };
  549. module_i2c_driver(max98373_i2c_driver)
  550. MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
  551. MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
  552. MODULE_LICENSE("GPL");