max98095.c 62 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * max98095.c -- MAX98095 ALSA SoC Audio driver
  4. *
  5. * Copyright 2011 Maxim Integrated Products
  6. */
  7. #include <linux/module.h>
  8. #include <linux/moduleparam.h>
  9. #include <linux/kernel.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/i2c.h>
  14. #include <linux/clk.h>
  15. #include <linux/mutex.h>
  16. #include <sound/core.h>
  17. #include <sound/pcm.h>
  18. #include <sound/pcm_params.h>
  19. #include <sound/soc.h>
  20. #include <sound/initval.h>
  21. #include <sound/tlv.h>
  22. #include <linux/slab.h>
  23. #include <asm/div64.h>
  24. #include <sound/max98095.h>
  25. #include <sound/jack.h>
  26. #include "max98095.h"
  27. enum max98095_type {
  28. MAX98095,
  29. };
  30. struct max98095_cdata {
  31. unsigned int rate;
  32. unsigned int fmt;
  33. int eq_sel;
  34. int bq_sel;
  35. };
  36. struct max98095_priv {
  37. struct regmap *regmap;
  38. enum max98095_type devtype;
  39. struct max98095_pdata *pdata;
  40. struct clk *mclk;
  41. unsigned int sysclk;
  42. struct max98095_cdata dai[3];
  43. const char **eq_texts;
  44. const char **bq_texts;
  45. struct soc_enum eq_enum;
  46. struct soc_enum bq_enum;
  47. int eq_textcnt;
  48. int bq_textcnt;
  49. u8 lin_state;
  50. unsigned int mic1pre;
  51. unsigned int mic2pre;
  52. struct snd_soc_jack *headphone_jack;
  53. struct snd_soc_jack *mic_jack;
  54. struct mutex lock;
  55. };
  56. static const struct reg_default max98095_reg_def[] = {
  57. { 0xf, 0x00 }, /* 0F */
  58. { 0x10, 0x00 }, /* 10 */
  59. { 0x11, 0x00 }, /* 11 */
  60. { 0x12, 0x00 }, /* 12 */
  61. { 0x13, 0x00 }, /* 13 */
  62. { 0x14, 0x00 }, /* 14 */
  63. { 0x15, 0x00 }, /* 15 */
  64. { 0x16, 0x00 }, /* 16 */
  65. { 0x17, 0x00 }, /* 17 */
  66. { 0x18, 0x00 }, /* 18 */
  67. { 0x19, 0x00 }, /* 19 */
  68. { 0x1a, 0x00 }, /* 1A */
  69. { 0x1b, 0x00 }, /* 1B */
  70. { 0x1c, 0x00 }, /* 1C */
  71. { 0x1d, 0x00 }, /* 1D */
  72. { 0x1e, 0x00 }, /* 1E */
  73. { 0x1f, 0x00 }, /* 1F */
  74. { 0x20, 0x00 }, /* 20 */
  75. { 0x21, 0x00 }, /* 21 */
  76. { 0x22, 0x00 }, /* 22 */
  77. { 0x23, 0x00 }, /* 23 */
  78. { 0x24, 0x00 }, /* 24 */
  79. { 0x25, 0x00 }, /* 25 */
  80. { 0x26, 0x00 }, /* 26 */
  81. { 0x27, 0x00 }, /* 27 */
  82. { 0x28, 0x00 }, /* 28 */
  83. { 0x29, 0x00 }, /* 29 */
  84. { 0x2a, 0x00 }, /* 2A */
  85. { 0x2b, 0x00 }, /* 2B */
  86. { 0x2c, 0x00 }, /* 2C */
  87. { 0x2d, 0x00 }, /* 2D */
  88. { 0x2e, 0x00 }, /* 2E */
  89. { 0x2f, 0x00 }, /* 2F */
  90. { 0x30, 0x00 }, /* 30 */
  91. { 0x31, 0x00 }, /* 31 */
  92. { 0x32, 0x00 }, /* 32 */
  93. { 0x33, 0x00 }, /* 33 */
  94. { 0x34, 0x00 }, /* 34 */
  95. { 0x35, 0x00 }, /* 35 */
  96. { 0x36, 0x00 }, /* 36 */
  97. { 0x37, 0x00 }, /* 37 */
  98. { 0x38, 0x00 }, /* 38 */
  99. { 0x39, 0x00 }, /* 39 */
  100. { 0x3a, 0x00 }, /* 3A */
  101. { 0x3b, 0x00 }, /* 3B */
  102. { 0x3c, 0x00 }, /* 3C */
  103. { 0x3d, 0x00 }, /* 3D */
  104. { 0x3e, 0x00 }, /* 3E */
  105. { 0x3f, 0x00 }, /* 3F */
  106. { 0x40, 0x00 }, /* 40 */
  107. { 0x41, 0x00 }, /* 41 */
  108. { 0x42, 0x00 }, /* 42 */
  109. { 0x43, 0x00 }, /* 43 */
  110. { 0x44, 0x00 }, /* 44 */
  111. { 0x45, 0x00 }, /* 45 */
  112. { 0x46, 0x00 }, /* 46 */
  113. { 0x47, 0x00 }, /* 47 */
  114. { 0x48, 0x00 }, /* 48 */
  115. { 0x49, 0x00 }, /* 49 */
  116. { 0x4a, 0x00 }, /* 4A */
  117. { 0x4b, 0x00 }, /* 4B */
  118. { 0x4c, 0x00 }, /* 4C */
  119. { 0x4d, 0x00 }, /* 4D */
  120. { 0x4e, 0x00 }, /* 4E */
  121. { 0x4f, 0x00 }, /* 4F */
  122. { 0x50, 0x00 }, /* 50 */
  123. { 0x51, 0x00 }, /* 51 */
  124. { 0x52, 0x00 }, /* 52 */
  125. { 0x53, 0x00 }, /* 53 */
  126. { 0x54, 0x00 }, /* 54 */
  127. { 0x55, 0x00 }, /* 55 */
  128. { 0x56, 0x00 }, /* 56 */
  129. { 0x57, 0x00 }, /* 57 */
  130. { 0x58, 0x00 }, /* 58 */
  131. { 0x59, 0x00 }, /* 59 */
  132. { 0x5a, 0x00 }, /* 5A */
  133. { 0x5b, 0x00 }, /* 5B */
  134. { 0x5c, 0x00 }, /* 5C */
  135. { 0x5d, 0x00 }, /* 5D */
  136. { 0x5e, 0x00 }, /* 5E */
  137. { 0x5f, 0x00 }, /* 5F */
  138. { 0x60, 0x00 }, /* 60 */
  139. { 0x61, 0x00 }, /* 61 */
  140. { 0x62, 0x00 }, /* 62 */
  141. { 0x63, 0x00 }, /* 63 */
  142. { 0x64, 0x00 }, /* 64 */
  143. { 0x65, 0x00 }, /* 65 */
  144. { 0x66, 0x00 }, /* 66 */
  145. { 0x67, 0x00 }, /* 67 */
  146. { 0x68, 0x00 }, /* 68 */
  147. { 0x69, 0x00 }, /* 69 */
  148. { 0x6a, 0x00 }, /* 6A */
  149. { 0x6b, 0x00 }, /* 6B */
  150. { 0x6c, 0x00 }, /* 6C */
  151. { 0x6d, 0x00 }, /* 6D */
  152. { 0x6e, 0x00 }, /* 6E */
  153. { 0x6f, 0x00 }, /* 6F */
  154. { 0x70, 0x00 }, /* 70 */
  155. { 0x71, 0x00 }, /* 71 */
  156. { 0x72, 0x00 }, /* 72 */
  157. { 0x73, 0x00 }, /* 73 */
  158. { 0x74, 0x00 }, /* 74 */
  159. { 0x75, 0x00 }, /* 75 */
  160. { 0x76, 0x00 }, /* 76 */
  161. { 0x77, 0x00 }, /* 77 */
  162. { 0x78, 0x00 }, /* 78 */
  163. { 0x79, 0x00 }, /* 79 */
  164. { 0x7a, 0x00 }, /* 7A */
  165. { 0x7b, 0x00 }, /* 7B */
  166. { 0x7c, 0x00 }, /* 7C */
  167. { 0x7d, 0x00 }, /* 7D */
  168. { 0x7e, 0x00 }, /* 7E */
  169. { 0x7f, 0x00 }, /* 7F */
  170. { 0x80, 0x00 }, /* 80 */
  171. { 0x81, 0x00 }, /* 81 */
  172. { 0x82, 0x00 }, /* 82 */
  173. { 0x83, 0x00 }, /* 83 */
  174. { 0x84, 0x00 }, /* 84 */
  175. { 0x85, 0x00 }, /* 85 */
  176. { 0x86, 0x00 }, /* 86 */
  177. { 0x87, 0x00 }, /* 87 */
  178. { 0x88, 0x00 }, /* 88 */
  179. { 0x89, 0x00 }, /* 89 */
  180. { 0x8a, 0x00 }, /* 8A */
  181. { 0x8b, 0x00 }, /* 8B */
  182. { 0x8c, 0x00 }, /* 8C */
  183. { 0x8d, 0x00 }, /* 8D */
  184. { 0x8e, 0x00 }, /* 8E */
  185. { 0x8f, 0x00 }, /* 8F */
  186. { 0x90, 0x00 }, /* 90 */
  187. { 0x91, 0x00 }, /* 91 */
  188. { 0x92, 0x30 }, /* 92 */
  189. { 0x93, 0xF0 }, /* 93 */
  190. { 0x94, 0x00 }, /* 94 */
  191. { 0x95, 0x00 }, /* 95 */
  192. { 0x96, 0x3F }, /* 96 */
  193. { 0x97, 0x00 }, /* 97 */
  194. { 0xff, 0x00 }, /* FF */
  195. };
  196. static bool max98095_readable(struct device *dev, unsigned int reg)
  197. {
  198. switch (reg) {
  199. case M98095_001_HOST_INT_STS ... M98095_097_PWR_SYS:
  200. case M98095_0FF_REV_ID:
  201. return true;
  202. default:
  203. return false;
  204. }
  205. }
  206. static bool max98095_writeable(struct device *dev, unsigned int reg)
  207. {
  208. switch (reg) {
  209. case M98095_00F_HOST_CFG ... M98095_097_PWR_SYS:
  210. return true;
  211. default:
  212. return false;
  213. }
  214. }
  215. static bool max98095_volatile(struct device *dev, unsigned int reg)
  216. {
  217. switch (reg) {
  218. case M98095_000_HOST_DATA ... M98095_00E_TEMP_SENSOR_STS:
  219. case M98095_REG_MAX_CACHED + 1 ... M98095_0FF_REV_ID:
  220. return true;
  221. default:
  222. return false;
  223. }
  224. }
  225. static const struct regmap_config max98095_regmap = {
  226. .reg_bits = 8,
  227. .val_bits = 8,
  228. .reg_defaults = max98095_reg_def,
  229. .num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
  230. .max_register = M98095_0FF_REV_ID,
  231. .cache_type = REGCACHE_RBTREE,
  232. .readable_reg = max98095_readable,
  233. .writeable_reg = max98095_writeable,
  234. .volatile_reg = max98095_volatile,
  235. };
  236. /*
  237. * Load equalizer DSP coefficient configurations registers
  238. */
  239. static void m98095_eq_band(struct snd_soc_component *component, unsigned int dai,
  240. unsigned int band, u16 *coefs)
  241. {
  242. unsigned int eq_reg;
  243. unsigned int i;
  244. if (WARN_ON(band > 4) ||
  245. WARN_ON(dai > 1))
  246. return;
  247. /* Load the base register address */
  248. eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
  249. /* Add the band address offset, note adjustment for word address */
  250. eq_reg += band * (M98095_COEFS_PER_BAND << 1);
  251. /* Step through the registers and coefs */
  252. for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
  253. snd_soc_component_write(component, eq_reg++, M98095_BYTE1(coefs[i]));
  254. snd_soc_component_write(component, eq_reg++, M98095_BYTE0(coefs[i]));
  255. }
  256. }
  257. /*
  258. * Load biquad filter coefficient configurations registers
  259. */
  260. static void m98095_biquad_band(struct snd_soc_component *component, unsigned int dai,
  261. unsigned int band, u16 *coefs)
  262. {
  263. unsigned int bq_reg;
  264. unsigned int i;
  265. if (WARN_ON(band > 1) ||
  266. WARN_ON(dai > 1))
  267. return;
  268. /* Load the base register address */
  269. bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
  270. /* Add the band address offset, note adjustment for word address */
  271. bq_reg += band * (M98095_COEFS_PER_BAND << 1);
  272. /* Step through the registers and coefs */
  273. for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
  274. snd_soc_component_write(component, bq_reg++, M98095_BYTE1(coefs[i]));
  275. snd_soc_component_write(component, bq_reg++, M98095_BYTE0(coefs[i]));
  276. }
  277. }
  278. static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
  279. static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum,
  280. M98095_02E_DAI1_FILTERS, 7,
  281. max98095_fltr_mode);
  282. static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum,
  283. M98095_038_DAI2_FILTERS, 7,
  284. max98095_fltr_mode);
  285. static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
  286. static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum,
  287. M98095_087_CFG_MIC, 0,
  288. max98095_extmic_text);
  289. static const struct snd_kcontrol_new max98095_extmic_mux =
  290. SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
  291. static const char * const max98095_linein_text[] = { "INA", "INB" };
  292. static SOC_ENUM_SINGLE_DECL(max98095_linein_enum,
  293. M98095_086_CFG_LINE, 6,
  294. max98095_linein_text);
  295. static const struct snd_kcontrol_new max98095_linein_mux =
  296. SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
  297. static const char * const max98095_line_mode_text[] = {
  298. "Stereo", "Differential"};
  299. static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum,
  300. M98095_086_CFG_LINE, 7,
  301. max98095_line_mode_text);
  302. static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum,
  303. M98095_086_CFG_LINE, 4,
  304. max98095_line_mode_text);
  305. static const char * const max98095_dai_fltr[] = {
  306. "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
  307. "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
  308. static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum,
  309. M98095_02E_DAI1_FILTERS, 0,
  310. max98095_dai_fltr);
  311. static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum,
  312. M98095_038_DAI2_FILTERS, 0,
  313. max98095_dai_fltr);
  314. static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum,
  315. M98095_042_DAI3_FILTERS, 0,
  316. max98095_dai_fltr);
  317. static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
  318. struct snd_ctl_elem_value *ucontrol)
  319. {
  320. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  321. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  322. unsigned int sel = ucontrol->value.integer.value[0];
  323. max98095->mic1pre = sel;
  324. snd_soc_component_update_bits(component, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
  325. (1+sel)<<M98095_MICPRE_SHIFT);
  326. return 0;
  327. }
  328. static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
  329. struct snd_ctl_elem_value *ucontrol)
  330. {
  331. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  332. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  333. ucontrol->value.integer.value[0] = max98095->mic1pre;
  334. return 0;
  335. }
  336. static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
  337. struct snd_ctl_elem_value *ucontrol)
  338. {
  339. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  340. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  341. unsigned int sel = ucontrol->value.integer.value[0];
  342. max98095->mic2pre = sel;
  343. snd_soc_component_update_bits(component, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
  344. (1+sel)<<M98095_MICPRE_SHIFT);
  345. return 0;
  346. }
  347. static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
  348. struct snd_ctl_elem_value *ucontrol)
  349. {
  350. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  351. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  352. ucontrol->value.integer.value[0] = max98095->mic2pre;
  353. return 0;
  354. }
  355. static const DECLARE_TLV_DB_RANGE(max98095_micboost_tlv,
  356. 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
  357. 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
  358. );
  359. static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
  360. static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
  361. static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
  362. static const DECLARE_TLV_DB_RANGE(max98095_hp_tlv,
  363. 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
  364. 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
  365. 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
  366. 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
  367. 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
  368. );
  369. static const DECLARE_TLV_DB_RANGE(max98095_spk_tlv,
  370. 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
  371. 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
  372. 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
  373. 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0)
  374. );
  375. static const DECLARE_TLV_DB_RANGE(max98095_rcv_lout_tlv,
  376. 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
  377. 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
  378. 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
  379. 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
  380. 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
  381. );
  382. static const DECLARE_TLV_DB_RANGE(max98095_lin_tlv,
  383. 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
  384. 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
  385. 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
  386. );
  387. static const struct snd_kcontrol_new max98095_snd_controls[] = {
  388. SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
  389. M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
  390. SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
  391. M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
  392. SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
  393. 0, 31, 0, max98095_rcv_lout_tlv),
  394. SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
  395. M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
  396. SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
  397. M98095_065_LVL_HP_R, 7, 1, 1),
  398. SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
  399. M98095_068_LVL_SPK_R, 7, 1, 1),
  400. SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
  401. SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
  402. M98095_063_LVL_LINEOUT2, 7, 1, 1),
  403. SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
  404. max98095_mic_tlv),
  405. SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
  406. max98095_mic_tlv),
  407. SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
  408. M98095_05F_LVL_MIC1, 5, 2, 0,
  409. max98095_mic1pre_get, max98095_mic1pre_set,
  410. max98095_micboost_tlv),
  411. SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
  412. M98095_060_LVL_MIC2, 5, 2, 0,
  413. max98095_mic2pre_get, max98095_mic2pre_set,
  414. max98095_micboost_tlv),
  415. SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
  416. max98095_lin_tlv),
  417. SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
  418. max98095_adc_tlv),
  419. SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
  420. max98095_adc_tlv),
  421. SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
  422. max98095_adcboost_tlv),
  423. SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
  424. max98095_adcboost_tlv),
  425. SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
  426. SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
  427. SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
  428. SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
  429. SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
  430. SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
  431. SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
  432. SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
  433. SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
  434. SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
  435. SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
  436. };
  437. /* Left speaker mixer switch */
  438. static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
  439. SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
  440. SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
  441. SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
  442. SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
  443. SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
  444. SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
  445. SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
  446. SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
  447. };
  448. /* Right speaker mixer switch */
  449. static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
  450. SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
  451. SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
  452. SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
  453. SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
  454. SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
  455. SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
  456. SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
  457. SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
  458. };
  459. /* Left headphone mixer switch */
  460. static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
  461. SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
  462. SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
  463. SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
  464. SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
  465. SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
  466. SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
  467. };
  468. /* Right headphone mixer switch */
  469. static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
  470. SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
  471. SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
  472. SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
  473. SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
  474. SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
  475. SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
  476. };
  477. /* Receiver earpiece mixer switch */
  478. static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
  479. SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
  480. SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
  481. SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
  482. SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
  483. SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
  484. SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
  485. };
  486. /* Left lineout mixer switch */
  487. static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
  488. SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
  489. SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
  490. SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
  491. SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
  492. SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
  493. SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
  494. };
  495. /* Right lineout mixer switch */
  496. static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
  497. SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
  498. SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
  499. SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
  500. SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
  501. SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
  502. SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
  503. };
  504. /* Left ADC mixer switch */
  505. static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
  506. SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
  507. SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
  508. SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
  509. SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
  510. };
  511. /* Right ADC mixer switch */
  512. static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
  513. SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
  514. SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
  515. SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
  516. SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
  517. };
  518. static int max98095_mic_event(struct snd_soc_dapm_widget *w,
  519. struct snd_kcontrol *kcontrol, int event)
  520. {
  521. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  522. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  523. switch (event) {
  524. case SND_SOC_DAPM_POST_PMU:
  525. if (w->reg == M98095_05F_LVL_MIC1) {
  526. snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
  527. (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
  528. } else {
  529. snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK,
  530. (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
  531. }
  532. break;
  533. case SND_SOC_DAPM_POST_PMD:
  534. snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, 0);
  535. break;
  536. default:
  537. return -EINVAL;
  538. }
  539. return 0;
  540. }
  541. /*
  542. * The line inputs are stereo inputs with the left and right
  543. * channels sharing a common PGA power control signal.
  544. */
  545. static int max98095_line_pga(struct snd_soc_dapm_widget *w,
  546. int event, u8 channel)
  547. {
  548. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  549. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  550. u8 *state;
  551. if (WARN_ON(!(channel == 1 || channel == 2)))
  552. return -EINVAL;
  553. state = &max98095->lin_state;
  554. switch (event) {
  555. case SND_SOC_DAPM_POST_PMU:
  556. *state |= channel;
  557. snd_soc_component_update_bits(component, w->reg,
  558. (1 << w->shift), (1 << w->shift));
  559. break;
  560. case SND_SOC_DAPM_POST_PMD:
  561. *state &= ~channel;
  562. if (*state == 0) {
  563. snd_soc_component_update_bits(component, w->reg,
  564. (1 << w->shift), 0);
  565. }
  566. break;
  567. default:
  568. return -EINVAL;
  569. }
  570. return 0;
  571. }
  572. static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
  573. struct snd_kcontrol *k, int event)
  574. {
  575. return max98095_line_pga(w, event, 1);
  576. }
  577. static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
  578. struct snd_kcontrol *k, int event)
  579. {
  580. return max98095_line_pga(w, event, 2);
  581. }
  582. /*
  583. * The stereo line out mixer outputs to two stereo line outs.
  584. * The 2nd pair has a separate set of enables.
  585. */
  586. static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
  587. struct snd_kcontrol *kcontrol, int event)
  588. {
  589. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  590. switch (event) {
  591. case SND_SOC_DAPM_POST_PMU:
  592. snd_soc_component_update_bits(component, w->reg,
  593. (1 << (w->shift+2)), (1 << (w->shift+2)));
  594. break;
  595. case SND_SOC_DAPM_POST_PMD:
  596. snd_soc_component_update_bits(component, w->reg,
  597. (1 << (w->shift+2)), 0);
  598. break;
  599. default:
  600. return -EINVAL;
  601. }
  602. return 0;
  603. }
  604. static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
  605. SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
  606. SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
  607. SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
  608. M98095_091_PWR_EN_OUT, 0, 0),
  609. SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
  610. M98095_091_PWR_EN_OUT, 1, 0),
  611. SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
  612. M98095_091_PWR_EN_OUT, 2, 0),
  613. SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
  614. M98095_091_PWR_EN_OUT, 2, 0),
  615. SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
  616. 6, 0, NULL, 0),
  617. SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
  618. 7, 0, NULL, 0),
  619. SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
  620. 4, 0, NULL, 0),
  621. SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
  622. 5, 0, NULL, 0),
  623. SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
  624. 3, 0, NULL, 0),
  625. SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
  626. 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
  627. SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
  628. 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
  629. SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
  630. &max98095_extmic_mux),
  631. SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
  632. &max98095_linein_mux),
  633. SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
  634. &max98095_left_hp_mixer_controls[0],
  635. ARRAY_SIZE(max98095_left_hp_mixer_controls)),
  636. SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
  637. &max98095_right_hp_mixer_controls[0],
  638. ARRAY_SIZE(max98095_right_hp_mixer_controls)),
  639. SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
  640. &max98095_left_speaker_mixer_controls[0],
  641. ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
  642. SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
  643. &max98095_right_speaker_mixer_controls[0],
  644. ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
  645. SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
  646. &max98095_mono_rcv_mixer_controls[0],
  647. ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
  648. SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
  649. &max98095_left_lineout_mixer_controls[0],
  650. ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
  651. SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
  652. &max98095_right_lineout_mixer_controls[0],
  653. ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
  654. SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
  655. &max98095_left_ADC_mixer_controls[0],
  656. ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
  657. SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
  658. &max98095_right_ADC_mixer_controls[0],
  659. ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
  660. SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
  661. 5, 0, NULL, 0, max98095_mic_event,
  662. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  663. SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
  664. 5, 0, NULL, 0, max98095_mic_event,
  665. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  666. SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
  667. 7, 0, NULL, 0, max98095_pga_in1_event,
  668. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  669. SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
  670. 7, 0, NULL, 0, max98095_pga_in2_event,
  671. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  672. SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
  673. SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
  674. SND_SOC_DAPM_OUTPUT("HPL"),
  675. SND_SOC_DAPM_OUTPUT("HPR"),
  676. SND_SOC_DAPM_OUTPUT("SPKL"),
  677. SND_SOC_DAPM_OUTPUT("SPKR"),
  678. SND_SOC_DAPM_OUTPUT("RCV"),
  679. SND_SOC_DAPM_OUTPUT("OUT1"),
  680. SND_SOC_DAPM_OUTPUT("OUT2"),
  681. SND_SOC_DAPM_OUTPUT("OUT3"),
  682. SND_SOC_DAPM_OUTPUT("OUT4"),
  683. SND_SOC_DAPM_INPUT("MIC1"),
  684. SND_SOC_DAPM_INPUT("MIC2"),
  685. SND_SOC_DAPM_INPUT("INA1"),
  686. SND_SOC_DAPM_INPUT("INA2"),
  687. SND_SOC_DAPM_INPUT("INB1"),
  688. SND_SOC_DAPM_INPUT("INB2"),
  689. };
  690. static const struct snd_soc_dapm_route max98095_audio_map[] = {
  691. /* Left headphone output mixer */
  692. {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
  693. {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
  694. {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
  695. {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
  696. {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
  697. {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
  698. /* Right headphone output mixer */
  699. {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
  700. {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
  701. {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
  702. {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
  703. {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
  704. {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
  705. /* Left speaker output mixer */
  706. {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
  707. {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
  708. {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
  709. {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
  710. {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
  711. {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
  712. {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
  713. {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
  714. /* Right speaker output mixer */
  715. {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
  716. {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
  717. {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
  718. {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
  719. {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
  720. {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
  721. {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
  722. {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
  723. /* Earpiece/Receiver output mixer */
  724. {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
  725. {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
  726. {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
  727. {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
  728. {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
  729. {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
  730. /* Left Lineout output mixer */
  731. {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
  732. {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
  733. {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
  734. {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
  735. {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
  736. {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
  737. /* Right lineout output mixer */
  738. {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
  739. {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
  740. {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
  741. {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
  742. {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
  743. {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
  744. {"HP Left Out", NULL, "Left Headphone Mixer"},
  745. {"HP Right Out", NULL, "Right Headphone Mixer"},
  746. {"SPK Left Out", NULL, "Left Speaker Mixer"},
  747. {"SPK Right Out", NULL, "Right Speaker Mixer"},
  748. {"RCV Mono Out", NULL, "Receiver Mixer"},
  749. {"LINE Left Out", NULL, "Left Lineout Mixer"},
  750. {"LINE Right Out", NULL, "Right Lineout Mixer"},
  751. {"HPL", NULL, "HP Left Out"},
  752. {"HPR", NULL, "HP Right Out"},
  753. {"SPKL", NULL, "SPK Left Out"},
  754. {"SPKR", NULL, "SPK Right Out"},
  755. {"RCV", NULL, "RCV Mono Out"},
  756. {"OUT1", NULL, "LINE Left Out"},
  757. {"OUT2", NULL, "LINE Right Out"},
  758. {"OUT3", NULL, "LINE Left Out"},
  759. {"OUT4", NULL, "LINE Right Out"},
  760. /* Left ADC input mixer */
  761. {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
  762. {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
  763. {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
  764. {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
  765. /* Right ADC input mixer */
  766. {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
  767. {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
  768. {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
  769. {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
  770. /* Inputs */
  771. {"ADCL", NULL, "Left ADC Mixer"},
  772. {"ADCR", NULL, "Right ADC Mixer"},
  773. {"IN1 Input", NULL, "INA1"},
  774. {"IN2 Input", NULL, "INA2"},
  775. {"MIC1 Input", NULL, "MIC1"},
  776. {"MIC2 Input", NULL, "MIC2"},
  777. };
  778. /* codec mclk clock divider coefficients */
  779. static const struct {
  780. u32 rate;
  781. u8 sr;
  782. } rate_table[] = {
  783. {8000, 0x01},
  784. {11025, 0x02},
  785. {16000, 0x03},
  786. {22050, 0x04},
  787. {24000, 0x05},
  788. {32000, 0x06},
  789. {44100, 0x07},
  790. {48000, 0x08},
  791. {88200, 0x09},
  792. {96000, 0x0A},
  793. };
  794. static int rate_value(int rate, u8 *value)
  795. {
  796. int i;
  797. for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
  798. if (rate_table[i].rate >= rate) {
  799. *value = rate_table[i].sr;
  800. return 0;
  801. }
  802. }
  803. *value = rate_table[0].sr;
  804. return -EINVAL;
  805. }
  806. static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
  807. struct snd_pcm_hw_params *params,
  808. struct snd_soc_dai *dai)
  809. {
  810. struct snd_soc_component *component = dai->component;
  811. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  812. struct max98095_cdata *cdata;
  813. unsigned long long ni;
  814. unsigned int rate;
  815. u8 regval;
  816. cdata = &max98095->dai[0];
  817. rate = params_rate(params);
  818. switch (params_width(params)) {
  819. case 16:
  820. snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
  821. M98095_DAI_WS, 0);
  822. break;
  823. case 24:
  824. snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
  825. M98095_DAI_WS, M98095_DAI_WS);
  826. break;
  827. default:
  828. return -EINVAL;
  829. }
  830. if (rate_value(rate, &regval))
  831. return -EINVAL;
  832. snd_soc_component_update_bits(component, M98095_027_DAI1_CLKMODE,
  833. M98095_CLKMODE_MASK, regval);
  834. cdata->rate = rate;
  835. /* Configure NI when operating as master */
  836. if (snd_soc_component_read(component, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
  837. if (max98095->sysclk == 0) {
  838. dev_err(component->dev, "Invalid system clock frequency\n");
  839. return -EINVAL;
  840. }
  841. ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
  842. * (unsigned long long int)rate;
  843. do_div(ni, (unsigned long long int)max98095->sysclk);
  844. snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
  845. (ni >> 8) & 0x7F);
  846. snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
  847. ni & 0xFF);
  848. }
  849. /* Update sample rate mode */
  850. if (rate < 50000)
  851. snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
  852. M98095_DAI_DHF, 0);
  853. else
  854. snd_soc_component_update_bits(component, M98095_02E_DAI1_FILTERS,
  855. M98095_DAI_DHF, M98095_DAI_DHF);
  856. return 0;
  857. }
  858. static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
  859. struct snd_pcm_hw_params *params,
  860. struct snd_soc_dai *dai)
  861. {
  862. struct snd_soc_component *component = dai->component;
  863. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  864. struct max98095_cdata *cdata;
  865. unsigned long long ni;
  866. unsigned int rate;
  867. u8 regval;
  868. cdata = &max98095->dai[1];
  869. rate = params_rate(params);
  870. switch (params_width(params)) {
  871. case 16:
  872. snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
  873. M98095_DAI_WS, 0);
  874. break;
  875. case 24:
  876. snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
  877. M98095_DAI_WS, M98095_DAI_WS);
  878. break;
  879. default:
  880. return -EINVAL;
  881. }
  882. if (rate_value(rate, &regval))
  883. return -EINVAL;
  884. snd_soc_component_update_bits(component, M98095_031_DAI2_CLKMODE,
  885. M98095_CLKMODE_MASK, regval);
  886. cdata->rate = rate;
  887. /* Configure NI when operating as master */
  888. if (snd_soc_component_read(component, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
  889. if (max98095->sysclk == 0) {
  890. dev_err(component->dev, "Invalid system clock frequency\n");
  891. return -EINVAL;
  892. }
  893. ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
  894. * (unsigned long long int)rate;
  895. do_div(ni, (unsigned long long int)max98095->sysclk);
  896. snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
  897. (ni >> 8) & 0x7F);
  898. snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
  899. ni & 0xFF);
  900. }
  901. /* Update sample rate mode */
  902. if (rate < 50000)
  903. snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
  904. M98095_DAI_DHF, 0);
  905. else
  906. snd_soc_component_update_bits(component, M98095_038_DAI2_FILTERS,
  907. M98095_DAI_DHF, M98095_DAI_DHF);
  908. return 0;
  909. }
  910. static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
  911. struct snd_pcm_hw_params *params,
  912. struct snd_soc_dai *dai)
  913. {
  914. struct snd_soc_component *component = dai->component;
  915. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  916. struct max98095_cdata *cdata;
  917. unsigned long long ni;
  918. unsigned int rate;
  919. u8 regval;
  920. cdata = &max98095->dai[2];
  921. rate = params_rate(params);
  922. switch (params_width(params)) {
  923. case 16:
  924. snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
  925. M98095_DAI_WS, 0);
  926. break;
  927. case 24:
  928. snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
  929. M98095_DAI_WS, M98095_DAI_WS);
  930. break;
  931. default:
  932. return -EINVAL;
  933. }
  934. if (rate_value(rate, &regval))
  935. return -EINVAL;
  936. snd_soc_component_update_bits(component, M98095_03B_DAI3_CLKMODE,
  937. M98095_CLKMODE_MASK, regval);
  938. cdata->rate = rate;
  939. /* Configure NI when operating as master */
  940. if (snd_soc_component_read(component, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
  941. if (max98095->sysclk == 0) {
  942. dev_err(component->dev, "Invalid system clock frequency\n");
  943. return -EINVAL;
  944. }
  945. ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
  946. * (unsigned long long int)rate;
  947. do_div(ni, (unsigned long long int)max98095->sysclk);
  948. snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
  949. (ni >> 8) & 0x7F);
  950. snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
  951. ni & 0xFF);
  952. }
  953. /* Update sample rate mode */
  954. if (rate < 50000)
  955. snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
  956. M98095_DAI_DHF, 0);
  957. else
  958. snd_soc_component_update_bits(component, M98095_042_DAI3_FILTERS,
  959. M98095_DAI_DHF, M98095_DAI_DHF);
  960. return 0;
  961. }
  962. static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
  963. int clk_id, unsigned int freq, int dir)
  964. {
  965. struct snd_soc_component *component = dai->component;
  966. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  967. /* Requested clock frequency is already setup */
  968. if (freq == max98095->sysclk)
  969. return 0;
  970. if (!IS_ERR(max98095->mclk)) {
  971. freq = clk_round_rate(max98095->mclk, freq);
  972. clk_set_rate(max98095->mclk, freq);
  973. }
  974. /* Setup clocks for slave mode, and using the PLL
  975. * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
  976. * 0x02 (when master clk is 20MHz to 40MHz)..
  977. * 0x03 (when master clk is 40MHz to 60MHz)..
  978. */
  979. if ((freq >= 10000000) && (freq < 20000000)) {
  980. snd_soc_component_write(component, M98095_026_SYS_CLK, 0x10);
  981. } else if ((freq >= 20000000) && (freq < 40000000)) {
  982. snd_soc_component_write(component, M98095_026_SYS_CLK, 0x20);
  983. } else if ((freq >= 40000000) && (freq < 60000000)) {
  984. snd_soc_component_write(component, M98095_026_SYS_CLK, 0x30);
  985. } else {
  986. dev_err(component->dev, "Invalid master clock frequency\n");
  987. return -EINVAL;
  988. }
  989. dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
  990. max98095->sysclk = freq;
  991. return 0;
  992. }
  993. static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
  994. unsigned int fmt)
  995. {
  996. struct snd_soc_component *component = codec_dai->component;
  997. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  998. struct max98095_cdata *cdata;
  999. u8 regval = 0;
  1000. cdata = &max98095->dai[0];
  1001. if (fmt != cdata->fmt) {
  1002. cdata->fmt = fmt;
  1003. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1004. case SND_SOC_DAIFMT_CBS_CFS:
  1005. /* Slave mode PLL */
  1006. snd_soc_component_write(component, M98095_028_DAI1_CLKCFG_HI,
  1007. 0x80);
  1008. snd_soc_component_write(component, M98095_029_DAI1_CLKCFG_LO,
  1009. 0x00);
  1010. break;
  1011. case SND_SOC_DAIFMT_CBM_CFM:
  1012. /* Set to master mode */
  1013. regval |= M98095_DAI_MAS;
  1014. break;
  1015. case SND_SOC_DAIFMT_CBS_CFM:
  1016. case SND_SOC_DAIFMT_CBM_CFS:
  1017. default:
  1018. dev_err(component->dev, "Clock mode unsupported");
  1019. return -EINVAL;
  1020. }
  1021. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1022. case SND_SOC_DAIFMT_I2S:
  1023. regval |= M98095_DAI_DLY;
  1024. break;
  1025. case SND_SOC_DAIFMT_LEFT_J:
  1026. break;
  1027. default:
  1028. return -EINVAL;
  1029. }
  1030. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1031. case SND_SOC_DAIFMT_NB_NF:
  1032. break;
  1033. case SND_SOC_DAIFMT_NB_IF:
  1034. regval |= M98095_DAI_WCI;
  1035. break;
  1036. case SND_SOC_DAIFMT_IB_NF:
  1037. regval |= M98095_DAI_BCI;
  1038. break;
  1039. case SND_SOC_DAIFMT_IB_IF:
  1040. regval |= M98095_DAI_BCI|M98095_DAI_WCI;
  1041. break;
  1042. default:
  1043. return -EINVAL;
  1044. }
  1045. snd_soc_component_update_bits(component, M98095_02A_DAI1_FORMAT,
  1046. M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
  1047. M98095_DAI_WCI, regval);
  1048. snd_soc_component_write(component, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
  1049. }
  1050. return 0;
  1051. }
  1052. static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
  1053. unsigned int fmt)
  1054. {
  1055. struct snd_soc_component *component = codec_dai->component;
  1056. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1057. struct max98095_cdata *cdata;
  1058. u8 regval = 0;
  1059. cdata = &max98095->dai[1];
  1060. if (fmt != cdata->fmt) {
  1061. cdata->fmt = fmt;
  1062. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1063. case SND_SOC_DAIFMT_CBS_CFS:
  1064. /* Slave mode PLL */
  1065. snd_soc_component_write(component, M98095_032_DAI2_CLKCFG_HI,
  1066. 0x80);
  1067. snd_soc_component_write(component, M98095_033_DAI2_CLKCFG_LO,
  1068. 0x00);
  1069. break;
  1070. case SND_SOC_DAIFMT_CBM_CFM:
  1071. /* Set to master mode */
  1072. regval |= M98095_DAI_MAS;
  1073. break;
  1074. case SND_SOC_DAIFMT_CBS_CFM:
  1075. case SND_SOC_DAIFMT_CBM_CFS:
  1076. default:
  1077. dev_err(component->dev, "Clock mode unsupported");
  1078. return -EINVAL;
  1079. }
  1080. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1081. case SND_SOC_DAIFMT_I2S:
  1082. regval |= M98095_DAI_DLY;
  1083. break;
  1084. case SND_SOC_DAIFMT_LEFT_J:
  1085. break;
  1086. default:
  1087. return -EINVAL;
  1088. }
  1089. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1090. case SND_SOC_DAIFMT_NB_NF:
  1091. break;
  1092. case SND_SOC_DAIFMT_NB_IF:
  1093. regval |= M98095_DAI_WCI;
  1094. break;
  1095. case SND_SOC_DAIFMT_IB_NF:
  1096. regval |= M98095_DAI_BCI;
  1097. break;
  1098. case SND_SOC_DAIFMT_IB_IF:
  1099. regval |= M98095_DAI_BCI|M98095_DAI_WCI;
  1100. break;
  1101. default:
  1102. return -EINVAL;
  1103. }
  1104. snd_soc_component_update_bits(component, M98095_034_DAI2_FORMAT,
  1105. M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
  1106. M98095_DAI_WCI, regval);
  1107. snd_soc_component_write(component, M98095_035_DAI2_CLOCK,
  1108. M98095_DAI_BSEL64);
  1109. }
  1110. return 0;
  1111. }
  1112. static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
  1113. unsigned int fmt)
  1114. {
  1115. struct snd_soc_component *component = codec_dai->component;
  1116. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1117. struct max98095_cdata *cdata;
  1118. u8 regval = 0;
  1119. cdata = &max98095->dai[2];
  1120. if (fmt != cdata->fmt) {
  1121. cdata->fmt = fmt;
  1122. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1123. case SND_SOC_DAIFMT_CBS_CFS:
  1124. /* Slave mode PLL */
  1125. snd_soc_component_write(component, M98095_03C_DAI3_CLKCFG_HI,
  1126. 0x80);
  1127. snd_soc_component_write(component, M98095_03D_DAI3_CLKCFG_LO,
  1128. 0x00);
  1129. break;
  1130. case SND_SOC_DAIFMT_CBM_CFM:
  1131. /* Set to master mode */
  1132. regval |= M98095_DAI_MAS;
  1133. break;
  1134. case SND_SOC_DAIFMT_CBS_CFM:
  1135. case SND_SOC_DAIFMT_CBM_CFS:
  1136. default:
  1137. dev_err(component->dev, "Clock mode unsupported");
  1138. return -EINVAL;
  1139. }
  1140. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1141. case SND_SOC_DAIFMT_I2S:
  1142. regval |= M98095_DAI_DLY;
  1143. break;
  1144. case SND_SOC_DAIFMT_LEFT_J:
  1145. break;
  1146. default:
  1147. return -EINVAL;
  1148. }
  1149. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1150. case SND_SOC_DAIFMT_NB_NF:
  1151. break;
  1152. case SND_SOC_DAIFMT_NB_IF:
  1153. regval |= M98095_DAI_WCI;
  1154. break;
  1155. case SND_SOC_DAIFMT_IB_NF:
  1156. regval |= M98095_DAI_BCI;
  1157. break;
  1158. case SND_SOC_DAIFMT_IB_IF:
  1159. regval |= M98095_DAI_BCI|M98095_DAI_WCI;
  1160. break;
  1161. default:
  1162. return -EINVAL;
  1163. }
  1164. snd_soc_component_update_bits(component, M98095_03E_DAI3_FORMAT,
  1165. M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
  1166. M98095_DAI_WCI, regval);
  1167. snd_soc_component_write(component, M98095_03F_DAI3_CLOCK,
  1168. M98095_DAI_BSEL64);
  1169. }
  1170. return 0;
  1171. }
  1172. static int max98095_set_bias_level(struct snd_soc_component *component,
  1173. enum snd_soc_bias_level level)
  1174. {
  1175. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1176. int ret;
  1177. switch (level) {
  1178. case SND_SOC_BIAS_ON:
  1179. break;
  1180. case SND_SOC_BIAS_PREPARE:
  1181. /*
  1182. * SND_SOC_BIAS_PREPARE is called while preparing for a
  1183. * transition to ON or away from ON. If current bias_level
  1184. * is SND_SOC_BIAS_ON, then it is preparing for a transition
  1185. * away from ON. Disable the clock in that case, otherwise
  1186. * enable it.
  1187. */
  1188. if (IS_ERR(max98095->mclk))
  1189. break;
  1190. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
  1191. clk_disable_unprepare(max98095->mclk);
  1192. } else {
  1193. ret = clk_prepare_enable(max98095->mclk);
  1194. if (ret)
  1195. return ret;
  1196. }
  1197. break;
  1198. case SND_SOC_BIAS_STANDBY:
  1199. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  1200. ret = regcache_sync(max98095->regmap);
  1201. if (ret != 0) {
  1202. dev_err(component->dev, "Failed to sync cache: %d\n", ret);
  1203. return ret;
  1204. }
  1205. }
  1206. snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
  1207. M98095_MBEN, M98095_MBEN);
  1208. break;
  1209. case SND_SOC_BIAS_OFF:
  1210. snd_soc_component_update_bits(component, M98095_090_PWR_EN_IN,
  1211. M98095_MBEN, 0);
  1212. regcache_mark_dirty(max98095->regmap);
  1213. break;
  1214. }
  1215. return 0;
  1216. }
  1217. #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
  1218. #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
  1219. static const struct snd_soc_dai_ops max98095_dai1_ops = {
  1220. .set_sysclk = max98095_dai_set_sysclk,
  1221. .set_fmt = max98095_dai1_set_fmt,
  1222. .hw_params = max98095_dai1_hw_params,
  1223. };
  1224. static const struct snd_soc_dai_ops max98095_dai2_ops = {
  1225. .set_sysclk = max98095_dai_set_sysclk,
  1226. .set_fmt = max98095_dai2_set_fmt,
  1227. .hw_params = max98095_dai2_hw_params,
  1228. };
  1229. static const struct snd_soc_dai_ops max98095_dai3_ops = {
  1230. .set_sysclk = max98095_dai_set_sysclk,
  1231. .set_fmt = max98095_dai3_set_fmt,
  1232. .hw_params = max98095_dai3_hw_params,
  1233. };
  1234. static struct snd_soc_dai_driver max98095_dai[] = {
  1235. {
  1236. .name = "HiFi",
  1237. .playback = {
  1238. .stream_name = "HiFi Playback",
  1239. .channels_min = 1,
  1240. .channels_max = 2,
  1241. .rates = MAX98095_RATES,
  1242. .formats = MAX98095_FORMATS,
  1243. },
  1244. .capture = {
  1245. .stream_name = "HiFi Capture",
  1246. .channels_min = 1,
  1247. .channels_max = 2,
  1248. .rates = MAX98095_RATES,
  1249. .formats = MAX98095_FORMATS,
  1250. },
  1251. .ops = &max98095_dai1_ops,
  1252. },
  1253. {
  1254. .name = "Aux",
  1255. .playback = {
  1256. .stream_name = "Aux Playback",
  1257. .channels_min = 1,
  1258. .channels_max = 1,
  1259. .rates = MAX98095_RATES,
  1260. .formats = MAX98095_FORMATS,
  1261. },
  1262. .ops = &max98095_dai2_ops,
  1263. },
  1264. {
  1265. .name = "Voice",
  1266. .playback = {
  1267. .stream_name = "Voice Playback",
  1268. .channels_min = 1,
  1269. .channels_max = 1,
  1270. .rates = MAX98095_RATES,
  1271. .formats = MAX98095_FORMATS,
  1272. },
  1273. .ops = &max98095_dai3_ops,
  1274. }
  1275. };
  1276. static int max98095_get_eq_channel(const char *name)
  1277. {
  1278. if (strcmp(name, "EQ1 Mode") == 0)
  1279. return 0;
  1280. if (strcmp(name, "EQ2 Mode") == 0)
  1281. return 1;
  1282. return -EINVAL;
  1283. }
  1284. static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
  1285. struct snd_ctl_elem_value *ucontrol)
  1286. {
  1287. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1288. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1289. struct max98095_pdata *pdata = max98095->pdata;
  1290. int channel = max98095_get_eq_channel(kcontrol->id.name);
  1291. struct max98095_cdata *cdata;
  1292. unsigned int sel = ucontrol->value.enumerated.item[0];
  1293. struct max98095_eq_cfg *coef_set;
  1294. int fs, best, best_val, i;
  1295. int regmask, regsave;
  1296. if (WARN_ON(channel > 1))
  1297. return -EINVAL;
  1298. if (!pdata || !max98095->eq_textcnt)
  1299. return 0;
  1300. if (sel >= pdata->eq_cfgcnt)
  1301. return -EINVAL;
  1302. cdata = &max98095->dai[channel];
  1303. cdata->eq_sel = sel;
  1304. fs = cdata->rate;
  1305. /* Find the selected configuration with nearest sample rate */
  1306. best = 0;
  1307. best_val = INT_MAX;
  1308. for (i = 0; i < pdata->eq_cfgcnt; i++) {
  1309. if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
  1310. abs(pdata->eq_cfg[i].rate - fs) < best_val) {
  1311. best = i;
  1312. best_val = abs(pdata->eq_cfg[i].rate - fs);
  1313. }
  1314. }
  1315. dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
  1316. pdata->eq_cfg[best].name,
  1317. pdata->eq_cfg[best].rate, fs);
  1318. coef_set = &pdata->eq_cfg[best];
  1319. regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
  1320. /* Disable filter while configuring, and save current on/off state */
  1321. regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
  1322. snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
  1323. mutex_lock(&max98095->lock);
  1324. snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
  1325. m98095_eq_band(component, channel, 0, coef_set->band1);
  1326. m98095_eq_band(component, channel, 1, coef_set->band2);
  1327. m98095_eq_band(component, channel, 2, coef_set->band3);
  1328. m98095_eq_band(component, channel, 3, coef_set->band4);
  1329. m98095_eq_band(component, channel, 4, coef_set->band5);
  1330. snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, 0);
  1331. mutex_unlock(&max98095->lock);
  1332. /* Restore the original on/off state */
  1333. snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
  1334. return 0;
  1335. }
  1336. static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
  1337. struct snd_ctl_elem_value *ucontrol)
  1338. {
  1339. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1340. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1341. int channel = max98095_get_eq_channel(kcontrol->id.name);
  1342. struct max98095_cdata *cdata;
  1343. cdata = &max98095->dai[channel];
  1344. ucontrol->value.enumerated.item[0] = cdata->eq_sel;
  1345. return 0;
  1346. }
  1347. static void max98095_handle_eq_pdata(struct snd_soc_component *component)
  1348. {
  1349. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1350. struct max98095_pdata *pdata = max98095->pdata;
  1351. struct max98095_eq_cfg *cfg;
  1352. unsigned int cfgcnt;
  1353. int i, j;
  1354. const char **t;
  1355. int ret;
  1356. struct snd_kcontrol_new controls[] = {
  1357. SOC_ENUM_EXT("EQ1 Mode",
  1358. max98095->eq_enum,
  1359. max98095_get_eq_enum,
  1360. max98095_put_eq_enum),
  1361. SOC_ENUM_EXT("EQ2 Mode",
  1362. max98095->eq_enum,
  1363. max98095_get_eq_enum,
  1364. max98095_put_eq_enum),
  1365. };
  1366. cfg = pdata->eq_cfg;
  1367. cfgcnt = pdata->eq_cfgcnt;
  1368. /* Setup an array of texts for the equalizer enum.
  1369. * This is based on Mark Brown's equalizer driver code.
  1370. */
  1371. max98095->eq_textcnt = 0;
  1372. max98095->eq_texts = NULL;
  1373. for (i = 0; i < cfgcnt; i++) {
  1374. for (j = 0; j < max98095->eq_textcnt; j++) {
  1375. if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
  1376. break;
  1377. }
  1378. if (j != max98095->eq_textcnt)
  1379. continue;
  1380. /* Expand the array */
  1381. t = krealloc(max98095->eq_texts,
  1382. sizeof(char *) * (max98095->eq_textcnt + 1),
  1383. GFP_KERNEL);
  1384. if (t == NULL)
  1385. continue;
  1386. /* Store the new entry */
  1387. t[max98095->eq_textcnt] = cfg[i].name;
  1388. max98095->eq_textcnt++;
  1389. max98095->eq_texts = t;
  1390. }
  1391. /* Now point the soc_enum to .texts array items */
  1392. max98095->eq_enum.texts = max98095->eq_texts;
  1393. max98095->eq_enum.items = max98095->eq_textcnt;
  1394. ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
  1395. if (ret != 0)
  1396. dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
  1397. }
  1398. static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
  1399. static int max98095_get_bq_channel(struct snd_soc_component *component,
  1400. const char *name)
  1401. {
  1402. int ret;
  1403. ret = match_string(bq_mode_name, ARRAY_SIZE(bq_mode_name), name);
  1404. if (ret < 0)
  1405. dev_err(component->dev, "Bad biquad channel name '%s'\n", name);
  1406. return ret;
  1407. }
  1408. static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
  1409. struct snd_ctl_elem_value *ucontrol)
  1410. {
  1411. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1412. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1413. struct max98095_pdata *pdata = max98095->pdata;
  1414. int channel = max98095_get_bq_channel(component, kcontrol->id.name);
  1415. struct max98095_cdata *cdata;
  1416. unsigned int sel = ucontrol->value.enumerated.item[0];
  1417. struct max98095_biquad_cfg *coef_set;
  1418. int fs, best, best_val, i;
  1419. int regmask, regsave;
  1420. if (channel < 0)
  1421. return channel;
  1422. if (!pdata || !max98095->bq_textcnt)
  1423. return 0;
  1424. if (sel >= pdata->bq_cfgcnt)
  1425. return -EINVAL;
  1426. cdata = &max98095->dai[channel];
  1427. cdata->bq_sel = sel;
  1428. fs = cdata->rate;
  1429. /* Find the selected configuration with nearest sample rate */
  1430. best = 0;
  1431. best_val = INT_MAX;
  1432. for (i = 0; i < pdata->bq_cfgcnt; i++) {
  1433. if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
  1434. abs(pdata->bq_cfg[i].rate - fs) < best_val) {
  1435. best = i;
  1436. best_val = abs(pdata->bq_cfg[i].rate - fs);
  1437. }
  1438. }
  1439. dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
  1440. pdata->bq_cfg[best].name,
  1441. pdata->bq_cfg[best].rate, fs);
  1442. coef_set = &pdata->bq_cfg[best];
  1443. regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
  1444. /* Disable filter while configuring, and save current on/off state */
  1445. regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
  1446. snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
  1447. mutex_lock(&max98095->lock);
  1448. snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
  1449. m98095_biquad_band(component, channel, 0, coef_set->band1);
  1450. m98095_biquad_band(component, channel, 1, coef_set->band2);
  1451. snd_soc_component_update_bits(component, M98095_00F_HOST_CFG, M98095_SEG, 0);
  1452. mutex_unlock(&max98095->lock);
  1453. /* Restore the original on/off state */
  1454. snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, regsave);
  1455. return 0;
  1456. }
  1457. static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
  1458. struct snd_ctl_elem_value *ucontrol)
  1459. {
  1460. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1461. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1462. int channel = max98095_get_bq_channel(component, kcontrol->id.name);
  1463. struct max98095_cdata *cdata;
  1464. if (channel < 0)
  1465. return channel;
  1466. cdata = &max98095->dai[channel];
  1467. ucontrol->value.enumerated.item[0] = cdata->bq_sel;
  1468. return 0;
  1469. }
  1470. static void max98095_handle_bq_pdata(struct snd_soc_component *component)
  1471. {
  1472. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1473. struct max98095_pdata *pdata = max98095->pdata;
  1474. struct max98095_biquad_cfg *cfg;
  1475. unsigned int cfgcnt;
  1476. int i, j;
  1477. const char **t;
  1478. int ret;
  1479. struct snd_kcontrol_new controls[] = {
  1480. SOC_ENUM_EXT((char *)bq_mode_name[0],
  1481. max98095->bq_enum,
  1482. max98095_get_bq_enum,
  1483. max98095_put_bq_enum),
  1484. SOC_ENUM_EXT((char *)bq_mode_name[1],
  1485. max98095->bq_enum,
  1486. max98095_get_bq_enum,
  1487. max98095_put_bq_enum),
  1488. };
  1489. BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
  1490. cfg = pdata->bq_cfg;
  1491. cfgcnt = pdata->bq_cfgcnt;
  1492. /* Setup an array of texts for the biquad enum.
  1493. * This is based on Mark Brown's equalizer driver code.
  1494. */
  1495. max98095->bq_textcnt = 0;
  1496. max98095->bq_texts = NULL;
  1497. for (i = 0; i < cfgcnt; i++) {
  1498. for (j = 0; j < max98095->bq_textcnt; j++) {
  1499. if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
  1500. break;
  1501. }
  1502. if (j != max98095->bq_textcnt)
  1503. continue;
  1504. /* Expand the array */
  1505. t = krealloc(max98095->bq_texts,
  1506. sizeof(char *) * (max98095->bq_textcnt + 1),
  1507. GFP_KERNEL);
  1508. if (t == NULL)
  1509. continue;
  1510. /* Store the new entry */
  1511. t[max98095->bq_textcnt] = cfg[i].name;
  1512. max98095->bq_textcnt++;
  1513. max98095->bq_texts = t;
  1514. }
  1515. /* Now point the soc_enum to .texts array items */
  1516. max98095->bq_enum.texts = max98095->bq_texts;
  1517. max98095->bq_enum.items = max98095->bq_textcnt;
  1518. ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
  1519. if (ret != 0)
  1520. dev_err(component->dev, "Failed to add Biquad control: %d\n", ret);
  1521. }
  1522. static void max98095_handle_pdata(struct snd_soc_component *component)
  1523. {
  1524. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1525. struct max98095_pdata *pdata = max98095->pdata;
  1526. u8 regval = 0;
  1527. if (!pdata) {
  1528. dev_dbg(component->dev, "No platform data\n");
  1529. return;
  1530. }
  1531. /* Configure mic for analog/digital mic mode */
  1532. if (pdata->digmic_left_mode)
  1533. regval |= M98095_DIGMIC_L;
  1534. if (pdata->digmic_right_mode)
  1535. regval |= M98095_DIGMIC_R;
  1536. snd_soc_component_write(component, M98095_087_CFG_MIC, regval);
  1537. /* Configure equalizers */
  1538. if (pdata->eq_cfgcnt)
  1539. max98095_handle_eq_pdata(component);
  1540. /* Configure bi-quad filters */
  1541. if (pdata->bq_cfgcnt)
  1542. max98095_handle_bq_pdata(component);
  1543. }
  1544. static irqreturn_t max98095_report_jack(int irq, void *data)
  1545. {
  1546. struct snd_soc_component *component = data;
  1547. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1548. unsigned int value;
  1549. int hp_report = 0;
  1550. int mic_report = 0;
  1551. /* Read the Jack Status Register */
  1552. value = snd_soc_component_read(component, M98095_007_JACK_AUTO_STS);
  1553. /* If ddone is not set, then detection isn't finished yet */
  1554. if ((value & M98095_DDONE) == 0)
  1555. return IRQ_NONE;
  1556. /* if hp, check its bit, and if set, clear it */
  1557. if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
  1558. max98095->headphone_jack)
  1559. hp_report |= SND_JACK_HEADPHONE;
  1560. /* if mic, check its bit, and if set, clear it */
  1561. if ((value & M98095_MIC_IN) && max98095->mic_jack)
  1562. mic_report |= SND_JACK_MICROPHONE;
  1563. if (max98095->headphone_jack == max98095->mic_jack) {
  1564. snd_soc_jack_report(max98095->headphone_jack,
  1565. hp_report | mic_report,
  1566. SND_JACK_HEADSET);
  1567. } else {
  1568. if (max98095->headphone_jack)
  1569. snd_soc_jack_report(max98095->headphone_jack,
  1570. hp_report, SND_JACK_HEADPHONE);
  1571. if (max98095->mic_jack)
  1572. snd_soc_jack_report(max98095->mic_jack,
  1573. mic_report, SND_JACK_MICROPHONE);
  1574. }
  1575. return IRQ_HANDLED;
  1576. }
  1577. static int max98095_jack_detect_enable(struct snd_soc_component *component)
  1578. {
  1579. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1580. int ret = 0;
  1581. int detect_enable = M98095_JDEN;
  1582. unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
  1583. if (max98095->pdata->jack_detect_pin5en)
  1584. detect_enable |= M98095_PIN5EN;
  1585. if (max98095->pdata->jack_detect_delay)
  1586. slew = max98095->pdata->jack_detect_delay;
  1587. ret = snd_soc_component_write(component, M98095_08E_JACK_DC_SLEW, slew);
  1588. if (ret < 0) {
  1589. dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
  1590. return ret;
  1591. }
  1592. /* configure auto detection to be enabled */
  1593. ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, detect_enable);
  1594. if (ret < 0) {
  1595. dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
  1596. return ret;
  1597. }
  1598. return ret;
  1599. }
  1600. static int max98095_jack_detect_disable(struct snd_soc_component *component)
  1601. {
  1602. int ret = 0;
  1603. /* configure auto detection to be disabled */
  1604. ret = snd_soc_component_write(component, M98095_089_JACK_DET_AUTO, 0x0);
  1605. if (ret < 0) {
  1606. dev_err(component->dev, "Failed to cfg auto detect %d\n", ret);
  1607. return ret;
  1608. }
  1609. return ret;
  1610. }
  1611. int max98095_jack_detect(struct snd_soc_component *component,
  1612. struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
  1613. {
  1614. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1615. struct i2c_client *client = to_i2c_client(component->dev);
  1616. int ret = 0;
  1617. max98095->headphone_jack = hp_jack;
  1618. max98095->mic_jack = mic_jack;
  1619. /* only progress if we have at least 1 jack pointer */
  1620. if (!hp_jack && !mic_jack)
  1621. return -EINVAL;
  1622. max98095_jack_detect_enable(component);
  1623. /* enable interrupts for headphone jack detection */
  1624. ret = snd_soc_component_update_bits(component, M98095_013_JACK_INT_EN,
  1625. M98095_IDDONE, M98095_IDDONE);
  1626. if (ret < 0) {
  1627. dev_err(component->dev, "Failed to cfg jack irqs %d\n", ret);
  1628. return ret;
  1629. }
  1630. max98095_report_jack(client->irq, component);
  1631. return 0;
  1632. }
  1633. EXPORT_SYMBOL_GPL(max98095_jack_detect);
  1634. #ifdef CONFIG_PM
  1635. static int max98095_suspend(struct snd_soc_component *component)
  1636. {
  1637. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1638. if (max98095->headphone_jack || max98095->mic_jack)
  1639. max98095_jack_detect_disable(component);
  1640. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
  1641. return 0;
  1642. }
  1643. static int max98095_resume(struct snd_soc_component *component)
  1644. {
  1645. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1646. struct i2c_client *client = to_i2c_client(component->dev);
  1647. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
  1648. if (max98095->headphone_jack || max98095->mic_jack) {
  1649. max98095_jack_detect_enable(component);
  1650. max98095_report_jack(client->irq, component);
  1651. }
  1652. return 0;
  1653. }
  1654. #else
  1655. #define max98095_suspend NULL
  1656. #define max98095_resume NULL
  1657. #endif
  1658. static int max98095_reset(struct snd_soc_component *component)
  1659. {
  1660. int i, ret;
  1661. /* Gracefully reset the DSP core and the codec hardware
  1662. * in a proper sequence */
  1663. ret = snd_soc_component_write(component, M98095_00F_HOST_CFG, 0);
  1664. if (ret < 0) {
  1665. dev_err(component->dev, "Failed to reset DSP: %d\n", ret);
  1666. return ret;
  1667. }
  1668. ret = snd_soc_component_write(component, M98095_097_PWR_SYS, 0);
  1669. if (ret < 0) {
  1670. dev_err(component->dev, "Failed to reset component: %d\n", ret);
  1671. return ret;
  1672. }
  1673. /* Reset to hardware default for registers, as there is not
  1674. * a soft reset hardware control register */
  1675. for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
  1676. ret = snd_soc_component_write(component, i, snd_soc_component_read(component, i));
  1677. if (ret < 0) {
  1678. dev_err(component->dev, "Failed to reset: %d\n", ret);
  1679. return ret;
  1680. }
  1681. }
  1682. return ret;
  1683. }
  1684. static int max98095_probe(struct snd_soc_component *component)
  1685. {
  1686. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1687. struct max98095_cdata *cdata;
  1688. struct i2c_client *client;
  1689. int ret = 0;
  1690. max98095->mclk = devm_clk_get(component->dev, "mclk");
  1691. if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER)
  1692. return -EPROBE_DEFER;
  1693. /* reset the codec, the DSP core, and disable all interrupts */
  1694. max98095_reset(component);
  1695. client = to_i2c_client(component->dev);
  1696. /* initialize private data */
  1697. max98095->sysclk = (unsigned)-1;
  1698. max98095->eq_textcnt = 0;
  1699. max98095->bq_textcnt = 0;
  1700. cdata = &max98095->dai[0];
  1701. cdata->rate = (unsigned)-1;
  1702. cdata->fmt = (unsigned)-1;
  1703. cdata->eq_sel = 0;
  1704. cdata->bq_sel = 0;
  1705. cdata = &max98095->dai[1];
  1706. cdata->rate = (unsigned)-1;
  1707. cdata->fmt = (unsigned)-1;
  1708. cdata->eq_sel = 0;
  1709. cdata->bq_sel = 0;
  1710. cdata = &max98095->dai[2];
  1711. cdata->rate = (unsigned)-1;
  1712. cdata->fmt = (unsigned)-1;
  1713. cdata->eq_sel = 0;
  1714. cdata->bq_sel = 0;
  1715. max98095->lin_state = 0;
  1716. max98095->mic1pre = 0;
  1717. max98095->mic2pre = 0;
  1718. if (client->irq) {
  1719. /* register an audio interrupt */
  1720. ret = request_threaded_irq(client->irq, NULL,
  1721. max98095_report_jack,
  1722. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
  1723. IRQF_ONESHOT, "max98095", component);
  1724. if (ret) {
  1725. dev_err(component->dev, "Failed to request IRQ: %d\n", ret);
  1726. goto err_access;
  1727. }
  1728. }
  1729. ret = snd_soc_component_read(component, M98095_0FF_REV_ID);
  1730. if (ret < 0) {
  1731. dev_err(component->dev, "Failure reading hardware revision: %d\n",
  1732. ret);
  1733. goto err_irq;
  1734. }
  1735. dev_info(component->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
  1736. snd_soc_component_write(component, M98095_097_PWR_SYS, M98095_PWRSV);
  1737. snd_soc_component_write(component, M98095_048_MIX_DAC_LR,
  1738. M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
  1739. snd_soc_component_write(component, M98095_049_MIX_DAC_M,
  1740. M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
  1741. snd_soc_component_write(component, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
  1742. snd_soc_component_write(component, M98095_045_CFG_DSP, M98095_DSPNORMAL);
  1743. snd_soc_component_write(component, M98095_04E_CFG_HP, M98095_HPNORMAL);
  1744. snd_soc_component_write(component, M98095_02C_DAI1_IOCFG,
  1745. M98095_S1NORMAL|M98095_SDATA);
  1746. snd_soc_component_write(component, M98095_036_DAI2_IOCFG,
  1747. M98095_S2NORMAL|M98095_SDATA);
  1748. snd_soc_component_write(component, M98095_040_DAI3_IOCFG,
  1749. M98095_S3NORMAL|M98095_SDATA);
  1750. max98095_handle_pdata(component);
  1751. /* take the codec out of the shut down */
  1752. snd_soc_component_update_bits(component, M98095_097_PWR_SYS, M98095_SHDNRUN,
  1753. M98095_SHDNRUN);
  1754. return 0;
  1755. err_irq:
  1756. if (client->irq)
  1757. free_irq(client->irq, component);
  1758. err_access:
  1759. return ret;
  1760. }
  1761. static void max98095_remove(struct snd_soc_component *component)
  1762. {
  1763. struct max98095_priv *max98095 = snd_soc_component_get_drvdata(component);
  1764. struct i2c_client *client = to_i2c_client(component->dev);
  1765. if (max98095->headphone_jack || max98095->mic_jack)
  1766. max98095_jack_detect_disable(component);
  1767. if (client->irq)
  1768. free_irq(client->irq, component);
  1769. }
  1770. static const struct snd_soc_component_driver soc_component_dev_max98095 = {
  1771. .probe = max98095_probe,
  1772. .remove = max98095_remove,
  1773. .suspend = max98095_suspend,
  1774. .resume = max98095_resume,
  1775. .set_bias_level = max98095_set_bias_level,
  1776. .controls = max98095_snd_controls,
  1777. .num_controls = ARRAY_SIZE(max98095_snd_controls),
  1778. .dapm_widgets = max98095_dapm_widgets,
  1779. .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
  1780. .dapm_routes = max98095_audio_map,
  1781. .num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
  1782. .idle_bias_on = 1,
  1783. .use_pmdown_time = 1,
  1784. .endianness = 1,
  1785. .non_legacy_dai_naming = 1,
  1786. };
  1787. static int max98095_i2c_probe(struct i2c_client *i2c,
  1788. const struct i2c_device_id *id)
  1789. {
  1790. struct max98095_priv *max98095;
  1791. int ret;
  1792. max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
  1793. GFP_KERNEL);
  1794. if (max98095 == NULL)
  1795. return -ENOMEM;
  1796. mutex_init(&max98095->lock);
  1797. max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
  1798. if (IS_ERR(max98095->regmap)) {
  1799. ret = PTR_ERR(max98095->regmap);
  1800. dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
  1801. return ret;
  1802. }
  1803. max98095->devtype = id->driver_data;
  1804. i2c_set_clientdata(i2c, max98095);
  1805. max98095->pdata = i2c->dev.platform_data;
  1806. ret = devm_snd_soc_register_component(&i2c->dev,
  1807. &soc_component_dev_max98095,
  1808. max98095_dai, ARRAY_SIZE(max98095_dai));
  1809. return ret;
  1810. }
  1811. static const struct i2c_device_id max98095_i2c_id[] = {
  1812. { "max98095", MAX98095 },
  1813. { }
  1814. };
  1815. MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
  1816. static const struct of_device_id max98095_of_match[] = {
  1817. { .compatible = "maxim,max98095", },
  1818. { }
  1819. };
  1820. MODULE_DEVICE_TABLE(of, max98095_of_match);
  1821. static struct i2c_driver max98095_i2c_driver = {
  1822. .driver = {
  1823. .name = "max98095",
  1824. .of_match_table = of_match_ptr(max98095_of_match),
  1825. },
  1826. .probe = max98095_i2c_probe,
  1827. .id_table = max98095_i2c_id,
  1828. };
  1829. module_i2c_driver(max98095_i2c_driver);
  1830. MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
  1831. MODULE_AUTHOR("Peter Hsiang");
  1832. MODULE_LICENSE("GPL");