max98090.h 45 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * max98090.h -- MAX98090 ALSA SoC Audio driver
  4. *
  5. * Copyright 2011-2012 Maxim Integrated Products
  6. */
  7. #ifndef _MAX98090_H
  8. #define _MAX98090_H
  9. /*
  10. * The default operating frequency for a DMIC attached to the codec.
  11. * This can be overridden by a device tree property.
  12. */
  13. #define MAX98090_DEFAULT_DMIC_FREQ 2500000
  14. /*
  15. * MAX98090 Register Definitions
  16. */
  17. #define M98090_REG_SOFTWARE_RESET 0x00
  18. #define M98090_REG_DEVICE_STATUS 0x01
  19. #define M98090_REG_JACK_STATUS 0x02
  20. #define M98090_REG_INTERRUPT_S 0x03
  21. #define M98090_REG_QUICK_SYSTEM_CLOCK 0x04
  22. #define M98090_REG_QUICK_SAMPLE_RATE 0x05
  23. #define M98090_REG_DAI_INTERFACE 0x06
  24. #define M98090_REG_DAC_PATH 0x07
  25. #define M98090_REG_MIC_DIRECT_TO_ADC 0x08
  26. #define M98090_REG_LINE_TO_ADC 0x09
  27. #define M98090_REG_ANALOG_MIC_LOOP 0x0A
  28. #define M98090_REG_ANALOG_LINE_LOOP 0x0B
  29. #define M98090_REG_RESERVED 0x0C
  30. #define M98090_REG_LINE_INPUT_CONFIG 0x0D
  31. #define M98090_REG_LINE_INPUT_LEVEL 0x0E
  32. #define M98090_REG_INPUT_MODE 0x0F
  33. #define M98090_REG_MIC1_INPUT_LEVEL 0x10
  34. #define M98090_REG_MIC2_INPUT_LEVEL 0x11
  35. #define M98090_REG_MIC_BIAS_VOLTAGE 0x12
  36. #define M98090_REG_DIGITAL_MIC_ENABLE 0x13
  37. #define M98090_REG_DIGITAL_MIC_CONFIG 0x14
  38. #define M98090_REG_LEFT_ADC_MIXER 0x15
  39. #define M98090_REG_RIGHT_ADC_MIXER 0x16
  40. #define M98090_REG_LEFT_ADC_LEVEL 0x17
  41. #define M98090_REG_RIGHT_ADC_LEVEL 0x18
  42. #define M98090_REG_ADC_BIQUAD_LEVEL 0x19
  43. #define M98090_REG_ADC_SIDETONE 0x1A
  44. #define M98090_REG_SYSTEM_CLOCK 0x1B
  45. #define M98090_REG_CLOCK_MODE 0x1C
  46. #define M98090_REG_CLOCK_RATIO_NI_MSB 0x1D
  47. #define M98090_REG_CLOCK_RATIO_NI_LSB 0x1E
  48. #define M98090_REG_CLOCK_RATIO_MI_MSB 0x1F
  49. #define M98090_REG_CLOCK_RATIO_MI_LSB 0x20
  50. #define M98090_REG_MASTER_MODE 0x21
  51. #define M98090_REG_INTERFACE_FORMAT 0x22
  52. #define M98090_REG_TDM_CONTROL 0x23
  53. #define M98090_REG_TDM_FORMAT 0x24
  54. #define M98090_REG_IO_CONFIGURATION 0x25
  55. #define M98090_REG_FILTER_CONFIG 0x26
  56. #define M98090_REG_DAI_PLAYBACK_LEVEL 0x27
  57. #define M98090_REG_DAI_PLAYBACK_LEVEL_EQ 0x28
  58. #define M98090_REG_LEFT_HP_MIXER 0x29
  59. #define M98090_REG_RIGHT_HP_MIXER 0x2A
  60. #define M98090_REG_HP_CONTROL 0x2B
  61. #define M98090_REG_LEFT_HP_VOLUME 0x2C
  62. #define M98090_REG_RIGHT_HP_VOLUME 0x2D
  63. #define M98090_REG_LEFT_SPK_MIXER 0x2E
  64. #define M98090_REG_RIGHT_SPK_MIXER 0x2F
  65. #define M98090_REG_SPK_CONTROL 0x30
  66. #define M98090_REG_LEFT_SPK_VOLUME 0x31
  67. #define M98090_REG_RIGHT_SPK_VOLUME 0x32
  68. #define M98090_REG_DRC_TIMING 0x33
  69. #define M98090_REG_DRC_COMPRESSOR 0x34
  70. #define M98090_REG_DRC_EXPANDER 0x35
  71. #define M98090_REG_DRC_GAIN 0x36
  72. #define M98090_REG_RCV_LOUTL_MIXER 0x37
  73. #define M98090_REG_RCV_LOUTL_CONTROL 0x38
  74. #define M98090_REG_RCV_LOUTL_VOLUME 0x39
  75. #define M98090_REG_LOUTR_MIXER 0x3A
  76. #define M98090_REG_LOUTR_CONTROL 0x3B
  77. #define M98090_REG_LOUTR_VOLUME 0x3C
  78. #define M98090_REG_JACK_DETECT 0x3D
  79. #define M98090_REG_INPUT_ENABLE 0x3E
  80. #define M98090_REG_OUTPUT_ENABLE 0x3F
  81. #define M98090_REG_LEVEL_CONTROL 0x40
  82. #define M98090_REG_DSP_FILTER_ENABLE 0x41
  83. #define M98090_REG_BIAS_CONTROL 0x42
  84. #define M98090_REG_DAC_CONTROL 0x43
  85. #define M98090_REG_ADC_CONTROL 0x44
  86. #define M98090_REG_DEVICE_SHUTDOWN 0x45
  87. #define M98090_REG_EQUALIZER_BASE 0x46
  88. #define M98090_REG_RECORD_BIQUAD_BASE 0xAF
  89. #define M98090_REG_DMIC3_VOLUME 0xBE
  90. #define M98090_REG_DMIC4_VOLUME 0xBF
  91. #define M98090_REG_DMIC34_BQ_PREATTEN 0xC0
  92. #define M98090_REG_RECORD_TDM_SLOT 0xC1
  93. #define M98090_REG_SAMPLE_RATE 0xC2
  94. #define M98090_REG_DMIC34_BIQUAD_BASE 0xC3
  95. #define M98090_REG_REVISION_ID 0xFF
  96. #define M98090_REG_CNT (0xFF+1)
  97. #define MAX98090_MAX_REGISTER 0xFF
  98. /* MAX98090 Register Bit Fields */
  99. /*
  100. * M98090_REG_SOFTWARE_RESET
  101. */
  102. #define M98090_SWRESET_MASK (1<<7)
  103. #define M98090_SWRESET_SHIFT 7
  104. #define M98090_SWRESET_WIDTH 1
  105. /*
  106. * M98090_REG_DEVICE_STATUS
  107. */
  108. #define M98090_CLD_MASK (1<<7)
  109. #define M98090_CLD_SHIFT 7
  110. #define M98090_CLD_WIDTH 1
  111. #define M98090_SLD_MASK (1<<6)
  112. #define M98090_SLD_SHIFT 6
  113. #define M98090_SLD_WIDTH 1
  114. #define M98090_ULK_MASK (1<<5)
  115. #define M98090_ULK_SHIFT 5
  116. #define M98090_ULK_WIDTH 1
  117. #define M98090_JDET_MASK (1<<2)
  118. #define M98090_JDET_SHIFT 2
  119. #define M98090_JDET_WIDTH 1
  120. #define M98090_DRCACT_MASK (1<<1)
  121. #define M98090_DRCACT_SHIFT 1
  122. #define M98090_DRCACT_WIDTH 1
  123. #define M98090_DRCCLP_MASK (1<<0)
  124. #define M98090_DRCCLP_SHIFT 0
  125. #define M98090_DRCCLP_WIDTH 1
  126. /*
  127. * M98090_REG_JACK_STATUS
  128. */
  129. #define M98090_LSNS_MASK (1<<2)
  130. #define M98090_LSNS_SHIFT 2
  131. #define M98090_LSNS_WIDTH 1
  132. #define M98090_JKSNS_MASK (1<<1)
  133. #define M98090_JKSNS_SHIFT 1
  134. #define M98090_JKSNS_WIDTH 1
  135. /*
  136. * M98090_REG_INTERRUPT_S
  137. */
  138. #define M98090_ICLD_MASK (1<<7)
  139. #define M98090_ICLD_SHIFT 7
  140. #define M98090_ICLD_WIDTH 1
  141. #define M98090_ISLD_MASK (1<<6)
  142. #define M98090_ISLD_SHIFT 6
  143. #define M98090_ISLD_WIDTH 1
  144. #define M98090_IULK_MASK (1<<5)
  145. #define M98090_IULK_SHIFT 5
  146. #define M98090_IULK_WIDTH 1
  147. #define M98090_IJDET_MASK (1<<2)
  148. #define M98090_IJDET_SHIFT 2
  149. #define M98090_IJDET_WIDTH 1
  150. #define M98090_IDRCACT_MASK (1<<1)
  151. #define M98090_IDRCACT_SHIFT 1
  152. #define M98090_IDRCACT_WIDTH 1
  153. #define M98090_IDRCCLP_MASK (1<<0)
  154. #define M98090_IDRCCLP_SHIFT 0
  155. #define M98090_IDRCCLP_WIDTH 1
  156. /*
  157. * M98090_REG_QUICK_SYSTEM_CLOCK
  158. */
  159. #define M98090_26M_MASK (1<<7)
  160. #define M98090_26M_SHIFT 7
  161. #define M98090_26M_WIDTH 1
  162. #define M98090_19P2M_MASK (1<<6)
  163. #define M98090_19P2M_SHIFT 6
  164. #define M98090_19P2M_WIDTH 1
  165. #define M98090_13M_MASK (1<<5)
  166. #define M98090_13M_SHIFT 5
  167. #define M98090_13M_WIDTH 1
  168. #define M98090_12P288M_MASK (1<<4)
  169. #define M98090_12P288M_SHIFT 4
  170. #define M98090_12P288M_WIDTH 1
  171. #define M98090_12M_MASK (1<<3)
  172. #define M98090_12M_SHIFT 3
  173. #define M98090_12M_WIDTH 1
  174. #define M98090_11P2896M_MASK (1<<2)
  175. #define M98090_11P2896M_SHIFT 2
  176. #define M98090_11P2896M_WIDTH 1
  177. #define M98090_256FS_MASK (1<<0)
  178. #define M98090_256FS_SHIFT 0
  179. #define M98090_256FS_WIDTH 1
  180. #define M98090_CLK_ALL_SHIFT 0
  181. #define M98090_CLK_ALL_WIDTH 8
  182. #define M98090_CLK_ALL_NUM (1<<M98090_CLK_ALL_WIDTH)
  183. /*
  184. * M98090_REG_QUICK_SAMPLE_RATE
  185. */
  186. #define M98090_SR_96K_MASK (1<<5)
  187. #define M98090_SR_96K_SHIFT 5
  188. #define M98090_SR_96K_WIDTH 1
  189. #define M98090_SR_32K_MASK (1<<4)
  190. #define M98090_SR_32K_SHIFT 4
  191. #define M98090_SR_32K_WIDTH 1
  192. #define M98090_SR_48K_MASK (1<<3)
  193. #define M98090_SR_48K_SHIFT 3
  194. #define M98090_SR_48K_WIDTH 1
  195. #define M98090_SR_44K1_MASK (1<<2)
  196. #define M98090_SR_44K1_SHIFT 2
  197. #define M98090_SR_44K1_WIDTH 1
  198. #define M98090_SR_16K_MASK (1<<1)
  199. #define M98090_SR_16K_SHIFT 1
  200. #define M98090_SR_16K_WIDTH 1
  201. #define M98090_SR_8K_MASK (1<<0)
  202. #define M98090_SR_8K_SHIFT 0
  203. #define M98090_SR_8K_WIDTH 1
  204. #define M98090_SR_MASK 0x3F
  205. #define M98090_SR_ALL_SHIFT 0
  206. #define M98090_SR_ALL_WIDTH 8
  207. #define M98090_SR_ALL_NUM (1<<M98090_SR_ALL_WIDTH)
  208. /*
  209. * M98090_REG_DAI_INTERFACE
  210. */
  211. #define M98090_RJ_M_MASK (1<<5)
  212. #define M98090_RJ_M_SHIFT 5
  213. #define M98090_RJ_M_WIDTH 1
  214. #define M98090_RJ_S_MASK (1<<4)
  215. #define M98090_RJ_S_SHIFT 4
  216. #define M98090_RJ_S_WIDTH 1
  217. #define M98090_LJ_M_MASK (1<<3)
  218. #define M98090_LJ_M_SHIFT 3
  219. #define M98090_LJ_M_WIDTH 1
  220. #define M98090_LJ_S_MASK (1<<2)
  221. #define M98090_LJ_S_SHIFT 2
  222. #define M98090_LJ_S_WIDTH 1
  223. #define M98090_I2S_M_MASK (1<<1)
  224. #define M98090_I2S_M_SHIFT 1
  225. #define M98090_I2S_M_WIDTH 1
  226. #define M98090_I2S_S_MASK (1<<0)
  227. #define M98090_I2S_S_SHIFT 0
  228. #define M98090_I2S_S_WIDTH 1
  229. #define M98090_DAI_ALL_SHIFT 0
  230. #define M98090_DAI_ALL_WIDTH 8
  231. #define M98090_DAI_ALL_NUM (1<<M98090_DAI_ALL_WIDTH)
  232. /*
  233. * M98090_REG_DAC_PATH
  234. */
  235. #define M98090_DIG2_HP_MASK (1<<7)
  236. #define M98090_DIG2_HP_SHIFT 7
  237. #define M98090_DIG2_HP_WIDTH 1
  238. #define M98090_DIG2_EAR_MASK (1<<6)
  239. #define M98090_DIG2_EAR_SHIFT 6
  240. #define M98090_DIG2_EAR_WIDTH 1
  241. #define M98090_DIG2_SPK_MASK (1<<5)
  242. #define M98090_DIG2_SPK_SHIFT 5
  243. #define M98090_DIG2_SPK_WIDTH 1
  244. #define M98090_DIG2_LOUT_MASK (1<<4)
  245. #define M98090_DIG2_LOUT_SHIFT 4
  246. #define M98090_DIG2_LOUT_WIDTH 1
  247. #define M98090_DIG2_ALL_SHIFT 0
  248. #define M98090_DIG2_ALL_WIDTH 8
  249. #define M98090_DIG2_ALL_NUM (1<<M98090_DIG2_ALL_WIDTH)
  250. /*
  251. * M98090_REG_MIC_DIRECT_TO_ADC
  252. */
  253. #define M98090_IN12_MIC1_MASK (1<<7)
  254. #define M98090_IN12_MIC1_SHIFT 7
  255. #define M98090_IN12_MIC1_WIDTH 1
  256. #define M98090_IN34_MIC2_MASK (1<<6)
  257. #define M98090_IN34_MIC2_SHIFT 6
  258. #define M98090_IN34_MIC2_WIDTH 1
  259. #define M98090_IN56_MIC1_MASK (1<<5)
  260. #define M98090_IN56_MIC1_SHIFT 5
  261. #define M98090_IN56_MIC1_WIDTH 1
  262. #define M98090_IN56_MIC2_MASK (1<<4)
  263. #define M98090_IN56_MIC2_SHIFT 4
  264. #define M98090_IN56_MIC2_WIDTH 1
  265. #define M98090_IN12_DADC_MASK (1<<3)
  266. #define M98090_IN12_DADC_SHIFT 3
  267. #define M98090_IN12_DADC_WIDTH 1
  268. #define M98090_IN34_DADC_MASK (1<<2)
  269. #define M98090_IN34_DADC_SHIFT 2
  270. #define M98090_IN34_DADC_WIDTH 1
  271. #define M98090_IN56_DADC_MASK (1<<1)
  272. #define M98090_IN56_DADC_SHIFT 1
  273. #define M98090_IN56_DADC_WIDTH 1
  274. #define M98090_MIC_ALL_SHIFT 0
  275. #define M98090_MIC_ALL_WIDTH 8
  276. #define M98090_MIC_ALL_NUM (1<<M98090_MIC_ALL_WIDTH)
  277. /*
  278. * M98090_REG_LINE_TO_ADC
  279. */
  280. #define M98090_IN12S_AB_MASK (1<<7)
  281. #define M98090_IN12S_AB_SHIFT 7
  282. #define M98090_IN12S_AB_WIDTH 1
  283. #define M98090_IN34S_AB_MASK (1<<6)
  284. #define M98090_IN34S_AB_SHIFT 6
  285. #define M98090_IN34S_AB_WIDTH 1
  286. #define M98090_IN56S_AB_MASK (1<<5)
  287. #define M98090_IN56S_AB_SHIFT 5
  288. #define M98090_IN56S_AB_WIDTH 1
  289. #define M98090_IN34D_A_MASK (1<<4)
  290. #define M98090_IN34D_A_SHIFT 4
  291. #define M98090_IN34D_A_WIDTH 1
  292. #define M98090_IN56D_B_MASK (1<<3)
  293. #define M98090_IN56D_B_SHIFT 3
  294. #define M98090_IN56D_B_WIDTH 1
  295. #define M98090_LINE_ALL_SHIFT 0
  296. #define M98090_LINE_ALL_WIDTH 8
  297. #define M98090_LINE_ALL_NUM (1<<M98090_LINE_ALL_WIDTH)
  298. /*
  299. * M98090_REG_ANALOG_MIC_LOOP
  300. */
  301. #define M98090_IN12_M1HPL_MASK (1<<7)
  302. #define M98090_IN12_M1HPL_SHIFT 7
  303. #define M98090_IN12_M1HPL_WIDTH 1
  304. #define M98090_IN12_M1SPKL_MASK (1<<6)
  305. #define M98090_IN12_M1SPKL_SHIFT 6
  306. #define M98090_IN12_M1SPKL_WIDTH 1
  307. #define M98090_IN12_M1EAR_MASK (1<<5)
  308. #define M98090_IN12_M1EAR_SHIFT 5
  309. #define M98090_IN12_M1EAR_WIDTH 1
  310. #define M98090_IN12_M1LOUTL_MASK (1<<4)
  311. #define M98090_IN12_M1LOUTL_SHIFT 4
  312. #define M98090_IN12_M1LOUTL_WIDTH 1
  313. #define M98090_IN34_M2HPR_MASK (1<<3)
  314. #define M98090_IN34_M2HPR_SHIFT 3
  315. #define M98090_IN34_M2HPR_WIDTH 1
  316. #define M98090_IN34_M2SPKR_MASK (1<<2)
  317. #define M98090_IN34_M2SPKR_SHIFT 2
  318. #define M98090_IN34_M2SPKR_WIDTH 1
  319. #define M98090_IN34_M2EAR_MASK (1<<1)
  320. #define M98090_IN34_M2EAR_SHIFT 1
  321. #define M98090_IN34_M2EAR_WIDTH 1
  322. #define M98090_IN34_M2LOUTR_MASK (1<<0)
  323. #define M98090_IN34_M2LOUTR_SHIFT 0
  324. #define M98090_IN34_M2LOUTR_WIDTH 1
  325. #define M98090_AMIC_ALL_SHIFT 0
  326. #define M98090_AMIC_ALL_WIDTH 8
  327. #define M98090_AMIC_ALL_NUM (1<<M98090_AMIC_ALL_WIDTH)
  328. /*
  329. * M98090_REG_ANALOG_LINE_LOOP
  330. */
  331. #define M98090_IN12S_ABHP_MASK (1<<7)
  332. #define M98090_IN12S_ABHP_SHIFT 7
  333. #define M98090_IN12S_ABHP_WIDTH 1
  334. #define M98090_IN34D_ASPKL_MASK (1<<6)
  335. #define M98090_IN34D_ASPKL_SHIFT 6
  336. #define M98090_IN34D_ASPKL_WIDTH 1
  337. #define M98090_IN34D_AEAR_MASK (1<<5)
  338. #define M98090_IN34D_AEAR_SHIFT 5
  339. #define M98090_IN34D_AEAR_WIDTH 1
  340. #define M98090_IN12S_ABLOUT_MASK (1<<4)
  341. #define M98090_IN12S_ABLOUT_SHIFT 4
  342. #define M98090_IN12S_ABLOUT_WIDTH 1
  343. #define M98090_IN34S_ABHP_MASK (1<<3)
  344. #define M98090_IN34S_ABHP_SHIFT 3
  345. #define M98090_IN34S_ABHP_WIDTH 1
  346. #define M98090_IN56D_BSPKR_MASK (1<<2)
  347. #define M98090_IN56D_BSPKR_SHIFT 2
  348. #define M98090_IN56D_BSPKR_WIDTH 1
  349. #define M98090_IN56D_BEAR_MASK (1<<1)
  350. #define M98090_IN56D_BEAR_SHIFT 1
  351. #define M98090_IN56D_BEAR_WIDTH 1
  352. #define M98090_IN34S_ABLOUT_MASK (1<<0)
  353. #define M98090_IN34S_ABLOUT_SHIFT 0
  354. #define M98090_IN34S_ABLOUT_WIDTH 1
  355. #define M98090_ALIN_ALL_SHIFT 0
  356. #define M98090_ALIN_ALL_WIDTH 8
  357. #define M98090_ALIN_ALL_NUM (1<<M98090_ALIN_ALL_WIDTH)
  358. /*
  359. * M98090_REG_RESERVED
  360. */
  361. /*
  362. * M98090_REG_LINE_INPUT_CONFIG
  363. */
  364. #define M98090_IN34DIFF_MASK (1<<7)
  365. #define M98090_IN34DIFF_SHIFT 7
  366. #define M98090_IN34DIFF_WIDTH 1
  367. #define M98090_IN56DIFF_MASK (1<<6)
  368. #define M98090_IN56DIFF_SHIFT 6
  369. #define M98090_IN56DIFF_WIDTH 1
  370. #define M98090_IN1SEEN_MASK (1<<5)
  371. #define M98090_IN1SEEN_SHIFT 5
  372. #define M98090_IN1SEEN_WIDTH 1
  373. #define M98090_IN2SEEN_MASK (1<<4)
  374. #define M98090_IN2SEEN_SHIFT 4
  375. #define M98090_IN2SEEN_WIDTH 1
  376. #define M98090_IN3SEEN_MASK (1<<3)
  377. #define M98090_IN3SEEN_SHIFT 3
  378. #define M98090_IN3SEEN_WIDTH 1
  379. #define M98090_IN4SEEN_MASK (1<<2)
  380. #define M98090_IN4SEEN_SHIFT 2
  381. #define M98090_IN4SEEN_WIDTH 1
  382. #define M98090_IN5SEEN_MASK (1<<1)
  383. #define M98090_IN5SEEN_SHIFT 1
  384. #define M98090_IN5SEEN_WIDTH 1
  385. #define M98090_IN6SEEN_MASK (1<<0)
  386. #define M98090_IN6SEEN_SHIFT 0
  387. #define M98090_IN6SEEN_WIDTH 1
  388. /*
  389. * M98090_REG_LINE_INPUT_LEVEL
  390. */
  391. #define M98090_MIXG135_MASK (1<<7)
  392. #define M98090_MIXG135_SHIFT 7
  393. #define M98090_MIXG135_WIDTH 1
  394. #define M98090_MIXG135_NUM (1<<M98090_MIXG135_WIDTH)
  395. #define M98090_MIXG246_MASK (1<<6)
  396. #define M98090_MIXG246_SHIFT 6
  397. #define M98090_MIXG246_WIDTH 1
  398. #define M98090_MIXG246_NUM (1<<M98090_MIXG246_WIDTH)
  399. #define M98090_LINAPGA_MASK (7<<3)
  400. #define M98090_LINAPGA_SHIFT 3
  401. #define M98090_LINAPGA_WIDTH 3
  402. #define M98090_LINAPGA_NUM 6
  403. #define M98090_LINBPGA_MASK (7<<0)
  404. #define M98090_LINBPGA_SHIFT 0
  405. #define M98090_LINBPGA_WIDTH 3
  406. #define M98090_LINBPGA_NUM 6
  407. /*
  408. * M98090_REG_INPUT_MODE
  409. */
  410. #define M98090_EXTBUFA_MASK (1<<7)
  411. #define M98090_EXTBUFA_SHIFT 7
  412. #define M98090_EXTBUFA_WIDTH 1
  413. #define M98090_EXTBUFA_NUM (1<<M98090_EXTBUFA_WIDTH)
  414. #define M98090_EXTBUFB_MASK (1<<6)
  415. #define M98090_EXTBUFB_SHIFT 6
  416. #define M98090_EXTBUFB_WIDTH 1
  417. #define M98090_EXTBUFB_NUM (1<<M98090_EXTBUFB_WIDTH)
  418. #define M98090_EXTMIC_MASK (3<<0)
  419. #define M98090_EXTMIC_SHIFT 0
  420. #define M98090_EXTMIC1_SHIFT 0
  421. #define M98090_EXTMIC2_SHIFT 1
  422. #define M98090_EXTMIC_WIDTH 2
  423. #define M98090_EXTMIC_NONE (0<<0)
  424. #define M98090_EXTMIC_MIC1 (1<<0)
  425. #define M98090_EXTMIC_MIC2 (2<<0)
  426. /*
  427. * M98090_REG_MIC1_INPUT_LEVEL
  428. */
  429. #define M98090_MIC_PA1EN_MASK (3<<5)
  430. #define M98090_MIC_PA1EN_SHIFT 5
  431. #define M98090_MIC_PA1EN_WIDTH 2
  432. #define M98090_MIC_PA1EN_NUM 3
  433. #define M98090_MIC_PGAM1_MASK (31<<0)
  434. #define M98090_MIC_PGAM1_SHIFT 0
  435. #define M98090_MIC_PGAM1_WIDTH 5
  436. #define M98090_MIC_PGAM1_NUM 21
  437. /*
  438. * M98090_REG_MIC2_INPUT_LEVEL
  439. */
  440. #define M98090_MIC_PA2EN_MASK (3<<5)
  441. #define M98090_MIC_PA2EN_SHIFT 5
  442. #define M98090_MIC_PA2EN_WIDTH 2
  443. #define M98090_MIC_PA2EN_NUM 3
  444. #define M98090_MIC_PGAM2_MASK (31<<0)
  445. #define M98090_MIC_PGAM2_SHIFT 0
  446. #define M98090_MIC_PGAM2_WIDTH 5
  447. #define M98090_MIC_PGAM2_NUM 21
  448. /*
  449. * M98090_REG_MIC_BIAS_VOLTAGE
  450. */
  451. #define M98090_MBVSEL_MASK (3<<0)
  452. #define M98090_MBVSEL_SHIFT 0
  453. #define M98090_MBVSEL_WIDTH 2
  454. #define M98090_MBVSEL_2V8 (3<<0)
  455. #define M98090_MBVSEL_2V55 (2<<0)
  456. #define M98090_MBVSEL_2V4 (1<<0)
  457. #define M98090_MBVSEL_2V2 (0<<0)
  458. /*
  459. * M98090_REG_DIGITAL_MIC_ENABLE
  460. */
  461. #define M98090_MICCLK_MASK (7<<4)
  462. #define M98090_MICCLK_SHIFT 4
  463. #define M98090_MICCLK_WIDTH 3
  464. #define M98090_DIGMIC4_MASK (1<<3)
  465. #define M98090_DIGMIC4_SHIFT 3
  466. #define M98090_DIGMIC4_WIDTH 1
  467. #define M98090_DIGMIC4_NUM (1<<M98090_DIGMIC4_WIDTH)
  468. #define M98090_DIGMIC3_MASK (1<<2)
  469. #define M98090_DIGMIC3_SHIFT 2
  470. #define M98090_DIGMIC3_WIDTH 1
  471. #define M98090_DIGMIC3_NUM (1<<M98090_DIGMIC3_WIDTH)
  472. #define M98090_DIGMICR_MASK (1<<1)
  473. #define M98090_DIGMICR_SHIFT 1
  474. #define M98090_DIGMICR_WIDTH 1
  475. #define M98090_DIGMICR_NUM (1<<M98090_DIGMICR_WIDTH)
  476. #define M98090_DIGMICL_MASK (1<<0)
  477. #define M98090_DIGMICL_SHIFT 0
  478. #define M98090_DIGMICL_WIDTH 1
  479. #define M98090_DIGMICL_NUM (1<<M98090_DIGMICL_WIDTH)
  480. /*
  481. * M98090_REG_DIGITAL_MIC_CONFIG
  482. */
  483. #define M98090_DMIC_COMP_MASK (15<<4)
  484. #define M98090_DMIC_COMP_SHIFT 4
  485. #define M98090_DMIC_COMP_WIDTH 4
  486. #define M98090_DMIC_COMP_NUM (1<<M98090_DMIC_COMP_WIDTH)
  487. #define M98090_DMIC_FREQ_MASK (3<<0)
  488. #define M98090_DMIC_FREQ_SHIFT 0
  489. #define M98090_DMIC_FREQ_WIDTH 2
  490. /*
  491. * M98090_REG_LEFT_ADC_MIXER
  492. */
  493. #define M98090_MIXADL_MIC2_MASK (1<<6)
  494. #define M98090_MIXADL_MIC2_SHIFT 6
  495. #define M98090_MIXADL_MIC2_WIDTH 1
  496. #define M98090_MIXADL_MIC1_MASK (1<<5)
  497. #define M98090_MIXADL_MIC1_SHIFT 5
  498. #define M98090_MIXADL_MIC1_WIDTH 1
  499. #define M98090_MIXADL_LINEB_MASK (1<<4)
  500. #define M98090_MIXADL_LINEB_SHIFT 4
  501. #define M98090_MIXADL_LINEB_WIDTH 1
  502. #define M98090_MIXADL_LINEA_MASK (1<<3)
  503. #define M98090_MIXADL_LINEA_SHIFT 3
  504. #define M98090_MIXADL_LINEA_WIDTH 1
  505. #define M98090_MIXADL_IN65DIFF_MASK (1<<2)
  506. #define M98090_MIXADL_IN65DIFF_SHIFT 2
  507. #define M98090_MIXADL_IN65DIFF_WIDTH 1
  508. #define M98090_MIXADL_IN34DIFF_MASK (1<<1)
  509. #define M98090_MIXADL_IN34DIFF_SHIFT 1
  510. #define M98090_MIXADL_IN34DIFF_WIDTH 1
  511. #define M98090_MIXADL_IN12DIFF_MASK (1<<0)
  512. #define M98090_MIXADL_IN12DIFF_SHIFT 0
  513. #define M98090_MIXADL_IN12DIFF_WIDTH 1
  514. #define M98090_MIXADL_MASK (255<<0)
  515. #define M98090_MIXADL_SHIFT 0
  516. #define M98090_MIXADL_WIDTH 8
  517. /*
  518. * M98090_REG_RIGHT_ADC_MIXER
  519. */
  520. #define M98090_MIXADR_MIC2_MASK (1<<6)
  521. #define M98090_MIXADR_MIC2_SHIFT 6
  522. #define M98090_MIXADR_MIC2_WIDTH 1
  523. #define M98090_MIXADR_MIC1_MASK (1<<5)
  524. #define M98090_MIXADR_MIC1_SHIFT 5
  525. #define M98090_MIXADR_MIC1_WIDTH 1
  526. #define M98090_MIXADR_LINEB_MASK (1<<4)
  527. #define M98090_MIXADR_LINEB_SHIFT 4
  528. #define M98090_MIXADR_LINEB_WIDTH 1
  529. #define M98090_MIXADR_LINEA_MASK (1<<3)
  530. #define M98090_MIXADR_LINEA_SHIFT 3
  531. #define M98090_MIXADR_LINEA_WIDTH 1
  532. #define M98090_MIXADR_IN65DIFF_MASK (1<<2)
  533. #define M98090_MIXADR_IN65DIFF_SHIFT 2
  534. #define M98090_MIXADR_IN65DIFF_WIDTH 1
  535. #define M98090_MIXADR_IN34DIFF_MASK (1<<1)
  536. #define M98090_MIXADR_IN34DIFF_SHIFT 1
  537. #define M98090_MIXADR_IN34DIFF_WIDTH 1
  538. #define M98090_MIXADR_IN12DIFF_MASK (1<<0)
  539. #define M98090_MIXADR_IN12DIFF_SHIFT 0
  540. #define M98090_MIXADR_IN12DIFF_WIDTH 1
  541. #define M98090_MIXADR_MASK (255<<0)
  542. #define M98090_MIXADR_SHIFT 0
  543. #define M98090_MIXADR_WIDTH 8
  544. /*
  545. * M98090_REG_LEFT_ADC_LEVEL
  546. */
  547. #define M98090_AVLG_MASK (7<<4)
  548. #define M98090_AVLG_SHIFT 4
  549. #define M98090_AVLG_WIDTH 3
  550. #define M98090_AVLG_NUM (1<<M98090_AVLG_WIDTH)
  551. #define M98090_AVL_MASK (15<<0)
  552. #define M98090_AVL_SHIFT 0
  553. #define M98090_AVL_WIDTH 4
  554. #define M98090_AVL_NUM (1<<M98090_AVL_WIDTH)
  555. /*
  556. * M98090_REG_RIGHT_ADC_LEVEL
  557. */
  558. #define M98090_AVRG_MASK (7<<4)
  559. #define M98090_AVRG_SHIFT 4
  560. #define M98090_AVRG_WIDTH 3
  561. #define M98090_AVRG_NUM (1<<M98090_AVRG_WIDTH)
  562. #define M98090_AVR_MASK (15<<0)
  563. #define M98090_AVR_SHIFT 0
  564. #define M98090_AVR_WIDTH 4
  565. #define M98090_AVR_NUM (1<<M98090_AVR_WIDTH)
  566. /*
  567. * M98090_REG_ADC_BIQUAD_LEVEL
  568. */
  569. #define M98090_AVBQ_MASK (15<<0)
  570. #define M98090_AVBQ_SHIFT 0
  571. #define M98090_AVBQ_WIDTH 4
  572. #define M98090_AVBQ_NUM (1<<M98090_AVBQ_WIDTH)
  573. /*
  574. * M98090_REG_ADC_SIDETONE
  575. */
  576. #define M98090_DSTSR_MASK (1<<7)
  577. #define M98090_DSTSR_SHIFT 7
  578. #define M98090_DSTSR_WIDTH 1
  579. #define M98090_DSTSL_MASK (1<<6)
  580. #define M98090_DSTSL_SHIFT 6
  581. #define M98090_DSTSL_WIDTH 1
  582. #define M98090_DVST_MASK (31<<0)
  583. #define M98090_DVST_SHIFT 0
  584. #define M98090_DVST_WIDTH 5
  585. #define M98090_DVST_NUM 31
  586. /*
  587. * M98090_REG_SYSTEM_CLOCK
  588. */
  589. #define M98090_PSCLK_MASK (3<<4)
  590. #define M98090_PSCLK_SHIFT 4
  591. #define M98090_PSCLK_WIDTH 2
  592. #define M98090_PSCLK_DISABLED (0<<4)
  593. #define M98090_PSCLK_DIV1 (1<<4)
  594. #define M98090_PSCLK_DIV2 (2<<4)
  595. #define M98090_PSCLK_DIV4 (3<<4)
  596. /*
  597. * M98090_REG_CLOCK_MODE
  598. */
  599. #define M98090_FREQ_MASK (15<<4)
  600. #define M98090_FREQ_SHIFT 4
  601. #define M98090_FREQ_WIDTH 4
  602. #define M98090_USE_M1_MASK (1<<0)
  603. #define M98090_USE_M1_SHIFT 0
  604. #define M98090_USE_M1_WIDTH 1
  605. #define M98090_USE_M1_NUM (1<<M98090_USE_M1_WIDTH)
  606. /*
  607. * M98090_REG_CLOCK_RATIO_NI_MSB
  608. */
  609. #define M98090_NI_HI_MASK (127<<0)
  610. #define M98090_NI_HI_SHIFT 0
  611. #define M98090_NI_HI_WIDTH 7
  612. #define M98090_NI_HI_NUM (1<<M98090_NI_HI_WIDTH)
  613. /*
  614. * M98090_REG_CLOCK_RATIO_NI_LSB
  615. */
  616. #define M98090_NI_LO_MASK (255<<0)
  617. #define M98090_NI_LO_SHIFT 0
  618. #define M98090_NI_LO_WIDTH 8
  619. #define M98090_NI_LO_NUM (1<<M98090_NI_LO_WIDTH)
  620. /*
  621. * M98090_REG_CLOCK_RATIO_MI_MSB
  622. */
  623. #define M98090_MI_HI_MASK (255<<0)
  624. #define M98090_MI_HI_SHIFT 0
  625. #define M98090_MI_HI_WIDTH 8
  626. #define M98090_MI_HI_NUM (1<<M98090_MI_HI_WIDTH)
  627. /*
  628. * M98090_REG_CLOCK_RATIO_MI_LSB
  629. */
  630. #define M98090_MI_LO_MASK (255<<0)
  631. #define M98090_MI_LO_SHIFT 0
  632. #define M98090_MI_LO_WIDTH 8
  633. #define M98090_MI_LO_NUM (1<<M98090_MI_LO_WIDTH)
  634. /*
  635. * M98090_REG_MASTER_MODE
  636. */
  637. #define M98090_MAS_MASK (1<<7)
  638. #define M98090_MAS_SHIFT 7
  639. #define M98090_MAS_WIDTH 1
  640. #define M98090_BSEL_MASK (1<<0)
  641. #define M98090_BSEL_SHIFT 0
  642. #define M98090_BSEL_WIDTH 1
  643. #define M98090_BSEL_32 (1<<0)
  644. #define M98090_BSEL_48 (2<<0)
  645. #define M98090_BSEL_64 (3<<0)
  646. /*
  647. * M98090_REG_INTERFACE_FORMAT
  648. */
  649. #define M98090_RJ_MASK (1<<5)
  650. #define M98090_RJ_SHIFT 5
  651. #define M98090_RJ_WIDTH 1
  652. #define M98090_WCI_MASK (1<<4)
  653. #define M98090_WCI_SHIFT 4
  654. #define M98090_WCI_WIDTH 1
  655. #define M98090_BCI_MASK (1<<3)
  656. #define M98090_BCI_SHIFT 3
  657. #define M98090_BCI_WIDTH 1
  658. #define M98090_DLY_MASK (1<<2)
  659. #define M98090_DLY_SHIFT 2
  660. #define M98090_DLY_WIDTH 1
  661. #define M98090_WS_MASK (3<<0)
  662. #define M98090_WS_SHIFT 0
  663. #define M98090_WS_WIDTH 2
  664. #define M98090_WS_NUM (1<<M98090_WS_WIDTH)
  665. /*
  666. * M98090_REG_TDM_CONTROL
  667. */
  668. #define M98090_FSW_MASK (1<<1)
  669. #define M98090_FSW_SHIFT 1
  670. #define M98090_FSW_WIDTH 1
  671. #define M98090_TDM_MASK (1<<0)
  672. #define M98090_TDM_SHIFT 0
  673. #define M98090_TDM_WIDTH 1
  674. #define M98090_TDM_NUM (1<<M98090_TDM_WIDTH)
  675. /*
  676. * M98090_REG_TDM_FORMAT
  677. */
  678. #define M98090_TDM_SLOTL_MASK (3<<6)
  679. #define M98090_TDM_SLOTL_SHIFT 6
  680. #define M98090_TDM_SLOTL_WIDTH 2
  681. #define M98090_TDM_SLOTL_NUM (1<<M98090_TDM_SLOTL_WIDTH)
  682. #define M98090_TDM_SLOTR_MASK (3<<4)
  683. #define M98090_TDM_SLOTR_SHIFT 4
  684. #define M98090_TDM_SLOTR_WIDTH 2
  685. #define M98090_TDM_SLOTR_NUM (1<<M98090_TDM_SLOTR_WIDTH)
  686. #define M98090_TDM_SLOTDLY_MASK (15<<0)
  687. #define M98090_TDM_SLOTDLY_SHIFT 0
  688. #define M98090_TDM_SLOTDLY_WIDTH 4
  689. #define M98090_TDM_SLOTDLY_NUM (1<<M98090_TDM_SLOTDLY_WIDTH)
  690. /*
  691. * M98090_REG_IO_CONFIGURATION
  692. */
  693. #define M98090_LTEN_MASK (1<<5)
  694. #define M98090_LTEN_SHIFT 5
  695. #define M98090_LTEN_WIDTH 1
  696. #define M98090_LTEN_NUM (1<<M98090_LTEN_WIDTH)
  697. #define M98090_LBEN_MASK (1<<4)
  698. #define M98090_LBEN_SHIFT 4
  699. #define M98090_LBEN_WIDTH 1
  700. #define M98090_LBEN_NUM (1<<M98090_LBEN_WIDTH)
  701. #define M98090_DMONO_MASK (1<<3)
  702. #define M98090_DMONO_SHIFT 3
  703. #define M98090_DMONO_WIDTH 1
  704. #define M98090_DMONO_NUM (1<<M98090_DMONO_WIDTH)
  705. #define M98090_HIZOFF_MASK (1<<2)
  706. #define M98090_HIZOFF_SHIFT 2
  707. #define M98090_HIZOFF_WIDTH 1
  708. #define M98090_HIZOFF_NUM (1<<M98090_HIZOFF_WIDTH)
  709. #define M98090_SDOEN_MASK (1<<1)
  710. #define M98090_SDOEN_SHIFT 1
  711. #define M98090_SDOEN_WIDTH 1
  712. #define M98090_SDOEN_NUM (1<<M98090_SDOEN_WIDTH)
  713. #define M98090_SDIEN_MASK (1<<0)
  714. #define M98090_SDIEN_SHIFT 0
  715. #define M98090_SDIEN_WIDTH 1
  716. #define M98090_SDIEN_NUM (1<<M98090_SDIEN_WIDTH)
  717. /*
  718. * M98090_REG_FILTER_CONFIG
  719. */
  720. #define M98090_MODE_MASK (1<<7)
  721. #define M98090_MODE_SHIFT 7
  722. #define M98090_MODE_WIDTH 1
  723. #define M98090_AHPF_MASK (1<<6)
  724. #define M98090_AHPF_SHIFT 6
  725. #define M98090_AHPF_WIDTH 1
  726. #define M98090_AHPF_NUM (1<<M98090_AHPF_WIDTH)
  727. #define M98090_DHPF_MASK (1<<5)
  728. #define M98090_DHPF_SHIFT 5
  729. #define M98090_DHPF_WIDTH 1
  730. #define M98090_DHPF_NUM (1<<M98090_DHPF_WIDTH)
  731. #define M98090_DHF_MASK (1<<4)
  732. #define M98090_DHF_SHIFT 4
  733. #define M98090_DHF_WIDTH 1
  734. #define M98090_FLT_DMIC34MODE_MASK (1<<3)
  735. #define M98090_FLT_DMIC34MODE_SHIFT 3
  736. #define M98090_FLT_DMIC34MODE_WIDTH 1
  737. #define M98090_FLT_DMIC34HPF_MASK (1<<2)
  738. #define M98090_FLT_DMIC34HPF_SHIFT 2
  739. #define M98090_FLT_DMIC34HPF_WIDTH 1
  740. #define M98090_FLT_DMIC34HPF_NUM (1<<M98090_FLT_DMIC34HPF_WIDTH)
  741. /*
  742. * M98090_REG_DAI_PLAYBACK_LEVEL
  743. */
  744. #define M98090_DVM_MASK (1<<7)
  745. #define M98090_DVM_SHIFT 7
  746. #define M98090_DVM_WIDTH 1
  747. #define M98090_DVG_MASK (3<<4)
  748. #define M98090_DVG_SHIFT 4
  749. #define M98090_DVG_WIDTH 2
  750. #define M98090_DVG_NUM (1<<M98090_DVG_WIDTH)
  751. #define M98090_DV_MASK (15<<0)
  752. #define M98090_DV_SHIFT 0
  753. #define M98090_DV_WIDTH 4
  754. #define M98090_DV_NUM (1<<M98090_DV_WIDTH)
  755. /*
  756. * M98090_REG_DAI_PLAYBACK_LEVEL_EQ
  757. */
  758. #define M98090_EQCLPN_MASK (1<<4)
  759. #define M98090_EQCLPN_SHIFT 4
  760. #define M98090_EQCLPN_WIDTH 1
  761. #define M98090_EQCLPN_NUM (1<<M98090_EQCLPN_WIDTH)
  762. #define M98090_DVEQ_MASK (15<<0)
  763. #define M98090_DVEQ_SHIFT 0
  764. #define M98090_DVEQ_WIDTH 4
  765. #define M98090_DVEQ_NUM (1<<M98090_DVEQ_WIDTH)
  766. /*
  767. * M98090_REG_LEFT_HP_MIXER
  768. */
  769. #define M98090_MIXHPL_MIC2_MASK (1<<5)
  770. #define M98090_MIXHPL_MIC2_SHIFT 5
  771. #define M98090_MIXHPL_MIC2_WIDTH 1
  772. #define M98090_MIXHPL_MIC1_MASK (1<<4)
  773. #define M98090_MIXHPL_MIC1_SHIFT 4
  774. #define M98090_MIXHPL_MIC1_WIDTH 1
  775. #define M98090_MIXHPL_LINEB_MASK (1<<3)
  776. #define M98090_MIXHPL_LINEB_SHIFT 3
  777. #define M98090_MIXHPL_LINEB_WIDTH 1
  778. #define M98090_MIXHPL_LINEA_MASK (1<<2)
  779. #define M98090_MIXHPL_LINEA_SHIFT 2
  780. #define M98090_MIXHPL_LINEA_WIDTH 1
  781. #define M98090_MIXHPL_DACR_MASK (1<<1)
  782. #define M98090_MIXHPL_DACR_SHIFT 1
  783. #define M98090_MIXHPL_DACR_WIDTH 1
  784. #define M98090_MIXHPL_DACL_MASK (1<<0)
  785. #define M98090_MIXHPL_DACL_SHIFT 0
  786. #define M98090_MIXHPL_DACL_WIDTH 1
  787. #define M98090_MIXHPL_MASK (63<<0)
  788. #define M98090_MIXHPL_SHIFT 0
  789. #define M98090_MIXHPL_WIDTH 6
  790. /*
  791. * M98090_REG_RIGHT_HP_MIXER
  792. */
  793. #define M98090_MIXHPR_MIC2_MASK (1<<5)
  794. #define M98090_MIXHPR_MIC2_SHIFT 5
  795. #define M98090_MIXHPR_MIC2_WIDTH 1
  796. #define M98090_MIXHPR_MIC1_MASK (1<<4)
  797. #define M98090_MIXHPR_MIC1_SHIFT 4
  798. #define M98090_MIXHPR_MIC1_WIDTH 1
  799. #define M98090_MIXHPR_LINEB_MASK (1<<3)
  800. #define M98090_MIXHPR_LINEB_SHIFT 3
  801. #define M98090_MIXHPR_LINEB_WIDTH 1
  802. #define M98090_MIXHPR_LINEA_MASK (1<<2)
  803. #define M98090_MIXHPR_LINEA_SHIFT 2
  804. #define M98090_MIXHPR_LINEA_WIDTH 1
  805. #define M98090_MIXHPR_DACR_MASK (1<<1)
  806. #define M98090_MIXHPR_DACR_SHIFT 1
  807. #define M98090_MIXHPR_DACR_WIDTH 1
  808. #define M98090_MIXHPR_DACL_MASK (1<<0)
  809. #define M98090_MIXHPR_DACL_SHIFT 0
  810. #define M98090_MIXHPR_DACL_WIDTH 1
  811. #define M98090_MIXHPR_MASK (63<<0)
  812. #define M98090_MIXHPR_SHIFT 0
  813. #define M98090_MIXHPR_WIDTH 6
  814. /*
  815. * M98090_REG_HP_CONTROL
  816. */
  817. #define M98090_MIXHPRSEL_MASK (1<<5)
  818. #define M98090_MIXHPRSEL_SHIFT 5
  819. #define M98090_MIXHPRSEL_WIDTH 1
  820. #define M98090_MIXHPLSEL_MASK (1<<4)
  821. #define M98090_MIXHPLSEL_SHIFT 4
  822. #define M98090_MIXHPLSEL_WIDTH 1
  823. #define M98090_MIXHPRG_MASK (3<<2)
  824. #define M98090_MIXHPRG_SHIFT 2
  825. #define M98090_MIXHPRG_WIDTH 2
  826. #define M98090_MIXHPRG_NUM (1<<M98090_MIXHPRG_WIDTH)
  827. #define M98090_MIXHPLG_MASK (3<<0)
  828. #define M98090_MIXHPLG_SHIFT 0
  829. #define M98090_MIXHPLG_WIDTH 2
  830. #define M98090_MIXHPLG_NUM (1<<M98090_MIXHPLG_WIDTH)
  831. /*
  832. * M98090_REG_LEFT_HP_VOLUME
  833. */
  834. #define M98090_HPLM_MASK (1<<7)
  835. #define M98090_HPLM_SHIFT 7
  836. #define M98090_HPLM_WIDTH 1
  837. #define M98090_HPVOLL_MASK (31<<0)
  838. #define M98090_HPVOLL_SHIFT 0
  839. #define M98090_HPVOLL_WIDTH 5
  840. #define M98090_HPVOLL_NUM (1<<M98090_HPVOLL_WIDTH)
  841. /*
  842. * M98090_REG_RIGHT_HP_VOLUME
  843. */
  844. #define M98090_HPRM_MASK (1<<7)
  845. #define M98090_HPRM_SHIFT 7
  846. #define M98090_HPRM_WIDTH 1
  847. #define M98090_HPVOLR_MASK (31<<0)
  848. #define M98090_HPVOLR_SHIFT 0
  849. #define M98090_HPVOLR_WIDTH 5
  850. #define M98090_HPVOLR_NUM (1<<M98090_HPVOLR_WIDTH)
  851. /*
  852. * M98090_REG_LEFT_SPK_MIXER
  853. */
  854. #define M98090_MIXSPL_MIC2_MASK (1<<5)
  855. #define M98090_MIXSPL_MIC2_SHIFT 5
  856. #define M98090_MIXSPL_MIC2_WIDTH 1
  857. #define M98090_MIXSPL_MIC1_MASK (1<<4)
  858. #define M98090_MIXSPL_MIC1_SHIFT 4
  859. #define M98090_MIXSPL_MIC1_WIDTH 1
  860. #define M98090_MIXSPL_LINEB_MASK (1<<3)
  861. #define M98090_MIXSPL_LINEB_SHIFT 3
  862. #define M98090_MIXSPL_LINEB_WIDTH 1
  863. #define M98090_MIXSPL_LINEA_MASK (1<<2)
  864. #define M98090_MIXSPL_LINEA_SHIFT 2
  865. #define M98090_MIXSPL_LINEA_WIDTH 1
  866. #define M98090_MIXSPL_DACR_MASK (1<<1)
  867. #define M98090_MIXSPL_DACR_SHIFT 1
  868. #define M98090_MIXSPL_DACR_WIDTH 1
  869. #define M98090_MIXSPL_DACL_MASK (1<<0)
  870. #define M98090_MIXSPL_DACL_SHIFT 0
  871. #define M98090_MIXSPL_DACL_WIDTH 1
  872. #define M98090_MIXSPL_MASK (63<<0)
  873. #define M98090_MIXSPL_SHIFT 0
  874. #define M98090_MIXSPL_WIDTH 6
  875. #define M98090_MIXSPR_DACR_MASK (1<<1)
  876. #define M98090_MIXSPR_DACR_SHIFT 1
  877. #define M98090_MIXSPR_DACR_WIDTH 1
  878. /*
  879. * M98090_REG_RIGHT_SPK_MIXER
  880. */
  881. #define M98090_SPK_SLAVE_MASK (1<<6)
  882. #define M98090_SPK_SLAVE_SHIFT 6
  883. #define M98090_SPK_SLAVE_WIDTH 1
  884. #define M98090_MIXSPR_MIC2_MASK (1<<5)
  885. #define M98090_MIXSPR_MIC2_SHIFT 5
  886. #define M98090_MIXSPR_MIC2_WIDTH 1
  887. #define M98090_MIXSPR_MIC1_MASK (1<<4)
  888. #define M98090_MIXSPR_MIC1_SHIFT 4
  889. #define M98090_MIXSPR_MIC1_WIDTH 1
  890. #define M98090_MIXSPR_LINEB_MASK (1<<3)
  891. #define M98090_MIXSPR_LINEB_SHIFT 3
  892. #define M98090_MIXSPR_LINEB_WIDTH 1
  893. #define M98090_MIXSPR_LINEA_MASK (1<<2)
  894. #define M98090_MIXSPR_LINEA_SHIFT 2
  895. #define M98090_MIXSPR_LINEA_WIDTH 1
  896. #define M98090_MIXSPR_DACR_MASK (1<<1)
  897. #define M98090_MIXSPR_DACR_SHIFT 1
  898. #define M98090_MIXSPR_DACR_WIDTH 1
  899. #define M98090_MIXSPR_DACL_MASK (1<<0)
  900. #define M98090_MIXSPR_DACL_SHIFT 0
  901. #define M98090_MIXSPR_DACL_WIDTH 1
  902. #define M98090_MIXSPR_MASK (63<<0)
  903. #define M98090_MIXSPR_SHIFT 0
  904. #define M98090_MIXSPR_WIDTH 6
  905. /*
  906. * M98090_REG_SPK_CONTROL
  907. */
  908. #define M98090_MIXSPRG_MASK (3<<2)
  909. #define M98090_MIXSPRG_SHIFT 2
  910. #define M98090_MIXSPRG_WIDTH 2
  911. #define M98090_MIXSPRG_NUM (1<<M98090_MIXSPRG_WIDTH)
  912. #define M98090_MIXSPLG_MASK (3<<0)
  913. #define M98090_MIXSPLG_SHIFT 0
  914. #define M98090_MIXSPLG_WIDTH 2
  915. #define M98090_MIXSPLG_NUM (1<<M98090_MIXSPLG_WIDTH)
  916. /*
  917. * M98090_REG_LEFT_SPK_VOLUME
  918. */
  919. #define M98090_SPLM_MASK (1<<7)
  920. #define M98090_SPLM_SHIFT 7
  921. #define M98090_SPLM_WIDTH 1
  922. #define M98090_SPVOLL_MASK (63<<0)
  923. #define M98090_SPVOLL_SHIFT 0
  924. #define M98090_SPVOLL_WIDTH 6
  925. #define M98090_SPVOLL_NUM 40
  926. /*
  927. * M98090_REG_RIGHT_SPK_VOLUME
  928. */
  929. #define M98090_SPRM_MASK (1<<7)
  930. #define M98090_SPRM_SHIFT 7
  931. #define M98090_SPRM_WIDTH 1
  932. #define M98090_SPVOLR_MASK (63<<0)
  933. #define M98090_SPVOLR_SHIFT 0
  934. #define M98090_SPVOLR_WIDTH 6
  935. #define M98090_SPVOLR_NUM 40
  936. /*
  937. * M98090_REG_DRC_TIMING
  938. */
  939. #define M98090_DRCEN_MASK (1<<7)
  940. #define M98090_DRCEN_SHIFT 7
  941. #define M98090_DRCEN_WIDTH 1
  942. #define M98090_DRCEN_NUM (1<<M98090_DRCEN_WIDTH)
  943. #define M98090_DRCRLS_MASK (7<<4)
  944. #define M98090_DRCRLS_SHIFT 4
  945. #define M98090_DRCRLS_WIDTH 3
  946. #define M98090_DRCATK_MASK (7<<0)
  947. #define M98090_DRCATK_SHIFT 0
  948. #define M98090_DRCATK_WIDTH 3
  949. /*
  950. * M98090_REG_DRC_COMPRESSOR
  951. */
  952. #define M98090_DRCCMP_MASK (7<<5)
  953. #define M98090_DRCCMP_SHIFT 5
  954. #define M98090_DRCCMP_WIDTH 3
  955. #define M98090_DRCTHC_MASK (31<<0)
  956. #define M98090_DRCTHC_SHIFT 0
  957. #define M98090_DRCTHC_WIDTH 5
  958. #define M98090_DRCTHC_NUM (1<<M98090_DRCTHC_WIDTH)
  959. /*
  960. * M98090_REG_DRC_EXPANDER
  961. */
  962. #define M98090_DRCEXP_MASK (7<<5)
  963. #define M98090_DRCEXP_SHIFT 5
  964. #define M98090_DRCEXP_WIDTH 3
  965. #define M98090_DRCTHE_MASK (31<<0)
  966. #define M98090_DRCTHE_SHIFT 0
  967. #define M98090_DRCTHE_WIDTH 5
  968. #define M98090_DRCTHE_NUM (1<<M98090_DRCTHE_WIDTH)
  969. /*
  970. * M98090_REG_DRC_GAIN
  971. */
  972. #define M98090_DRCG_MASK (31<<0)
  973. #define M98090_DRCG_SHIFT 0
  974. #define M98090_DRCG_WIDTH 5
  975. #define M98090_DRCG_NUM 13
  976. /*
  977. * M98090_REG_RCV_LOUTL_MIXER
  978. */
  979. #define M98090_MIXRCVL_MIC2_MASK (1<<5)
  980. #define M98090_MIXRCVL_MIC2_SHIFT 5
  981. #define M98090_MIXRCVL_MIC2_WIDTH 1
  982. #define M98090_MIXRCVL_MIC1_MASK (1<<4)
  983. #define M98090_MIXRCVL_MIC1_SHIFT 4
  984. #define M98090_MIXRCVL_MIC1_WIDTH 1
  985. #define M98090_MIXRCVL_LINEB_MASK (1<<3)
  986. #define M98090_MIXRCVL_LINEB_SHIFT 3
  987. #define M98090_MIXRCVL_LINEB_WIDTH 1
  988. #define M98090_MIXRCVL_LINEA_MASK (1<<2)
  989. #define M98090_MIXRCVL_LINEA_SHIFT 2
  990. #define M98090_MIXRCVL_LINEA_WIDTH 1
  991. #define M98090_MIXRCVL_DACR_MASK (1<<1)
  992. #define M98090_MIXRCVL_DACR_SHIFT 1
  993. #define M98090_MIXRCVL_DACR_WIDTH 1
  994. #define M98090_MIXRCVL_DACL_MASK (1<<0)
  995. #define M98090_MIXRCVL_DACL_SHIFT 0
  996. #define M98090_MIXRCVL_DACL_WIDTH 1
  997. #define M98090_MIXRCVL_MASK (63<<0)
  998. #define M98090_MIXRCVL_SHIFT 0
  999. #define M98090_MIXRCVL_WIDTH 6
  1000. /*
  1001. * M98090_REG_RCV_LOUTL_CONTROL
  1002. */
  1003. #define M98090_MIXRCVLG_MASK (3<<0)
  1004. #define M98090_MIXRCVLG_SHIFT 0
  1005. #define M98090_MIXRCVLG_WIDTH 2
  1006. #define M98090_MIXRCVLG_NUM (1<<M98090_MIXRCVLG_WIDTH)
  1007. /*
  1008. * M98090_REG_RCV_LOUTL_VOLUME
  1009. */
  1010. #define M98090_RCVLM_MASK (1<<7)
  1011. #define M98090_RCVLM_SHIFT 7
  1012. #define M98090_RCVLM_WIDTH 1
  1013. #define M98090_RCVLVOL_MASK (31<<0)
  1014. #define M98090_RCVLVOL_SHIFT 0
  1015. #define M98090_RCVLVOL_WIDTH 5
  1016. #define M98090_RCVLVOL_NUM (1<<M98090_RCVLVOL_WIDTH)
  1017. /*
  1018. * M98090_REG_LOUTR_MIXER
  1019. */
  1020. #define M98090_LINMOD_MASK (1<<7)
  1021. #define M98090_LINMOD_SHIFT 7
  1022. #define M98090_LINMOD_WIDTH 1
  1023. #define M98090_MIXRCVR_MIC2_MASK (1<<5)
  1024. #define M98090_MIXRCVR_MIC2_SHIFT 5
  1025. #define M98090_MIXRCVR_MIC2_WIDTH 1
  1026. #define M98090_MIXRCVR_MIC1_MASK (1<<4)
  1027. #define M98090_MIXRCVR_MIC1_SHIFT 4
  1028. #define M98090_MIXRCVR_MIC1_WIDTH 1
  1029. #define M98090_MIXRCVR_LINEB_MASK (1<<3)
  1030. #define M98090_MIXRCVR_LINEB_SHIFT 3
  1031. #define M98090_MIXRCVR_LINEB_WIDTH 1
  1032. #define M98090_MIXRCVR_LINEA_MASK (1<<2)
  1033. #define M98090_MIXRCVR_LINEA_SHIFT 2
  1034. #define M98090_MIXRCVR_LINEA_WIDTH 1
  1035. #define M98090_MIXRCVR_DACR_MASK (1<<1)
  1036. #define M98090_MIXRCVR_DACR_SHIFT 1
  1037. #define M98090_MIXRCVR_DACR_WIDTH 1
  1038. #define M98090_MIXRCVR_DACL_MASK (1<<0)
  1039. #define M98090_MIXRCVR_DACL_SHIFT 0
  1040. #define M98090_MIXRCVR_DACL_WIDTH 1
  1041. #define M98090_MIXRCVR_MASK (63<<0)
  1042. #define M98090_MIXRCVR_SHIFT 0
  1043. #define M98090_MIXRCVR_WIDTH 6
  1044. /*
  1045. * M98090_REG_LOUTR_CONTROL
  1046. */
  1047. #define M98090_MIXRCVRG_MASK (3<<0)
  1048. #define M98090_MIXRCVRG_SHIFT 0
  1049. #define M98090_MIXRCVRG_WIDTH 2
  1050. #define M98090_MIXRCVRG_NUM (1<<M98090_MIXRCVRG_WIDTH)
  1051. /*
  1052. * M98090_REG_LOUTR_VOLUME
  1053. */
  1054. #define M98090_RCVRM_MASK (1<<7)
  1055. #define M98090_RCVRM_SHIFT 7
  1056. #define M98090_RCVRM_WIDTH 1
  1057. #define M98090_RCVRVOL_MASK (31<<0)
  1058. #define M98090_RCVRVOL_SHIFT 0
  1059. #define M98090_RCVRVOL_WIDTH 5
  1060. #define M98090_RCVRVOL_NUM (1<<M98090_RCVRVOL_WIDTH)
  1061. /*
  1062. * M98090_REG_JACK_DETECT
  1063. */
  1064. #define M98090_JDETEN_MASK (1<<7)
  1065. #define M98090_JDETEN_SHIFT 7
  1066. #define M98090_JDETEN_WIDTH 1
  1067. #define M98090_JDWK_MASK (1<<6)
  1068. #define M98090_JDWK_SHIFT 6
  1069. #define M98090_JDWK_WIDTH 1
  1070. #define M98090_JDEB_MASK (3<<0)
  1071. #define M98090_JDEB_SHIFT 0
  1072. #define M98090_JDEB_WIDTH 2
  1073. #define M98090_JDEB_25MS (0<<0)
  1074. #define M98090_JDEB_50MS (1<<0)
  1075. #define M98090_JDEB_100MS (2<<0)
  1076. #define M98090_JDEB_200MS (3<<0)
  1077. /*
  1078. * M98090_REG_INPUT_ENABLE
  1079. */
  1080. #define M98090_MBEN_MASK (1<<4)
  1081. #define M98090_MBEN_SHIFT 4
  1082. #define M98090_MBEN_WIDTH 1
  1083. #define M98090_LINEAEN_MASK (1<<3)
  1084. #define M98090_LINEAEN_SHIFT 3
  1085. #define M98090_LINEAEN_WIDTH 1
  1086. #define M98090_LINEBEN_MASK (1<<2)
  1087. #define M98090_LINEBEN_SHIFT 2
  1088. #define M98090_LINEBEN_WIDTH 1
  1089. #define M98090_ADREN_MASK (1<<1)
  1090. #define M98090_ADREN_SHIFT 1
  1091. #define M98090_ADREN_WIDTH 1
  1092. #define M98090_ADLEN_MASK (1<<0)
  1093. #define M98090_ADLEN_SHIFT 0
  1094. #define M98090_ADLEN_WIDTH 1
  1095. /*
  1096. * M98090_REG_OUTPUT_ENABLE
  1097. */
  1098. #define M98090_HPREN_MASK (1<<7)
  1099. #define M98090_HPREN_SHIFT 7
  1100. #define M98090_HPREN_WIDTH 1
  1101. #define M98090_HPLEN_MASK (1<<6)
  1102. #define M98090_HPLEN_SHIFT 6
  1103. #define M98090_HPLEN_WIDTH 1
  1104. #define M98090_SPREN_MASK (1<<5)
  1105. #define M98090_SPREN_SHIFT 5
  1106. #define M98090_SPREN_WIDTH 1
  1107. #define M98090_SPLEN_MASK (1<<4)
  1108. #define M98090_SPLEN_SHIFT 4
  1109. #define M98090_SPLEN_WIDTH 1
  1110. #define M98090_RCVLEN_MASK (1<<3)
  1111. #define M98090_RCVLEN_SHIFT 3
  1112. #define M98090_RCVLEN_WIDTH 1
  1113. #define M98090_RCVREN_MASK (1<<2)
  1114. #define M98090_RCVREN_SHIFT 2
  1115. #define M98090_RCVREN_WIDTH 1
  1116. #define M98090_DAREN_MASK (1<<1)
  1117. #define M98090_DAREN_SHIFT 1
  1118. #define M98090_DAREN_WIDTH 1
  1119. #define M98090_DALEN_MASK (1<<0)
  1120. #define M98090_DALEN_SHIFT 0
  1121. #define M98090_DALEN_WIDTH 1
  1122. /*
  1123. * M98090_REG_LEVEL_CONTROL
  1124. */
  1125. #define M98090_ZDENN_MASK (1<<2)
  1126. #define M98090_ZDENN_SHIFT 2
  1127. #define M98090_ZDENN_WIDTH 1
  1128. #define M98090_ZDENN_NUM (1<<M98090_ZDENN_WIDTH)
  1129. #define M98090_VS2ENN_MASK (1<<1)
  1130. #define M98090_VS2ENN_SHIFT 1
  1131. #define M98090_VS2ENN_WIDTH 1
  1132. #define M98090_VS2ENN_NUM (1<<M98090_VS2ENN_WIDTH)
  1133. #define M98090_VSENN_MASK (1<<0)
  1134. #define M98090_VSENN_SHIFT 0
  1135. #define M98090_VSENN_WIDTH 1
  1136. #define M98090_VSENN_NUM (1<<M98090_VSENN_WIDTH)
  1137. /*
  1138. * M98090_REG_DSP_FILTER_ENABLE
  1139. */
  1140. #define M98090_DMIC34BQEN_MASK (1<<4)
  1141. #define M98090_DMIC34BQEN_SHIFT 4
  1142. #define M98090_DMIC34BQEN_WIDTH 1
  1143. #define M98090_DMIC34BQEN_NUM (1<<M98090_DMIC34BQEN_WIDTH)
  1144. #define M98090_ADCBQEN_MASK (1<<3)
  1145. #define M98090_ADCBQEN_SHIFT 3
  1146. #define M98090_ADCBQEN_WIDTH 1
  1147. #define M98090_ADCBQEN_NUM (1<<M98090_ADCBQEN_WIDTH)
  1148. #define M98090_EQ3BANDEN_MASK (1<<2)
  1149. #define M98090_EQ3BANDEN_SHIFT 2
  1150. #define M98090_EQ3BANDEN_WIDTH 1
  1151. #define M98090_EQ3BANDEN_NUM (1<<M98090_EQ3BANDEN_WIDTH)
  1152. #define M98090_EQ5BANDEN_MASK (1<<1)
  1153. #define M98090_EQ5BANDEN_SHIFT 1
  1154. #define M98090_EQ5BANDEN_WIDTH 1
  1155. #define M98090_EQ5BANDEN_NUM (1<<M98090_EQ5BANDEN_WIDTH)
  1156. #define M98090_EQ7BANDEN_MASK (1<<0)
  1157. #define M98090_EQ7BANDEN_SHIFT 0
  1158. #define M98090_EQ7BANDEN_WIDTH 1
  1159. #define M98090_EQ7BANDEN_NUM (1<<M98090_EQ7BANDEN_WIDTH)
  1160. /*
  1161. * M98090_REG_BIAS_CONTROL
  1162. */
  1163. #define M98090_VCM_MODE_MASK (1<<0)
  1164. #define M98090_VCM_MODE_SHIFT 0
  1165. #define M98090_VCM_MODE_WIDTH 1
  1166. #define M98090_VCM_MODE_NUM (1<<M98090_VCM_MODE_WIDTH)
  1167. /*
  1168. * M98090_REG_DAC_CONTROL
  1169. */
  1170. #define M98090_PERFMODE_MASK (1<<1)
  1171. #define M98090_PERFMODE_SHIFT 1
  1172. #define M98090_PERFMODE_WIDTH 1
  1173. #define M98090_PERFMODE_NUM (1<<M98090_PERFMODE_WIDTH)
  1174. #define M98090_DACHP_MASK (1<<0)
  1175. #define M98090_DACHP_SHIFT 0
  1176. #define M98090_DACHP_WIDTH 1
  1177. #define M98090_DACHP_NUM (1<<M98090_DACHP_WIDTH)
  1178. /*
  1179. * M98090_REG_ADC_CONTROL
  1180. */
  1181. #define M98090_OSR128_MASK (1<<2)
  1182. #define M98090_OSR128_SHIFT 2
  1183. #define M98090_OSR128_WIDTH 1
  1184. #define M98090_ADCDITHER_MASK (1<<1)
  1185. #define M98090_ADCDITHER_SHIFT 1
  1186. #define M98090_ADCDITHER_WIDTH 1
  1187. #define M98090_ADCDITHER_NUM (1<<M98090_ADCDITHER_WIDTH)
  1188. #define M98090_ADCHP_MASK (1<<0)
  1189. #define M98090_ADCHP_SHIFT 0
  1190. #define M98090_ADCHP_WIDTH 1
  1191. #define M98090_ADCHP_NUM (1<<M98090_ADCHP_WIDTH)
  1192. /*
  1193. * M98090_REG_DEVICE_SHUTDOWN
  1194. */
  1195. #define M98090_SHDNN_MASK (1<<7)
  1196. #define M98090_SHDNN_SHIFT 7
  1197. #define M98090_SHDNN_WIDTH 1
  1198. /*
  1199. * M98090_REG_EQUALIZER_BASE
  1200. */
  1201. #define M98090_B0_1_HI_MASK (255<<0)
  1202. #define M98090_B0_1_HI_SHIFT 0
  1203. #define M98090_B0_1_HI_WIDTH 8
  1204. #define M98090_B0_1_MID_MASK (255<<0)
  1205. #define M98090_B0_1_MID_SHIFT 0
  1206. #define M98090_B0_1_MID_WIDTH 8
  1207. #define M98090_B0_1_LO_MASK (255<<0)
  1208. #define M98090_B0_1_LO_SHIFT 0
  1209. #define M98090_B0_1_LO_WIDTH 8
  1210. #define M98090_B1_1_HI_MASK (255<<0)
  1211. #define M98090_B1_1_HI_SHIFT 0
  1212. #define M98090_B1_1_HI_WIDTH 8
  1213. #define M98090_B1_1_MID_MASK (255<<0)
  1214. #define M98090_B1_1_MID_SHIFT 0
  1215. #define M98090_B1_1_MID_WIDTH 8
  1216. #define M98090_B1_1_LO_MASK (255<<0)
  1217. #define M98090_B1_1_LO_SHIFT 0
  1218. #define M98090_B1_1_LO_WIDTH 8
  1219. #define M98090_B2_1_HI_MASK (255<<0)
  1220. #define M98090_B2_1_HI_SHIFT 0
  1221. #define M98090_B2_1_HI_WIDTH 8
  1222. #define M98090_B2_1_MID_MASK (255<<0)
  1223. #define M98090_B2_1_MID_SHIFT 0
  1224. #define M98090_B2_1_MID_WIDTH 8
  1225. #define M98090_B2_1_LO_MASK (255<<0)
  1226. #define M98090_B2_1_LO_SHIFT 0
  1227. #define M98090_B2_1_LO_WIDTH 8
  1228. #define M98090_A1_1_HI_MASK (255<<0)
  1229. #define M98090_A1_1_HI_SHIFT 0
  1230. #define M98090_A1_1_HI_WIDTH 8
  1231. #define M98090_A1_1_MID_MASK (255<<0)
  1232. #define M98090_A1_1_MID_SHIFT 0
  1233. #define M98090_A1_1_MID_WIDTH 8
  1234. #define M98090_A1_1_LO_MASK (255<<0)
  1235. #define M98090_A1_1_LO_SHIFT 0
  1236. #define M98090_A1_1_LO_WIDTH 8
  1237. #define M98090_A2_1_HI_MASK (255<<0)
  1238. #define M98090_A2_1_HI_SHIFT 0
  1239. #define M98090_A2_1_HI_WIDTH 8
  1240. #define M98090_A2_1_MID_MASK (255<<0)
  1241. #define M98090_A2_1_MID_SHIFT 0
  1242. #define M98090_A2_1_MID_WIDTH 8
  1243. #define M98090_A2_1_LO_MASK (255<<0)
  1244. #define M98090_A2_1_LO_SHIFT 0
  1245. #define M98090_A2_1_LO_WIDTH 8
  1246. #define M98090_COEFS_PER_BAND 5
  1247. #define M98090_COEFS_BLK_SZ (M98090_COEFS_PER_BAND * 3)
  1248. #define M98090_COEFS_MAX_SZ (M98090_COEFS_BLK_SZ * 7)
  1249. /*
  1250. * M98090_REG_RECORD_BIQUAD_BASE
  1251. */
  1252. #define M98090_REC_B0_HI_MASK (255<<0)
  1253. #define M98090_REC_B0_HI_SHIFT 0
  1254. #define M98090_REC_B0_HI_WIDTH 8
  1255. #define M98090_REC_B0_MID_MASK (255<<0)
  1256. #define M98090_REC_B0_MID_SHIFT 0
  1257. #define M98090_REC_B0_MID_WIDTH 8
  1258. #define M98090_REC_B0_LO_MASK (255<<0)
  1259. #define M98090_REC_B0_LO_SHIFT 0
  1260. #define M98090_REC_B0_LO_WIDTH 8
  1261. #define M98090_REC_B1_HI_MASK (255<<0)
  1262. #define M98090_REC_B1_HI_SHIFT 0
  1263. #define M98090_REC_B1_HI_WIDTH 8
  1264. #define M98090_REC_B1_MID_MASK (255<<0)
  1265. #define M98090_REC_B1_MID_SHIFT 0
  1266. #define M98090_REC_B1_MID_WIDTH 8
  1267. #define M98090_REC_B1_LO_MASK (255<<0)
  1268. #define M98090_REC_B1_LO_SHIFT 0
  1269. #define M98090_REC_B1_LO_WIDTH 8
  1270. #define M98090_REC_B2_HI_MASK (255<<0)
  1271. #define M98090_REC_B2_HI_SHIFT 0
  1272. #define M98090_REC_B2_HI_WIDTH 8
  1273. #define M98090_REC_B2_MID_MASK (255<<0)
  1274. #define M98090_REC_B2_MID_SHIFT 0
  1275. #define M98090_REC_B2_MID_WIDTH 8
  1276. #define M98090_REC_B2_LO_MASK (255<<0)
  1277. #define M98090_REC_B2_LO_SHIFT 0
  1278. #define M98090_REC_B2_LO_WIDTH 8
  1279. #define M98090_REC_A1_HI_MASK (255<<0)
  1280. #define M98090_REC_A1_HI_SHIFT 0
  1281. #define M98090_REC_A1_HI_WIDTH 8
  1282. #define M98090_REC_A1_MID_MASK (255<<0)
  1283. #define M98090_REC_A1_MID_SHIFT 0
  1284. #define M98090_REC_A1_MID_WIDTH 8
  1285. #define M98090_REC_A1_LO_MASK (255<<0)
  1286. #define M98090_REC_A1_LO_SHIFT 0
  1287. #define M98090_REC_A1_LO_WIDTH 8
  1288. #define M98090_REC_A2_HI_MASK (255<<0)
  1289. #define M98090_REC_A2_HI_SHIFT 0
  1290. #define M98090_REC_A2_HI_WIDTH 8
  1291. #define M98090_REC_A2_MID_MASK (255<<0)
  1292. #define M98090_REC_A2_MID_SHIFT 0
  1293. #define M98090_REC_A2_MID_WIDTH 8
  1294. #define M98090_REC_A2_LO_MASK (255<<0)
  1295. #define M98090_REC_A2_LO_SHIFT 0
  1296. #define M98090_REC_A2_LO_WIDTH 8
  1297. /*
  1298. * M98090_REG_DMIC3_VOLUME
  1299. */
  1300. #define M98090_DMIC_AV3G_MASK (7<<4)
  1301. #define M98090_DMIC_AV3G_SHIFT 4
  1302. #define M98090_DMIC_AV3G_WIDTH 3
  1303. #define M98090_DMIC_AV3G_NUM (1<<M98090_DMIC_AV3G_WIDTH)
  1304. #define M98090_DMIC_AV3_MASK (15<<0)
  1305. #define M98090_DMIC_AV3_SHIFT 0
  1306. #define M98090_DMIC_AV3_WIDTH 4
  1307. #define M98090_DMIC_AV3_NUM (1<<M98090_DMIC_AV3_WIDTH)
  1308. /*
  1309. * M98090_REG_DMIC4_VOLUME
  1310. */
  1311. #define M98090_DMIC_AV4G_MASK (7<<4)
  1312. #define M98090_DMIC_AV4G_SHIFT 4
  1313. #define M98090_DMIC_AV4G_WIDTH 3
  1314. #define M98090_DMIC_AV4G_NUM (1<<M98090_DMIC_AV4G_WIDTH)
  1315. #define M98090_DMIC_AV4_MASK (15<<0)
  1316. #define M98090_DMIC_AV4_SHIFT 0
  1317. #define M98090_DMIC_AV4_WIDTH 4
  1318. #define M98090_DMIC_AV4_NUM (1<<M98090_DMIC_AV4_WIDTH)
  1319. /*
  1320. * M98090_REG_DMIC34_BQ_PREATTEN
  1321. */
  1322. #define M98090_AV34BQ_MASK (15<<0)
  1323. #define M98090_AV34BQ_SHIFT 0
  1324. #define M98090_AV34BQ_WIDTH 4
  1325. #define M98090_AV34BQ_NUM (1<<M98090_AV34BQ_WIDTH)
  1326. /*
  1327. * M98090_REG_RECORD_TDM_SLOT
  1328. */
  1329. #define M98090_TDM_SLOTADCL_MASK (3<<6)
  1330. #define M98090_TDM_SLOTADCL_SHIFT 6
  1331. #define M98090_TDM_SLOTADCL_WIDTH 2
  1332. #define M98090_TDM_SLOTADCL_NUM (1<<M98090_TDM_SLOTADCL_WIDTH)
  1333. #define M98090_TDM_SLOTADCR_MASK (3<<4)
  1334. #define M98090_TDM_SLOTADCR_SHIFT 4
  1335. #define M98090_TDM_SLOTADCR_WIDTH 2
  1336. #define M98090_TDM_SLOTADCR_NUM (1<<M98090_TDM_SLOTADCR_WIDTH)
  1337. #define M98090_TDM_SLOTDMIC3_MASK (3<<2)
  1338. #define M98090_TDM_SLOTDMIC3_SHIFT 2
  1339. #define M98090_TDM_SLOTDMIC3_WIDTH 2
  1340. #define M98090_TDM_SLOTDMIC3_NUM (1<<M98090_TDM_SLOTDMIC3_WIDTH)
  1341. #define M98090_TDM_SLOTDMIC4_MASK (3<<0)
  1342. #define M98090_TDM_SLOTDMIC4_SHIFT 0
  1343. #define M98090_TDM_SLOTDMIC4_WIDTH 2
  1344. #define M98090_TDM_SLOTDMIC4_NUM (1<<M98090_TDM_SLOTDMIC4_WIDTH)
  1345. /*
  1346. * M98090_REG_SAMPLE_RATE
  1347. */
  1348. #define M98090_DMIC34_ZEROPAD_MASK (1<<4)
  1349. #define M98090_DMIC34_ZEROPAD_SHIFT 4
  1350. #define M98090_DMIC34_ZEROPAD_WIDTH 1
  1351. #define M98090_DMIC34_ZEROPAD_NUM (1<<M98090_DIGMIC4_WIDTH)
  1352. #define M98090_DMIC34_SRDIV_MASK (7<<0)
  1353. #define M98090_DMIC34_SRDIV_SHIFT 0
  1354. #define M98090_DMIC34_SRDIV_WIDTH 3
  1355. /*
  1356. * M98090_REG_DMIC34_BIQUAD_BASE
  1357. */
  1358. #define M98090_DMIC34_B0_HI_MASK (255<<0)
  1359. #define M98090_DMIC34_B0_HI_SHIFT 0
  1360. #define M98090_DMIC34_B0_HI_WIDTH 8
  1361. #define M98090_DMIC34_B0_MID_MASK (255<<0)
  1362. #define M98090_DMIC34_B0_MID_SHIFT 0
  1363. #define M98090_DMIC34_B0_MID_WIDTH 8
  1364. #define M98090_DMIC34_B0_LO_MASK (255<<0)
  1365. #define M98090_DMIC34_B0_LO_SHIFT 0
  1366. #define M98090_DMIC34_B0_LO_WIDTH 8
  1367. #define M98090_DMIC34_B1_HI_MASK (255<<0)
  1368. #define M98090_DMIC34_B1_HI_SHIFT 0
  1369. #define M98090_DMIC34_B1_HI_WIDTH 8
  1370. #define M98090_DMIC34_B1_MID_MASK (255<<0)
  1371. #define M98090_DMIC34_B1_MID_SHIFT 0
  1372. #define M98090_DMIC34_B1_MID_WIDTH 8
  1373. #define M98090_DMIC34_B1_LO_MASK (255<<0)
  1374. #define M98090_DMIC34_B1_LO_SHIFT 0
  1375. #define M98090_DMIC34_B1_LO_WIDTH 8
  1376. #define M98090_DMIC34_B2_HI_MASK (255<<0)
  1377. #define M98090_DMIC34_B2_HI_SHIFT 0
  1378. #define M98090_DMIC34_B2_HI_WIDTH 8
  1379. #define M98090_DMIC34_B2_MID_MASK (255<<0)
  1380. #define M98090_DMIC34_B2_MID_SHIFT 0
  1381. #define M98090_DMIC34_B2_MID_WIDTH 8
  1382. #define M98090_DMIC34_B2_LO_MASK (255<<0)
  1383. #define M98090_DMIC34_B2_LO_SHIFT 0
  1384. #define M98090_DMIC34_B2_LO_WIDTH 8
  1385. #define M98090_DMIC34_A1_HI_MASK (255<<0)
  1386. #define M98090_DMIC34_A1_HI_SHIFT 0
  1387. #define M98090_DMIC34_A1_HI_WIDTH 8
  1388. #define M98090_DMIC34_A1_MID_MASK (255<<0)
  1389. #define M98090_DMIC34_A1_MID_SHIFT 0
  1390. #define M98090_DMIC34_A1_MID_WIDTH 8
  1391. #define M98090_DMIC34_A1_LO_MASK (255<<0)
  1392. #define M98090_DMIC34_A1_LO_SHIFT 0
  1393. #define M98090_DMIC34_A1_LO_WIDTH 8
  1394. #define M98090_DMIC34_A2_HI_MASK (255<<0)
  1395. #define M98090_DMIC34_A2_HI_SHIFT 0
  1396. #define M98090_DMIC34_A2_HI_WIDTH 8
  1397. #define M98090_DMIC34_A2_MID_MASK (255<<0)
  1398. #define M98090_DMIC34_A2_MID_SHIFT 0
  1399. #define M98090_DMIC34_A2_MID_WIDTH 8
  1400. #define M98090_DMIC34_A2_LO_MASK (255<<0)
  1401. #define M98090_DMIC34_A2_LO_SHIFT 0
  1402. #define M98090_DMIC34_A2_LO_WIDTH 8
  1403. #define M98090_JACK_STATE_NO_HEADSET 0
  1404. #define M98090_JACK_STATE_NO_HEADSET_2 1
  1405. #define M98090_JACK_STATE_HEADPHONE 2
  1406. #define M98090_JACK_STATE_HEADSET 3
  1407. /*
  1408. * M98090_REG_REVISION_ID
  1409. */
  1410. #define M98090_REVID_MASK (255<<0)
  1411. #define M98090_REVID_SHIFT 0
  1412. #define M98090_REVID_WIDTH 8
  1413. #define M98090_REVID_NUM (1<<M98090_REVID_WIDTH)
  1414. /* Silicon revision number */
  1415. #define M98090_REVA 0x40
  1416. #define M98091_REVA 0x50
  1417. enum max98090_type {
  1418. MAX98090,
  1419. MAX98091,
  1420. };
  1421. struct max98090_cdata {
  1422. unsigned int rate;
  1423. unsigned int fmt;
  1424. };
  1425. struct max98090_priv {
  1426. struct regmap *regmap;
  1427. struct snd_soc_component *component;
  1428. enum max98090_type devtype;
  1429. struct max98090_pdata *pdata;
  1430. struct clk *mclk;
  1431. unsigned int sysclk;
  1432. unsigned int pclk;
  1433. unsigned int bclk;
  1434. unsigned int lrclk;
  1435. u32 dmic_freq;
  1436. struct max98090_cdata dai[1];
  1437. int jack_state;
  1438. struct delayed_work jack_work;
  1439. struct delayed_work pll_det_enable_work;
  1440. struct work_struct pll_det_disable_work;
  1441. struct snd_soc_jack *jack;
  1442. unsigned int dai_fmt;
  1443. int tdm_slots;
  1444. int tdm_width;
  1445. u8 lin_state;
  1446. unsigned int pa1en;
  1447. unsigned int pa2en;
  1448. unsigned int sidetone;
  1449. bool master;
  1450. bool shdn_pending;
  1451. };
  1452. int max98090_mic_detect(struct snd_soc_component *component,
  1453. struct snd_soc_jack *jack);
  1454. #endif