max98090.c 85 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * max98090.c -- MAX98090 ALSA SoC Audio driver
  4. *
  5. * Copyright 2011-2012 Maxim Integrated Products
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/i2c.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/pm.h>
  12. #include <linux/pm_runtime.h>
  13. #include <linux/regmap.h>
  14. #include <linux/slab.h>
  15. #include <linux/acpi.h>
  16. #include <linux/clk.h>
  17. #include <sound/jack.h>
  18. #include <sound/pcm.h>
  19. #include <sound/pcm_params.h>
  20. #include <sound/soc.h>
  21. #include <sound/tlv.h>
  22. #include <sound/max98090.h>
  23. #include "max98090.h"
  24. /* Allows for sparsely populated register maps */
  25. static const struct reg_default max98090_reg[] = {
  26. { 0x00, 0x00 }, /* 00 Software Reset */
  27. { 0x03, 0x04 }, /* 03 Interrupt Masks */
  28. { 0x04, 0x00 }, /* 04 System Clock Quick */
  29. { 0x05, 0x00 }, /* 05 Sample Rate Quick */
  30. { 0x06, 0x00 }, /* 06 DAI Interface Quick */
  31. { 0x07, 0x00 }, /* 07 DAC Path Quick */
  32. { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
  33. { 0x09, 0x00 }, /* 09 Line to ADC Quick */
  34. { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
  35. { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
  36. { 0x0C, 0x00 }, /* 0C Reserved */
  37. { 0x0D, 0x00 }, /* 0D Input Config */
  38. { 0x0E, 0x1B }, /* 0E Line Input Level */
  39. { 0x0F, 0x00 }, /* 0F Line Config */
  40. { 0x10, 0x14 }, /* 10 Mic1 Input Level */
  41. { 0x11, 0x14 }, /* 11 Mic2 Input Level */
  42. { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
  43. { 0x13, 0x00 }, /* 13 Digital Mic Config */
  44. { 0x14, 0x00 }, /* 14 Digital Mic Mode */
  45. { 0x15, 0x00 }, /* 15 Left ADC Mixer */
  46. { 0x16, 0x00 }, /* 16 Right ADC Mixer */
  47. { 0x17, 0x03 }, /* 17 Left ADC Level */
  48. { 0x18, 0x03 }, /* 18 Right ADC Level */
  49. { 0x19, 0x00 }, /* 19 ADC Biquad Level */
  50. { 0x1A, 0x00 }, /* 1A ADC Sidetone */
  51. { 0x1B, 0x00 }, /* 1B System Clock */
  52. { 0x1C, 0x00 }, /* 1C Clock Mode */
  53. { 0x1D, 0x00 }, /* 1D Any Clock 1 */
  54. { 0x1E, 0x00 }, /* 1E Any Clock 2 */
  55. { 0x1F, 0x00 }, /* 1F Any Clock 3 */
  56. { 0x20, 0x00 }, /* 20 Any Clock 4 */
  57. { 0x21, 0x00 }, /* 21 Master Mode */
  58. { 0x22, 0x00 }, /* 22 Interface Format */
  59. { 0x23, 0x00 }, /* 23 TDM Format 1*/
  60. { 0x24, 0x00 }, /* 24 TDM Format 2*/
  61. { 0x25, 0x00 }, /* 25 I/O Configuration */
  62. { 0x26, 0x80 }, /* 26 Filter Config */
  63. { 0x27, 0x00 }, /* 27 DAI Playback Level */
  64. { 0x28, 0x00 }, /* 28 EQ Playback Level */
  65. { 0x29, 0x00 }, /* 29 Left HP Mixer */
  66. { 0x2A, 0x00 }, /* 2A Right HP Mixer */
  67. { 0x2B, 0x00 }, /* 2B HP Control */
  68. { 0x2C, 0x1A }, /* 2C Left HP Volume */
  69. { 0x2D, 0x1A }, /* 2D Right HP Volume */
  70. { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
  71. { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
  72. { 0x30, 0x00 }, /* 30 Spk Control */
  73. { 0x31, 0x2C }, /* 31 Left Spk Volume */
  74. { 0x32, 0x2C }, /* 32 Right Spk Volume */
  75. { 0x33, 0x00 }, /* 33 ALC Timing */
  76. { 0x34, 0x00 }, /* 34 ALC Compressor */
  77. { 0x35, 0x00 }, /* 35 ALC Expander */
  78. { 0x36, 0x00 }, /* 36 ALC Gain */
  79. { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
  80. { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
  81. { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
  82. { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
  83. { 0x3B, 0x00 }, /* 3B Line OutR Control */
  84. { 0x3C, 0x15 }, /* 3C Line OutR Volume */
  85. { 0x3D, 0x00 }, /* 3D Jack Detect */
  86. { 0x3E, 0x00 }, /* 3E Input Enable */
  87. { 0x3F, 0x00 }, /* 3F Output Enable */
  88. { 0x40, 0x00 }, /* 40 Level Control */
  89. { 0x41, 0x00 }, /* 41 DSP Filter Enable */
  90. { 0x42, 0x00 }, /* 42 Bias Control */
  91. { 0x43, 0x00 }, /* 43 DAC Control */
  92. { 0x44, 0x06 }, /* 44 ADC Control */
  93. { 0x45, 0x00 }, /* 45 Device Shutdown */
  94. { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
  95. { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
  96. { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
  97. { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
  98. { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
  99. { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
  100. { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
  101. { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
  102. { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
  103. { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
  104. { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
  105. { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
  106. { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
  107. { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
  108. { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
  109. { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
  110. { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
  111. { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
  112. { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
  113. { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
  114. { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
  115. { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
  116. { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
  117. { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
  118. { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
  119. { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
  120. { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
  121. { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
  122. { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
  123. { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
  124. { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
  125. { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
  126. { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
  127. { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
  128. { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
  129. { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
  130. { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
  131. { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
  132. { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
  133. { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
  134. { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
  135. { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
  136. { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
  137. { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
  138. { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
  139. { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
  140. { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
  141. { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
  142. { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
  143. { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
  144. { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
  145. { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
  146. { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
  147. { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
  148. { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
  149. { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
  150. { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
  151. { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
  152. { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
  153. { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
  154. { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
  155. { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
  156. { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
  157. { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
  158. { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
  159. { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
  160. { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
  161. { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
  162. { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
  163. { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
  164. { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
  165. { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
  166. { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
  167. { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
  168. { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
  169. { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
  170. { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
  171. { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
  172. { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
  173. { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
  174. { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
  175. { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
  176. { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
  177. { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
  178. { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
  179. { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
  180. { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
  181. { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
  182. { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
  183. { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
  184. { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
  185. { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
  186. { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
  187. { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
  188. { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
  189. { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
  190. { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
  191. { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
  192. { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
  193. { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
  194. { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
  195. { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
  196. { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
  197. { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
  198. { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
  199. { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
  200. { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
  201. { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
  202. { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
  203. { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
  204. { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
  205. { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
  206. { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
  207. { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
  208. { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
  209. { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
  210. { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
  211. { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
  212. { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
  213. { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
  214. { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
  215. { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
  216. { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
  217. { 0xC1, 0x00 }, /* C1 Record TDM Slot */
  218. { 0xC2, 0x00 }, /* C2 Sample Rate */
  219. { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
  220. { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
  221. { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
  222. { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
  223. { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
  224. { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
  225. { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
  226. { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
  227. { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
  228. { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
  229. { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
  230. { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
  231. { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
  232. { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
  233. { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
  234. };
  235. static bool max98090_volatile_register(struct device *dev, unsigned int reg)
  236. {
  237. switch (reg) {
  238. case M98090_REG_SOFTWARE_RESET:
  239. case M98090_REG_DEVICE_STATUS:
  240. case M98090_REG_JACK_STATUS:
  241. case M98090_REG_REVISION_ID:
  242. return true;
  243. default:
  244. return false;
  245. }
  246. }
  247. static bool max98090_readable_register(struct device *dev, unsigned int reg)
  248. {
  249. switch (reg) {
  250. case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
  251. case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
  252. case M98090_REG_REVISION_ID:
  253. return true;
  254. default:
  255. return false;
  256. }
  257. }
  258. static int max98090_reset(struct max98090_priv *max98090)
  259. {
  260. int ret;
  261. /* Reset the codec by writing to this write-only reset register */
  262. ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
  263. M98090_SWRESET_MASK);
  264. if (ret < 0) {
  265. dev_err(max98090->component->dev,
  266. "Failed to reset codec: %d\n", ret);
  267. return ret;
  268. }
  269. msleep(20);
  270. return ret;
  271. }
  272. static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv,
  273. 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
  274. 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
  275. );
  276. static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
  277. static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
  278. -600, 600, 0);
  279. static const DECLARE_TLV_DB_RANGE(max98090_line_tlv,
  280. 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
  281. 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
  282. );
  283. static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
  284. static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
  285. static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
  286. static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
  287. static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
  288. static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
  289. static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
  290. static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
  291. static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv,
  292. 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
  293. 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
  294. );
  295. static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv,
  296. 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
  297. 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
  298. 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
  299. 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
  300. 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
  301. );
  302. static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv,
  303. 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
  304. 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
  305. 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
  306. 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
  307. 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0)
  308. );
  309. static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv,
  310. 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
  311. 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
  312. 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
  313. 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
  314. 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
  315. );
  316. static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
  317. struct snd_ctl_elem_value *ucontrol)
  318. {
  319. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  320. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  321. struct soc_mixer_control *mc =
  322. (struct soc_mixer_control *)kcontrol->private_value;
  323. unsigned int mask = (1 << fls(mc->max)) - 1;
  324. unsigned int val = snd_soc_component_read(component, mc->reg);
  325. unsigned int *select;
  326. switch (mc->reg) {
  327. case M98090_REG_MIC1_INPUT_LEVEL:
  328. select = &(max98090->pa1en);
  329. break;
  330. case M98090_REG_MIC2_INPUT_LEVEL:
  331. select = &(max98090->pa2en);
  332. break;
  333. case M98090_REG_ADC_SIDETONE:
  334. select = &(max98090->sidetone);
  335. break;
  336. default:
  337. return -EINVAL;
  338. }
  339. val = (val >> mc->shift) & mask;
  340. if (val >= 1) {
  341. /* If on, return the volume */
  342. val = val - 1;
  343. *select = val;
  344. } else {
  345. /* If off, return last stored value */
  346. val = *select;
  347. }
  348. ucontrol->value.integer.value[0] = val;
  349. return 0;
  350. }
  351. static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
  352. struct snd_ctl_elem_value *ucontrol)
  353. {
  354. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  355. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  356. struct soc_mixer_control *mc =
  357. (struct soc_mixer_control *)kcontrol->private_value;
  358. unsigned int mask = (1 << fls(mc->max)) - 1;
  359. unsigned int sel = ucontrol->value.integer.value[0];
  360. unsigned int val = snd_soc_component_read(component, mc->reg);
  361. unsigned int *select;
  362. switch (mc->reg) {
  363. case M98090_REG_MIC1_INPUT_LEVEL:
  364. select = &(max98090->pa1en);
  365. break;
  366. case M98090_REG_MIC2_INPUT_LEVEL:
  367. select = &(max98090->pa2en);
  368. break;
  369. case M98090_REG_ADC_SIDETONE:
  370. select = &(max98090->sidetone);
  371. break;
  372. default:
  373. return -EINVAL;
  374. }
  375. val = (val >> mc->shift) & mask;
  376. *select = sel;
  377. /* Setting a volume is only valid if it is already On */
  378. if (val >= 1) {
  379. sel = sel + 1;
  380. } else {
  381. /* Write what was already there */
  382. sel = val;
  383. }
  384. snd_soc_component_update_bits(component, mc->reg,
  385. mask << mc->shift,
  386. sel << mc->shift);
  387. return 0;
  388. }
  389. static const char *max98090_perf_pwr_text[] =
  390. { "High Performance", "Low Power" };
  391. static const char *max98090_pwr_perf_text[] =
  392. { "Low Power", "High Performance" };
  393. static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
  394. M98090_REG_BIAS_CONTROL,
  395. M98090_VCM_MODE_SHIFT,
  396. max98090_pwr_perf_text);
  397. static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
  398. static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
  399. M98090_REG_ADC_CONTROL,
  400. M98090_OSR128_SHIFT,
  401. max98090_osr128_text);
  402. static const char *max98090_mode_text[] = { "Voice", "Music" };
  403. static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
  404. M98090_REG_FILTER_CONFIG,
  405. M98090_MODE_SHIFT,
  406. max98090_mode_text);
  407. static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
  408. M98090_REG_FILTER_CONFIG,
  409. M98090_FLT_DMIC34MODE_SHIFT,
  410. max98090_mode_text);
  411. static const char *max98090_drcatk_text[] =
  412. { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
  413. static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
  414. M98090_REG_DRC_TIMING,
  415. M98090_DRCATK_SHIFT,
  416. max98090_drcatk_text);
  417. static const char *max98090_drcrls_text[] =
  418. { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
  419. static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
  420. M98090_REG_DRC_TIMING,
  421. M98090_DRCRLS_SHIFT,
  422. max98090_drcrls_text);
  423. static const char *max98090_alccmp_text[] =
  424. { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
  425. static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
  426. M98090_REG_DRC_COMPRESSOR,
  427. M98090_DRCCMP_SHIFT,
  428. max98090_alccmp_text);
  429. static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
  430. static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
  431. M98090_REG_DRC_EXPANDER,
  432. M98090_DRCEXP_SHIFT,
  433. max98090_drcexp_text);
  434. static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
  435. M98090_REG_DAC_CONTROL,
  436. M98090_PERFMODE_SHIFT,
  437. max98090_perf_pwr_text);
  438. static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
  439. M98090_REG_DAC_CONTROL,
  440. M98090_DACHP_SHIFT,
  441. max98090_pwr_perf_text);
  442. static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
  443. M98090_REG_ADC_CONTROL,
  444. M98090_ADCHP_SHIFT,
  445. max98090_pwr_perf_text);
  446. static const struct snd_kcontrol_new max98090_snd_controls[] = {
  447. SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
  448. SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
  449. M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
  450. SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
  451. M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
  452. M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
  453. max98090_put_enab_tlv, max98090_micboost_tlv),
  454. SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
  455. M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
  456. M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
  457. max98090_put_enab_tlv, max98090_micboost_tlv),
  458. SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
  459. M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
  460. max98090_mic_tlv),
  461. SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
  462. M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
  463. max98090_mic_tlv),
  464. SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
  465. M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
  466. M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
  467. SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
  468. M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
  469. M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
  470. SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
  471. M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
  472. max98090_line_tlv),
  473. SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
  474. M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
  475. max98090_line_tlv),
  476. SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
  477. M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
  478. SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
  479. M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
  480. SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
  481. M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
  482. max98090_avg_tlv),
  483. SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
  484. M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
  485. max98090_avg_tlv),
  486. SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
  487. M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
  488. max98090_av_tlv),
  489. SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
  490. M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
  491. max98090_av_tlv),
  492. SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
  493. SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
  494. M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
  495. SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
  496. SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
  497. M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
  498. SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
  499. M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
  500. SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
  501. M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
  502. SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
  503. M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
  504. SOC_ENUM("Filter Mode", max98090_mode_enum),
  505. SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
  506. M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
  507. SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
  508. M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
  509. SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
  510. M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
  511. SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
  512. M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
  513. M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
  514. max98090_put_enab_tlv, max98090_sdg_tlv),
  515. SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
  516. M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
  517. max98090_dvg_tlv),
  518. SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
  519. M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
  520. max98090_dv_tlv),
  521. SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
  522. SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
  523. M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
  524. SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
  525. M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
  526. SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
  527. M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
  528. SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
  529. M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
  530. 1),
  531. SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
  532. M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
  533. max98090_dv_tlv),
  534. SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
  535. M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
  536. SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
  537. SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
  538. SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
  539. M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
  540. max98090_alcmakeup_tlv),
  541. SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
  542. SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
  543. SOC_SINGLE_TLV("ALC Compression Threshold Volume",
  544. M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
  545. M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
  546. SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
  547. M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
  548. M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
  549. SOC_ENUM("DAC HP Playback Performance Mode",
  550. max98090_dac_perfmode_enum),
  551. SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
  552. SOC_SINGLE_TLV("Headphone Left Mixer Volume",
  553. M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
  554. M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
  555. SOC_SINGLE_TLV("Headphone Right Mixer Volume",
  556. M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
  557. M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
  558. SOC_SINGLE_TLV("Speaker Left Mixer Volume",
  559. M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
  560. M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
  561. SOC_SINGLE_TLV("Speaker Right Mixer Volume",
  562. M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
  563. M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
  564. SOC_SINGLE_TLV("Receiver Left Mixer Volume",
  565. M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
  566. M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
  567. SOC_SINGLE_TLV("Receiver Right Mixer Volume",
  568. M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
  569. M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
  570. SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
  571. M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
  572. M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
  573. SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
  574. M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
  575. M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
  576. 0, max98090_spk_tlv),
  577. SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
  578. M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
  579. M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
  580. SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
  581. M98090_HPLM_SHIFT, 1, 1),
  582. SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
  583. M98090_HPRM_SHIFT, 1, 1),
  584. SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
  585. M98090_SPLM_SHIFT, 1, 1),
  586. SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
  587. M98090_SPRM_SHIFT, 1, 1),
  588. SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
  589. M98090_RCVLM_SHIFT, 1, 1),
  590. SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
  591. M98090_RCVRM_SHIFT, 1, 1),
  592. SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
  593. M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
  594. SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
  595. M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
  596. SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
  597. M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
  598. SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
  599. SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
  600. M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
  601. };
  602. static const struct snd_kcontrol_new max98091_snd_controls[] = {
  603. SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
  604. M98090_DMIC34_ZEROPAD_SHIFT,
  605. M98090_DMIC34_ZEROPAD_NUM - 1, 0),
  606. SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
  607. SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
  608. M98090_FLT_DMIC34HPF_SHIFT,
  609. M98090_FLT_DMIC34HPF_NUM - 1, 0),
  610. SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
  611. M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
  612. max98090_avg_tlv),
  613. SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
  614. M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
  615. max98090_avg_tlv),
  616. SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
  617. M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
  618. max98090_av_tlv),
  619. SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
  620. M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
  621. max98090_av_tlv),
  622. SND_SOC_BYTES("DMIC34 Biquad Coefficients",
  623. M98090_REG_DMIC34_BIQUAD_BASE, 15),
  624. SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
  625. M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
  626. SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
  627. M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
  628. M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
  629. };
  630. static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
  631. struct snd_kcontrol *kcontrol, int event)
  632. {
  633. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  634. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  635. unsigned int val = snd_soc_component_read(component, w->reg);
  636. if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
  637. val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
  638. else
  639. val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
  640. if (val >= 1) {
  641. if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
  642. max98090->pa1en = val - 1; /* Update for volatile */
  643. } else {
  644. max98090->pa2en = val - 1; /* Update for volatile */
  645. }
  646. }
  647. switch (event) {
  648. case SND_SOC_DAPM_POST_PMU:
  649. /* If turning on, set to most recently selected volume */
  650. if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
  651. val = max98090->pa1en + 1;
  652. else
  653. val = max98090->pa2en + 1;
  654. break;
  655. case SND_SOC_DAPM_POST_PMD:
  656. /* If turning off, turn off */
  657. val = 0;
  658. break;
  659. default:
  660. return -EINVAL;
  661. }
  662. if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
  663. snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK,
  664. val << M98090_MIC_PA1EN_SHIFT);
  665. else
  666. snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK,
  667. val << M98090_MIC_PA2EN_SHIFT);
  668. return 0;
  669. }
  670. static int max98090_shdn_event(struct snd_soc_dapm_widget *w,
  671. struct snd_kcontrol *kcontrol, int event)
  672. {
  673. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  674. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  675. if (event & SND_SOC_DAPM_POST_PMU)
  676. max98090->shdn_pending = true;
  677. return 0;
  678. }
  679. static const char *mic1_mux_text[] = { "IN12", "IN56" };
  680. static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
  681. M98090_REG_INPUT_MODE,
  682. M98090_EXTMIC1_SHIFT,
  683. mic1_mux_text);
  684. static const struct snd_kcontrol_new max98090_mic1_mux =
  685. SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
  686. static const char *mic2_mux_text[] = { "IN34", "IN56" };
  687. static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
  688. M98090_REG_INPUT_MODE,
  689. M98090_EXTMIC2_SHIFT,
  690. mic2_mux_text);
  691. static const struct snd_kcontrol_new max98090_mic2_mux =
  692. SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
  693. static const char *dmic_mux_text[] = { "ADC", "DMIC" };
  694. static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
  695. static const struct snd_kcontrol_new max98090_dmic_mux =
  696. SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
  697. /* LINEA mixer switch */
  698. static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
  699. SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
  700. M98090_IN1SEEN_SHIFT, 1, 0),
  701. SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
  702. M98090_IN3SEEN_SHIFT, 1, 0),
  703. SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
  704. M98090_IN5SEEN_SHIFT, 1, 0),
  705. SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
  706. M98090_IN34DIFF_SHIFT, 1, 0),
  707. };
  708. /* LINEB mixer switch */
  709. static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
  710. SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
  711. M98090_IN2SEEN_SHIFT, 1, 0),
  712. SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
  713. M98090_IN4SEEN_SHIFT, 1, 0),
  714. SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
  715. M98090_IN6SEEN_SHIFT, 1, 0),
  716. SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
  717. M98090_IN56DIFF_SHIFT, 1, 0),
  718. };
  719. /* Left ADC mixer switch */
  720. static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
  721. SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
  722. M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
  723. SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
  724. M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
  725. SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
  726. M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
  727. SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
  728. M98090_MIXADL_LINEA_SHIFT, 1, 0),
  729. SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
  730. M98090_MIXADL_LINEB_SHIFT, 1, 0),
  731. SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
  732. M98090_MIXADL_MIC1_SHIFT, 1, 0),
  733. SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
  734. M98090_MIXADL_MIC2_SHIFT, 1, 0),
  735. };
  736. /* Right ADC mixer switch */
  737. static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
  738. SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
  739. M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
  740. SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
  741. M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
  742. SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
  743. M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
  744. SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
  745. M98090_MIXADR_LINEA_SHIFT, 1, 0),
  746. SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
  747. M98090_MIXADR_LINEB_SHIFT, 1, 0),
  748. SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
  749. M98090_MIXADR_MIC1_SHIFT, 1, 0),
  750. SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
  751. M98090_MIXADR_MIC2_SHIFT, 1, 0),
  752. };
  753. static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
  754. static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
  755. M98090_REG_IO_CONFIGURATION,
  756. M98090_LTEN_SHIFT,
  757. lten_mux_text);
  758. static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
  759. M98090_REG_IO_CONFIGURATION,
  760. M98090_LTEN_SHIFT,
  761. lten_mux_text);
  762. static const struct snd_kcontrol_new max98090_ltenl_mux =
  763. SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
  764. static const struct snd_kcontrol_new max98090_ltenr_mux =
  765. SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
  766. static const char *lben_mux_text[] = { "Normal", "Loopback" };
  767. static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
  768. M98090_REG_IO_CONFIGURATION,
  769. M98090_LBEN_SHIFT,
  770. lben_mux_text);
  771. static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
  772. M98090_REG_IO_CONFIGURATION,
  773. M98090_LBEN_SHIFT,
  774. lben_mux_text);
  775. static const struct snd_kcontrol_new max98090_lbenl_mux =
  776. SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
  777. static const struct snd_kcontrol_new max98090_lbenr_mux =
  778. SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
  779. static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
  780. static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
  781. static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
  782. M98090_REG_ADC_SIDETONE,
  783. M98090_DSTSL_SHIFT,
  784. stenl_mux_text);
  785. static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
  786. M98090_REG_ADC_SIDETONE,
  787. M98090_DSTSR_SHIFT,
  788. stenr_mux_text);
  789. static const struct snd_kcontrol_new max98090_stenl_mux =
  790. SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
  791. static const struct snd_kcontrol_new max98090_stenr_mux =
  792. SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
  793. /* Left speaker mixer switch */
  794. static const struct
  795. snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
  796. SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
  797. M98090_MIXSPL_DACL_SHIFT, 1, 0),
  798. SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
  799. M98090_MIXSPL_DACR_SHIFT, 1, 0),
  800. SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
  801. M98090_MIXSPL_LINEA_SHIFT, 1, 0),
  802. SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
  803. M98090_MIXSPL_LINEB_SHIFT, 1, 0),
  804. SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
  805. M98090_MIXSPL_MIC1_SHIFT, 1, 0),
  806. SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
  807. M98090_MIXSPL_MIC2_SHIFT, 1, 0),
  808. };
  809. /* Right speaker mixer switch */
  810. static const struct
  811. snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
  812. SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
  813. M98090_MIXSPR_DACL_SHIFT, 1, 0),
  814. SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
  815. M98090_MIXSPR_DACR_SHIFT, 1, 0),
  816. SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
  817. M98090_MIXSPR_LINEA_SHIFT, 1, 0),
  818. SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
  819. M98090_MIXSPR_LINEB_SHIFT, 1, 0),
  820. SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
  821. M98090_MIXSPR_MIC1_SHIFT, 1, 0),
  822. SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
  823. M98090_MIXSPR_MIC2_SHIFT, 1, 0),
  824. };
  825. /* Left headphone mixer switch */
  826. static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
  827. SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
  828. M98090_MIXHPL_DACL_SHIFT, 1, 0),
  829. SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
  830. M98090_MIXHPL_DACR_SHIFT, 1, 0),
  831. SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
  832. M98090_MIXHPL_LINEA_SHIFT, 1, 0),
  833. SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
  834. M98090_MIXHPL_LINEB_SHIFT, 1, 0),
  835. SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
  836. M98090_MIXHPL_MIC1_SHIFT, 1, 0),
  837. SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
  838. M98090_MIXHPL_MIC2_SHIFT, 1, 0),
  839. };
  840. /* Right headphone mixer switch */
  841. static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
  842. SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
  843. M98090_MIXHPR_DACL_SHIFT, 1, 0),
  844. SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
  845. M98090_MIXHPR_DACR_SHIFT, 1, 0),
  846. SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
  847. M98090_MIXHPR_LINEA_SHIFT, 1, 0),
  848. SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
  849. M98090_MIXHPR_LINEB_SHIFT, 1, 0),
  850. SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
  851. M98090_MIXHPR_MIC1_SHIFT, 1, 0),
  852. SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
  853. M98090_MIXHPR_MIC2_SHIFT, 1, 0),
  854. };
  855. /* Left receiver mixer switch */
  856. static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
  857. SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
  858. M98090_MIXRCVL_DACL_SHIFT, 1, 0),
  859. SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
  860. M98090_MIXRCVL_DACR_SHIFT, 1, 0),
  861. SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
  862. M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
  863. SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
  864. M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
  865. SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
  866. M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
  867. SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
  868. M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
  869. };
  870. /* Right receiver mixer switch */
  871. static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
  872. SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
  873. M98090_MIXRCVR_DACL_SHIFT, 1, 0),
  874. SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
  875. M98090_MIXRCVR_DACR_SHIFT, 1, 0),
  876. SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
  877. M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
  878. SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
  879. M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
  880. SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
  881. M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
  882. SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
  883. M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
  884. };
  885. static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
  886. static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
  887. M98090_REG_LOUTR_MIXER,
  888. M98090_LINMOD_SHIFT,
  889. linmod_mux_text);
  890. static const struct snd_kcontrol_new max98090_linmod_mux =
  891. SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
  892. static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
  893. /*
  894. * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
  895. */
  896. static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
  897. M98090_REG_HP_CONTROL,
  898. M98090_MIXHPLSEL_SHIFT,
  899. mixhpsel_mux_text);
  900. static const struct snd_kcontrol_new max98090_mixhplsel_mux =
  901. SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
  902. static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
  903. M98090_REG_HP_CONTROL,
  904. M98090_MIXHPRSEL_SHIFT,
  905. mixhpsel_mux_text);
  906. static const struct snd_kcontrol_new max98090_mixhprsel_mux =
  907. SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
  908. static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
  909. SND_SOC_DAPM_INPUT("MIC1"),
  910. SND_SOC_DAPM_INPUT("MIC2"),
  911. SND_SOC_DAPM_INPUT("DMICL"),
  912. SND_SOC_DAPM_INPUT("DMICR"),
  913. SND_SOC_DAPM_INPUT("IN1"),
  914. SND_SOC_DAPM_INPUT("IN2"),
  915. SND_SOC_DAPM_INPUT("IN3"),
  916. SND_SOC_DAPM_INPUT("IN4"),
  917. SND_SOC_DAPM_INPUT("IN5"),
  918. SND_SOC_DAPM_INPUT("IN6"),
  919. SND_SOC_DAPM_INPUT("IN12"),
  920. SND_SOC_DAPM_INPUT("IN34"),
  921. SND_SOC_DAPM_INPUT("IN56"),
  922. SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
  923. M98090_MBEN_SHIFT, 0, NULL, 0),
  924. SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
  925. M98090_SHDNN_SHIFT, 0, NULL, 0),
  926. SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
  927. M98090_SDIEN_SHIFT, 0, NULL, 0),
  928. SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
  929. M98090_SDOEN_SHIFT, 0, NULL, 0),
  930. SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
  931. M98090_DIGMICL_SHIFT, 0, max98090_shdn_event,
  932. SND_SOC_DAPM_POST_PMU),
  933. SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
  934. M98090_DIGMICR_SHIFT, 0, max98090_shdn_event,
  935. SND_SOC_DAPM_POST_PMU),
  936. SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
  937. M98090_AHPF_SHIFT, 0, NULL, 0),
  938. /*
  939. * Note: Sysclk and misc power supplies are taken care of by SHDN
  940. */
  941. SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
  942. 0, 0, &max98090_mic1_mux),
  943. SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
  944. 0, 0, &max98090_mic2_mux),
  945. SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
  946. SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
  947. M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
  948. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  949. SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
  950. M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
  951. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  952. SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
  953. &max98090_linea_mixer_controls[0],
  954. ARRAY_SIZE(max98090_linea_mixer_controls)),
  955. SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
  956. &max98090_lineb_mixer_controls[0],
  957. ARRAY_SIZE(max98090_lineb_mixer_controls)),
  958. SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
  959. M98090_LINEAEN_SHIFT, 0, NULL, 0),
  960. SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
  961. M98090_LINEBEN_SHIFT, 0, NULL, 0),
  962. SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
  963. &max98090_left_adc_mixer_controls[0],
  964. ARRAY_SIZE(max98090_left_adc_mixer_controls)),
  965. SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
  966. &max98090_right_adc_mixer_controls[0],
  967. ARRAY_SIZE(max98090_right_adc_mixer_controls)),
  968. SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
  969. M98090_ADLEN_SHIFT, 0, max98090_shdn_event,
  970. SND_SOC_DAPM_POST_PMU),
  971. SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
  972. M98090_ADREN_SHIFT, 0, max98090_shdn_event,
  973. SND_SOC_DAPM_POST_PMU),
  974. SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
  975. SND_SOC_NOPM, 0, 0),
  976. SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
  977. SND_SOC_NOPM, 0, 0),
  978. SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
  979. 0, 0, &max98090_lbenl_mux),
  980. SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
  981. 0, 0, &max98090_lbenr_mux),
  982. SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
  983. 0, 0, &max98090_ltenl_mux),
  984. SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
  985. 0, 0, &max98090_ltenr_mux),
  986. SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
  987. 0, 0, &max98090_stenl_mux),
  988. SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
  989. 0, 0, &max98090_stenr_mux),
  990. SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
  991. SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
  992. SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
  993. M98090_DALEN_SHIFT, 0),
  994. SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
  995. M98090_DAREN_SHIFT, 0),
  996. SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
  997. &max98090_left_hp_mixer_controls[0],
  998. ARRAY_SIZE(max98090_left_hp_mixer_controls)),
  999. SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
  1000. &max98090_right_hp_mixer_controls[0],
  1001. ARRAY_SIZE(max98090_right_hp_mixer_controls)),
  1002. SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
  1003. &max98090_left_speaker_mixer_controls[0],
  1004. ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
  1005. SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
  1006. &max98090_right_speaker_mixer_controls[0],
  1007. ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
  1008. SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
  1009. &max98090_left_rcv_mixer_controls[0],
  1010. ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
  1011. SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
  1012. &max98090_right_rcv_mixer_controls[0],
  1013. ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
  1014. SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0,
  1015. &max98090_linmod_mux),
  1016. SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0,
  1017. &max98090_mixhplsel_mux),
  1018. SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0,
  1019. &max98090_mixhprsel_mux),
  1020. SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
  1021. M98090_HPLEN_SHIFT, 0, NULL, 0),
  1022. SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
  1023. M98090_HPREN_SHIFT, 0, NULL, 0),
  1024. SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
  1025. M98090_SPLEN_SHIFT, 0, NULL, 0),
  1026. SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
  1027. M98090_SPREN_SHIFT, 0, NULL, 0),
  1028. SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
  1029. M98090_RCVLEN_SHIFT, 0, NULL, 0),
  1030. SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
  1031. M98090_RCVREN_SHIFT, 0, NULL, 0),
  1032. SND_SOC_DAPM_OUTPUT("HPL"),
  1033. SND_SOC_DAPM_OUTPUT("HPR"),
  1034. SND_SOC_DAPM_OUTPUT("SPKL"),
  1035. SND_SOC_DAPM_OUTPUT("SPKR"),
  1036. SND_SOC_DAPM_OUTPUT("RCVL"),
  1037. SND_SOC_DAPM_OUTPUT("RCVR"),
  1038. };
  1039. static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
  1040. SND_SOC_DAPM_INPUT("DMIC3"),
  1041. SND_SOC_DAPM_INPUT("DMIC4"),
  1042. SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
  1043. M98090_DIGMIC3_SHIFT, 0, NULL, 0),
  1044. SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
  1045. M98090_DIGMIC4_SHIFT, 0, NULL, 0),
  1046. };
  1047. static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
  1048. {"MIC1 Input", NULL, "MIC1"},
  1049. {"MIC2 Input", NULL, "MIC2"},
  1050. {"DMICL", NULL, "DMICL_ENA"},
  1051. {"DMICL", NULL, "DMICR_ENA"},
  1052. {"DMICR", NULL, "DMICL_ENA"},
  1053. {"DMICR", NULL, "DMICR_ENA"},
  1054. {"DMICL", NULL, "AHPF"},
  1055. {"DMICR", NULL, "AHPF"},
  1056. /* MIC1 input mux */
  1057. {"MIC1 Mux", "IN12", "IN12"},
  1058. {"MIC1 Mux", "IN56", "IN56"},
  1059. /* MIC2 input mux */
  1060. {"MIC2 Mux", "IN34", "IN34"},
  1061. {"MIC2 Mux", "IN56", "IN56"},
  1062. {"MIC1 Input", NULL, "MIC1 Mux"},
  1063. {"MIC2 Input", NULL, "MIC2 Mux"},
  1064. /* Left ADC input mixer */
  1065. {"Left ADC Mixer", "IN12 Switch", "IN12"},
  1066. {"Left ADC Mixer", "IN34 Switch", "IN34"},
  1067. {"Left ADC Mixer", "IN56 Switch", "IN56"},
  1068. {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
  1069. {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
  1070. {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
  1071. {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
  1072. /* Right ADC input mixer */
  1073. {"Right ADC Mixer", "IN12 Switch", "IN12"},
  1074. {"Right ADC Mixer", "IN34 Switch", "IN34"},
  1075. {"Right ADC Mixer", "IN56 Switch", "IN56"},
  1076. {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
  1077. {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
  1078. {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
  1079. {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
  1080. /* Line A input mixer */
  1081. {"LINEA Mixer", "IN1 Switch", "IN1"},
  1082. {"LINEA Mixer", "IN3 Switch", "IN3"},
  1083. {"LINEA Mixer", "IN5 Switch", "IN5"},
  1084. {"LINEA Mixer", "IN34 Switch", "IN34"},
  1085. /* Line B input mixer */
  1086. {"LINEB Mixer", "IN2 Switch", "IN2"},
  1087. {"LINEB Mixer", "IN4 Switch", "IN4"},
  1088. {"LINEB Mixer", "IN6 Switch", "IN6"},
  1089. {"LINEB Mixer", "IN56 Switch", "IN56"},
  1090. {"LINEA Input", NULL, "LINEA Mixer"},
  1091. {"LINEB Input", NULL, "LINEB Mixer"},
  1092. /* Inputs */
  1093. {"ADCL", NULL, "Left ADC Mixer"},
  1094. {"ADCR", NULL, "Right ADC Mixer"},
  1095. {"ADCL", NULL, "SHDN"},
  1096. {"ADCR", NULL, "SHDN"},
  1097. {"DMIC Mux", "ADC", "ADCL"},
  1098. {"DMIC Mux", "ADC", "ADCR"},
  1099. {"DMIC Mux", "DMIC", "DMICL"},
  1100. {"DMIC Mux", "DMIC", "DMICR"},
  1101. {"LBENL Mux", "Normal", "DMIC Mux"},
  1102. {"LBENL Mux", "Loopback", "LTENL Mux"},
  1103. {"LBENR Mux", "Normal", "DMIC Mux"},
  1104. {"LBENR Mux", "Loopback", "LTENR Mux"},
  1105. {"AIFOUTL", NULL, "LBENL Mux"},
  1106. {"AIFOUTR", NULL, "LBENR Mux"},
  1107. {"AIFOUTL", NULL, "SHDN"},
  1108. {"AIFOUTR", NULL, "SHDN"},
  1109. {"AIFOUTL", NULL, "SDOEN"},
  1110. {"AIFOUTR", NULL, "SDOEN"},
  1111. {"LTENL Mux", "Normal", "AIFINL"},
  1112. {"LTENL Mux", "Loopthrough", "LBENL Mux"},
  1113. {"LTENR Mux", "Normal", "AIFINR"},
  1114. {"LTENR Mux", "Loopthrough", "LBENR Mux"},
  1115. {"DACL", NULL, "LTENL Mux"},
  1116. {"DACR", NULL, "LTENR Mux"},
  1117. {"STENL Mux", "Sidetone Left", "ADCL"},
  1118. {"STENL Mux", "Sidetone Left", "DMICL"},
  1119. {"STENR Mux", "Sidetone Right", "ADCR"},
  1120. {"STENR Mux", "Sidetone Right", "DMICR"},
  1121. {"DACL", NULL, "STENL Mux"},
  1122. {"DACR", NULL, "STENR Mux"},
  1123. {"AIFINL", NULL, "SHDN"},
  1124. {"AIFINR", NULL, "SHDN"},
  1125. {"AIFINL", NULL, "SDIEN"},
  1126. {"AIFINR", NULL, "SDIEN"},
  1127. {"DACL", NULL, "SHDN"},
  1128. {"DACR", NULL, "SHDN"},
  1129. /* Left headphone output mixer */
  1130. {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
  1131. {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
  1132. {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
  1133. {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
  1134. {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
  1135. {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
  1136. /* Right headphone output mixer */
  1137. {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
  1138. {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
  1139. {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
  1140. {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
  1141. {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
  1142. {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
  1143. /* Left speaker output mixer */
  1144. {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
  1145. {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
  1146. {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
  1147. {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
  1148. {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
  1149. {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
  1150. /* Right speaker output mixer */
  1151. {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
  1152. {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
  1153. {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
  1154. {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
  1155. {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
  1156. {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
  1157. /* Left Receiver output mixer */
  1158. {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
  1159. {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
  1160. {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
  1161. {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
  1162. {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
  1163. {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
  1164. /* Right Receiver output mixer */
  1165. {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
  1166. {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
  1167. {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
  1168. {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
  1169. {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
  1170. {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
  1171. {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
  1172. /*
  1173. * Disable this for lowest power if bypassing
  1174. * the DAC with an analog signal
  1175. */
  1176. {"HP Left Out", NULL, "DACL"},
  1177. {"HP Left Out", NULL, "MIXHPLSEL Mux"},
  1178. {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
  1179. /*
  1180. * Disable this for lowest power if bypassing
  1181. * the DAC with an analog signal
  1182. */
  1183. {"HP Right Out", NULL, "DACR"},
  1184. {"HP Right Out", NULL, "MIXHPRSEL Mux"},
  1185. {"SPK Left Out", NULL, "Left Speaker Mixer"},
  1186. {"SPK Right Out", NULL, "Right Speaker Mixer"},
  1187. {"RCV Left Out", NULL, "Left Receiver Mixer"},
  1188. {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
  1189. {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
  1190. {"RCV Right Out", NULL, "LINMOD Mux"},
  1191. {"HPL", NULL, "HP Left Out"},
  1192. {"HPR", NULL, "HP Right Out"},
  1193. {"SPKL", NULL, "SPK Left Out"},
  1194. {"SPKR", NULL, "SPK Right Out"},
  1195. {"RCVL", NULL, "RCV Left Out"},
  1196. {"RCVR", NULL, "RCV Right Out"},
  1197. };
  1198. static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
  1199. /* DMIC inputs */
  1200. {"DMIC3", NULL, "DMIC3_ENA"},
  1201. {"DMIC4", NULL, "DMIC4_ENA"},
  1202. {"DMIC3", NULL, "AHPF"},
  1203. {"DMIC4", NULL, "AHPF"},
  1204. };
  1205. static int max98090_add_widgets(struct snd_soc_component *component)
  1206. {
  1207. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  1208. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  1209. snd_soc_add_component_controls(component, max98090_snd_controls,
  1210. ARRAY_SIZE(max98090_snd_controls));
  1211. if (max98090->devtype == MAX98091) {
  1212. snd_soc_add_component_controls(component, max98091_snd_controls,
  1213. ARRAY_SIZE(max98091_snd_controls));
  1214. }
  1215. snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
  1216. ARRAY_SIZE(max98090_dapm_widgets));
  1217. snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
  1218. ARRAY_SIZE(max98090_dapm_routes));
  1219. if (max98090->devtype == MAX98091) {
  1220. snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
  1221. ARRAY_SIZE(max98091_dapm_widgets));
  1222. snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
  1223. ARRAY_SIZE(max98091_dapm_routes));
  1224. }
  1225. return 0;
  1226. }
  1227. static const int pclk_rates[] = {
  1228. 12000000, 12000000, 13000000, 13000000,
  1229. 16000000, 16000000, 19200000, 19200000
  1230. };
  1231. static const int lrclk_rates[] = {
  1232. 8000, 16000, 8000, 16000,
  1233. 8000, 16000, 8000, 16000
  1234. };
  1235. static const int user_pclk_rates[] = {
  1236. 13000000, 13000000, 19200000, 19200000,
  1237. };
  1238. static const int user_lrclk_rates[] = {
  1239. 44100, 48000, 44100, 48000,
  1240. };
  1241. static const unsigned long long ni_value[] = {
  1242. 3528, 768, 441, 8
  1243. };
  1244. static const unsigned long long mi_value[] = {
  1245. 8125, 1625, 1500, 25
  1246. };
  1247. static void max98090_configure_bclk(struct snd_soc_component *component)
  1248. {
  1249. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  1250. unsigned long long ni;
  1251. int i;
  1252. if (!max98090->sysclk) {
  1253. dev_err(component->dev, "No SYSCLK configured\n");
  1254. return;
  1255. }
  1256. if (!max98090->bclk || !max98090->lrclk) {
  1257. dev_err(component->dev, "No audio clocks configured\n");
  1258. return;
  1259. }
  1260. /* Skip configuration when operating as slave */
  1261. if (!(snd_soc_component_read(component, M98090_REG_MASTER_MODE) &
  1262. M98090_MAS_MASK)) {
  1263. return;
  1264. }
  1265. /* Check for supported PCLK to LRCLK ratios */
  1266. for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
  1267. if ((pclk_rates[i] == max98090->sysclk) &&
  1268. (lrclk_rates[i] == max98090->lrclk)) {
  1269. dev_dbg(component->dev,
  1270. "Found supported PCLK to LRCLK rates 0x%x\n",
  1271. i + 0x8);
  1272. snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
  1273. M98090_FREQ_MASK,
  1274. (i + 0x8) << M98090_FREQ_SHIFT);
  1275. snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
  1276. M98090_USE_M1_MASK, 0);
  1277. return;
  1278. }
  1279. }
  1280. /* Check for user calculated MI and NI ratios */
  1281. for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
  1282. if ((user_pclk_rates[i] == max98090->sysclk) &&
  1283. (user_lrclk_rates[i] == max98090->lrclk)) {
  1284. dev_dbg(component->dev,
  1285. "Found user supported PCLK to LRCLK rates\n");
  1286. dev_dbg(component->dev, "i %d ni %lld mi %lld\n",
  1287. i, ni_value[i], mi_value[i]);
  1288. snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
  1289. M98090_FREQ_MASK, 0);
  1290. snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
  1291. M98090_USE_M1_MASK,
  1292. 1 << M98090_USE_M1_SHIFT);
  1293. snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
  1294. (ni_value[i] >> 8) & 0x7F);
  1295. snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB,
  1296. ni_value[i] & 0xFF);
  1297. snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB,
  1298. (mi_value[i] >> 8) & 0x7F);
  1299. snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB,
  1300. mi_value[i] & 0xFF);
  1301. return;
  1302. }
  1303. }
  1304. /*
  1305. * Calculate based on MI = 65536 (not as good as either method above)
  1306. */
  1307. snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
  1308. M98090_FREQ_MASK, 0);
  1309. snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
  1310. M98090_USE_M1_MASK, 0);
  1311. /*
  1312. * Configure NI when operating as master
  1313. * Note: There is a small, but significant audio quality improvement
  1314. * by calculating ni and mi.
  1315. */
  1316. ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
  1317. * (unsigned long long int)max98090->lrclk;
  1318. do_div(ni, (unsigned long long int)max98090->sysclk);
  1319. dev_info(component->dev, "No better method found\n");
  1320. dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni);
  1321. snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
  1322. (ni >> 8) & 0x7F);
  1323. snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
  1324. }
  1325. static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
  1326. unsigned int fmt)
  1327. {
  1328. struct snd_soc_component *component = codec_dai->component;
  1329. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  1330. struct max98090_cdata *cdata;
  1331. u8 regval;
  1332. max98090->dai_fmt = fmt;
  1333. cdata = &max98090->dai[0];
  1334. if (fmt != cdata->fmt) {
  1335. cdata->fmt = fmt;
  1336. regval = 0;
  1337. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1338. case SND_SOC_DAIFMT_CBS_CFS:
  1339. /* Set to slave mode PLL - MAS mode off */
  1340. snd_soc_component_write(component,
  1341. M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
  1342. snd_soc_component_write(component,
  1343. M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
  1344. snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
  1345. M98090_USE_M1_MASK, 0);
  1346. max98090->master = false;
  1347. break;
  1348. case SND_SOC_DAIFMT_CBM_CFM:
  1349. /* Set to master mode */
  1350. if (max98090->tdm_slots == 4) {
  1351. /* TDM */
  1352. regval |= M98090_MAS_MASK |
  1353. M98090_BSEL_64;
  1354. } else if (max98090->tdm_slots == 3) {
  1355. /* TDM */
  1356. regval |= M98090_MAS_MASK |
  1357. M98090_BSEL_48;
  1358. } else {
  1359. /* Few TDM slots, or No TDM */
  1360. regval |= M98090_MAS_MASK |
  1361. M98090_BSEL_32;
  1362. }
  1363. max98090->master = true;
  1364. break;
  1365. case SND_SOC_DAIFMT_CBS_CFM:
  1366. case SND_SOC_DAIFMT_CBM_CFS:
  1367. default:
  1368. dev_err(component->dev, "DAI clock mode unsupported");
  1369. return -EINVAL;
  1370. }
  1371. snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval);
  1372. regval = 0;
  1373. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1374. case SND_SOC_DAIFMT_I2S:
  1375. regval |= M98090_DLY_MASK;
  1376. break;
  1377. case SND_SOC_DAIFMT_LEFT_J:
  1378. break;
  1379. case SND_SOC_DAIFMT_RIGHT_J:
  1380. regval |= M98090_RJ_MASK;
  1381. break;
  1382. case SND_SOC_DAIFMT_DSP_A:
  1383. /* Not supported mode */
  1384. default:
  1385. dev_err(component->dev, "DAI format unsupported");
  1386. return -EINVAL;
  1387. }
  1388. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1389. case SND_SOC_DAIFMT_NB_NF:
  1390. break;
  1391. case SND_SOC_DAIFMT_NB_IF:
  1392. regval |= M98090_WCI_MASK;
  1393. break;
  1394. case SND_SOC_DAIFMT_IB_NF:
  1395. regval |= M98090_BCI_MASK;
  1396. break;
  1397. case SND_SOC_DAIFMT_IB_IF:
  1398. regval |= M98090_BCI_MASK|M98090_WCI_MASK;
  1399. break;
  1400. default:
  1401. dev_err(component->dev, "DAI invert mode unsupported");
  1402. return -EINVAL;
  1403. }
  1404. /*
  1405. * This accommodates an inverted logic in the MAX98090 chip
  1406. * for Bit Clock Invert (BCI). The inverted logic is only
  1407. * seen for the case of TDM mode. The remaining cases have
  1408. * normal logic.
  1409. */
  1410. if (max98090->tdm_slots > 1)
  1411. regval ^= M98090_BCI_MASK;
  1412. snd_soc_component_write(component,
  1413. M98090_REG_INTERFACE_FORMAT, regval);
  1414. }
  1415. return 0;
  1416. }
  1417. static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
  1418. unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
  1419. {
  1420. struct snd_soc_component *component = codec_dai->component;
  1421. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  1422. struct max98090_cdata *cdata;
  1423. cdata = &max98090->dai[0];
  1424. if (slots < 0 || slots > 4)
  1425. return -EINVAL;
  1426. max98090->tdm_slots = slots;
  1427. max98090->tdm_width = slot_width;
  1428. if (max98090->tdm_slots > 1) {
  1429. /* SLOTL SLOTR SLOTDLY */
  1430. snd_soc_component_write(component, M98090_REG_TDM_FORMAT,
  1431. 0 << M98090_TDM_SLOTL_SHIFT |
  1432. 1 << M98090_TDM_SLOTR_SHIFT |
  1433. 0 << M98090_TDM_SLOTDLY_SHIFT);
  1434. /* FSW TDM */
  1435. snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL,
  1436. M98090_TDM_MASK,
  1437. M98090_TDM_MASK);
  1438. }
  1439. /*
  1440. * Normally advisable to set TDM first, but this permits either order
  1441. */
  1442. cdata->fmt = 0;
  1443. max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
  1444. return 0;
  1445. }
  1446. static int max98090_set_bias_level(struct snd_soc_component *component,
  1447. enum snd_soc_bias_level level)
  1448. {
  1449. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  1450. int ret;
  1451. switch (level) {
  1452. case SND_SOC_BIAS_ON:
  1453. break;
  1454. case SND_SOC_BIAS_PREPARE:
  1455. /*
  1456. * SND_SOC_BIAS_PREPARE is called while preparing for a
  1457. * transition to ON or away from ON. If current bias_level
  1458. * is SND_SOC_BIAS_ON, then it is preparing for a transition
  1459. * away from ON. Disable the clock in that case, otherwise
  1460. * enable it.
  1461. */
  1462. if (IS_ERR(max98090->mclk))
  1463. break;
  1464. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
  1465. clk_disable_unprepare(max98090->mclk);
  1466. } else {
  1467. ret = clk_prepare_enable(max98090->mclk);
  1468. if (ret)
  1469. return ret;
  1470. }
  1471. break;
  1472. case SND_SOC_BIAS_STANDBY:
  1473. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  1474. ret = regcache_sync(max98090->regmap);
  1475. if (ret != 0) {
  1476. dev_err(component->dev,
  1477. "Failed to sync cache: %d\n", ret);
  1478. return ret;
  1479. }
  1480. }
  1481. break;
  1482. case SND_SOC_BIAS_OFF:
  1483. /* Set internal pull-up to lowest power mode */
  1484. snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
  1485. M98090_JDWK_MASK, M98090_JDWK_MASK);
  1486. regcache_mark_dirty(max98090->regmap);
  1487. break;
  1488. }
  1489. return 0;
  1490. }
  1491. static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
  1492. static const int comp_lrclk_rates[] = {
  1493. 8000, 16000, 32000, 44100, 48000, 96000
  1494. };
  1495. struct dmic_table {
  1496. int pclk;
  1497. struct {
  1498. int freq;
  1499. int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
  1500. } settings[6]; /* One for each dmic divisor. */
  1501. };
  1502. static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
  1503. {
  1504. .pclk = 11289600,
  1505. .settings = {
  1506. { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
  1507. { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
  1508. { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
  1509. { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
  1510. { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
  1511. { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
  1512. },
  1513. },
  1514. {
  1515. .pclk = 12000000,
  1516. .settings = {
  1517. { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
  1518. { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
  1519. { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
  1520. { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
  1521. { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
  1522. { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
  1523. }
  1524. },
  1525. {
  1526. .pclk = 12288000,
  1527. .settings = {
  1528. { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
  1529. { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
  1530. { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
  1531. { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
  1532. { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
  1533. { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
  1534. }
  1535. },
  1536. {
  1537. .pclk = 13000000,
  1538. .settings = {
  1539. { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
  1540. { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
  1541. { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
  1542. { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
  1543. { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
  1544. { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
  1545. }
  1546. },
  1547. {
  1548. .pclk = 19200000,
  1549. .settings = {
  1550. { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
  1551. { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
  1552. { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
  1553. { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
  1554. { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
  1555. { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
  1556. }
  1557. },
  1558. };
  1559. static int max98090_find_divisor(int target_freq, int pclk)
  1560. {
  1561. int current_diff = INT_MAX;
  1562. int test_diff = INT_MAX;
  1563. int divisor_index = 0;
  1564. int i;
  1565. for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
  1566. test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
  1567. if (test_diff < current_diff) {
  1568. current_diff = test_diff;
  1569. divisor_index = i;
  1570. }
  1571. }
  1572. return divisor_index;
  1573. }
  1574. static int max98090_find_closest_pclk(int pclk)
  1575. {
  1576. int m1;
  1577. int m2;
  1578. int i;
  1579. for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
  1580. if (pclk == dmic_table[i].pclk)
  1581. return i;
  1582. if (pclk < dmic_table[i].pclk) {
  1583. if (i == 0)
  1584. return i;
  1585. m1 = pclk - dmic_table[i-1].pclk;
  1586. m2 = dmic_table[i].pclk - pclk;
  1587. if (m1 < m2)
  1588. return i - 1;
  1589. else
  1590. return i;
  1591. }
  1592. }
  1593. return -EINVAL;
  1594. }
  1595. static int max98090_configure_dmic(struct max98090_priv *max98090,
  1596. int target_dmic_clk, int pclk, int fs)
  1597. {
  1598. int micclk_index;
  1599. int pclk_index;
  1600. int dmic_freq;
  1601. int dmic_comp;
  1602. int i;
  1603. pclk_index = max98090_find_closest_pclk(pclk);
  1604. if (pclk_index < 0)
  1605. return pclk_index;
  1606. micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
  1607. for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
  1608. if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
  1609. break;
  1610. }
  1611. dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
  1612. dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
  1613. regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
  1614. M98090_MICCLK_MASK,
  1615. micclk_index << M98090_MICCLK_SHIFT);
  1616. regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
  1617. M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
  1618. dmic_comp << M98090_DMIC_COMP_SHIFT |
  1619. dmic_freq << M98090_DMIC_FREQ_SHIFT);
  1620. return 0;
  1621. }
  1622. static int max98090_dai_startup(struct snd_pcm_substream *substream,
  1623. struct snd_soc_dai *dai)
  1624. {
  1625. struct snd_soc_component *component = dai->component;
  1626. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  1627. unsigned int fmt = max98090->dai_fmt;
  1628. /* Remove 24-bit format support if it is not in right justified mode. */
  1629. if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) {
  1630. substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
  1631. snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16);
  1632. }
  1633. return 0;
  1634. }
  1635. static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
  1636. struct snd_pcm_hw_params *params,
  1637. struct snd_soc_dai *dai)
  1638. {
  1639. struct snd_soc_component *component = dai->component;
  1640. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  1641. struct max98090_cdata *cdata;
  1642. cdata = &max98090->dai[0];
  1643. max98090->bclk = snd_soc_params_to_bclk(params);
  1644. if (params_channels(params) == 1)
  1645. max98090->bclk *= 2;
  1646. max98090->lrclk = params_rate(params);
  1647. switch (params_width(params)) {
  1648. case 16:
  1649. snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT,
  1650. M98090_WS_MASK, 0);
  1651. break;
  1652. default:
  1653. return -EINVAL;
  1654. }
  1655. if (max98090->master)
  1656. max98090_configure_bclk(component);
  1657. cdata->rate = max98090->lrclk;
  1658. /* Update filter mode */
  1659. if (max98090->lrclk < 24000)
  1660. snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
  1661. M98090_MODE_MASK, 0);
  1662. else
  1663. snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
  1664. M98090_MODE_MASK, M98090_MODE_MASK);
  1665. /* Update sample rate mode */
  1666. if (max98090->lrclk < 50000)
  1667. snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
  1668. M98090_DHF_MASK, 0);
  1669. else
  1670. snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
  1671. M98090_DHF_MASK, M98090_DHF_MASK);
  1672. max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
  1673. max98090->lrclk);
  1674. return 0;
  1675. }
  1676. /*
  1677. * PLL / Sysclk
  1678. */
  1679. static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
  1680. int clk_id, unsigned int freq, int dir)
  1681. {
  1682. struct snd_soc_component *component = dai->component;
  1683. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  1684. /* Requested clock frequency is already setup */
  1685. if (freq == max98090->sysclk)
  1686. return 0;
  1687. if (!IS_ERR(max98090->mclk)) {
  1688. freq = clk_round_rate(max98090->mclk, freq);
  1689. clk_set_rate(max98090->mclk, freq);
  1690. }
  1691. /* Setup clocks for slave mode, and using the PLL
  1692. * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
  1693. * 0x02 (when master clk is 20MHz to 40MHz)..
  1694. * 0x03 (when master clk is 40MHz to 60MHz)..
  1695. */
  1696. if ((freq >= 10000000) && (freq <= 20000000)) {
  1697. snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
  1698. M98090_PSCLK_DIV1);
  1699. max98090->pclk = freq;
  1700. } else if ((freq > 20000000) && (freq <= 40000000)) {
  1701. snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
  1702. M98090_PSCLK_DIV2);
  1703. max98090->pclk = freq >> 1;
  1704. } else if ((freq > 40000000) && (freq <= 60000000)) {
  1705. snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
  1706. M98090_PSCLK_DIV4);
  1707. max98090->pclk = freq >> 2;
  1708. } else {
  1709. dev_err(component->dev, "Invalid master clock frequency\n");
  1710. return -EINVAL;
  1711. }
  1712. max98090->sysclk = freq;
  1713. return 0;
  1714. }
  1715. static int max98090_dai_mute(struct snd_soc_dai *codec_dai, int mute,
  1716. int direction)
  1717. {
  1718. struct snd_soc_component *component = codec_dai->component;
  1719. int regval;
  1720. regval = mute ? M98090_DVM_MASK : 0;
  1721. snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL,
  1722. M98090_DVM_MASK, regval);
  1723. return 0;
  1724. }
  1725. static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  1726. struct snd_soc_dai *dai)
  1727. {
  1728. struct snd_soc_component *component = dai->component;
  1729. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  1730. switch (cmd) {
  1731. case SNDRV_PCM_TRIGGER_START:
  1732. case SNDRV_PCM_TRIGGER_RESUME:
  1733. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1734. if (!max98090->master && snd_soc_dai_active(dai) == 1)
  1735. queue_delayed_work(system_power_efficient_wq,
  1736. &max98090->pll_det_enable_work,
  1737. msecs_to_jiffies(10));
  1738. break;
  1739. case SNDRV_PCM_TRIGGER_STOP:
  1740. case SNDRV_PCM_TRIGGER_SUSPEND:
  1741. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1742. if (!max98090->master && snd_soc_dai_active(dai) == 1)
  1743. schedule_work(&max98090->pll_det_disable_work);
  1744. break;
  1745. default:
  1746. break;
  1747. }
  1748. return 0;
  1749. }
  1750. static void max98090_pll_det_enable_work(struct work_struct *work)
  1751. {
  1752. struct max98090_priv *max98090 =
  1753. container_of(work, struct max98090_priv,
  1754. pll_det_enable_work.work);
  1755. struct snd_soc_component *component = max98090->component;
  1756. unsigned int status, mask;
  1757. /*
  1758. * Clear status register in order to clear possibly already occurred
  1759. * PLL unlock. If PLL hasn't still locked, the status will be set
  1760. * again and PLL unlock interrupt will occur.
  1761. * Note this will clear all status bits
  1762. */
  1763. regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
  1764. /*
  1765. * Queue jack work in case jack state has just changed but handler
  1766. * hasn't run yet
  1767. */
  1768. regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
  1769. status &= mask;
  1770. if (status & M98090_JDET_MASK)
  1771. queue_delayed_work(system_power_efficient_wq,
  1772. &max98090->jack_work,
  1773. msecs_to_jiffies(100));
  1774. /* Enable PLL unlock interrupt */
  1775. snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
  1776. M98090_IULK_MASK,
  1777. 1 << M98090_IULK_SHIFT);
  1778. }
  1779. static void max98090_pll_det_disable_work(struct work_struct *work)
  1780. {
  1781. struct max98090_priv *max98090 =
  1782. container_of(work, struct max98090_priv, pll_det_disable_work);
  1783. struct snd_soc_component *component = max98090->component;
  1784. cancel_delayed_work_sync(&max98090->pll_det_enable_work);
  1785. /* Disable PLL unlock interrupt */
  1786. snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
  1787. M98090_IULK_MASK, 0);
  1788. }
  1789. static void max98090_pll_work(struct max98090_priv *max98090)
  1790. {
  1791. struct snd_soc_component *component = max98090->component;
  1792. unsigned int pll;
  1793. int i;
  1794. if (!snd_soc_component_active(component))
  1795. return;
  1796. dev_info_ratelimited(component->dev, "PLL unlocked\n");
  1797. /*
  1798. * As the datasheet suggested, the maximum PLL lock time should be
  1799. * 7 msec. The workaround resets the codec softly by toggling SHDN
  1800. * off and on if PLL failed to lock for 10 msec. Notably, there is
  1801. * no suggested hold time for SHDN off.
  1802. */
  1803. /* Toggle shutdown OFF then ON */
  1804. snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
  1805. M98090_SHDNN_MASK, 0);
  1806. snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
  1807. M98090_SHDNN_MASK, M98090_SHDNN_MASK);
  1808. for (i = 0; i < 10; ++i) {
  1809. /* Give PLL time to lock */
  1810. usleep_range(1000, 1200);
  1811. /* Check lock status */
  1812. pll = snd_soc_component_read(
  1813. component, M98090_REG_DEVICE_STATUS);
  1814. if (!(pll & M98090_ULK_MASK))
  1815. break;
  1816. }
  1817. }
  1818. static void max98090_jack_work(struct work_struct *work)
  1819. {
  1820. struct max98090_priv *max98090 = container_of(work,
  1821. struct max98090_priv,
  1822. jack_work.work);
  1823. struct snd_soc_component *component = max98090->component;
  1824. int status = 0;
  1825. int reg;
  1826. /* Read a second time */
  1827. if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
  1828. /* Strong pull up allows mic detection */
  1829. snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
  1830. M98090_JDWK_MASK, 0);
  1831. msleep(50);
  1832. reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);
  1833. /* Weak pull up allows only insertion detection */
  1834. snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
  1835. M98090_JDWK_MASK, M98090_JDWK_MASK);
  1836. } else {
  1837. reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);
  1838. }
  1839. reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);
  1840. switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
  1841. case M98090_LSNS_MASK | M98090_JKSNS_MASK:
  1842. dev_dbg(component->dev, "No Headset Detected\n");
  1843. max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
  1844. status |= 0;
  1845. break;
  1846. case 0:
  1847. if (max98090->jack_state ==
  1848. M98090_JACK_STATE_HEADSET) {
  1849. dev_dbg(component->dev,
  1850. "Headset Button Down Detected\n");
  1851. /*
  1852. * max98090_headset_button_event(codec)
  1853. * could be defined, then called here.
  1854. */
  1855. status |= SND_JACK_HEADSET;
  1856. status |= SND_JACK_BTN_0;
  1857. break;
  1858. }
  1859. /* Line is reported as Headphone */
  1860. /* Nokia Headset is reported as Headphone */
  1861. /* Mono Headphone is reported as Headphone */
  1862. dev_dbg(component->dev, "Headphone Detected\n");
  1863. max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
  1864. status |= SND_JACK_HEADPHONE;
  1865. break;
  1866. case M98090_JKSNS_MASK:
  1867. dev_dbg(component->dev, "Headset Detected\n");
  1868. max98090->jack_state = M98090_JACK_STATE_HEADSET;
  1869. status |= SND_JACK_HEADSET;
  1870. break;
  1871. default:
  1872. dev_dbg(component->dev, "Unrecognized Jack Status\n");
  1873. break;
  1874. }
  1875. snd_soc_jack_report(max98090->jack, status,
  1876. SND_JACK_HEADSET | SND_JACK_BTN_0);
  1877. }
  1878. static irqreturn_t max98090_interrupt(int irq, void *data)
  1879. {
  1880. struct max98090_priv *max98090 = data;
  1881. struct snd_soc_component *component = max98090->component;
  1882. int ret;
  1883. unsigned int mask;
  1884. unsigned int active;
  1885. /* Treat interrupt before codec is initialized as spurious */
  1886. if (component == NULL)
  1887. return IRQ_NONE;
  1888. dev_dbg(component->dev, "***** max98090_interrupt *****\n");
  1889. ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
  1890. if (ret != 0) {
  1891. dev_err(component->dev,
  1892. "failed to read M98090_REG_INTERRUPT_S: %d\n",
  1893. ret);
  1894. return IRQ_NONE;
  1895. }
  1896. ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
  1897. if (ret != 0) {
  1898. dev_err(component->dev,
  1899. "failed to read M98090_REG_DEVICE_STATUS: %d\n",
  1900. ret);
  1901. return IRQ_NONE;
  1902. }
  1903. dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
  1904. active, mask, active & mask);
  1905. active &= mask;
  1906. if (!active)
  1907. return IRQ_NONE;
  1908. if (active & M98090_CLD_MASK)
  1909. dev_err(component->dev, "M98090_CLD_MASK\n");
  1910. if (active & M98090_SLD_MASK)
  1911. dev_dbg(component->dev, "M98090_SLD_MASK\n");
  1912. if (active & M98090_ULK_MASK) {
  1913. dev_dbg(component->dev, "M98090_ULK_MASK\n");
  1914. max98090_pll_work(max98090);
  1915. }
  1916. if (active & M98090_JDET_MASK) {
  1917. dev_dbg(component->dev, "M98090_JDET_MASK\n");
  1918. pm_wakeup_event(component->dev, 100);
  1919. queue_delayed_work(system_power_efficient_wq,
  1920. &max98090->jack_work,
  1921. msecs_to_jiffies(100));
  1922. }
  1923. if (active & M98090_DRCACT_MASK)
  1924. dev_dbg(component->dev, "M98090_DRCACT_MASK\n");
  1925. if (active & M98090_DRCCLP_MASK)
  1926. dev_err(component->dev, "M98090_DRCCLP_MASK\n");
  1927. return IRQ_HANDLED;
  1928. }
  1929. /**
  1930. * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
  1931. *
  1932. * @component: MAX98090 component
  1933. * @jack: jack to report detection events on
  1934. *
  1935. * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
  1936. * being used to bring out signals to the processor then only platform
  1937. * data configuration is needed for MAX98090 and processor GPIOs should
  1938. * be configured using snd_soc_jack_add_gpios() instead.
  1939. *
  1940. * If no jack is supplied detection will be disabled.
  1941. */
  1942. int max98090_mic_detect(struct snd_soc_component *component,
  1943. struct snd_soc_jack *jack)
  1944. {
  1945. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  1946. dev_dbg(component->dev, "max98090_mic_detect\n");
  1947. max98090->jack = jack;
  1948. if (jack) {
  1949. snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
  1950. M98090_IJDET_MASK,
  1951. 1 << M98090_IJDET_SHIFT);
  1952. } else {
  1953. snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
  1954. M98090_IJDET_MASK,
  1955. 0);
  1956. }
  1957. /* Send an initial empty report */
  1958. snd_soc_jack_report(max98090->jack, 0,
  1959. SND_JACK_HEADSET | SND_JACK_BTN_0);
  1960. queue_delayed_work(system_power_efficient_wq,
  1961. &max98090->jack_work,
  1962. msecs_to_jiffies(100));
  1963. return 0;
  1964. }
  1965. EXPORT_SYMBOL_GPL(max98090_mic_detect);
  1966. #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
  1967. #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
  1968. static const struct snd_soc_dai_ops max98090_dai_ops = {
  1969. .startup = max98090_dai_startup,
  1970. .set_sysclk = max98090_dai_set_sysclk,
  1971. .set_fmt = max98090_dai_set_fmt,
  1972. .set_tdm_slot = max98090_set_tdm_slot,
  1973. .hw_params = max98090_dai_hw_params,
  1974. .mute_stream = max98090_dai_mute,
  1975. .trigger = max98090_dai_trigger,
  1976. .no_capture_mute = 1,
  1977. };
  1978. static struct snd_soc_dai_driver max98090_dai[] = {
  1979. {
  1980. .name = "HiFi",
  1981. .playback = {
  1982. .stream_name = "HiFi Playback",
  1983. .channels_min = 2,
  1984. .channels_max = 2,
  1985. .rates = MAX98090_RATES,
  1986. .formats = MAX98090_FORMATS,
  1987. },
  1988. .capture = {
  1989. .stream_name = "HiFi Capture",
  1990. .channels_min = 1,
  1991. .channels_max = 2,
  1992. .rates = MAX98090_RATES,
  1993. .formats = MAX98090_FORMATS,
  1994. },
  1995. .ops = &max98090_dai_ops,
  1996. }
  1997. };
  1998. static int max98090_probe(struct snd_soc_component *component)
  1999. {
  2000. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  2001. struct max98090_cdata *cdata;
  2002. enum max98090_type devtype;
  2003. int ret = 0;
  2004. int err;
  2005. unsigned int micbias;
  2006. dev_dbg(component->dev, "max98090_probe\n");
  2007. max98090->mclk = devm_clk_get(component->dev, "mclk");
  2008. if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
  2009. return -EPROBE_DEFER;
  2010. max98090->component = component;
  2011. /* Reset the codec, the DSP core, and disable all interrupts */
  2012. max98090_reset(max98090);
  2013. /* Initialize private data */
  2014. max98090->sysclk = (unsigned)-1;
  2015. max98090->pclk = (unsigned)-1;
  2016. max98090->master = false;
  2017. cdata = &max98090->dai[0];
  2018. cdata->rate = (unsigned)-1;
  2019. cdata->fmt = (unsigned)-1;
  2020. max98090->lin_state = 0;
  2021. max98090->pa1en = 0;
  2022. max98090->pa2en = 0;
  2023. ret = snd_soc_component_read(component, M98090_REG_REVISION_ID);
  2024. if (ret < 0) {
  2025. dev_err(component->dev, "Failed to read device revision: %d\n",
  2026. ret);
  2027. goto err_access;
  2028. }
  2029. if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
  2030. devtype = MAX98090;
  2031. dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret);
  2032. } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
  2033. devtype = MAX98091;
  2034. dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret);
  2035. } else {
  2036. devtype = MAX98090;
  2037. dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret);
  2038. }
  2039. if (max98090->devtype != devtype) {
  2040. dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n");
  2041. max98090->devtype = devtype;
  2042. }
  2043. max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
  2044. INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
  2045. INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
  2046. max98090_pll_det_enable_work);
  2047. INIT_WORK(&max98090->pll_det_disable_work,
  2048. max98090_pll_det_disable_work);
  2049. /* Enable jack detection */
  2050. snd_soc_component_write(component, M98090_REG_JACK_DETECT,
  2051. M98090_JDETEN_MASK | M98090_JDEB_25MS);
  2052. /*
  2053. * Clear any old interrupts.
  2054. * An old interrupt ocurring prior to installing the ISR
  2055. * can keep a new interrupt from generating a trigger.
  2056. */
  2057. snd_soc_component_read(component, M98090_REG_DEVICE_STATUS);
  2058. /* High Performance is default */
  2059. snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
  2060. M98090_DACHP_MASK,
  2061. 1 << M98090_DACHP_SHIFT);
  2062. snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
  2063. M98090_PERFMODE_MASK,
  2064. 0 << M98090_PERFMODE_SHIFT);
  2065. snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL,
  2066. M98090_ADCHP_MASK,
  2067. 1 << M98090_ADCHP_SHIFT);
  2068. /* Turn on VCM bandgap reference */
  2069. snd_soc_component_write(component, M98090_REG_BIAS_CONTROL,
  2070. M98090_VCM_MODE_MASK);
  2071. err = device_property_read_u32(component->dev, "maxim,micbias", &micbias);
  2072. if (err) {
  2073. micbias = M98090_MBVSEL_2V8;
  2074. dev_info(component->dev, "use default 2.8v micbias\n");
  2075. } else if (micbias > M98090_MBVSEL_2V8) {
  2076. dev_err(component->dev, "micbias out of range 0x%x\n", micbias);
  2077. micbias = M98090_MBVSEL_2V8;
  2078. }
  2079. snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE,
  2080. M98090_MBVSEL_MASK, micbias);
  2081. max98090_add_widgets(component);
  2082. err_access:
  2083. return ret;
  2084. }
  2085. static void max98090_remove(struct snd_soc_component *component)
  2086. {
  2087. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  2088. cancel_delayed_work_sync(&max98090->jack_work);
  2089. cancel_delayed_work_sync(&max98090->pll_det_enable_work);
  2090. cancel_work_sync(&max98090->pll_det_disable_work);
  2091. max98090->component = NULL;
  2092. }
  2093. static void max98090_seq_notifier(struct snd_soc_component *component,
  2094. enum snd_soc_dapm_type event, int subseq)
  2095. {
  2096. struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
  2097. if (max98090->shdn_pending) {
  2098. snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
  2099. M98090_SHDNN_MASK, 0);
  2100. msleep(40);
  2101. snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
  2102. M98090_SHDNN_MASK, M98090_SHDNN_MASK);
  2103. max98090->shdn_pending = false;
  2104. }
  2105. }
  2106. static const struct snd_soc_component_driver soc_component_dev_max98090 = {
  2107. .probe = max98090_probe,
  2108. .remove = max98090_remove,
  2109. .seq_notifier = max98090_seq_notifier,
  2110. .set_bias_level = max98090_set_bias_level,
  2111. .idle_bias_on = 1,
  2112. .use_pmdown_time = 1,
  2113. .endianness = 1,
  2114. .non_legacy_dai_naming = 1,
  2115. };
  2116. static const struct regmap_config max98090_regmap = {
  2117. .reg_bits = 8,
  2118. .val_bits = 8,
  2119. .max_register = MAX98090_MAX_REGISTER,
  2120. .reg_defaults = max98090_reg,
  2121. .num_reg_defaults = ARRAY_SIZE(max98090_reg),
  2122. .volatile_reg = max98090_volatile_register,
  2123. .readable_reg = max98090_readable_register,
  2124. .cache_type = REGCACHE_RBTREE,
  2125. };
  2126. static int max98090_i2c_probe(struct i2c_client *i2c,
  2127. const struct i2c_device_id *i2c_id)
  2128. {
  2129. struct max98090_priv *max98090;
  2130. const struct acpi_device_id *acpi_id;
  2131. kernel_ulong_t driver_data = 0;
  2132. int ret;
  2133. pr_debug("max98090_i2c_probe\n");
  2134. max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
  2135. GFP_KERNEL);
  2136. if (max98090 == NULL)
  2137. return -ENOMEM;
  2138. if (ACPI_HANDLE(&i2c->dev)) {
  2139. acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
  2140. &i2c->dev);
  2141. if (!acpi_id) {
  2142. dev_err(&i2c->dev, "No driver data\n");
  2143. return -EINVAL;
  2144. }
  2145. driver_data = acpi_id->driver_data;
  2146. } else if (i2c_id) {
  2147. driver_data = i2c_id->driver_data;
  2148. }
  2149. max98090->devtype = driver_data;
  2150. i2c_set_clientdata(i2c, max98090);
  2151. max98090->pdata = i2c->dev.platform_data;
  2152. ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
  2153. &max98090->dmic_freq);
  2154. if (ret < 0)
  2155. max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
  2156. max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
  2157. if (IS_ERR(max98090->regmap)) {
  2158. ret = PTR_ERR(max98090->regmap);
  2159. dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
  2160. goto err_enable;
  2161. }
  2162. ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
  2163. max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  2164. "max98090_interrupt", max98090);
  2165. if (ret < 0) {
  2166. dev_err(&i2c->dev, "request_irq failed: %d\n",
  2167. ret);
  2168. return ret;
  2169. }
  2170. ret = devm_snd_soc_register_component(&i2c->dev,
  2171. &soc_component_dev_max98090, max98090_dai,
  2172. ARRAY_SIZE(max98090_dai));
  2173. err_enable:
  2174. return ret;
  2175. }
  2176. static void max98090_i2c_shutdown(struct i2c_client *i2c)
  2177. {
  2178. struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
  2179. /*
  2180. * Enable volume smoothing, disable zero cross. This will cause
  2181. * a quick 40ms ramp to mute on shutdown.
  2182. */
  2183. regmap_write(max98090->regmap,
  2184. M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK);
  2185. regmap_write(max98090->regmap,
  2186. M98090_REG_DEVICE_SHUTDOWN, 0x00);
  2187. msleep(40);
  2188. }
  2189. static int max98090_i2c_remove(struct i2c_client *client)
  2190. {
  2191. max98090_i2c_shutdown(client);
  2192. return 0;
  2193. }
  2194. #ifdef CONFIG_PM
  2195. static int max98090_runtime_resume(struct device *dev)
  2196. {
  2197. struct max98090_priv *max98090 = dev_get_drvdata(dev);
  2198. regcache_cache_only(max98090->regmap, false);
  2199. max98090_reset(max98090);
  2200. regcache_sync(max98090->regmap);
  2201. return 0;
  2202. }
  2203. static int max98090_runtime_suspend(struct device *dev)
  2204. {
  2205. struct max98090_priv *max98090 = dev_get_drvdata(dev);
  2206. regcache_cache_only(max98090->regmap, true);
  2207. return 0;
  2208. }
  2209. #endif
  2210. #ifdef CONFIG_PM_SLEEP
  2211. static int max98090_resume(struct device *dev)
  2212. {
  2213. struct max98090_priv *max98090 = dev_get_drvdata(dev);
  2214. unsigned int status;
  2215. regcache_mark_dirty(max98090->regmap);
  2216. max98090_reset(max98090);
  2217. /* clear IRQ status */
  2218. regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
  2219. regcache_sync(max98090->regmap);
  2220. return 0;
  2221. }
  2222. #endif
  2223. static const struct dev_pm_ops max98090_pm = {
  2224. SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
  2225. max98090_runtime_resume, NULL)
  2226. SET_SYSTEM_SLEEP_PM_OPS(NULL, max98090_resume)
  2227. };
  2228. static const struct i2c_device_id max98090_i2c_id[] = {
  2229. { "max98090", MAX98090 },
  2230. { "max98091", MAX98091 },
  2231. { }
  2232. };
  2233. MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
  2234. static const struct of_device_id max98090_of_match[] = {
  2235. { .compatible = "maxim,max98090", },
  2236. { .compatible = "maxim,max98091", },
  2237. { }
  2238. };
  2239. MODULE_DEVICE_TABLE(of, max98090_of_match);
  2240. #ifdef CONFIG_ACPI
  2241. static const struct acpi_device_id max98090_acpi_match[] = {
  2242. { "193C9890", MAX98090 },
  2243. { }
  2244. };
  2245. MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
  2246. #endif
  2247. static struct i2c_driver max98090_i2c_driver = {
  2248. .driver = {
  2249. .name = "max98090",
  2250. .pm = &max98090_pm,
  2251. .of_match_table = of_match_ptr(max98090_of_match),
  2252. .acpi_match_table = ACPI_PTR(max98090_acpi_match),
  2253. },
  2254. .probe = max98090_i2c_probe,
  2255. .shutdown = max98090_i2c_shutdown,
  2256. .remove = max98090_i2c_remove,
  2257. .id_table = max98090_i2c_id,
  2258. };
  2259. module_i2c_driver(max98090_i2c_driver);
  2260. MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
  2261. MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
  2262. MODULE_LICENSE("GPL");