max98088.h 8.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * max98088.h -- MAX98088 ALSA SoC Audio driver
  4. *
  5. * Copyright 2010 Maxim Integrated Products
  6. */
  7. #ifndef _MAX98088_H
  8. #define _MAX98088_H
  9. /*
  10. * MAX98088 Registers Definition
  11. */
  12. #define M98088_REG_00_IRQ_STATUS 0x00
  13. #define M98088_REG_01_MIC_STATUS 0x01
  14. #define M98088_REG_02_JACK_STATUS 0x02
  15. #define M98088_REG_03_BATTERY_VOLTAGE 0x03
  16. #define M98088_REG_0F_IRQ_ENABLE 0x0F
  17. #define M98088_REG_10_SYS_CLK 0x10
  18. #define M98088_REG_11_DAI1_CLKMODE 0x11
  19. #define M98088_REG_12_DAI1_CLKCFG_HI 0x12
  20. #define M98088_REG_13_DAI1_CLKCFG_LO 0x13
  21. #define M98088_REG_14_DAI1_FORMAT 0x14
  22. #define M98088_REG_15_DAI1_CLOCK 0x15
  23. #define M98088_REG_16_DAI1_IOCFG 0x16
  24. #define M98088_REG_17_DAI1_TDM 0x17
  25. #define M98088_REG_18_DAI1_FILTERS 0x18
  26. #define M98088_REG_19_DAI2_CLKMODE 0x19
  27. #define M98088_REG_1A_DAI2_CLKCFG_HI 0x1A
  28. #define M98088_REG_1B_DAI2_CLKCFG_LO 0x1B
  29. #define M98088_REG_1C_DAI2_FORMAT 0x1C
  30. #define M98088_REG_1D_DAI2_CLOCK 0x1D
  31. #define M98088_REG_1E_DAI2_IOCFG 0x1E
  32. #define M98088_REG_1F_DAI2_TDM 0x1F
  33. #define M98088_REG_20_DAI2_FILTERS 0x20
  34. #define M98088_REG_21_SRC 0x21
  35. #define M98088_REG_22_MIX_DAC 0x22
  36. #define M98088_REG_23_MIX_ADC_LEFT 0x23
  37. #define M98088_REG_24_MIX_ADC_RIGHT 0x24
  38. #define M98088_REG_25_MIX_HP_LEFT 0x25
  39. #define M98088_REG_26_MIX_HP_RIGHT 0x26
  40. #define M98088_REG_27_MIX_HP_CNTL 0x27
  41. #define M98088_REG_28_MIX_REC_LEFT 0x28
  42. #define M98088_REG_29_MIX_REC_RIGHT 0x29
  43. #define M98088_REG_2A_MIC_REC_CNTL 0x2A
  44. #define M98088_REG_2B_MIX_SPK_LEFT 0x2B
  45. #define M98088_REG_2C_MIX_SPK_RIGHT 0x2C
  46. #define M98088_REG_2D_MIX_SPK_CNTL 0x2D
  47. #define M98088_REG_2E_LVL_SIDETONE 0x2E
  48. #define M98088_REG_2F_LVL_DAI1_PLAY 0x2F
  49. #define M98088_REG_30_LVL_DAI1_PLAY_EQ 0x30
  50. #define M98088_REG_31_LVL_DAI2_PLAY 0x31
  51. #define M98088_REG_32_LVL_DAI2_PLAY_EQ 0x32
  52. #define M98088_REG_33_LVL_ADC_L 0x33
  53. #define M98088_REG_34_LVL_ADC_R 0x34
  54. #define M98088_REG_35_LVL_MIC1 0x35
  55. #define M98088_REG_36_LVL_MIC2 0x36
  56. #define M98088_REG_37_LVL_INA 0x37
  57. #define M98088_REG_38_LVL_INB 0x38
  58. #define M98088_REG_39_LVL_HP_L 0x39
  59. #define M98088_REG_3A_LVL_HP_R 0x3A
  60. #define M98088_REG_3B_LVL_REC_L 0x3B
  61. #define M98088_REG_3C_LVL_REC_R 0x3C
  62. #define M98088_REG_3D_LVL_SPK_L 0x3D
  63. #define M98088_REG_3E_LVL_SPK_R 0x3E
  64. #define M98088_REG_3F_MICAGC_CFG 0x3F
  65. #define M98088_REG_40_MICAGC_THRESH 0x40
  66. #define M98088_REG_41_SPKDHP 0x41
  67. #define M98088_REG_42_SPKDHP_THRESH 0x42
  68. #define M98088_REG_43_SPKALC_COMP 0x43
  69. #define M98088_REG_44_PWRLMT_CFG 0x44
  70. #define M98088_REG_45_PWRLMT_TIME 0x45
  71. #define M98088_REG_46_THDLMT_CFG 0x46
  72. #define M98088_REG_47_CFG_AUDIO_IN 0x47
  73. #define M98088_REG_48_CFG_MIC 0x48
  74. #define M98088_REG_49_CFG_LEVEL 0x49
  75. #define M98088_REG_4A_CFG_BYPASS 0x4A
  76. #define M98088_REG_4B_CFG_JACKDET 0x4B
  77. #define M98088_REG_4C_PWR_EN_IN 0x4C
  78. #define M98088_REG_4D_PWR_EN_OUT 0x4D
  79. #define M98088_REG_4E_BIAS_CNTL 0x4E
  80. #define M98088_REG_4F_DAC_BIAS1 0x4F
  81. #define M98088_REG_50_DAC_BIAS2 0x50
  82. #define M98088_REG_51_PWR_SYS 0x51
  83. #define M98088_REG_52_DAI1_EQ_BASE 0x52
  84. #define M98088_REG_84_DAI2_EQ_BASE 0x84
  85. #define M98088_REG_B6_DAI1_BIQUAD_BASE 0xB6
  86. #define M98088_REG_C0_DAI2_BIQUAD_BASE 0xC0
  87. #define M98088_REG_FF_REV_ID 0xFF
  88. #define M98088_REG_CNT (0xFF+1)
  89. /* MAX98088 Registers Bit Fields */
  90. /* M98088_REG_11_DAI1_CLKMODE, M98088_REG_19_DAI2_CLKMODE */
  91. #define M98088_CLKMODE_MASK 0xFF
  92. /* M98088_REG_14_DAI1_FORMAT, M98088_REG_1C_DAI2_FORMAT */
  93. #define M98088_DAI_MAS (1<<7)
  94. #define M98088_DAI_WCI (1<<6)
  95. #define M98088_DAI_BCI (1<<5)
  96. #define M98088_DAI_DLY (1<<4)
  97. #define M98088_DAI_TDM (1<<2)
  98. #define M98088_DAI_FSW (1<<1)
  99. #define M98088_DAI_WS (1<<0)
  100. /* M98088_REG_15_DAI1_CLOCK, M98088_REG_1D_DAI2_CLOCK */
  101. #define M98088_DAI_BSEL64 (1<<0)
  102. #define M98088_DAI_OSR64 (1<<6)
  103. /* M98088_REG_16_DAI1_IOCFG, M98088_REG_1E_DAI2_IOCFG */
  104. #define M98088_S1NORMAL (1<<6)
  105. #define M98088_S2NORMAL (2<<6)
  106. #define M98088_SDATA (3<<0)
  107. /* M98088_REG_18_DAI1_FILTERS, M98088_REG_20_DAI2_FILTERS */
  108. #define M98088_DAI_DHF (1<<3)
  109. /* M98088_REG_22_MIX_DAC */
  110. #define M98088_DAI1L_TO_DACL (1<<7)
  111. #define M98088_DAI1R_TO_DACL (1<<6)
  112. #define M98088_DAI2L_TO_DACL (1<<5)
  113. #define M98088_DAI2R_TO_DACL (1<<4)
  114. #define M98088_DAI1L_TO_DACR (1<<3)
  115. #define M98088_DAI1R_TO_DACR (1<<2)
  116. #define M98088_DAI2L_TO_DACR (1<<1)
  117. #define M98088_DAI2R_TO_DACR (1<<0)
  118. /* M98088_REG_2A_MIC_REC_CNTL */
  119. #define M98088_REC_LINEMODE (1<<7)
  120. #define M98088_REC_LINEMODE_MASK (1<<7)
  121. /* M98088_REG_2D_MIX_SPK_CNTL */
  122. #define M98088_MIX_SPKR_GAIN_MASK (3<<2)
  123. #define M98088_MIX_SPKR_GAIN_SHIFT 2
  124. #define M98088_MIX_SPKL_GAIN_MASK (3<<0)
  125. #define M98088_MIX_SPKL_GAIN_SHIFT 0
  126. /* M98088_REG_2F_LVL_DAI1_PLAY, M98088_REG_31_LVL_DAI2_PLAY */
  127. #define M98088_DAI_MUTE (1<<7)
  128. #define M98088_DAI_MUTE_MASK (1<<7)
  129. #define M98088_DAI_VOICE_GAIN_MASK (3<<4)
  130. #define M98088_DAI_ATTENUATION_MASK (0xF<<0)
  131. #define M98088_DAI_ATTENUATION_SHIFT 0
  132. /* M98088_REG_35_LVL_MIC1, M98088_REG_36_LVL_MIC2 */
  133. #define M98088_MICPRE_MASK (3<<5)
  134. #define M98088_MICPRE_SHIFT 5
  135. /* M98088_REG_3A_LVL_HP_R */
  136. #define M98088_HP_MUTE (1<<7)
  137. /* M98088_REG_3C_LVL_REC_R */
  138. #define M98088_REC_MUTE (1<<7)
  139. /* M98088_REG_3E_LVL_SPK_R */
  140. #define M98088_SP_MUTE (1<<7)
  141. /* M98088_REG_48_CFG_MIC */
  142. #define M98088_EXTMIC_MASK (3<<0)
  143. #define M98088_DIGMIC_L (1<<5)
  144. #define M98088_DIGMIC_R (1<<4)
  145. /* M98088_REG_49_CFG_LEVEL */
  146. #define M98088_VSEN (1<<6)
  147. #define M98088_ZDEN (1<<5)
  148. #define M98088_EQ2EN (1<<1)
  149. #define M98088_EQ1EN (1<<0)
  150. /* M98088_REG_4C_PWR_EN_IN */
  151. #define M98088_INAEN (1<<7)
  152. #define M98088_INBEN (1<<6)
  153. #define M98088_MBEN (1<<3)
  154. #define M98088_ADLEN (1<<1)
  155. #define M98088_ADREN (1<<0)
  156. /* M98088_REG_4D_PWR_EN_OUT */
  157. #define M98088_HPLEN (1<<7)
  158. #define M98088_HPREN (1<<6)
  159. #define M98088_HPEN ((1<<7)|(1<<6))
  160. #define M98088_SPLEN (1<<5)
  161. #define M98088_SPREN (1<<4)
  162. #define M98088_RECEN (1<<3)
  163. #define M98088_DALEN (1<<1)
  164. #define M98088_DAREN (1<<0)
  165. /* M98088_REG_51_PWR_SYS */
  166. #define M98088_SHDNRUN (1<<7)
  167. #define M98088_PERFMODE (1<<3)
  168. #define M98088_HPPLYBACK (1<<2)
  169. #define M98088_PWRSV8K (1<<1)
  170. #define M98088_PWRSV (1<<0)
  171. /* Line inputs */
  172. #define LINE_INA 0
  173. #define LINE_INB 1
  174. #define M98088_COEFS_PER_BAND 5
  175. #define M98088_BYTE1(w) ((w >> 8) & 0xff)
  176. #define M98088_BYTE0(w) (w & 0xff)
  177. #endif