max98088.c 65 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * max98088.c -- MAX98088 ALSA SoC Audio driver
  4. *
  5. * Copyright 2010 Maxim Integrated Products
  6. */
  7. #include <linux/module.h>
  8. #include <linux/moduleparam.h>
  9. #include <linux/kernel.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/i2c.h>
  14. #include <linux/regmap.h>
  15. #include <linux/clk.h>
  16. #include <sound/core.h>
  17. #include <sound/pcm.h>
  18. #include <sound/pcm_params.h>
  19. #include <sound/soc.h>
  20. #include <sound/initval.h>
  21. #include <sound/tlv.h>
  22. #include <linux/slab.h>
  23. #include <asm/div64.h>
  24. #include <sound/max98088.h>
  25. #include "max98088.h"
  26. enum max98088_type {
  27. MAX98088,
  28. MAX98089,
  29. };
  30. struct max98088_cdata {
  31. unsigned int rate;
  32. unsigned int fmt;
  33. int eq_sel;
  34. };
  35. struct max98088_priv {
  36. struct regmap *regmap;
  37. enum max98088_type devtype;
  38. struct max98088_pdata *pdata;
  39. struct clk *mclk;
  40. unsigned char mclk_prescaler;
  41. unsigned int sysclk;
  42. struct max98088_cdata dai[2];
  43. int eq_textcnt;
  44. const char **eq_texts;
  45. struct soc_enum eq_enum;
  46. u8 ina_state;
  47. u8 inb_state;
  48. unsigned int ex_mode;
  49. unsigned int digmic;
  50. unsigned int mic1pre;
  51. unsigned int mic2pre;
  52. unsigned int extmic_mode;
  53. };
  54. static const struct reg_default max98088_reg[] = {
  55. { 0xf, 0x00 }, /* 0F interrupt enable */
  56. { 0x10, 0x00 }, /* 10 master clock */
  57. { 0x11, 0x00 }, /* 11 DAI1 clock mode */
  58. { 0x12, 0x00 }, /* 12 DAI1 clock control */
  59. { 0x13, 0x00 }, /* 13 DAI1 clock control */
  60. { 0x14, 0x00 }, /* 14 DAI1 format */
  61. { 0x15, 0x00 }, /* 15 DAI1 clock */
  62. { 0x16, 0x00 }, /* 16 DAI1 config */
  63. { 0x17, 0x00 }, /* 17 DAI1 TDM */
  64. { 0x18, 0x00 }, /* 18 DAI1 filters */
  65. { 0x19, 0x00 }, /* 19 DAI2 clock mode */
  66. { 0x1a, 0x00 }, /* 1A DAI2 clock control */
  67. { 0x1b, 0x00 }, /* 1B DAI2 clock control */
  68. { 0x1c, 0x00 }, /* 1C DAI2 format */
  69. { 0x1d, 0x00 }, /* 1D DAI2 clock */
  70. { 0x1e, 0x00 }, /* 1E DAI2 config */
  71. { 0x1f, 0x00 }, /* 1F DAI2 TDM */
  72. { 0x20, 0x00 }, /* 20 DAI2 filters */
  73. { 0x21, 0x00 }, /* 21 data config */
  74. { 0x22, 0x00 }, /* 22 DAC mixer */
  75. { 0x23, 0x00 }, /* 23 left ADC mixer */
  76. { 0x24, 0x00 }, /* 24 right ADC mixer */
  77. { 0x25, 0x00 }, /* 25 left HP mixer */
  78. { 0x26, 0x00 }, /* 26 right HP mixer */
  79. { 0x27, 0x00 }, /* 27 HP control */
  80. { 0x28, 0x00 }, /* 28 left REC mixer */
  81. { 0x29, 0x00 }, /* 29 right REC mixer */
  82. { 0x2a, 0x00 }, /* 2A REC control */
  83. { 0x2b, 0x00 }, /* 2B left SPK mixer */
  84. { 0x2c, 0x00 }, /* 2C right SPK mixer */
  85. { 0x2d, 0x00 }, /* 2D SPK control */
  86. { 0x2e, 0x00 }, /* 2E sidetone */
  87. { 0x2f, 0x00 }, /* 2F DAI1 playback level */
  88. { 0x30, 0x00 }, /* 30 DAI1 playback level */
  89. { 0x31, 0x00 }, /* 31 DAI2 playback level */
  90. { 0x32, 0x00 }, /* 32 DAI2 playbakc level */
  91. { 0x33, 0x00 }, /* 33 left ADC level */
  92. { 0x34, 0x00 }, /* 34 right ADC level */
  93. { 0x35, 0x00 }, /* 35 MIC1 level */
  94. { 0x36, 0x00 }, /* 36 MIC2 level */
  95. { 0x37, 0x00 }, /* 37 INA level */
  96. { 0x38, 0x00 }, /* 38 INB level */
  97. { 0x39, 0x00 }, /* 39 left HP volume */
  98. { 0x3a, 0x00 }, /* 3A right HP volume */
  99. { 0x3b, 0x00 }, /* 3B left REC volume */
  100. { 0x3c, 0x00 }, /* 3C right REC volume */
  101. { 0x3d, 0x00 }, /* 3D left SPK volume */
  102. { 0x3e, 0x00 }, /* 3E right SPK volume */
  103. { 0x3f, 0x00 }, /* 3F MIC config */
  104. { 0x40, 0x00 }, /* 40 MIC threshold */
  105. { 0x41, 0x00 }, /* 41 excursion limiter filter */
  106. { 0x42, 0x00 }, /* 42 excursion limiter threshold */
  107. { 0x43, 0x00 }, /* 43 ALC */
  108. { 0x44, 0x00 }, /* 44 power limiter threshold */
  109. { 0x45, 0x00 }, /* 45 power limiter config */
  110. { 0x46, 0x00 }, /* 46 distortion limiter config */
  111. { 0x47, 0x00 }, /* 47 audio input */
  112. { 0x48, 0x00 }, /* 48 microphone */
  113. { 0x49, 0x00 }, /* 49 level control */
  114. { 0x4a, 0x00 }, /* 4A bypass switches */
  115. { 0x4b, 0x00 }, /* 4B jack detect */
  116. { 0x4c, 0x00 }, /* 4C input enable */
  117. { 0x4d, 0x00 }, /* 4D output enable */
  118. { 0x4e, 0xF0 }, /* 4E bias control */
  119. { 0x4f, 0x00 }, /* 4F DAC power */
  120. { 0x50, 0x0F }, /* 50 DAC power */
  121. { 0x51, 0x00 }, /* 51 system */
  122. { 0x52, 0x00 }, /* 52 DAI1 EQ1 */
  123. { 0x53, 0x00 }, /* 53 DAI1 EQ1 */
  124. { 0x54, 0x00 }, /* 54 DAI1 EQ1 */
  125. { 0x55, 0x00 }, /* 55 DAI1 EQ1 */
  126. { 0x56, 0x00 }, /* 56 DAI1 EQ1 */
  127. { 0x57, 0x00 }, /* 57 DAI1 EQ1 */
  128. { 0x58, 0x00 }, /* 58 DAI1 EQ1 */
  129. { 0x59, 0x00 }, /* 59 DAI1 EQ1 */
  130. { 0x5a, 0x00 }, /* 5A DAI1 EQ1 */
  131. { 0x5b, 0x00 }, /* 5B DAI1 EQ1 */
  132. { 0x5c, 0x00 }, /* 5C DAI1 EQ2 */
  133. { 0x5d, 0x00 }, /* 5D DAI1 EQ2 */
  134. { 0x5e, 0x00 }, /* 5E DAI1 EQ2 */
  135. { 0x5f, 0x00 }, /* 5F DAI1 EQ2 */
  136. { 0x60, 0x00 }, /* 60 DAI1 EQ2 */
  137. { 0x61, 0x00 }, /* 61 DAI1 EQ2 */
  138. { 0x62, 0x00 }, /* 62 DAI1 EQ2 */
  139. { 0x63, 0x00 }, /* 63 DAI1 EQ2 */
  140. { 0x64, 0x00 }, /* 64 DAI1 EQ2 */
  141. { 0x65, 0x00 }, /* 65 DAI1 EQ2 */
  142. { 0x66, 0x00 }, /* 66 DAI1 EQ3 */
  143. { 0x67, 0x00 }, /* 67 DAI1 EQ3 */
  144. { 0x68, 0x00 }, /* 68 DAI1 EQ3 */
  145. { 0x69, 0x00 }, /* 69 DAI1 EQ3 */
  146. { 0x6a, 0x00 }, /* 6A DAI1 EQ3 */
  147. { 0x6b, 0x00 }, /* 6B DAI1 EQ3 */
  148. { 0x6c, 0x00 }, /* 6C DAI1 EQ3 */
  149. { 0x6d, 0x00 }, /* 6D DAI1 EQ3 */
  150. { 0x6e, 0x00 }, /* 6E DAI1 EQ3 */
  151. { 0x6f, 0x00 }, /* 6F DAI1 EQ3 */
  152. { 0x70, 0x00 }, /* 70 DAI1 EQ4 */
  153. { 0x71, 0x00 }, /* 71 DAI1 EQ4 */
  154. { 0x72, 0x00 }, /* 72 DAI1 EQ4 */
  155. { 0x73, 0x00 }, /* 73 DAI1 EQ4 */
  156. { 0x74, 0x00 }, /* 74 DAI1 EQ4 */
  157. { 0x75, 0x00 }, /* 75 DAI1 EQ4 */
  158. { 0x76, 0x00 }, /* 76 DAI1 EQ4 */
  159. { 0x77, 0x00 }, /* 77 DAI1 EQ4 */
  160. { 0x78, 0x00 }, /* 78 DAI1 EQ4 */
  161. { 0x79, 0x00 }, /* 79 DAI1 EQ4 */
  162. { 0x7a, 0x00 }, /* 7A DAI1 EQ5 */
  163. { 0x7b, 0x00 }, /* 7B DAI1 EQ5 */
  164. { 0x7c, 0x00 }, /* 7C DAI1 EQ5 */
  165. { 0x7d, 0x00 }, /* 7D DAI1 EQ5 */
  166. { 0x7e, 0x00 }, /* 7E DAI1 EQ5 */
  167. { 0x7f, 0x00 }, /* 7F DAI1 EQ5 */
  168. { 0x80, 0x00 }, /* 80 DAI1 EQ5 */
  169. { 0x81, 0x00 }, /* 81 DAI1 EQ5 */
  170. { 0x82, 0x00 }, /* 82 DAI1 EQ5 */
  171. { 0x83, 0x00 }, /* 83 DAI1 EQ5 */
  172. { 0x84, 0x00 }, /* 84 DAI2 EQ1 */
  173. { 0x85, 0x00 }, /* 85 DAI2 EQ1 */
  174. { 0x86, 0x00 }, /* 86 DAI2 EQ1 */
  175. { 0x87, 0x00 }, /* 87 DAI2 EQ1 */
  176. { 0x88, 0x00 }, /* 88 DAI2 EQ1 */
  177. { 0x89, 0x00 }, /* 89 DAI2 EQ1 */
  178. { 0x8a, 0x00 }, /* 8A DAI2 EQ1 */
  179. { 0x8b, 0x00 }, /* 8B DAI2 EQ1 */
  180. { 0x8c, 0x00 }, /* 8C DAI2 EQ1 */
  181. { 0x8d, 0x00 }, /* 8D DAI2 EQ1 */
  182. { 0x8e, 0x00 }, /* 8E DAI2 EQ2 */
  183. { 0x8f, 0x00 }, /* 8F DAI2 EQ2 */
  184. { 0x90, 0x00 }, /* 90 DAI2 EQ2 */
  185. { 0x91, 0x00 }, /* 91 DAI2 EQ2 */
  186. { 0x92, 0x00 }, /* 92 DAI2 EQ2 */
  187. { 0x93, 0x00 }, /* 93 DAI2 EQ2 */
  188. { 0x94, 0x00 }, /* 94 DAI2 EQ2 */
  189. { 0x95, 0x00 }, /* 95 DAI2 EQ2 */
  190. { 0x96, 0x00 }, /* 96 DAI2 EQ2 */
  191. { 0x97, 0x00 }, /* 97 DAI2 EQ2 */
  192. { 0x98, 0x00 }, /* 98 DAI2 EQ3 */
  193. { 0x99, 0x00 }, /* 99 DAI2 EQ3 */
  194. { 0x9a, 0x00 }, /* 9A DAI2 EQ3 */
  195. { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */
  196. { 0x9c, 0x00 }, /* 9C DAI2 EQ3 */
  197. { 0x9d, 0x00 }, /* 9D DAI2 EQ3 */
  198. { 0x9e, 0x00 }, /* 9E DAI2 EQ3 */
  199. { 0x9f, 0x00 }, /* 9F DAI2 EQ3 */
  200. { 0xa0, 0x00 }, /* A0 DAI2 EQ3 */
  201. { 0xa1, 0x00 }, /* A1 DAI2 EQ3 */
  202. { 0xa2, 0x00 }, /* A2 DAI2 EQ4 */
  203. { 0xa3, 0x00 }, /* A3 DAI2 EQ4 */
  204. { 0xa4, 0x00 }, /* A4 DAI2 EQ4 */
  205. { 0xa5, 0x00 }, /* A5 DAI2 EQ4 */
  206. { 0xa6, 0x00 }, /* A6 DAI2 EQ4 */
  207. { 0xa7, 0x00 }, /* A7 DAI2 EQ4 */
  208. { 0xa8, 0x00 }, /* A8 DAI2 EQ4 */
  209. { 0xa9, 0x00 }, /* A9 DAI2 EQ4 */
  210. { 0xaa, 0x00 }, /* AA DAI2 EQ4 */
  211. { 0xab, 0x00 }, /* AB DAI2 EQ4 */
  212. { 0xac, 0x00 }, /* AC DAI2 EQ5 */
  213. { 0xad, 0x00 }, /* AD DAI2 EQ5 */
  214. { 0xae, 0x00 }, /* AE DAI2 EQ5 */
  215. { 0xaf, 0x00 }, /* AF DAI2 EQ5 */
  216. { 0xb0, 0x00 }, /* B0 DAI2 EQ5 */
  217. { 0xb1, 0x00 }, /* B1 DAI2 EQ5 */
  218. { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */
  219. { 0xb3, 0x00 }, /* B3 DAI2 EQ5 */
  220. { 0xb4, 0x00 }, /* B4 DAI2 EQ5 */
  221. { 0xb5, 0x00 }, /* B5 DAI2 EQ5 */
  222. { 0xb6, 0x00 }, /* B6 DAI1 biquad */
  223. { 0xb7, 0x00 }, /* B7 DAI1 biquad */
  224. { 0xb8 ,0x00 }, /* B8 DAI1 biquad */
  225. { 0xb9, 0x00 }, /* B9 DAI1 biquad */
  226. { 0xba, 0x00 }, /* BA DAI1 biquad */
  227. { 0xbb, 0x00 }, /* BB DAI1 biquad */
  228. { 0xbc, 0x00 }, /* BC DAI1 biquad */
  229. { 0xbd, 0x00 }, /* BD DAI1 biquad */
  230. { 0xbe, 0x00 }, /* BE DAI1 biquad */
  231. { 0xbf, 0x00 }, /* BF DAI1 biquad */
  232. { 0xc0, 0x00 }, /* C0 DAI2 biquad */
  233. { 0xc1, 0x00 }, /* C1 DAI2 biquad */
  234. { 0xc2, 0x00 }, /* C2 DAI2 biquad */
  235. { 0xc3, 0x00 }, /* C3 DAI2 biquad */
  236. { 0xc4, 0x00 }, /* C4 DAI2 biquad */
  237. { 0xc5, 0x00 }, /* C5 DAI2 biquad */
  238. { 0xc6, 0x00 }, /* C6 DAI2 biquad */
  239. { 0xc7, 0x00 }, /* C7 DAI2 biquad */
  240. { 0xc8, 0x00 }, /* C8 DAI2 biquad */
  241. { 0xc9, 0x00 }, /* C9 DAI2 biquad */
  242. };
  243. static bool max98088_readable_register(struct device *dev, unsigned int reg)
  244. {
  245. switch (reg) {
  246. case M98088_REG_00_IRQ_STATUS ... 0xC9:
  247. case M98088_REG_FF_REV_ID:
  248. return true;
  249. default:
  250. return false;
  251. }
  252. }
  253. static bool max98088_writeable_register(struct device *dev, unsigned int reg)
  254. {
  255. switch (reg) {
  256. case M98088_REG_03_BATTERY_VOLTAGE ... 0xC9:
  257. return true;
  258. default:
  259. return false;
  260. }
  261. }
  262. static bool max98088_volatile_register(struct device *dev, unsigned int reg)
  263. {
  264. switch (reg) {
  265. case M98088_REG_00_IRQ_STATUS ... M98088_REG_03_BATTERY_VOLTAGE:
  266. case M98088_REG_FF_REV_ID:
  267. return true;
  268. default:
  269. return false;
  270. }
  271. }
  272. static const struct regmap_config max98088_regmap = {
  273. .reg_bits = 8,
  274. .val_bits = 8,
  275. .readable_reg = max98088_readable_register,
  276. .writeable_reg = max98088_writeable_register,
  277. .volatile_reg = max98088_volatile_register,
  278. .max_register = 0xff,
  279. .reg_defaults = max98088_reg,
  280. .num_reg_defaults = ARRAY_SIZE(max98088_reg),
  281. .cache_type = REGCACHE_RBTREE,
  282. };
  283. /*
  284. * Load equalizer DSP coefficient configurations registers
  285. */
  286. static void m98088_eq_band(struct snd_soc_component *component, unsigned int dai,
  287. unsigned int band, u16 *coefs)
  288. {
  289. unsigned int eq_reg;
  290. unsigned int i;
  291. if (WARN_ON(band > 4) ||
  292. WARN_ON(dai > 1))
  293. return;
  294. /* Load the base register address */
  295. eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
  296. /* Add the band address offset, note adjustment for word address */
  297. eq_reg += band * (M98088_COEFS_PER_BAND << 1);
  298. /* Step through the registers and coefs */
  299. for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
  300. snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i]));
  301. snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i]));
  302. }
  303. }
  304. /*
  305. * Excursion limiter modes
  306. */
  307. static const char *max98088_exmode_texts[] = {
  308. "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
  309. "400-600Hz", "400-800Hz",
  310. };
  311. static const unsigned int max98088_exmode_values[] = {
  312. 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
  313. };
  314. static SOC_VALUE_ENUM_SINGLE_DECL(max98088_exmode_enum,
  315. M98088_REG_41_SPKDHP, 0, 127,
  316. max98088_exmode_texts,
  317. max98088_exmode_values);
  318. static const char *max98088_ex_thresh[] = { /* volts PP */
  319. "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
  320. static SOC_ENUM_SINGLE_DECL(max98088_ex_thresh_enum,
  321. M98088_REG_42_SPKDHP_THRESH, 0,
  322. max98088_ex_thresh);
  323. static const char *max98088_fltr_mode[] = {"Voice", "Music" };
  324. static SOC_ENUM_SINGLE_DECL(max98088_filter_mode_enum,
  325. M98088_REG_18_DAI1_FILTERS, 7,
  326. max98088_fltr_mode);
  327. static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
  328. static SOC_ENUM_SINGLE_DECL(max98088_extmic_enum,
  329. M98088_REG_48_CFG_MIC, 0,
  330. max98088_extmic_text);
  331. static const struct snd_kcontrol_new max98088_extmic_mux =
  332. SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
  333. static const char *max98088_dai1_fltr[] = {
  334. "Off", "fc=258/fs=16k", "fc=500/fs=16k",
  335. "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
  336. static SOC_ENUM_SINGLE_DECL(max98088_dai1_dac_filter_enum,
  337. M98088_REG_18_DAI1_FILTERS, 0,
  338. max98088_dai1_fltr);
  339. static SOC_ENUM_SINGLE_DECL(max98088_dai1_adc_filter_enum,
  340. M98088_REG_18_DAI1_FILTERS, 4,
  341. max98088_dai1_fltr);
  342. static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
  343. struct snd_ctl_elem_value *ucontrol)
  344. {
  345. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  346. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  347. unsigned int sel = ucontrol->value.integer.value[0];
  348. max98088->mic1pre = sel;
  349. snd_soc_component_update_bits(component, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
  350. (1+sel)<<M98088_MICPRE_SHIFT);
  351. return 0;
  352. }
  353. static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
  354. struct snd_ctl_elem_value *ucontrol)
  355. {
  356. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  357. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  358. ucontrol->value.integer.value[0] = max98088->mic1pre;
  359. return 0;
  360. }
  361. static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
  362. struct snd_ctl_elem_value *ucontrol)
  363. {
  364. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  365. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  366. unsigned int sel = ucontrol->value.integer.value[0];
  367. max98088->mic2pre = sel;
  368. snd_soc_component_update_bits(component, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
  369. (1+sel)<<M98088_MICPRE_SHIFT);
  370. return 0;
  371. }
  372. static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
  373. struct snd_ctl_elem_value *ucontrol)
  374. {
  375. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  376. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  377. ucontrol->value.integer.value[0] = max98088->mic2pre;
  378. return 0;
  379. }
  380. static const DECLARE_TLV_DB_RANGE(max98088_micboost_tlv,
  381. 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
  382. 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
  383. );
  384. static const DECLARE_TLV_DB_RANGE(max98088_hp_tlv,
  385. 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
  386. 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
  387. 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
  388. 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
  389. 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
  390. );
  391. static const DECLARE_TLV_DB_RANGE(max98088_spk_tlv,
  392. 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
  393. 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
  394. 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
  395. 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
  396. 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
  397. );
  398. static const struct snd_kcontrol_new max98088_snd_controls[] = {
  399. SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L,
  400. M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv),
  401. SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
  402. M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv),
  403. SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L,
  404. M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv),
  405. SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
  406. M98088_REG_3A_LVL_HP_R, 7, 1, 1),
  407. SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
  408. M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
  409. SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
  410. M98088_REG_3C_LVL_REC_R, 7, 1, 1),
  411. SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
  412. SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
  413. SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
  414. M98088_REG_35_LVL_MIC1, 5, 2, 0,
  415. max98088_mic1pre_get, max98088_mic1pre_set,
  416. max98088_micboost_tlv),
  417. SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
  418. M98088_REG_36_LVL_MIC2, 5, 2, 0,
  419. max98088_mic2pre_get, max98088_mic2pre_set,
  420. max98088_micboost_tlv),
  421. SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
  422. SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
  423. SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
  424. SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
  425. SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
  426. SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
  427. SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
  428. SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
  429. SOC_ENUM("EX Limiter Mode", max98088_exmode_enum),
  430. SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
  431. SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
  432. SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
  433. SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
  434. SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
  435. 0, 1, 0),
  436. SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
  437. SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
  438. SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
  439. SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
  440. SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
  441. 4, 15, 0),
  442. SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
  443. SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
  444. SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
  445. SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
  446. SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
  447. };
  448. /* Left speaker mixer switch */
  449. static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
  450. SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
  451. SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
  452. SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
  453. SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
  454. SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
  455. SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
  456. SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
  457. SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
  458. SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
  459. SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
  460. };
  461. /* Right speaker mixer switch */
  462. static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
  463. SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
  464. SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
  465. SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
  466. SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
  467. SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
  468. SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
  469. SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
  470. SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
  471. SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
  472. SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
  473. };
  474. /* Left headphone mixer switch */
  475. static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
  476. SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
  477. SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
  478. SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
  479. SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
  480. SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
  481. SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
  482. SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
  483. SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
  484. SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
  485. SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
  486. };
  487. /* Right headphone mixer switch */
  488. static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
  489. SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
  490. SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
  491. SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
  492. SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
  493. SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
  494. SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
  495. SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
  496. SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
  497. SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
  498. SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
  499. };
  500. /* Left earpiece/receiver mixer switch */
  501. static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
  502. SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
  503. SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
  504. SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
  505. SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
  506. SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
  507. SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
  508. SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
  509. SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
  510. SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
  511. SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
  512. };
  513. /* Right earpiece/receiver mixer switch */
  514. static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
  515. SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
  516. SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
  517. SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
  518. SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
  519. SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
  520. SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
  521. SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
  522. SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
  523. SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
  524. SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
  525. };
  526. /* Left ADC mixer switch */
  527. static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
  528. SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
  529. SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
  530. SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
  531. SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
  532. SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
  533. SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
  534. };
  535. /* Right ADC mixer switch */
  536. static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
  537. SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
  538. SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
  539. SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
  540. SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
  541. SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
  542. SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
  543. };
  544. static int max98088_mic_event(struct snd_soc_dapm_widget *w,
  545. struct snd_kcontrol *kcontrol, int event)
  546. {
  547. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  548. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  549. switch (event) {
  550. case SND_SOC_DAPM_POST_PMU:
  551. if (w->reg == M98088_REG_35_LVL_MIC1) {
  552. snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
  553. (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
  554. } else {
  555. snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
  556. (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
  557. }
  558. break;
  559. case SND_SOC_DAPM_POST_PMD:
  560. snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 0);
  561. break;
  562. default:
  563. return -EINVAL;
  564. }
  565. return 0;
  566. }
  567. /*
  568. * The line inputs are 2-channel stereo inputs with the left
  569. * and right channels sharing a common PGA power control signal.
  570. */
  571. static int max98088_line_pga(struct snd_soc_dapm_widget *w,
  572. int event, int line, u8 channel)
  573. {
  574. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  575. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  576. u8 *state;
  577. if (WARN_ON(!(channel == 1 || channel == 2)))
  578. return -EINVAL;
  579. switch (line) {
  580. case LINE_INA:
  581. state = &max98088->ina_state;
  582. break;
  583. case LINE_INB:
  584. state = &max98088->inb_state;
  585. break;
  586. default:
  587. return -EINVAL;
  588. }
  589. switch (event) {
  590. case SND_SOC_DAPM_POST_PMU:
  591. *state |= channel;
  592. snd_soc_component_update_bits(component, w->reg,
  593. (1 << w->shift), (1 << w->shift));
  594. break;
  595. case SND_SOC_DAPM_POST_PMD:
  596. *state &= ~channel;
  597. if (*state == 0) {
  598. snd_soc_component_update_bits(component, w->reg,
  599. (1 << w->shift), 0);
  600. }
  601. break;
  602. default:
  603. return -EINVAL;
  604. }
  605. return 0;
  606. }
  607. static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
  608. struct snd_kcontrol *k, int event)
  609. {
  610. return max98088_line_pga(w, event, LINE_INA, 1);
  611. }
  612. static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
  613. struct snd_kcontrol *k, int event)
  614. {
  615. return max98088_line_pga(w, event, LINE_INA, 2);
  616. }
  617. static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
  618. struct snd_kcontrol *k, int event)
  619. {
  620. return max98088_line_pga(w, event, LINE_INB, 1);
  621. }
  622. static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
  623. struct snd_kcontrol *k, int event)
  624. {
  625. return max98088_line_pga(w, event, LINE_INB, 2);
  626. }
  627. static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
  628. SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
  629. SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
  630. SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
  631. M98088_REG_4D_PWR_EN_OUT, 1, 0),
  632. SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
  633. M98088_REG_4D_PWR_EN_OUT, 0, 0),
  634. SND_SOC_DAPM_DAC("DACL2", "Aux Playback",
  635. M98088_REG_4D_PWR_EN_OUT, 1, 0),
  636. SND_SOC_DAPM_DAC("DACR2", "Aux Playback",
  637. M98088_REG_4D_PWR_EN_OUT, 0, 0),
  638. SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
  639. 7, 0, NULL, 0),
  640. SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
  641. 6, 0, NULL, 0),
  642. SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
  643. 5, 0, NULL, 0),
  644. SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
  645. 4, 0, NULL, 0),
  646. SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
  647. 3, 0, NULL, 0),
  648. SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
  649. 2, 0, NULL, 0),
  650. SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
  651. &max98088_extmic_mux),
  652. SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
  653. &max98088_left_hp_mixer_controls[0],
  654. ARRAY_SIZE(max98088_left_hp_mixer_controls)),
  655. SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
  656. &max98088_right_hp_mixer_controls[0],
  657. ARRAY_SIZE(max98088_right_hp_mixer_controls)),
  658. SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
  659. &max98088_left_speaker_mixer_controls[0],
  660. ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
  661. SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
  662. &max98088_right_speaker_mixer_controls[0],
  663. ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
  664. SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
  665. &max98088_left_rec_mixer_controls[0],
  666. ARRAY_SIZE(max98088_left_rec_mixer_controls)),
  667. SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
  668. &max98088_right_rec_mixer_controls[0],
  669. ARRAY_SIZE(max98088_right_rec_mixer_controls)),
  670. SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
  671. &max98088_left_ADC_mixer_controls[0],
  672. ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
  673. SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
  674. &max98088_right_ADC_mixer_controls[0],
  675. ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
  676. SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
  677. 5, 0, NULL, 0, max98088_mic_event,
  678. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  679. SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
  680. 5, 0, NULL, 0, max98088_mic_event,
  681. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  682. SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
  683. 7, 0, NULL, 0, max98088_pga_ina1_event,
  684. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  685. SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
  686. 7, 0, NULL, 0, max98088_pga_ina2_event,
  687. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  688. SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
  689. 6, 0, NULL, 0, max98088_pga_inb1_event,
  690. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  691. SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
  692. 6, 0, NULL, 0, max98088_pga_inb2_event,
  693. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  694. SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
  695. SND_SOC_DAPM_OUTPUT("HPL"),
  696. SND_SOC_DAPM_OUTPUT("HPR"),
  697. SND_SOC_DAPM_OUTPUT("SPKL"),
  698. SND_SOC_DAPM_OUTPUT("SPKR"),
  699. SND_SOC_DAPM_OUTPUT("RECL"),
  700. SND_SOC_DAPM_OUTPUT("RECR"),
  701. SND_SOC_DAPM_INPUT("MIC1"),
  702. SND_SOC_DAPM_INPUT("MIC2"),
  703. SND_SOC_DAPM_INPUT("INA1"),
  704. SND_SOC_DAPM_INPUT("INA2"),
  705. SND_SOC_DAPM_INPUT("INB1"),
  706. SND_SOC_DAPM_INPUT("INB2"),
  707. };
  708. static const struct snd_soc_dapm_route max98088_audio_map[] = {
  709. /* Left headphone output mixer */
  710. {"Left HP Mixer", "Left DAC1 Switch", "DACL1"},
  711. {"Left HP Mixer", "Left DAC2 Switch", "DACL2"},
  712. {"Left HP Mixer", "Right DAC1 Switch", "DACR1"},
  713. {"Left HP Mixer", "Right DAC2 Switch", "DACR2"},
  714. {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
  715. {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
  716. {"Left HP Mixer", "INA1 Switch", "INA1 Input"},
  717. {"Left HP Mixer", "INA2 Switch", "INA2 Input"},
  718. {"Left HP Mixer", "INB1 Switch", "INB1 Input"},
  719. {"Left HP Mixer", "INB2 Switch", "INB2 Input"},
  720. /* Right headphone output mixer */
  721. {"Right HP Mixer", "Left DAC1 Switch", "DACL1"},
  722. {"Right HP Mixer", "Left DAC2 Switch", "DACL2" },
  723. {"Right HP Mixer", "Right DAC1 Switch", "DACR1"},
  724. {"Right HP Mixer", "Right DAC2 Switch", "DACR2"},
  725. {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
  726. {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
  727. {"Right HP Mixer", "INA1 Switch", "INA1 Input"},
  728. {"Right HP Mixer", "INA2 Switch", "INA2 Input"},
  729. {"Right HP Mixer", "INB1 Switch", "INB1 Input"},
  730. {"Right HP Mixer", "INB2 Switch", "INB2 Input"},
  731. /* Left speaker output mixer */
  732. {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"},
  733. {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"},
  734. {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"},
  735. {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"},
  736. {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
  737. {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
  738. {"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
  739. {"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
  740. {"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
  741. {"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
  742. /* Right speaker output mixer */
  743. {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"},
  744. {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"},
  745. {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"},
  746. {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"},
  747. {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
  748. {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
  749. {"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
  750. {"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
  751. {"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
  752. {"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
  753. /* Earpiece/Receiver output mixer */
  754. {"Left REC Mixer", "Left DAC1 Switch", "DACL1"},
  755. {"Left REC Mixer", "Left DAC2 Switch", "DACL2"},
  756. {"Left REC Mixer", "Right DAC1 Switch", "DACR1"},
  757. {"Left REC Mixer", "Right DAC2 Switch", "DACR2"},
  758. {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
  759. {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
  760. {"Left REC Mixer", "INA1 Switch", "INA1 Input"},
  761. {"Left REC Mixer", "INA2 Switch", "INA2 Input"},
  762. {"Left REC Mixer", "INB1 Switch", "INB1 Input"},
  763. {"Left REC Mixer", "INB2 Switch", "INB2 Input"},
  764. /* Earpiece/Receiver output mixer */
  765. {"Right REC Mixer", "Left DAC1 Switch", "DACL1"},
  766. {"Right REC Mixer", "Left DAC2 Switch", "DACL2"},
  767. {"Right REC Mixer", "Right DAC1 Switch", "DACR1"},
  768. {"Right REC Mixer", "Right DAC2 Switch", "DACR2"},
  769. {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
  770. {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
  771. {"Right REC Mixer", "INA1 Switch", "INA1 Input"},
  772. {"Right REC Mixer", "INA2 Switch", "INA2 Input"},
  773. {"Right REC Mixer", "INB1 Switch", "INB1 Input"},
  774. {"Right REC Mixer", "INB2 Switch", "INB2 Input"},
  775. {"HP Left Out", NULL, "Left HP Mixer"},
  776. {"HP Right Out", NULL, "Right HP Mixer"},
  777. {"SPK Left Out", NULL, "Left SPK Mixer"},
  778. {"SPK Right Out", NULL, "Right SPK Mixer"},
  779. {"REC Left Out", NULL, "Left REC Mixer"},
  780. {"REC Right Out", NULL, "Right REC Mixer"},
  781. {"HPL", NULL, "HP Left Out"},
  782. {"HPR", NULL, "HP Right Out"},
  783. {"SPKL", NULL, "SPK Left Out"},
  784. {"SPKR", NULL, "SPK Right Out"},
  785. {"RECL", NULL, "REC Left Out"},
  786. {"RECR", NULL, "REC Right Out"},
  787. /* Left ADC input mixer */
  788. {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
  789. {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
  790. {"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
  791. {"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
  792. {"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
  793. {"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
  794. /* Right ADC input mixer */
  795. {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
  796. {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
  797. {"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
  798. {"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
  799. {"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
  800. {"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
  801. /* Inputs */
  802. {"ADCL", NULL, "Left ADC Mixer"},
  803. {"ADCR", NULL, "Right ADC Mixer"},
  804. {"INA1 Input", NULL, "INA1"},
  805. {"INA2 Input", NULL, "INA2"},
  806. {"INB1 Input", NULL, "INB1"},
  807. {"INB2 Input", NULL, "INB2"},
  808. {"MIC1 Input", NULL, "MIC1"},
  809. {"MIC2 Input", NULL, "MIC2"},
  810. };
  811. /* codec mclk clock divider coefficients */
  812. static const struct {
  813. u32 rate;
  814. u8 sr;
  815. } rate_table[] = {
  816. {8000, 0x10},
  817. {11025, 0x20},
  818. {16000, 0x30},
  819. {22050, 0x40},
  820. {24000, 0x50},
  821. {32000, 0x60},
  822. {44100, 0x70},
  823. {48000, 0x80},
  824. {88200, 0x90},
  825. {96000, 0xA0},
  826. };
  827. static inline int rate_value(int rate, u8 *value)
  828. {
  829. int i;
  830. for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
  831. if (rate_table[i].rate >= rate) {
  832. *value = rate_table[i].sr;
  833. return 0;
  834. }
  835. }
  836. *value = rate_table[0].sr;
  837. return -EINVAL;
  838. }
  839. static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
  840. struct snd_pcm_hw_params *params,
  841. struct snd_soc_dai *dai)
  842. {
  843. struct snd_soc_component *component = dai->component;
  844. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  845. struct max98088_cdata *cdata;
  846. unsigned long long ni;
  847. unsigned int rate;
  848. u8 regval;
  849. cdata = &max98088->dai[0];
  850. rate = params_rate(params);
  851. switch (params_width(params)) {
  852. case 16:
  853. snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
  854. M98088_DAI_WS, 0);
  855. break;
  856. case 24:
  857. snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
  858. M98088_DAI_WS, M98088_DAI_WS);
  859. break;
  860. default:
  861. return -EINVAL;
  862. }
  863. snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
  864. if (rate_value(rate, &regval))
  865. return -EINVAL;
  866. snd_soc_component_update_bits(component, M98088_REG_11_DAI1_CLKMODE,
  867. M98088_CLKMODE_MASK, regval);
  868. cdata->rate = rate;
  869. /* Configure NI when operating as master */
  870. if (snd_soc_component_read(component, M98088_REG_14_DAI1_FORMAT)
  871. & M98088_DAI_MAS) {
  872. unsigned long pclk;
  873. if (max98088->sysclk == 0) {
  874. dev_err(component->dev, "Invalid system clock frequency\n");
  875. return -EINVAL;
  876. }
  877. ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
  878. * (unsigned long long int)rate;
  879. pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);
  880. ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);
  881. snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
  882. (ni >> 8) & 0x7F);
  883. snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
  884. ni & 0xFF);
  885. }
  886. /* Update sample rate mode */
  887. if (rate < 50000)
  888. snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
  889. M98088_DAI_DHF, 0);
  890. else
  891. snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
  892. M98088_DAI_DHF, M98088_DAI_DHF);
  893. snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
  894. M98088_SHDNRUN);
  895. return 0;
  896. }
  897. static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
  898. struct snd_pcm_hw_params *params,
  899. struct snd_soc_dai *dai)
  900. {
  901. struct snd_soc_component *component = dai->component;
  902. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  903. struct max98088_cdata *cdata;
  904. unsigned long long ni;
  905. unsigned int rate;
  906. u8 regval;
  907. cdata = &max98088->dai[1];
  908. rate = params_rate(params);
  909. switch (params_width(params)) {
  910. case 16:
  911. snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
  912. M98088_DAI_WS, 0);
  913. break;
  914. case 24:
  915. snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
  916. M98088_DAI_WS, M98088_DAI_WS);
  917. break;
  918. default:
  919. return -EINVAL;
  920. }
  921. snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
  922. if (rate_value(rate, &regval))
  923. return -EINVAL;
  924. snd_soc_component_update_bits(component, M98088_REG_19_DAI2_CLKMODE,
  925. M98088_CLKMODE_MASK, regval);
  926. cdata->rate = rate;
  927. /* Configure NI when operating as master */
  928. if (snd_soc_component_read(component, M98088_REG_1C_DAI2_FORMAT)
  929. & M98088_DAI_MAS) {
  930. unsigned long pclk;
  931. if (max98088->sysclk == 0) {
  932. dev_err(component->dev, "Invalid system clock frequency\n");
  933. return -EINVAL;
  934. }
  935. ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
  936. * (unsigned long long int)rate;
  937. pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);
  938. ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);
  939. snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
  940. (ni >> 8) & 0x7F);
  941. snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
  942. ni & 0xFF);
  943. }
  944. /* Update sample rate mode */
  945. if (rate < 50000)
  946. snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
  947. M98088_DAI_DHF, 0);
  948. else
  949. snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
  950. M98088_DAI_DHF, M98088_DAI_DHF);
  951. snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
  952. M98088_SHDNRUN);
  953. return 0;
  954. }
  955. static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
  956. int clk_id, unsigned int freq, int dir)
  957. {
  958. struct snd_soc_component *component = dai->component;
  959. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  960. /* Requested clock frequency is already setup */
  961. if (freq == max98088->sysclk)
  962. return 0;
  963. if (!IS_ERR(max98088->mclk)) {
  964. freq = clk_round_rate(max98088->mclk, freq);
  965. clk_set_rate(max98088->mclk, freq);
  966. }
  967. /* Setup clocks for slave mode, and using the PLL
  968. * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
  969. * 0x02 (when master clk is 20MHz to 30MHz)..
  970. */
  971. if ((freq >= 10000000) && (freq < 20000000)) {
  972. snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10);
  973. max98088->mclk_prescaler = 1;
  974. } else if ((freq >= 20000000) && (freq < 30000000)) {
  975. snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20);
  976. max98088->mclk_prescaler = 2;
  977. } else {
  978. dev_err(component->dev, "Invalid master clock frequency\n");
  979. return -EINVAL;
  980. }
  981. if (snd_soc_component_read(component, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) {
  982. snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
  983. M98088_SHDNRUN, 0);
  984. snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
  985. M98088_SHDNRUN, M98088_SHDNRUN);
  986. }
  987. dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
  988. max98088->sysclk = freq;
  989. return 0;
  990. }
  991. static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
  992. unsigned int fmt)
  993. {
  994. struct snd_soc_component *component = codec_dai->component;
  995. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  996. struct max98088_cdata *cdata;
  997. u8 reg15val;
  998. u8 reg14val = 0;
  999. cdata = &max98088->dai[0];
  1000. if (fmt != cdata->fmt) {
  1001. cdata->fmt = fmt;
  1002. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1003. case SND_SOC_DAIFMT_CBS_CFS:
  1004. /* Slave mode PLL */
  1005. snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
  1006. 0x80);
  1007. snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
  1008. 0x00);
  1009. break;
  1010. case SND_SOC_DAIFMT_CBM_CFM:
  1011. /* Set to master mode */
  1012. reg14val |= M98088_DAI_MAS;
  1013. break;
  1014. case SND_SOC_DAIFMT_CBS_CFM:
  1015. case SND_SOC_DAIFMT_CBM_CFS:
  1016. default:
  1017. dev_err(component->dev, "Clock mode unsupported");
  1018. return -EINVAL;
  1019. }
  1020. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1021. case SND_SOC_DAIFMT_I2S:
  1022. reg14val |= M98088_DAI_DLY;
  1023. break;
  1024. case SND_SOC_DAIFMT_LEFT_J:
  1025. break;
  1026. default:
  1027. return -EINVAL;
  1028. }
  1029. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1030. case SND_SOC_DAIFMT_NB_NF:
  1031. break;
  1032. case SND_SOC_DAIFMT_NB_IF:
  1033. reg14val |= M98088_DAI_WCI;
  1034. break;
  1035. case SND_SOC_DAIFMT_IB_NF:
  1036. reg14val |= M98088_DAI_BCI;
  1037. break;
  1038. case SND_SOC_DAIFMT_IB_IF:
  1039. reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
  1040. break;
  1041. default:
  1042. return -EINVAL;
  1043. }
  1044. snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
  1045. M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
  1046. M98088_DAI_WCI, reg14val);
  1047. reg15val = M98088_DAI_BSEL64;
  1048. if (max98088->digmic)
  1049. reg15val |= M98088_DAI_OSR64;
  1050. snd_soc_component_write(component, M98088_REG_15_DAI1_CLOCK, reg15val);
  1051. }
  1052. return 0;
  1053. }
  1054. static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
  1055. unsigned int fmt)
  1056. {
  1057. struct snd_soc_component *component = codec_dai->component;
  1058. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  1059. struct max98088_cdata *cdata;
  1060. u8 reg1Cval = 0;
  1061. cdata = &max98088->dai[1];
  1062. if (fmt != cdata->fmt) {
  1063. cdata->fmt = fmt;
  1064. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1065. case SND_SOC_DAIFMT_CBS_CFS:
  1066. /* Slave mode PLL */
  1067. snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
  1068. 0x80);
  1069. snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
  1070. 0x00);
  1071. break;
  1072. case SND_SOC_DAIFMT_CBM_CFM:
  1073. /* Set to master mode */
  1074. reg1Cval |= M98088_DAI_MAS;
  1075. break;
  1076. case SND_SOC_DAIFMT_CBS_CFM:
  1077. case SND_SOC_DAIFMT_CBM_CFS:
  1078. default:
  1079. dev_err(component->dev, "Clock mode unsupported");
  1080. return -EINVAL;
  1081. }
  1082. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1083. case SND_SOC_DAIFMT_I2S:
  1084. reg1Cval |= M98088_DAI_DLY;
  1085. break;
  1086. case SND_SOC_DAIFMT_LEFT_J:
  1087. break;
  1088. default:
  1089. return -EINVAL;
  1090. }
  1091. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1092. case SND_SOC_DAIFMT_NB_NF:
  1093. break;
  1094. case SND_SOC_DAIFMT_NB_IF:
  1095. reg1Cval |= M98088_DAI_WCI;
  1096. break;
  1097. case SND_SOC_DAIFMT_IB_NF:
  1098. reg1Cval |= M98088_DAI_BCI;
  1099. break;
  1100. case SND_SOC_DAIFMT_IB_IF:
  1101. reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
  1102. break;
  1103. default:
  1104. return -EINVAL;
  1105. }
  1106. snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
  1107. M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
  1108. M98088_DAI_WCI, reg1Cval);
  1109. snd_soc_component_write(component, M98088_REG_1D_DAI2_CLOCK,
  1110. M98088_DAI_BSEL64);
  1111. }
  1112. return 0;
  1113. }
  1114. static int max98088_dai1_mute(struct snd_soc_dai *codec_dai, int mute,
  1115. int direction)
  1116. {
  1117. struct snd_soc_component *component = codec_dai->component;
  1118. int reg;
  1119. if (mute)
  1120. reg = M98088_DAI_MUTE;
  1121. else
  1122. reg = 0;
  1123. snd_soc_component_update_bits(component, M98088_REG_2F_LVL_DAI1_PLAY,
  1124. M98088_DAI_MUTE_MASK, reg);
  1125. return 0;
  1126. }
  1127. static int max98088_dai2_mute(struct snd_soc_dai *codec_dai, int mute,
  1128. int direction)
  1129. {
  1130. struct snd_soc_component *component = codec_dai->component;
  1131. int reg;
  1132. if (mute)
  1133. reg = M98088_DAI_MUTE;
  1134. else
  1135. reg = 0;
  1136. snd_soc_component_update_bits(component, M98088_REG_31_LVL_DAI2_PLAY,
  1137. M98088_DAI_MUTE_MASK, reg);
  1138. return 0;
  1139. }
  1140. static int max98088_set_bias_level(struct snd_soc_component *component,
  1141. enum snd_soc_bias_level level)
  1142. {
  1143. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  1144. switch (level) {
  1145. case SND_SOC_BIAS_ON:
  1146. break;
  1147. case SND_SOC_BIAS_PREPARE:
  1148. /*
  1149. * SND_SOC_BIAS_PREPARE is called while preparing for a
  1150. * transition to ON or away from ON. If current bias_level
  1151. * is SND_SOC_BIAS_ON, then it is preparing for a transition
  1152. * away from ON. Disable the clock in that case, otherwise
  1153. * enable it.
  1154. */
  1155. if (!IS_ERR(max98088->mclk)) {
  1156. if (snd_soc_component_get_bias_level(component) ==
  1157. SND_SOC_BIAS_ON)
  1158. clk_disable_unprepare(max98088->mclk);
  1159. else
  1160. clk_prepare_enable(max98088->mclk);
  1161. }
  1162. break;
  1163. case SND_SOC_BIAS_STANDBY:
  1164. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
  1165. regcache_sync(max98088->regmap);
  1166. snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
  1167. M98088_MBEN, M98088_MBEN);
  1168. break;
  1169. case SND_SOC_BIAS_OFF:
  1170. snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
  1171. M98088_MBEN, 0);
  1172. regcache_mark_dirty(max98088->regmap);
  1173. break;
  1174. }
  1175. return 0;
  1176. }
  1177. #define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
  1178. #define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
  1179. static const struct snd_soc_dai_ops max98088_dai1_ops = {
  1180. .set_sysclk = max98088_dai_set_sysclk,
  1181. .set_fmt = max98088_dai1_set_fmt,
  1182. .hw_params = max98088_dai1_hw_params,
  1183. .mute_stream = max98088_dai1_mute,
  1184. .no_capture_mute = 1,
  1185. };
  1186. static const struct snd_soc_dai_ops max98088_dai2_ops = {
  1187. .set_sysclk = max98088_dai_set_sysclk,
  1188. .set_fmt = max98088_dai2_set_fmt,
  1189. .hw_params = max98088_dai2_hw_params,
  1190. .mute_stream = max98088_dai2_mute,
  1191. .no_capture_mute = 1,
  1192. };
  1193. static struct snd_soc_dai_driver max98088_dai[] = {
  1194. {
  1195. .name = "HiFi",
  1196. .playback = {
  1197. .stream_name = "HiFi Playback",
  1198. .channels_min = 1,
  1199. .channels_max = 2,
  1200. .rates = MAX98088_RATES,
  1201. .formats = MAX98088_FORMATS,
  1202. },
  1203. .capture = {
  1204. .stream_name = "HiFi Capture",
  1205. .channels_min = 1,
  1206. .channels_max = 2,
  1207. .rates = MAX98088_RATES,
  1208. .formats = MAX98088_FORMATS,
  1209. },
  1210. .ops = &max98088_dai1_ops,
  1211. },
  1212. {
  1213. .name = "Aux",
  1214. .playback = {
  1215. .stream_name = "Aux Playback",
  1216. .channels_min = 1,
  1217. .channels_max = 2,
  1218. .rates = MAX98088_RATES,
  1219. .formats = MAX98088_FORMATS,
  1220. },
  1221. .ops = &max98088_dai2_ops,
  1222. }
  1223. };
  1224. static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"};
  1225. static int max98088_get_channel(struct snd_soc_component *component, const char *name)
  1226. {
  1227. int ret;
  1228. ret = match_string(eq_mode_name, ARRAY_SIZE(eq_mode_name), name);
  1229. if (ret < 0)
  1230. dev_err(component->dev, "Bad EQ channel name '%s'\n", name);
  1231. return ret;
  1232. }
  1233. static void max98088_setup_eq1(struct snd_soc_component *component)
  1234. {
  1235. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  1236. struct max98088_pdata *pdata = max98088->pdata;
  1237. struct max98088_eq_cfg *coef_set;
  1238. int best, best_val, save, i, sel, fs;
  1239. struct max98088_cdata *cdata;
  1240. cdata = &max98088->dai[0];
  1241. if (!pdata || !max98088->eq_textcnt)
  1242. return;
  1243. /* Find the selected configuration with nearest sample rate */
  1244. fs = cdata->rate;
  1245. sel = cdata->eq_sel;
  1246. best = 0;
  1247. best_val = INT_MAX;
  1248. for (i = 0; i < pdata->eq_cfgcnt; i++) {
  1249. if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
  1250. abs(pdata->eq_cfg[i].rate - fs) < best_val) {
  1251. best = i;
  1252. best_val = abs(pdata->eq_cfg[i].rate - fs);
  1253. }
  1254. }
  1255. dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
  1256. pdata->eq_cfg[best].name,
  1257. pdata->eq_cfg[best].rate, fs);
  1258. /* Disable EQ while configuring, and save current on/off state */
  1259. save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
  1260. snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
  1261. coef_set = &pdata->eq_cfg[sel];
  1262. m98088_eq_band(component, 0, 0, coef_set->band1);
  1263. m98088_eq_band(component, 0, 1, coef_set->band2);
  1264. m98088_eq_band(component, 0, 2, coef_set->band3);
  1265. m98088_eq_band(component, 0, 3, coef_set->band4);
  1266. m98088_eq_band(component, 0, 4, coef_set->band5);
  1267. /* Restore the original on/off state */
  1268. snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
  1269. }
  1270. static void max98088_setup_eq2(struct snd_soc_component *component)
  1271. {
  1272. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  1273. struct max98088_pdata *pdata = max98088->pdata;
  1274. struct max98088_eq_cfg *coef_set;
  1275. int best, best_val, save, i, sel, fs;
  1276. struct max98088_cdata *cdata;
  1277. cdata = &max98088->dai[1];
  1278. if (!pdata || !max98088->eq_textcnt)
  1279. return;
  1280. /* Find the selected configuration with nearest sample rate */
  1281. fs = cdata->rate;
  1282. sel = cdata->eq_sel;
  1283. best = 0;
  1284. best_val = INT_MAX;
  1285. for (i = 0; i < pdata->eq_cfgcnt; i++) {
  1286. if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
  1287. abs(pdata->eq_cfg[i].rate - fs) < best_val) {
  1288. best = i;
  1289. best_val = abs(pdata->eq_cfg[i].rate - fs);
  1290. }
  1291. }
  1292. dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
  1293. pdata->eq_cfg[best].name,
  1294. pdata->eq_cfg[best].rate, fs);
  1295. /* Disable EQ while configuring, and save current on/off state */
  1296. save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
  1297. snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
  1298. coef_set = &pdata->eq_cfg[sel];
  1299. m98088_eq_band(component, 1, 0, coef_set->band1);
  1300. m98088_eq_band(component, 1, 1, coef_set->band2);
  1301. m98088_eq_band(component, 1, 2, coef_set->band3);
  1302. m98088_eq_band(component, 1, 3, coef_set->band4);
  1303. m98088_eq_band(component, 1, 4, coef_set->band5);
  1304. /* Restore the original on/off state */
  1305. snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
  1306. save);
  1307. }
  1308. static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
  1309. struct snd_ctl_elem_value *ucontrol)
  1310. {
  1311. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1312. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  1313. struct max98088_pdata *pdata = max98088->pdata;
  1314. int channel = max98088_get_channel(component, kcontrol->id.name);
  1315. struct max98088_cdata *cdata;
  1316. int sel = ucontrol->value.enumerated.item[0];
  1317. if (channel < 0)
  1318. return channel;
  1319. cdata = &max98088->dai[channel];
  1320. if (sel >= pdata->eq_cfgcnt)
  1321. return -EINVAL;
  1322. cdata->eq_sel = sel;
  1323. switch (channel) {
  1324. case 0:
  1325. max98088_setup_eq1(component);
  1326. break;
  1327. case 1:
  1328. max98088_setup_eq2(component);
  1329. break;
  1330. }
  1331. return 0;
  1332. }
  1333. static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
  1334. struct snd_ctl_elem_value *ucontrol)
  1335. {
  1336. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1337. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  1338. int channel = max98088_get_channel(component, kcontrol->id.name);
  1339. struct max98088_cdata *cdata;
  1340. if (channel < 0)
  1341. return channel;
  1342. cdata = &max98088->dai[channel];
  1343. ucontrol->value.enumerated.item[0] = cdata->eq_sel;
  1344. return 0;
  1345. }
  1346. static void max98088_handle_eq_pdata(struct snd_soc_component *component)
  1347. {
  1348. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  1349. struct max98088_pdata *pdata = max98088->pdata;
  1350. struct max98088_eq_cfg *cfg;
  1351. unsigned int cfgcnt;
  1352. int i, j;
  1353. const char **t;
  1354. int ret;
  1355. struct snd_kcontrol_new controls[] = {
  1356. SOC_ENUM_EXT((char *)eq_mode_name[0],
  1357. max98088->eq_enum,
  1358. max98088_get_eq_enum,
  1359. max98088_put_eq_enum),
  1360. SOC_ENUM_EXT((char *)eq_mode_name[1],
  1361. max98088->eq_enum,
  1362. max98088_get_eq_enum,
  1363. max98088_put_eq_enum),
  1364. };
  1365. BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name));
  1366. cfg = pdata->eq_cfg;
  1367. cfgcnt = pdata->eq_cfgcnt;
  1368. /* Setup an array of texts for the equalizer enum.
  1369. * This is based on Mark Brown's equalizer driver code.
  1370. */
  1371. max98088->eq_textcnt = 0;
  1372. max98088->eq_texts = NULL;
  1373. for (i = 0; i < cfgcnt; i++) {
  1374. for (j = 0; j < max98088->eq_textcnt; j++) {
  1375. if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
  1376. break;
  1377. }
  1378. if (j != max98088->eq_textcnt)
  1379. continue;
  1380. /* Expand the array */
  1381. t = krealloc(max98088->eq_texts,
  1382. sizeof(char *) * (max98088->eq_textcnt + 1),
  1383. GFP_KERNEL);
  1384. if (t == NULL)
  1385. continue;
  1386. /* Store the new entry */
  1387. t[max98088->eq_textcnt] = cfg[i].name;
  1388. max98088->eq_textcnt++;
  1389. max98088->eq_texts = t;
  1390. }
  1391. /* Now point the soc_enum to .texts array items */
  1392. max98088->eq_enum.texts = max98088->eq_texts;
  1393. max98088->eq_enum.items = max98088->eq_textcnt;
  1394. ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
  1395. if (ret != 0)
  1396. dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
  1397. }
  1398. static void max98088_handle_pdata(struct snd_soc_component *component)
  1399. {
  1400. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  1401. struct max98088_pdata *pdata = max98088->pdata;
  1402. u8 regval = 0;
  1403. if (!pdata) {
  1404. dev_dbg(component->dev, "No platform data\n");
  1405. return;
  1406. }
  1407. /* Configure mic for analog/digital mic mode */
  1408. if (pdata->digmic_left_mode)
  1409. regval |= M98088_DIGMIC_L;
  1410. if (pdata->digmic_right_mode)
  1411. regval |= M98088_DIGMIC_R;
  1412. max98088->digmic = (regval ? 1 : 0);
  1413. snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval);
  1414. /* Configure receiver output */
  1415. regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
  1416. snd_soc_component_update_bits(component, M98088_REG_2A_MIC_REC_CNTL,
  1417. M98088_REC_LINEMODE_MASK, regval);
  1418. /* Configure equalizers */
  1419. if (pdata->eq_cfgcnt)
  1420. max98088_handle_eq_pdata(component);
  1421. }
  1422. static int max98088_probe(struct snd_soc_component *component)
  1423. {
  1424. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  1425. struct max98088_cdata *cdata;
  1426. int ret = 0;
  1427. regcache_mark_dirty(max98088->regmap);
  1428. /* initialize private data */
  1429. max98088->sysclk = (unsigned)-1;
  1430. max98088->eq_textcnt = 0;
  1431. cdata = &max98088->dai[0];
  1432. cdata->rate = (unsigned)-1;
  1433. cdata->fmt = (unsigned)-1;
  1434. cdata->eq_sel = 0;
  1435. cdata = &max98088->dai[1];
  1436. cdata->rate = (unsigned)-1;
  1437. cdata->fmt = (unsigned)-1;
  1438. cdata->eq_sel = 0;
  1439. max98088->ina_state = 0;
  1440. max98088->inb_state = 0;
  1441. max98088->ex_mode = 0;
  1442. max98088->digmic = 0;
  1443. max98088->mic1pre = 0;
  1444. max98088->mic2pre = 0;
  1445. ret = snd_soc_component_read(component, M98088_REG_FF_REV_ID);
  1446. if (ret < 0) {
  1447. dev_err(component->dev, "Failed to read device revision: %d\n",
  1448. ret);
  1449. goto err_access;
  1450. }
  1451. dev_info(component->dev, "revision %c\n", ret - 0x40 + 'A');
  1452. snd_soc_component_write(component, M98088_REG_51_PWR_SYS, M98088_PWRSV);
  1453. snd_soc_component_write(component, M98088_REG_0F_IRQ_ENABLE, 0x00);
  1454. snd_soc_component_write(component, M98088_REG_22_MIX_DAC,
  1455. M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
  1456. M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
  1457. snd_soc_component_write(component, M98088_REG_4E_BIAS_CNTL, 0xF0);
  1458. snd_soc_component_write(component, M98088_REG_50_DAC_BIAS2, 0x0F);
  1459. snd_soc_component_write(component, M98088_REG_16_DAI1_IOCFG,
  1460. M98088_S1NORMAL|M98088_SDATA);
  1461. snd_soc_component_write(component, M98088_REG_1E_DAI2_IOCFG,
  1462. M98088_S2NORMAL|M98088_SDATA);
  1463. max98088_handle_pdata(component);
  1464. err_access:
  1465. return ret;
  1466. }
  1467. static void max98088_remove(struct snd_soc_component *component)
  1468. {
  1469. struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
  1470. kfree(max98088->eq_texts);
  1471. }
  1472. static const struct snd_soc_component_driver soc_component_dev_max98088 = {
  1473. .probe = max98088_probe,
  1474. .remove = max98088_remove,
  1475. .set_bias_level = max98088_set_bias_level,
  1476. .controls = max98088_snd_controls,
  1477. .num_controls = ARRAY_SIZE(max98088_snd_controls),
  1478. .dapm_widgets = max98088_dapm_widgets,
  1479. .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets),
  1480. .dapm_routes = max98088_audio_map,
  1481. .num_dapm_routes = ARRAY_SIZE(max98088_audio_map),
  1482. .suspend_bias_off = 1,
  1483. .idle_bias_on = 1,
  1484. .use_pmdown_time = 1,
  1485. .endianness = 1,
  1486. .non_legacy_dai_naming = 1,
  1487. };
  1488. static int max98088_i2c_probe(struct i2c_client *i2c,
  1489. const struct i2c_device_id *id)
  1490. {
  1491. struct max98088_priv *max98088;
  1492. int ret;
  1493. max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv),
  1494. GFP_KERNEL);
  1495. if (max98088 == NULL)
  1496. return -ENOMEM;
  1497. max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap);
  1498. if (IS_ERR(max98088->regmap))
  1499. return PTR_ERR(max98088->regmap);
  1500. max98088->mclk = devm_clk_get(&i2c->dev, "mclk");
  1501. if (IS_ERR(max98088->mclk))
  1502. if (PTR_ERR(max98088->mclk) == -EPROBE_DEFER)
  1503. return PTR_ERR(max98088->mclk);
  1504. max98088->devtype = id->driver_data;
  1505. i2c_set_clientdata(i2c, max98088);
  1506. max98088->pdata = i2c->dev.platform_data;
  1507. ret = devm_snd_soc_register_component(&i2c->dev,
  1508. &soc_component_dev_max98088, &max98088_dai[0], 2);
  1509. return ret;
  1510. }
  1511. static const struct i2c_device_id max98088_i2c_id[] = {
  1512. { "max98088", MAX98088 },
  1513. { "max98089", MAX98089 },
  1514. { }
  1515. };
  1516. MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
  1517. #if defined(CONFIG_OF)
  1518. static const struct of_device_id max98088_of_match[] = {
  1519. { .compatible = "maxim,max98088" },
  1520. { .compatible = "maxim,max98089" },
  1521. { }
  1522. };
  1523. MODULE_DEVICE_TABLE(of, max98088_of_match);
  1524. #endif
  1525. static struct i2c_driver max98088_i2c_driver = {
  1526. .driver = {
  1527. .name = "max98088",
  1528. .of_match_table = of_match_ptr(max98088_of_match),
  1529. },
  1530. .probe = max98088_i2c_probe,
  1531. .id_table = max98088_i2c_id,
  1532. };
  1533. module_i2c_driver(max98088_i2c_driver);
  1534. MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
  1535. MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
  1536. MODULE_LICENSE("GPL");