lm49453.c 52 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * lm49453.c - LM49453 ALSA Soc Audio driver
  4. *
  5. * Copyright (c) 2012 Texas Instruments, Inc
  6. *
  7. * Initially based on sound/soc/codecs/wm8350.c
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/pm.h>
  15. #include <linux/i2c.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/soc-dapm.h>
  23. #include <sound/tlv.h>
  24. #include <sound/jack.h>
  25. #include <sound/initval.h>
  26. #include <asm/div64.h>
  27. #include "lm49453.h"
  28. static const struct reg_default lm49453_reg_defs[] = {
  29. { 0, 0x00 },
  30. { 1, 0x00 },
  31. { 2, 0x00 },
  32. { 3, 0x00 },
  33. { 4, 0x00 },
  34. { 5, 0x00 },
  35. { 6, 0x00 },
  36. { 7, 0x00 },
  37. { 8, 0x00 },
  38. { 9, 0x00 },
  39. { 10, 0x00 },
  40. { 11, 0x00 },
  41. { 12, 0x00 },
  42. { 13, 0x00 },
  43. { 14, 0x00 },
  44. { 15, 0x00 },
  45. { 16, 0x00 },
  46. { 17, 0x00 },
  47. { 18, 0x00 },
  48. { 19, 0x00 },
  49. { 20, 0x00 },
  50. { 21, 0x00 },
  51. { 22, 0x00 },
  52. { 23, 0x00 },
  53. { 32, 0x00 },
  54. { 33, 0x00 },
  55. { 35, 0x00 },
  56. { 36, 0x00 },
  57. { 37, 0x00 },
  58. { 46, 0x00 },
  59. { 48, 0x00 },
  60. { 49, 0x00 },
  61. { 51, 0x00 },
  62. { 56, 0x00 },
  63. { 58, 0x00 },
  64. { 59, 0x00 },
  65. { 60, 0x00 },
  66. { 61, 0x00 },
  67. { 62, 0x00 },
  68. { 63, 0x00 },
  69. { 64, 0x00 },
  70. { 65, 0x00 },
  71. { 66, 0x00 },
  72. { 67, 0x00 },
  73. { 68, 0x00 },
  74. { 69, 0x00 },
  75. { 70, 0x00 },
  76. { 71, 0x00 },
  77. { 72, 0x00 },
  78. { 73, 0x00 },
  79. { 74, 0x00 },
  80. { 75, 0x00 },
  81. { 76, 0x00 },
  82. { 77, 0x00 },
  83. { 78, 0x00 },
  84. { 79, 0x00 },
  85. { 80, 0x00 },
  86. { 81, 0x00 },
  87. { 82, 0x00 },
  88. { 83, 0x00 },
  89. { 85, 0x00 },
  90. { 85, 0x00 },
  91. { 86, 0x00 },
  92. { 87, 0x00 },
  93. { 88, 0x00 },
  94. { 89, 0x00 },
  95. { 90, 0x00 },
  96. { 91, 0x00 },
  97. { 92, 0x00 },
  98. { 93, 0x00 },
  99. { 94, 0x00 },
  100. { 95, 0x00 },
  101. { 96, 0x01 },
  102. { 97, 0x00 },
  103. { 98, 0x00 },
  104. { 99, 0x00 },
  105. { 100, 0x00 },
  106. { 101, 0x00 },
  107. { 102, 0x00 },
  108. { 103, 0x01 },
  109. { 104, 0x01 },
  110. { 105, 0x00 },
  111. { 106, 0x01 },
  112. { 107, 0x00 },
  113. { 108, 0x00 },
  114. { 109, 0x00 },
  115. { 110, 0x00 },
  116. { 111, 0x02 },
  117. { 112, 0x02 },
  118. { 113, 0x00 },
  119. { 121, 0x80 },
  120. { 122, 0xBB },
  121. { 123, 0x80 },
  122. { 124, 0xBB },
  123. { 128, 0x00 },
  124. { 130, 0x00 },
  125. { 131, 0x00 },
  126. { 132, 0x00 },
  127. { 133, 0x0A },
  128. { 134, 0x0A },
  129. { 135, 0x0A },
  130. { 136, 0x0F },
  131. { 137, 0x00 },
  132. { 138, 0x73 },
  133. { 139, 0x33 },
  134. { 140, 0x73 },
  135. { 141, 0x33 },
  136. { 142, 0x73 },
  137. { 143, 0x33 },
  138. { 144, 0x73 },
  139. { 145, 0x33 },
  140. { 146, 0x73 },
  141. { 147, 0x33 },
  142. { 148, 0x73 },
  143. { 149, 0x33 },
  144. { 150, 0x73 },
  145. { 151, 0x33 },
  146. { 152, 0x00 },
  147. { 153, 0x00 },
  148. { 154, 0x00 },
  149. { 155, 0x00 },
  150. { 176, 0x00 },
  151. { 177, 0x00 },
  152. { 178, 0x00 },
  153. { 179, 0x00 },
  154. { 180, 0x00 },
  155. { 181, 0x00 },
  156. { 182, 0x00 },
  157. { 183, 0x00 },
  158. { 184, 0x00 },
  159. { 185, 0x00 },
  160. { 186, 0x00 },
  161. { 187, 0x00 },
  162. { 188, 0x00 },
  163. { 189, 0x00 },
  164. { 208, 0x06 },
  165. { 209, 0x00 },
  166. { 210, 0x08 },
  167. { 211, 0x54 },
  168. { 212, 0x14 },
  169. { 213, 0x0d },
  170. { 214, 0x0d },
  171. { 215, 0x14 },
  172. { 216, 0x60 },
  173. { 221, 0x00 },
  174. { 222, 0x00 },
  175. { 223, 0x00 },
  176. { 224, 0x00 },
  177. { 248, 0x00 },
  178. { 249, 0x00 },
  179. { 250, 0x00 },
  180. { 255, 0x00 },
  181. };
  182. /* codec private data */
  183. struct lm49453_priv {
  184. struct regmap *regmap;
  185. };
  186. /* capture path controls */
  187. static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"};
  188. static SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5,
  189. lm49453_mic2mode_text);
  190. static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"};
  191. static SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum,
  192. LM49453_P0_DIGITAL_MIC1_CONFIG_REG, 7,
  193. lm49453_dmic_cfg_text);
  194. static SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum,
  195. LM49453_P0_DIGITAL_MIC2_CONFIG_REG, 7,
  196. lm49453_dmic_cfg_text);
  197. /* MUX Controls */
  198. static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" };
  199. static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" };
  200. static SOC_ENUM_SINGLE_DECL(lm49453_adcl_enum,
  201. LM49453_P0_ANALOG_MIXER_ADC_REG, 0,
  202. lm49453_adcl_mux_text);
  203. static SOC_ENUM_SINGLE_DECL(lm49453_adcr_enum,
  204. LM49453_P0_ANALOG_MIXER_ADC_REG, 1,
  205. lm49453_adcr_mux_text);
  206. static const struct snd_kcontrol_new lm49453_adcl_mux_control =
  207. SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum);
  208. static const struct snd_kcontrol_new lm49453_adcr_mux_control =
  209. SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum);
  210. static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = {
  211. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0),
  212. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0),
  213. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0),
  214. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0),
  215. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0),
  216. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0),
  217. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0),
  218. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0),
  219. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0),
  220. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0),
  221. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0),
  222. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0),
  223. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0),
  224. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0),
  225. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0),
  226. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0),
  227. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0),
  228. };
  229. static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = {
  230. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0),
  231. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0),
  232. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0),
  233. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0),
  234. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0),
  235. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0),
  236. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0),
  237. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0),
  238. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0),
  239. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0),
  240. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0),
  241. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0),
  242. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0),
  243. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0),
  244. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0),
  245. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0),
  246. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0),
  247. };
  248. static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = {
  249. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0),
  250. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0),
  251. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0),
  252. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0),
  253. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0),
  254. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0),
  255. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0),
  256. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0),
  257. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0),
  258. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0),
  259. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0),
  260. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0),
  261. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0),
  262. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0),
  263. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0),
  264. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0),
  265. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0),
  266. };
  267. static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = {
  268. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0),
  269. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0),
  270. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0),
  271. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0),
  272. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0),
  273. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0),
  274. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0),
  275. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0),
  276. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0),
  277. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0),
  278. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0),
  279. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0),
  280. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0),
  281. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0),
  282. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0),
  283. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0),
  284. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0),
  285. };
  286. static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = {
  287. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0),
  288. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0),
  289. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0),
  290. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0),
  291. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0),
  292. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0),
  293. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0),
  294. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0),
  295. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0),
  296. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0),
  297. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0),
  298. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0),
  299. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0),
  300. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0),
  301. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0),
  302. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0),
  303. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0),
  304. };
  305. static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = {
  306. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0),
  307. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0),
  308. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0),
  309. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0),
  310. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0),
  311. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0),
  312. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0),
  313. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0),
  314. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0),
  315. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0),
  316. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0),
  317. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0),
  318. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0),
  319. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0),
  320. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0),
  321. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0),
  322. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0),
  323. };
  324. static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = {
  325. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0),
  326. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0),
  327. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0),
  328. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0),
  329. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0),
  330. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0),
  331. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0),
  332. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0),
  333. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0),
  334. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0),
  335. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0),
  336. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0),
  337. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0),
  338. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0),
  339. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0),
  340. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0),
  341. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0),
  342. };
  343. static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = {
  344. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0),
  345. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0),
  346. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0),
  347. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0),
  348. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0),
  349. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0),
  350. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0),
  351. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0),
  352. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0),
  353. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0),
  354. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0),
  355. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0),
  356. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0),
  357. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0),
  358. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0),
  359. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0),
  360. SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0),
  361. };
  362. static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = {
  363. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0),
  364. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0),
  365. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0),
  366. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0),
  367. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0),
  368. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0),
  369. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0),
  370. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0),
  371. };
  372. static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = {
  373. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0),
  374. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0),
  375. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0),
  376. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0),
  377. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0),
  378. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0),
  379. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0),
  380. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0),
  381. };
  382. static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = {
  383. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0),
  384. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0),
  385. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0),
  386. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0),
  387. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0),
  388. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0),
  389. SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0),
  390. };
  391. static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = {
  392. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0),
  393. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0),
  394. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0),
  395. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0),
  396. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0),
  397. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0),
  398. SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0),
  399. };
  400. static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = {
  401. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0),
  402. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0),
  403. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0),
  404. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0),
  405. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0),
  406. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0),
  407. SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0),
  408. };
  409. static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = {
  410. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0),
  411. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0),
  412. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0),
  413. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0),
  414. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0),
  415. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0),
  416. SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0),
  417. };
  418. static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = {
  419. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0),
  420. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0),
  421. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0),
  422. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0),
  423. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0),
  424. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0),
  425. SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0),
  426. };
  427. static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = {
  428. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0),
  429. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0),
  430. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0),
  431. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0),
  432. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0),
  433. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0),
  434. SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0),
  435. };
  436. static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = {
  437. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0),
  438. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0),
  439. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0),
  440. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0),
  441. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0),
  442. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0),
  443. SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0),
  444. SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0),
  445. };
  446. static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = {
  447. SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0),
  448. SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0),
  449. SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0),
  450. SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0),
  451. SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0),
  452. SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0),
  453. SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0),
  454. SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0),
  455. };
  456. /* TLV Declarations */
  457. static const DECLARE_TLV_DB_SCALE(adc_dac_tlv, -7650, 150, 1);
  458. static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 200, 1);
  459. static const DECLARE_TLV_DB_SCALE(port_tlv, -1800, 600, 0);
  460. static const DECLARE_TLV_DB_SCALE(stn_tlv, -7200, 150, 0);
  461. static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = {
  462. /* Sidetone supports mono only */
  463. SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG,
  464. 0, 0x3F, 0, stn_tlv),
  465. SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
  466. 0, 0x3F, 0, stn_tlv),
  467. SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG,
  468. 0, 0x3F, 0, stn_tlv),
  469. SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG,
  470. 0, 0x3F, 0, stn_tlv),
  471. SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG,
  472. 0, 0x3F, 0, stn_tlv),
  473. SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG,
  474. 0, 0x3F, 0, stn_tlv),
  475. };
  476. static const struct snd_kcontrol_new lm49453_snd_controls[] = {
  477. /* mic1 and mic2 supports mono only */
  478. SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_MICL_REG, 0, 15, 0, mic_tlv),
  479. SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_MICR_REG, 0, 15, 0, mic_tlv),
  480. SOC_SINGLE_TLV("ADCL Volume", LM49453_P0_ADC_LEVELL_REG, 0, 63,
  481. 0, adc_dac_tlv),
  482. SOC_SINGLE_TLV("ADCR Volume", LM49453_P0_ADC_LEVELR_REG, 0, 63,
  483. 0, adc_dac_tlv),
  484. SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG,
  485. LM49453_P0_DMIC1_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  486. SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG,
  487. LM49453_P0_DMIC2_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  488. SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum),
  489. SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum),
  490. SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum),
  491. /* Capture path filter enable */
  492. SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
  493. 0, 1, 0),
  494. SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
  495. 1, 1, 0),
  496. SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
  497. 2, 1, 0),
  498. SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG,
  499. LM49453_P0_DAC_HP_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  500. SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG,
  501. LM49453_P0_DAC_LO_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  502. SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG,
  503. LM49453_P0_DAC_LS_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  504. SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG,
  505. LM49453_P0_DAC_HA_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
  506. SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG,
  507. 0, 63, 0, adc_dac_tlv),
  508. SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
  509. 0, 3, 0, port_tlv),
  510. SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
  511. 2, 3, 0, port_tlv),
  512. SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
  513. 4, 3, 0, port_tlv),
  514. SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
  515. 6, 3, 0, port_tlv),
  516. SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
  517. 0, 3, 0, port_tlv),
  518. SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
  519. 2, 3, 0, port_tlv),
  520. SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
  521. 4, 3, 0, port_tlv),
  522. SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
  523. 6, 3, 0, port_tlv),
  524. SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
  525. 0, 3, 0, port_tlv),
  526. SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
  527. 2, 3, 0, port_tlv),
  528. SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
  529. 1, 1, 0),
  530. SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
  531. 1, 1, 0),
  532. SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
  533. 2, 1, 0),
  534. SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
  535. 2, 1, 0)
  536. };
  537. /* DAPM widgets */
  538. static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = {
  539. /* All end points HP,EP, LS, Lineout and Haptic */
  540. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  541. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  542. SND_SOC_DAPM_OUTPUT("EPOUT"),
  543. SND_SOC_DAPM_OUTPUT("LSOUTL"),
  544. SND_SOC_DAPM_OUTPUT("LSOUTR"),
  545. SND_SOC_DAPM_OUTPUT("LOOUTR"),
  546. SND_SOC_DAPM_OUTPUT("LOOUTL"),
  547. SND_SOC_DAPM_OUTPUT("HAOUTL"),
  548. SND_SOC_DAPM_OUTPUT("HAOUTR"),
  549. SND_SOC_DAPM_INPUT("AMIC1"),
  550. SND_SOC_DAPM_INPUT("AMIC2"),
  551. SND_SOC_DAPM_INPUT("DMIC1DAT"),
  552. SND_SOC_DAPM_INPUT("DMIC2DAT"),
  553. SND_SOC_DAPM_INPUT("AUXL"),
  554. SND_SOC_DAPM_INPUT("AUXR"),
  555. SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  556. SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  557. SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  558. SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  559. SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  560. SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  561. SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  562. SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  563. SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  564. SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  565. SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0),
  566. SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0),
  567. /* playback path driver enables */
  568. SND_SOC_DAPM_OUT_DRV("Headset Switch",
  569. LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0),
  570. SND_SOC_DAPM_OUT_DRV("Earpiece Switch",
  571. LM49453_P0_EP_REG, 0, 0, NULL, 0),
  572. SND_SOC_DAPM_OUT_DRV("Speaker Left Switch",
  573. LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0),
  574. SND_SOC_DAPM_OUT_DRV("Speaker Right Switch",
  575. LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0),
  576. SND_SOC_DAPM_OUT_DRV("Haptic Left Switch",
  577. LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0),
  578. SND_SOC_DAPM_OUT_DRV("Haptic Right Switch",
  579. LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0),
  580. /* DAC */
  581. SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0),
  582. SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0),
  583. SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0),
  584. SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0),
  585. SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0),
  586. SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0),
  587. SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0),
  588. SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0),
  589. SND_SOC_DAPM_PGA("AUXL Input",
  590. LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0),
  591. SND_SOC_DAPM_PGA("AUXR Input",
  592. LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0),
  593. SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0),
  594. /* ADC */
  595. SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0),
  596. SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0),
  597. SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0),
  598. SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0),
  599. SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0),
  600. SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0),
  601. SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0,
  602. &lm49453_adcl_mux_control),
  603. SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
  604. &lm49453_adcr_mux_control),
  605. SND_SOC_DAPM_MUX("Mic1 Input",
  606. SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control),
  607. SND_SOC_DAPM_MUX("Mic2 Input",
  608. SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control),
  609. /* AIF */
  610. SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0,
  611. LM49453_P0_PULL_CONFIG1_REG, 2, 0),
  612. SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0,
  613. LM49453_P0_PULL_CONFIG1_REG, 6, 0),
  614. SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0,
  615. LM49453_P0_PULL_CONFIG1_REG, 3, 0),
  616. SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0,
  617. LM49453_P0_PULL_CONFIG1_REG, 7, 0),
  618. /* Port1 TX controls */
  619. SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  620. SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  621. SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  622. SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  623. SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  624. SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  625. SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  626. SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  627. /* Port2 TX controls */
  628. SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  629. SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  630. /* Sidetone Mixer */
  631. SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0,
  632. lm49453_sidetone_mixer_controls,
  633. ARRAY_SIZE(lm49453_sidetone_mixer_controls)),
  634. /* DAC MIXERS */
  635. SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0,
  636. lm49453_headset_left_mixer,
  637. ARRAY_SIZE(lm49453_headset_left_mixer)),
  638. SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0,
  639. lm49453_headset_right_mixer,
  640. ARRAY_SIZE(lm49453_headset_right_mixer)),
  641. SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0,
  642. lm49453_lineout_left_mixer,
  643. ARRAY_SIZE(lm49453_lineout_left_mixer)),
  644. SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0,
  645. lm49453_lineout_right_mixer,
  646. ARRAY_SIZE(lm49453_lineout_right_mixer)),
  647. SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0,
  648. lm49453_speaker_left_mixer,
  649. ARRAY_SIZE(lm49453_speaker_left_mixer)),
  650. SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0,
  651. lm49453_speaker_right_mixer,
  652. ARRAY_SIZE(lm49453_speaker_right_mixer)),
  653. SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0,
  654. lm49453_haptic_left_mixer,
  655. ARRAY_SIZE(lm49453_haptic_left_mixer)),
  656. SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0,
  657. lm49453_haptic_right_mixer,
  658. ARRAY_SIZE(lm49453_haptic_right_mixer)),
  659. /* Capture Mixer */
  660. SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0,
  661. lm49453_port1_tx1_mixer,
  662. ARRAY_SIZE(lm49453_port1_tx1_mixer)),
  663. SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0,
  664. lm49453_port1_tx2_mixer,
  665. ARRAY_SIZE(lm49453_port1_tx2_mixer)),
  666. SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0,
  667. lm49453_port1_tx3_mixer,
  668. ARRAY_SIZE(lm49453_port1_tx3_mixer)),
  669. SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0,
  670. lm49453_port1_tx4_mixer,
  671. ARRAY_SIZE(lm49453_port1_tx4_mixer)),
  672. SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0,
  673. lm49453_port1_tx5_mixer,
  674. ARRAY_SIZE(lm49453_port1_tx5_mixer)),
  675. SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0,
  676. lm49453_port1_tx6_mixer,
  677. ARRAY_SIZE(lm49453_port1_tx6_mixer)),
  678. SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0,
  679. lm49453_port1_tx7_mixer,
  680. ARRAY_SIZE(lm49453_port1_tx7_mixer)),
  681. SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0,
  682. lm49453_port1_tx8_mixer,
  683. ARRAY_SIZE(lm49453_port1_tx8_mixer)),
  684. SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0,
  685. lm49453_port2_tx1_mixer,
  686. ARRAY_SIZE(lm49453_port2_tx1_mixer)),
  687. SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0,
  688. lm49453_port2_tx2_mixer,
  689. ARRAY_SIZE(lm49453_port2_tx2_mixer)),
  690. };
  691. static const struct snd_soc_dapm_route lm49453_audio_map[] = {
  692. /* Port SDI mapping */
  693. { "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" },
  694. { "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" },
  695. { "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" },
  696. { "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" },
  697. { "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" },
  698. { "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" },
  699. { "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" },
  700. { "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" },
  701. { "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" },
  702. { "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" },
  703. /* HP mapping */
  704. { "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  705. { "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  706. { "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  707. { "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  708. { "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  709. { "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  710. { "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  711. { "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  712. { "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  713. { "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  714. { "HPL Mixer", "ADCL Switch", "ADC Left" },
  715. { "HPL Mixer", "ADCR Switch", "ADC Right" },
  716. { "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" },
  717. { "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" },
  718. { "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" },
  719. { "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" },
  720. { "HPL Mixer", "Sidetone Switch", "Sidetone" },
  721. { "HPL DAC", NULL, "HPL Mixer" },
  722. { "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  723. { "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  724. { "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  725. { "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  726. { "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  727. { "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  728. { "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  729. { "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  730. /* Port 2 */
  731. { "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  732. { "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  733. { "HPR Mixer", "ADCL Switch", "ADC Left" },
  734. { "HPR Mixer", "ADCR Switch", "ADC Right" },
  735. { "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" },
  736. { "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" },
  737. { "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" },
  738. { "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" },
  739. { "HPR Mixer", "Sidetone Switch", "Sidetone" },
  740. { "HPR DAC", NULL, "HPR Mixer" },
  741. { "HPOUTL", "Headset Switch", "HPL DAC"},
  742. { "HPOUTR", "Headset Switch", "HPR DAC"},
  743. /* EP map */
  744. { "EPOUT", "Earpiece Switch", "HPL DAC" },
  745. /* Speaker map */
  746. { "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  747. { "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  748. { "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  749. { "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  750. { "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  751. { "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  752. { "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  753. { "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  754. /* Port 2 */
  755. { "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  756. { "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  757. { "LSL Mixer", "ADCL Switch", "ADC Left" },
  758. { "LSL Mixer", "ADCR Switch", "ADC Right" },
  759. { "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" },
  760. { "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" },
  761. { "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" },
  762. { "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" },
  763. { "LSL Mixer", "Sidetone Switch", "Sidetone" },
  764. { "LSL DAC", NULL, "LSL Mixer" },
  765. { "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  766. { "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  767. { "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  768. { "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  769. { "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  770. { "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  771. { "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  772. { "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  773. /* Port 2 */
  774. { "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  775. { "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  776. { "LSR Mixer", "ADCL Switch", "ADC Left" },
  777. { "LSR Mixer", "ADCR Switch", "ADC Right" },
  778. { "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" },
  779. { "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" },
  780. { "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" },
  781. { "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" },
  782. { "LSR Mixer", "Sidetone Switch", "Sidetone" },
  783. { "LSR DAC", NULL, "LSR Mixer" },
  784. { "LSOUTL", "Speaker Left Switch", "LSL DAC"},
  785. { "LSOUTR", "Speaker Left Switch", "LSR DAC"},
  786. /* Haptic map */
  787. { "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  788. { "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  789. { "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  790. { "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  791. { "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  792. { "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  793. { "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  794. { "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  795. /* Port 2 */
  796. { "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  797. { "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  798. { "HAL Mixer", "ADCL Switch", "ADC Left" },
  799. { "HAL Mixer", "ADCR Switch", "ADC Right" },
  800. { "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" },
  801. { "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" },
  802. { "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" },
  803. { "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" },
  804. { "HAL Mixer", "Sidetone Switch", "Sidetone" },
  805. { "HAL DAC", NULL, "HAL Mixer" },
  806. { "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  807. { "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  808. { "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  809. { "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  810. { "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  811. { "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  812. { "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  813. { "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  814. /* Port 2 */
  815. { "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  816. { "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  817. { "HAR Mixer", "ADCL Switch", "ADC Left" },
  818. { "HAR Mixer", "ADCR Switch", "ADC Right" },
  819. { "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" },
  820. { "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" },
  821. { "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" },
  822. { "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" },
  823. { "HAR Mixer", "Sideton Switch", "Sidetone" },
  824. { "HAR DAC", NULL, "HAR Mixer" },
  825. { "HAOUTL", "Haptic Left Switch", "HAL DAC" },
  826. { "HAOUTR", "Haptic Right Switch", "HAR DAC" },
  827. /* Lineout map */
  828. { "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  829. { "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  830. { "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  831. { "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  832. { "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  833. { "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  834. { "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  835. { "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  836. /* Port 2 */
  837. { "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  838. { "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  839. { "LOL Mixer", "ADCL Switch", "ADC Left" },
  840. { "LOL Mixer", "ADCR Switch", "ADC Right" },
  841. { "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" },
  842. { "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" },
  843. { "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" },
  844. { "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" },
  845. { "LOL Mixer", "Sidetone Switch", "Sidetone" },
  846. { "LOL DAC", NULL, "LOL Mixer" },
  847. { "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
  848. { "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
  849. { "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
  850. { "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
  851. { "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
  852. { "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
  853. { "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
  854. { "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
  855. /* Port 2 */
  856. { "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
  857. { "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
  858. { "LOR Mixer", "ADCL Switch", "ADC Left" },
  859. { "LOR Mixer", "ADCR Switch", "ADC Right" },
  860. { "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" },
  861. { "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" },
  862. { "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" },
  863. { "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" },
  864. { "LOR Mixer", "Sidetone Switch", "Sidetone" },
  865. { "LOR DAC", NULL, "LOR Mixer" },
  866. { "LOOUTL", NULL, "LOL DAC" },
  867. { "LOOUTR", NULL, "LOR DAC" },
  868. /* TX map */
  869. /* Port1 mappings */
  870. { "Port1_1 Mixer", "ADCL Switch", "ADC Left" },
  871. { "Port1_1 Mixer", "ADCR Switch", "ADC Right" },
  872. { "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  873. { "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  874. { "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  875. { "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  876. { "Port1_2 Mixer", "ADCL Switch", "ADC Left" },
  877. { "Port1_2 Mixer", "ADCR Switch", "ADC Right" },
  878. { "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  879. { "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  880. { "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  881. { "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  882. { "Port1_3 Mixer", "ADCL Switch", "ADC Left" },
  883. { "Port1_3 Mixer", "ADCR Switch", "ADC Right" },
  884. { "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  885. { "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  886. { "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  887. { "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  888. { "Port1_4 Mixer", "ADCL Switch", "ADC Left" },
  889. { "Port1_4 Mixer", "ADCR Switch", "ADC Right" },
  890. { "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  891. { "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  892. { "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  893. { "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  894. { "Port1_5 Mixer", "ADCL Switch", "ADC Left" },
  895. { "Port1_5 Mixer", "ADCR Switch", "ADC Right" },
  896. { "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  897. { "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  898. { "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  899. { "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  900. { "Port1_6 Mixer", "ADCL Switch", "ADC Left" },
  901. { "Port1_6 Mixer", "ADCR Switch", "ADC Right" },
  902. { "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  903. { "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  904. { "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  905. { "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  906. { "Port1_7 Mixer", "ADCL Switch", "ADC Left" },
  907. { "Port1_7 Mixer", "ADCR Switch", "ADC Right" },
  908. { "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  909. { "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  910. { "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  911. { "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  912. { "Port1_8 Mixer", "ADCL Switch", "ADC Left" },
  913. { "Port1_8 Mixer", "ADCR Switch", "ADC Right" },
  914. { "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  915. { "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  916. { "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  917. { "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  918. { "Port2_1 Mixer", "ADCL Switch", "ADC Left" },
  919. { "Port2_1 Mixer", "ADCR Switch", "ADC Right" },
  920. { "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  921. { "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  922. { "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  923. { "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  924. { "Port2_2 Mixer", "ADCL Switch", "ADC Left" },
  925. { "Port2_2 Mixer", "ADCR Switch", "ADC Right" },
  926. { "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
  927. { "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
  928. { "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
  929. { "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
  930. { "P1_1_TX", NULL, "Port1_1 Mixer" },
  931. { "P1_2_TX", NULL, "Port1_2 Mixer" },
  932. { "P1_3_TX", NULL, "Port1_3 Mixer" },
  933. { "P1_4_TX", NULL, "Port1_4 Mixer" },
  934. { "P1_5_TX", NULL, "Port1_5 Mixer" },
  935. { "P1_6_TX", NULL, "Port1_6 Mixer" },
  936. { "P1_7_TX", NULL, "Port1_7 Mixer" },
  937. { "P1_8_TX", NULL, "Port1_8 Mixer" },
  938. { "P2_1_TX", NULL, "Port2_1 Mixer" },
  939. { "P2_2_TX", NULL, "Port2_2 Mixer" },
  940. { "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"},
  941. { "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"},
  942. { "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"},
  943. { "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"},
  944. { "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"},
  945. { "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"},
  946. { "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"},
  947. { "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"},
  948. { "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"},
  949. { "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"},
  950. { "Mic1 Input", NULL, "AMIC1" },
  951. { "Mic2 Input", NULL, "AMIC2" },
  952. { "AUXL Input", NULL, "AUXL" },
  953. { "AUXR Input", NULL, "AUXR" },
  954. /* AUX connections */
  955. { "ADCL Mux", "Aux_L", "AUXL Input" },
  956. { "ADCL Mux", "MIC1", "Mic1 Input" },
  957. { "ADCR Mux", "Aux_R", "AUXR Input" },
  958. { "ADCR Mux", "MIC2", "Mic2 Input" },
  959. /* ADC connection */
  960. { "ADC Left", NULL, "ADCL Mux"},
  961. { "ADC Right", NULL, "ADCR Mux"},
  962. { "DMIC1 Left", NULL, "DMIC1DAT"},
  963. { "DMIC1 Right", NULL, "DMIC1DAT"},
  964. { "DMIC2 Left", NULL, "DMIC2DAT"},
  965. { "DMIC2 Right", NULL, "DMIC2DAT"},
  966. /* Sidetone map */
  967. { "Sidetone Mixer", NULL, "ADC Left" },
  968. { "Sidetone Mixer", NULL, "ADC Right" },
  969. { "Sidetone Mixer", NULL, "DMIC1 Left" },
  970. { "Sidetone Mixer", NULL, "DMIC1 Right" },
  971. { "Sidetone Mixer", NULL, "DMIC2 Left" },
  972. { "Sidetone Mixer", NULL, "DMIC2 Right" },
  973. { "Sidetone", "Sidetone Switch", "Sidetone Mixer" },
  974. };
  975. static int lm49453_hw_params(struct snd_pcm_substream *substream,
  976. struct snd_pcm_hw_params *params,
  977. struct snd_soc_dai *dai)
  978. {
  979. struct snd_soc_component *component = dai->component;
  980. u16 clk_div = 0;
  981. /* Setting DAC clock dividers based on substream sample rate. */
  982. switch (params_rate(params)) {
  983. case 8000:
  984. case 16000:
  985. case 32000:
  986. case 24000:
  987. case 48000:
  988. clk_div = 256;
  989. break;
  990. case 11025:
  991. case 22050:
  992. case 44100:
  993. clk_div = 216;
  994. break;
  995. case 96000:
  996. clk_div = 127;
  997. break;
  998. default:
  999. return -EINVAL;
  1000. }
  1001. snd_soc_component_write(component, LM49453_P0_ADC_CLK_DIV_REG, clk_div);
  1002. snd_soc_component_write(component, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div);
  1003. return 0;
  1004. }
  1005. static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  1006. {
  1007. struct snd_soc_component *component = codec_dai->component;
  1008. u16 aif_val;
  1009. int mode = 0;
  1010. int clk_phase = 0;
  1011. int clk_shift = 0;
  1012. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1013. case SND_SOC_DAIFMT_CBS_CFS:
  1014. aif_val = 0;
  1015. break;
  1016. case SND_SOC_DAIFMT_CBS_CFM:
  1017. aif_val = LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
  1018. break;
  1019. case SND_SOC_DAIFMT_CBM_CFS:
  1020. aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS;
  1021. break;
  1022. case SND_SOC_DAIFMT_CBM_CFM:
  1023. aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS |
  1024. LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
  1025. break;
  1026. default:
  1027. return -EINVAL;
  1028. }
  1029. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1030. case SND_SOC_DAIFMT_I2S:
  1031. break;
  1032. case SND_SOC_DAIFMT_DSP_A:
  1033. mode = 1;
  1034. clk_phase = (1 << 5);
  1035. clk_shift = 1;
  1036. break;
  1037. case SND_SOC_DAIFMT_DSP_B:
  1038. mode = 1;
  1039. clk_phase = (1 << 5);
  1040. clk_shift = 0;
  1041. break;
  1042. default:
  1043. return -EINVAL;
  1044. }
  1045. snd_soc_component_update_bits(component, LM49453_P0_AUDIO_PORT1_BASIC_REG,
  1046. LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(0)|BIT(5),
  1047. (aif_val | mode | clk_phase));
  1048. snd_soc_component_write(component, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift);
  1049. return 0;
  1050. }
  1051. static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  1052. unsigned int freq, int dir)
  1053. {
  1054. struct snd_soc_component *component = dai->component;
  1055. u16 pll_clk = 0;
  1056. switch (freq) {
  1057. case 12288000:
  1058. case 26000000:
  1059. case 19200000:
  1060. /* pll clk slection */
  1061. pll_clk = 0;
  1062. break;
  1063. case 48000:
  1064. case 32576:
  1065. /* fll clk slection */
  1066. pll_clk = BIT(4);
  1067. return 0;
  1068. default:
  1069. return -EINVAL;
  1070. }
  1071. snd_soc_component_update_bits(component, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk);
  1072. return 0;
  1073. }
  1074. static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute, int direction)
  1075. {
  1076. snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0),
  1077. (mute ? (BIT(1)|BIT(0)) : 0));
  1078. return 0;
  1079. }
  1080. static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute, int direction)
  1081. {
  1082. snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2),
  1083. (mute ? (BIT(3)|BIT(2)) : 0));
  1084. return 0;
  1085. }
  1086. static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute, int direction)
  1087. {
  1088. snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4),
  1089. (mute ? (BIT(5)|BIT(4)) : 0));
  1090. return 0;
  1091. }
  1092. static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute, int direction)
  1093. {
  1094. snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(4),
  1095. (mute ? BIT(4) : 0));
  1096. return 0;
  1097. }
  1098. static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute, int direction)
  1099. {
  1100. snd_soc_component_update_bits(dai->component, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6),
  1101. (mute ? (BIT(7)|BIT(6)) : 0));
  1102. return 0;
  1103. }
  1104. static int lm49453_set_bias_level(struct snd_soc_component *component,
  1105. enum snd_soc_bias_level level)
  1106. {
  1107. struct lm49453_priv *lm49453 = snd_soc_component_get_drvdata(component);
  1108. switch (level) {
  1109. case SND_SOC_BIAS_ON:
  1110. case SND_SOC_BIAS_PREPARE:
  1111. break;
  1112. case SND_SOC_BIAS_STANDBY:
  1113. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
  1114. regcache_sync(lm49453->regmap);
  1115. snd_soc_component_update_bits(component, LM49453_P0_PMC_SETUP_REG,
  1116. LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN);
  1117. break;
  1118. case SND_SOC_BIAS_OFF:
  1119. snd_soc_component_update_bits(component, LM49453_P0_PMC_SETUP_REG,
  1120. LM49453_PMC_SETUP_CHIP_EN, 0);
  1121. break;
  1122. }
  1123. return 0;
  1124. }
  1125. /* Formates supported by LM49453 driver. */
  1126. #define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1127. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1128. static const struct snd_soc_dai_ops lm49453_headset_dai_ops = {
  1129. .hw_params = lm49453_hw_params,
  1130. .set_sysclk = lm49453_set_dai_sysclk,
  1131. .set_fmt = lm49453_set_dai_fmt,
  1132. .mute_stream = lm49453_hp_mute,
  1133. .no_capture_mute = 1,
  1134. };
  1135. static const struct snd_soc_dai_ops lm49453_speaker_dai_ops = {
  1136. .hw_params = lm49453_hw_params,
  1137. .set_sysclk = lm49453_set_dai_sysclk,
  1138. .set_fmt = lm49453_set_dai_fmt,
  1139. .mute_stream = lm49453_ls_mute,
  1140. .no_capture_mute = 1,
  1141. };
  1142. static const struct snd_soc_dai_ops lm49453_haptic_dai_ops = {
  1143. .hw_params = lm49453_hw_params,
  1144. .set_sysclk = lm49453_set_dai_sysclk,
  1145. .set_fmt = lm49453_set_dai_fmt,
  1146. .mute_stream = lm49453_ha_mute,
  1147. .no_capture_mute = 1,
  1148. };
  1149. static const struct snd_soc_dai_ops lm49453_ep_dai_ops = {
  1150. .hw_params = lm49453_hw_params,
  1151. .set_sysclk = lm49453_set_dai_sysclk,
  1152. .set_fmt = lm49453_set_dai_fmt,
  1153. .mute_stream = lm49453_ep_mute,
  1154. .no_capture_mute = 1,
  1155. };
  1156. static const struct snd_soc_dai_ops lm49453_lineout_dai_ops = {
  1157. .hw_params = lm49453_hw_params,
  1158. .set_sysclk = lm49453_set_dai_sysclk,
  1159. .set_fmt = lm49453_set_dai_fmt,
  1160. .mute_stream = lm49453_lo_mute,
  1161. .no_capture_mute = 1,
  1162. };
  1163. /* LM49453 dai structure. */
  1164. static struct snd_soc_dai_driver lm49453_dai[] = {
  1165. {
  1166. .name = "LM49453 Headset",
  1167. .playback = {
  1168. .stream_name = "Headset",
  1169. .channels_min = 2,
  1170. .channels_max = 2,
  1171. .rates = SNDRV_PCM_RATE_8000_192000,
  1172. .formats = LM49453_FORMATS,
  1173. },
  1174. .capture = {
  1175. .stream_name = "Capture",
  1176. .channels_min = 1,
  1177. .channels_max = 5,
  1178. .rates = SNDRV_PCM_RATE_8000_192000,
  1179. .formats = LM49453_FORMATS,
  1180. },
  1181. .ops = &lm49453_headset_dai_ops,
  1182. .symmetric_rates = 1,
  1183. },
  1184. {
  1185. .name = "LM49453 Speaker",
  1186. .playback = {
  1187. .stream_name = "Speaker",
  1188. .channels_min = 2,
  1189. .channels_max = 2,
  1190. .rates = SNDRV_PCM_RATE_8000_192000,
  1191. .formats = LM49453_FORMATS,
  1192. },
  1193. .ops = &lm49453_speaker_dai_ops,
  1194. },
  1195. {
  1196. .name = "LM49453 Haptic",
  1197. .playback = {
  1198. .stream_name = "Haptic",
  1199. .channels_min = 2,
  1200. .channels_max = 2,
  1201. .rates = SNDRV_PCM_RATE_8000_192000,
  1202. .formats = LM49453_FORMATS,
  1203. },
  1204. .ops = &lm49453_haptic_dai_ops,
  1205. },
  1206. {
  1207. .name = "LM49453 Earpiece",
  1208. .playback = {
  1209. .stream_name = "Earpiece",
  1210. .channels_min = 1,
  1211. .channels_max = 1,
  1212. .rates = SNDRV_PCM_RATE_8000_192000,
  1213. .formats = LM49453_FORMATS,
  1214. },
  1215. .ops = &lm49453_ep_dai_ops,
  1216. },
  1217. {
  1218. .name = "LM49453 line out",
  1219. .playback = {
  1220. .stream_name = "Lineout",
  1221. .channels_min = 2,
  1222. .channels_max = 2,
  1223. .rates = SNDRV_PCM_RATE_8000_192000,
  1224. .formats = LM49453_FORMATS,
  1225. },
  1226. .ops = &lm49453_lineout_dai_ops,
  1227. },
  1228. };
  1229. static const struct snd_soc_component_driver soc_component_dev_lm49453 = {
  1230. .set_bias_level = lm49453_set_bias_level,
  1231. .controls = lm49453_snd_controls,
  1232. .num_controls = ARRAY_SIZE(lm49453_snd_controls),
  1233. .dapm_widgets = lm49453_dapm_widgets,
  1234. .num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets),
  1235. .dapm_routes = lm49453_audio_map,
  1236. .num_dapm_routes = ARRAY_SIZE(lm49453_audio_map),
  1237. .use_pmdown_time = 1,
  1238. .endianness = 1,
  1239. .non_legacy_dai_naming = 1,
  1240. };
  1241. static const struct regmap_config lm49453_regmap_config = {
  1242. .reg_bits = 8,
  1243. .val_bits = 8,
  1244. .max_register = LM49453_MAX_REGISTER,
  1245. .reg_defaults = lm49453_reg_defs,
  1246. .num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs),
  1247. .cache_type = REGCACHE_RBTREE,
  1248. };
  1249. static int lm49453_i2c_probe(struct i2c_client *i2c,
  1250. const struct i2c_device_id *id)
  1251. {
  1252. struct lm49453_priv *lm49453;
  1253. int ret = 0;
  1254. lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv),
  1255. GFP_KERNEL);
  1256. if (lm49453 == NULL)
  1257. return -ENOMEM;
  1258. i2c_set_clientdata(i2c, lm49453);
  1259. lm49453->regmap = devm_regmap_init_i2c(i2c, &lm49453_regmap_config);
  1260. if (IS_ERR(lm49453->regmap)) {
  1261. ret = PTR_ERR(lm49453->regmap);
  1262. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1263. ret);
  1264. return ret;
  1265. }
  1266. ret = devm_snd_soc_register_component(&i2c->dev,
  1267. &soc_component_dev_lm49453,
  1268. lm49453_dai, ARRAY_SIZE(lm49453_dai));
  1269. if (ret < 0)
  1270. dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
  1271. return ret;
  1272. }
  1273. static int lm49453_i2c_remove(struct i2c_client *client)
  1274. {
  1275. return 0;
  1276. }
  1277. static const struct i2c_device_id lm49453_i2c_id[] = {
  1278. { "lm49453", 0 },
  1279. { }
  1280. };
  1281. MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id);
  1282. static struct i2c_driver lm49453_i2c_driver = {
  1283. .driver = {
  1284. .name = "lm49453",
  1285. },
  1286. .probe = lm49453_i2c_probe,
  1287. .remove = lm49453_i2c_remove,
  1288. .id_table = lm49453_i2c_id,
  1289. };
  1290. module_i2c_driver(lm49453_i2c_driver);
  1291. MODULE_DESCRIPTION("ASoC LM49453 driver");
  1292. MODULE_AUTHOR("M R Swami Reddy <MR.Swami.Reddy@ti.com>");
  1293. MODULE_LICENSE("GPL v2");