jz4740.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // JZ4740 CODEC driver
  4. //
  5. // Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  6. #include <linux/kernel.h>
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/io.h>
  11. #include <linux/regmap.h>
  12. #include <linux/delay.h>
  13. #include <sound/core.h>
  14. #include <sound/pcm.h>
  15. #include <sound/pcm_params.h>
  16. #include <sound/initval.h>
  17. #include <sound/soc.h>
  18. #include <sound/tlv.h>
  19. #define JZ4740_REG_CODEC_1 0x0
  20. #define JZ4740_REG_CODEC_2 0x4
  21. #define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
  22. #define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
  23. #define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
  24. #define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
  25. #define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
  26. #define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
  27. #define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
  28. #define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
  29. #define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
  30. #define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
  31. #define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
  32. #define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
  33. #define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
  34. #define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
  35. #define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
  36. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
  37. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
  38. #define JZ4740_CODEC_1_SUSPEND BIT(1)
  39. #define JZ4740_CODEC_1_RESET BIT(0)
  40. #define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
  41. #define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
  42. #define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
  43. #define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
  44. #define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
  45. #define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
  46. #define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
  47. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
  48. #define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
  49. #define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
  50. #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
  51. #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
  52. #define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16
  53. #define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8
  54. #define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
  55. #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
  56. static const struct reg_default jz4740_codec_reg_defaults[] = {
  57. { JZ4740_REG_CODEC_1, 0x021b2302 },
  58. { JZ4740_REG_CODEC_2, 0x00170803 },
  59. };
  60. struct jz4740_codec {
  61. struct regmap *regmap;
  62. };
  63. static const DECLARE_TLV_DB_RANGE(jz4740_mic_tlv,
  64. 0, 2, TLV_DB_SCALE_ITEM(0, 600, 0),
  65. 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0)
  66. );
  67. static const DECLARE_TLV_DB_SCALE(jz4740_out_tlv, 0, 200, 0);
  68. static const DECLARE_TLV_DB_SCALE(jz4740_in_tlv, -3450, 150, 0);
  69. static const struct snd_kcontrol_new jz4740_codec_controls[] = {
  70. SOC_SINGLE_TLV("Master Playback Volume", JZ4740_REG_CODEC_2,
  71. JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0,
  72. jz4740_out_tlv),
  73. SOC_SINGLE_TLV("Master Capture Volume", JZ4740_REG_CODEC_2,
  74. JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0,
  75. jz4740_in_tlv),
  76. SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
  77. JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
  78. SOC_SINGLE_TLV("Mic Capture Volume", JZ4740_REG_CODEC_2,
  79. JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0,
  80. jz4740_mic_tlv),
  81. };
  82. static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
  83. SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
  84. JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
  85. SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
  86. JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
  87. };
  88. static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
  89. SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
  90. JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
  91. SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
  92. JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
  93. };
  94. static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
  95. SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
  96. JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
  97. SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
  98. JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
  99. SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
  100. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
  101. jz4740_codec_output_controls,
  102. ARRAY_SIZE(jz4740_codec_output_controls)),
  103. SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
  104. jz4740_codec_input_controls,
  105. ARRAY_SIZE(jz4740_codec_input_controls)),
  106. SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
  107. SND_SOC_DAPM_OUTPUT("LOUT"),
  108. SND_SOC_DAPM_OUTPUT("ROUT"),
  109. SND_SOC_DAPM_INPUT("MIC"),
  110. SND_SOC_DAPM_INPUT("LIN"),
  111. SND_SOC_DAPM_INPUT("RIN"),
  112. };
  113. static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
  114. {"Line Input", NULL, "LIN"},
  115. {"Line Input", NULL, "RIN"},
  116. {"Input Mixer", "Line Capture Switch", "Line Input"},
  117. {"Input Mixer", "Mic Capture Switch", "MIC"},
  118. {"ADC", NULL, "Input Mixer"},
  119. {"Output Mixer", "Bypass Switch", "Input Mixer"},
  120. {"Output Mixer", "DAC Switch", "DAC"},
  121. {"LOUT", NULL, "Output Mixer"},
  122. {"ROUT", NULL, "Output Mixer"},
  123. };
  124. static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
  125. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  126. {
  127. struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(dai->component);
  128. uint32_t val;
  129. switch (params_rate(params)) {
  130. case 8000:
  131. val = 0;
  132. break;
  133. case 11025:
  134. val = 1;
  135. break;
  136. case 12000:
  137. val = 2;
  138. break;
  139. case 16000:
  140. val = 3;
  141. break;
  142. case 22050:
  143. val = 4;
  144. break;
  145. case 24000:
  146. val = 5;
  147. break;
  148. case 32000:
  149. val = 6;
  150. break;
  151. case 44100:
  152. val = 7;
  153. break;
  154. case 48000:
  155. val = 8;
  156. break;
  157. default:
  158. return -EINVAL;
  159. }
  160. val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
  161. regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_2,
  162. JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
  163. return 0;
  164. }
  165. static const struct snd_soc_dai_ops jz4740_codec_dai_ops = {
  166. .hw_params = jz4740_codec_hw_params,
  167. };
  168. static struct snd_soc_dai_driver jz4740_codec_dai = {
  169. .name = "jz4740-hifi",
  170. .playback = {
  171. .stream_name = "Playback",
  172. .channels_min = 2,
  173. .channels_max = 2,
  174. .rates = SNDRV_PCM_RATE_8000_48000,
  175. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  176. },
  177. .capture = {
  178. .stream_name = "Capture",
  179. .channels_min = 2,
  180. .channels_max = 2,
  181. .rates = SNDRV_PCM_RATE_8000_48000,
  182. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  183. },
  184. .ops = &jz4740_codec_dai_ops,
  185. .symmetric_rates = 1,
  186. };
  187. static void jz4740_codec_wakeup(struct regmap *regmap)
  188. {
  189. regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
  190. JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
  191. udelay(2);
  192. regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
  193. JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0);
  194. regcache_sync(regmap);
  195. }
  196. static int jz4740_codec_set_bias_level(struct snd_soc_component *component,
  197. enum snd_soc_bias_level level)
  198. {
  199. struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
  200. struct regmap *regmap = jz4740_codec->regmap;
  201. unsigned int mask;
  202. unsigned int value;
  203. switch (level) {
  204. case SND_SOC_BIAS_ON:
  205. break;
  206. case SND_SOC_BIAS_PREPARE:
  207. mask = JZ4740_CODEC_1_VREF_DISABLE |
  208. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  209. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  210. value = 0;
  211. regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
  212. break;
  213. case SND_SOC_BIAS_STANDBY:
  214. /* The only way to clear the suspend flag is to reset the codec */
  215. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
  216. jz4740_codec_wakeup(regmap);
  217. mask = JZ4740_CODEC_1_VREF_DISABLE |
  218. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  219. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  220. value = JZ4740_CODEC_1_VREF_DISABLE |
  221. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  222. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  223. regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
  224. break;
  225. case SND_SOC_BIAS_OFF:
  226. mask = JZ4740_CODEC_1_SUSPEND;
  227. value = JZ4740_CODEC_1_SUSPEND;
  228. regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
  229. regcache_mark_dirty(regmap);
  230. break;
  231. default:
  232. break;
  233. }
  234. return 0;
  235. }
  236. static int jz4740_codec_dev_probe(struct snd_soc_component *component)
  237. {
  238. struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
  239. regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_1,
  240. JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
  241. return 0;
  242. }
  243. static const struct snd_soc_component_driver soc_codec_dev_jz4740_codec = {
  244. .probe = jz4740_codec_dev_probe,
  245. .set_bias_level = jz4740_codec_set_bias_level,
  246. .controls = jz4740_codec_controls,
  247. .num_controls = ARRAY_SIZE(jz4740_codec_controls),
  248. .dapm_widgets = jz4740_codec_dapm_widgets,
  249. .num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
  250. .dapm_routes = jz4740_codec_dapm_routes,
  251. .num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
  252. .suspend_bias_off = 1,
  253. .idle_bias_on = 1,
  254. .use_pmdown_time = 1,
  255. .endianness = 1,
  256. .non_legacy_dai_naming = 1,
  257. };
  258. static const struct regmap_config jz4740_codec_regmap_config = {
  259. .reg_bits = 32,
  260. .reg_stride = 4,
  261. .val_bits = 32,
  262. .max_register = JZ4740_REG_CODEC_2,
  263. .reg_defaults = jz4740_codec_reg_defaults,
  264. .num_reg_defaults = ARRAY_SIZE(jz4740_codec_reg_defaults),
  265. .cache_type = REGCACHE_RBTREE,
  266. };
  267. static int jz4740_codec_probe(struct platform_device *pdev)
  268. {
  269. int ret;
  270. struct jz4740_codec *jz4740_codec;
  271. void __iomem *base;
  272. jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec),
  273. GFP_KERNEL);
  274. if (!jz4740_codec)
  275. return -ENOMEM;
  276. base = devm_platform_ioremap_resource(pdev, 0);
  277. if (IS_ERR(base))
  278. return PTR_ERR(base);
  279. jz4740_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
  280. &jz4740_codec_regmap_config);
  281. if (IS_ERR(jz4740_codec->regmap))
  282. return PTR_ERR(jz4740_codec->regmap);
  283. platform_set_drvdata(pdev, jz4740_codec);
  284. ret = devm_snd_soc_register_component(&pdev->dev,
  285. &soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
  286. if (ret)
  287. dev_err(&pdev->dev, "Failed to register codec\n");
  288. return ret;
  289. }
  290. static const struct of_device_id jz4740_codec_of_matches[] = {
  291. { .compatible = "ingenic,jz4740-codec", },
  292. { }
  293. };
  294. MODULE_DEVICE_TABLE(of, jz4740_codec_of_matches);
  295. static struct platform_driver jz4740_codec_driver = {
  296. .probe = jz4740_codec_probe,
  297. .driver = {
  298. .name = "jz4740-codec",
  299. .of_match_table = jz4740_codec_of_matches,
  300. },
  301. };
  302. module_platform_driver(jz4740_codec_driver);
  303. MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
  304. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  305. MODULE_LICENSE("GPL v2");
  306. MODULE_ALIAS("platform:jz4740-codec");