da9055.c 49 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DA9055 ALSA Soc codec driver
  4. *
  5. * Copyright (c) 2012 Dialog Semiconductor
  6. *
  7. * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C
  8. * Written by David Chen <david.chen@diasemi.com> and
  9. * Ashish Chavan <ashish.chavan@kpitcummins.com>
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/i2c.h>
  13. #include <linux/regmap.h>
  14. #include <linux/slab.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <sound/pcm.h>
  19. #include <sound/pcm_params.h>
  20. #include <sound/soc.h>
  21. #include <sound/initval.h>
  22. #include <sound/tlv.h>
  23. #include <sound/da9055.h>
  24. /* DA9055 register space */
  25. /* Status Registers */
  26. #define DA9055_STATUS1 0x02
  27. #define DA9055_PLL_STATUS 0x03
  28. #define DA9055_AUX_L_GAIN_STATUS 0x04
  29. #define DA9055_AUX_R_GAIN_STATUS 0x05
  30. #define DA9055_MIC_L_GAIN_STATUS 0x06
  31. #define DA9055_MIC_R_GAIN_STATUS 0x07
  32. #define DA9055_MIXIN_L_GAIN_STATUS 0x08
  33. #define DA9055_MIXIN_R_GAIN_STATUS 0x09
  34. #define DA9055_ADC_L_GAIN_STATUS 0x0A
  35. #define DA9055_ADC_R_GAIN_STATUS 0x0B
  36. #define DA9055_DAC_L_GAIN_STATUS 0x0C
  37. #define DA9055_DAC_R_GAIN_STATUS 0x0D
  38. #define DA9055_HP_L_GAIN_STATUS 0x0E
  39. #define DA9055_HP_R_GAIN_STATUS 0x0F
  40. #define DA9055_LINE_GAIN_STATUS 0x10
  41. /* System Initialisation Registers */
  42. #define DA9055_CIF_CTRL 0x20
  43. #define DA9055_DIG_ROUTING_AIF 0X21
  44. #define DA9055_SR 0x22
  45. #define DA9055_REFERENCES 0x23
  46. #define DA9055_PLL_FRAC_TOP 0x24
  47. #define DA9055_PLL_FRAC_BOT 0x25
  48. #define DA9055_PLL_INTEGER 0x26
  49. #define DA9055_PLL_CTRL 0x27
  50. #define DA9055_AIF_CLK_MODE 0x28
  51. #define DA9055_AIF_CTRL 0x29
  52. #define DA9055_DIG_ROUTING_DAC 0x2A
  53. #define DA9055_ALC_CTRL1 0x2B
  54. /* Input - Gain, Select and Filter Registers */
  55. #define DA9055_AUX_L_GAIN 0x30
  56. #define DA9055_AUX_R_GAIN 0x31
  57. #define DA9055_MIXIN_L_SELECT 0x32
  58. #define DA9055_MIXIN_R_SELECT 0x33
  59. #define DA9055_MIXIN_L_GAIN 0x34
  60. #define DA9055_MIXIN_R_GAIN 0x35
  61. #define DA9055_ADC_L_GAIN 0x36
  62. #define DA9055_ADC_R_GAIN 0x37
  63. #define DA9055_ADC_FILTERS1 0x38
  64. #define DA9055_MIC_L_GAIN 0x39
  65. #define DA9055_MIC_R_GAIN 0x3A
  66. /* Output - Gain, Select and Filter Registers */
  67. #define DA9055_DAC_FILTERS5 0x40
  68. #define DA9055_DAC_FILTERS2 0x41
  69. #define DA9055_DAC_FILTERS3 0x42
  70. #define DA9055_DAC_FILTERS4 0x43
  71. #define DA9055_DAC_FILTERS1 0x44
  72. #define DA9055_DAC_L_GAIN 0x45
  73. #define DA9055_DAC_R_GAIN 0x46
  74. #define DA9055_CP_CTRL 0x47
  75. #define DA9055_HP_L_GAIN 0x48
  76. #define DA9055_HP_R_GAIN 0x49
  77. #define DA9055_LINE_GAIN 0x4A
  78. #define DA9055_MIXOUT_L_SELECT 0x4B
  79. #define DA9055_MIXOUT_R_SELECT 0x4C
  80. /* System Controller Registers */
  81. #define DA9055_SYSTEM_MODES_INPUT 0x50
  82. #define DA9055_SYSTEM_MODES_OUTPUT 0x51
  83. /* Control Registers */
  84. #define DA9055_AUX_L_CTRL 0x60
  85. #define DA9055_AUX_R_CTRL 0x61
  86. #define DA9055_MIC_BIAS_CTRL 0x62
  87. #define DA9055_MIC_L_CTRL 0x63
  88. #define DA9055_MIC_R_CTRL 0x64
  89. #define DA9055_MIXIN_L_CTRL 0x65
  90. #define DA9055_MIXIN_R_CTRL 0x66
  91. #define DA9055_ADC_L_CTRL 0x67
  92. #define DA9055_ADC_R_CTRL 0x68
  93. #define DA9055_DAC_L_CTRL 0x69
  94. #define DA9055_DAC_R_CTRL 0x6A
  95. #define DA9055_HP_L_CTRL 0x6B
  96. #define DA9055_HP_R_CTRL 0x6C
  97. #define DA9055_LINE_CTRL 0x6D
  98. #define DA9055_MIXOUT_L_CTRL 0x6E
  99. #define DA9055_MIXOUT_R_CTRL 0x6F
  100. /* Configuration Registers */
  101. #define DA9055_LDO_CTRL 0x90
  102. #define DA9055_IO_CTRL 0x91
  103. #define DA9055_GAIN_RAMP_CTRL 0x92
  104. #define DA9055_MIC_CONFIG 0x93
  105. #define DA9055_PC_COUNT 0x94
  106. #define DA9055_CP_VOL_THRESHOLD1 0x95
  107. #define DA9055_CP_DELAY 0x96
  108. #define DA9055_CP_DETECTOR 0x97
  109. #define DA9055_AIF_OFFSET 0x98
  110. #define DA9055_DIG_CTRL 0x99
  111. #define DA9055_ALC_CTRL2 0x9A
  112. #define DA9055_ALC_CTRL3 0x9B
  113. #define DA9055_ALC_NOISE 0x9C
  114. #define DA9055_ALC_TARGET_MIN 0x9D
  115. #define DA9055_ALC_TARGET_MAX 0x9E
  116. #define DA9055_ALC_GAIN_LIMITS 0x9F
  117. #define DA9055_ALC_ANA_GAIN_LIMITS 0xA0
  118. #define DA9055_ALC_ANTICLIP_CTRL 0xA1
  119. #define DA9055_ALC_ANTICLIP_LEVEL 0xA2
  120. #define DA9055_ALC_OFFSET_OP2M_L 0xA6
  121. #define DA9055_ALC_OFFSET_OP2U_L 0xA7
  122. #define DA9055_ALC_OFFSET_OP2M_R 0xAB
  123. #define DA9055_ALC_OFFSET_OP2U_R 0xAC
  124. #define DA9055_ALC_CIC_OP_LVL_CTRL 0xAD
  125. #define DA9055_ALC_CIC_OP_LVL_DATA 0xAE
  126. #define DA9055_DAC_NG_SETUP_TIME 0xAF
  127. #define DA9055_DAC_NG_OFF_THRESHOLD 0xB0
  128. #define DA9055_DAC_NG_ON_THRESHOLD 0xB1
  129. #define DA9055_DAC_NG_CTRL 0xB2
  130. /* SR bit fields */
  131. #define DA9055_SR_8000 (0x1 << 0)
  132. #define DA9055_SR_11025 (0x2 << 0)
  133. #define DA9055_SR_12000 (0x3 << 0)
  134. #define DA9055_SR_16000 (0x5 << 0)
  135. #define DA9055_SR_22050 (0x6 << 0)
  136. #define DA9055_SR_24000 (0x7 << 0)
  137. #define DA9055_SR_32000 (0x9 << 0)
  138. #define DA9055_SR_44100 (0xA << 0)
  139. #define DA9055_SR_48000 (0xB << 0)
  140. #define DA9055_SR_88200 (0xE << 0)
  141. #define DA9055_SR_96000 (0xF << 0)
  142. /* REFERENCES bit fields */
  143. #define DA9055_BIAS_EN (1 << 3)
  144. #define DA9055_VMID_EN (1 << 7)
  145. /* PLL_CTRL bit fields */
  146. #define DA9055_PLL_INDIV_10_20_MHZ (1 << 2)
  147. #define DA9055_PLL_SRM_EN (1 << 6)
  148. #define DA9055_PLL_EN (1 << 7)
  149. /* AIF_CLK_MODE bit fields */
  150. #define DA9055_AIF_BCLKS_PER_WCLK_32 (0 << 0)
  151. #define DA9055_AIF_BCLKS_PER_WCLK_64 (1 << 0)
  152. #define DA9055_AIF_BCLKS_PER_WCLK_128 (2 << 0)
  153. #define DA9055_AIF_BCLKS_PER_WCLK_256 (3 << 0)
  154. #define DA9055_AIF_CLK_EN_SLAVE_MODE (0 << 7)
  155. #define DA9055_AIF_CLK_EN_MASTER_MODE (1 << 7)
  156. /* AIF_CTRL bit fields */
  157. #define DA9055_AIF_FORMAT_I2S_MODE (0 << 0)
  158. #define DA9055_AIF_FORMAT_LEFT_J (1 << 0)
  159. #define DA9055_AIF_FORMAT_RIGHT_J (2 << 0)
  160. #define DA9055_AIF_FORMAT_DSP (3 << 0)
  161. #define DA9055_AIF_WORD_S16_LE (0 << 2)
  162. #define DA9055_AIF_WORD_S20_3LE (1 << 2)
  163. #define DA9055_AIF_WORD_S24_LE (2 << 2)
  164. #define DA9055_AIF_WORD_S32_LE (3 << 2)
  165. /* MIC_L_CTRL bit fields */
  166. #define DA9055_MIC_L_MUTE_EN (1 << 6)
  167. /* MIC_R_CTRL bit fields */
  168. #define DA9055_MIC_R_MUTE_EN (1 << 6)
  169. /* MIXIN_L_CTRL bit fields */
  170. #define DA9055_MIXIN_L_MIX_EN (1 << 3)
  171. /* MIXIN_R_CTRL bit fields */
  172. #define DA9055_MIXIN_R_MIX_EN (1 << 3)
  173. /* ADC_L_CTRL bit fields */
  174. #define DA9055_ADC_L_EN (1 << 7)
  175. /* ADC_R_CTRL bit fields */
  176. #define DA9055_ADC_R_EN (1 << 7)
  177. /* DAC_L_CTRL bit fields */
  178. #define DA9055_DAC_L_MUTE_EN (1 << 6)
  179. /* DAC_R_CTRL bit fields */
  180. #define DA9055_DAC_R_MUTE_EN (1 << 6)
  181. /* HP_L_CTRL bit fields */
  182. #define DA9055_HP_L_AMP_OE (1 << 3)
  183. /* HP_R_CTRL bit fields */
  184. #define DA9055_HP_R_AMP_OE (1 << 3)
  185. /* LINE_CTRL bit fields */
  186. #define DA9055_LINE_AMP_OE (1 << 3)
  187. /* MIXOUT_L_CTRL bit fields */
  188. #define DA9055_MIXOUT_L_MIX_EN (1 << 3)
  189. /* MIXOUT_R_CTRL bit fields */
  190. #define DA9055_MIXOUT_R_MIX_EN (1 << 3)
  191. /* MIC bias select bit fields */
  192. #define DA9055_MICBIAS2_EN (1 << 6)
  193. /* ALC_CIC_OP_LEVEL_CTRL bit fields */
  194. #define DA9055_ALC_DATA_MIDDLE (2 << 0)
  195. #define DA9055_ALC_DATA_TOP (3 << 0)
  196. #define DA9055_ALC_CIC_OP_CHANNEL_LEFT (0 << 7)
  197. #define DA9055_ALC_CIC_OP_CHANNEL_RIGHT (1 << 7)
  198. #define DA9055_AIF_BCLK_MASK (3 << 0)
  199. #define DA9055_AIF_CLK_MODE_MASK (1 << 7)
  200. #define DA9055_AIF_FORMAT_MASK (3 << 0)
  201. #define DA9055_AIF_WORD_LENGTH_MASK (3 << 2)
  202. #define DA9055_GAIN_RAMPING_EN (1 << 5)
  203. #define DA9055_MICBIAS_LEVEL_MASK (3 << 4)
  204. #define DA9055_ALC_OFFSET_15_8 0x00FF00
  205. #define DA9055_ALC_OFFSET_17_16 0x030000
  206. #define DA9055_ALC_AVG_ITERATIONS 5
  207. struct pll_div {
  208. int fref;
  209. int fout;
  210. u8 frac_top;
  211. u8 frac_bot;
  212. u8 integer;
  213. u8 mode; /* 0 = slave, 1 = master */
  214. };
  215. /* PLL divisor table */
  216. static const struct pll_div da9055_pll_div[] = {
  217. /* for MASTER mode, fs = 44.1Khz and its harmonics */
  218. {11289600, 2822400, 0x00, 0x00, 0x20, 1}, /* MCLK=11.2896Mhz */
  219. {12000000, 2822400, 0x03, 0x61, 0x1E, 1}, /* MCLK=12Mhz */
  220. {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1}, /* MCLK=12.288Mhz */
  221. {13000000, 2822400, 0x19, 0x45, 0x1B, 1}, /* MCLK=13Mhz */
  222. {13500000, 2822400, 0x18, 0x56, 0x1A, 1}, /* MCLK=13.5Mhz */
  223. {14400000, 2822400, 0x02, 0xD0, 0x19, 1}, /* MCLK=14.4Mhz */
  224. {19200000, 2822400, 0x1A, 0x1C, 0x12, 1}, /* MCLK=19.2Mhz */
  225. {19680000, 2822400, 0x0B, 0x6D, 0x12, 1}, /* MCLK=19.68Mhz */
  226. {19800000, 2822400, 0x07, 0xDD, 0x12, 1}, /* MCLK=19.8Mhz */
  227. /* for MASTER mode, fs = 48Khz and its harmonics */
  228. {11289600, 3072000, 0x1A, 0x8E, 0x22, 1}, /* MCLK=11.2896Mhz */
  229. {12000000, 3072000, 0x18, 0x93, 0x20, 1}, /* MCLK=12Mhz */
  230. {12288000, 3072000, 0x00, 0x00, 0x20, 1}, /* MCLK=12.288Mhz */
  231. {13000000, 3072000, 0x07, 0xEA, 0x1E, 1}, /* MCLK=13Mhz */
  232. {13500000, 3072000, 0x04, 0x11, 0x1D, 1}, /* MCLK=13.5Mhz */
  233. {14400000, 3072000, 0x09, 0xD0, 0x1B, 1}, /* MCLK=14.4Mhz */
  234. {19200000, 3072000, 0x0F, 0x5C, 0x14, 1}, /* MCLK=19.2Mhz */
  235. {19680000, 3072000, 0x1F, 0x60, 0x13, 1}, /* MCLK=19.68Mhz */
  236. {19800000, 3072000, 0x1B, 0x80, 0x13, 1}, /* MCLK=19.8Mhz */
  237. /* for SLAVE mode with SRM */
  238. {11289600, 2822400, 0x0D, 0x47, 0x21, 0}, /* MCLK=11.2896Mhz */
  239. {12000000, 2822400, 0x0D, 0xFA, 0x1F, 0}, /* MCLK=12Mhz */
  240. {12288000, 2822400, 0x16, 0x66, 0x1E, 0}, /* MCLK=12.288Mhz */
  241. {13000000, 2822400, 0x00, 0x98, 0x1D, 0}, /* MCLK=13Mhz */
  242. {13500000, 2822400, 0x1E, 0x33, 0x1B, 0}, /* MCLK=13.5Mhz */
  243. {14400000, 2822400, 0x06, 0x50, 0x1A, 0}, /* MCLK=14.4Mhz */
  244. {19200000, 2822400, 0x14, 0xBC, 0x13, 0}, /* MCLK=19.2Mhz */
  245. {19680000, 2822400, 0x05, 0x66, 0x13, 0}, /* MCLK=19.68Mhz */
  246. {19800000, 2822400, 0x01, 0xAE, 0x13, 0}, /* MCLK=19.8Mhz */
  247. };
  248. enum clk_src {
  249. DA9055_CLKSRC_MCLK
  250. };
  251. /* Gain and Volume */
  252. static const DECLARE_TLV_DB_RANGE(aux_vol_tlv,
  253. 0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
  254. /* -54dB to 15dB */
  255. 0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
  256. );
  257. static const DECLARE_TLV_DB_RANGE(digital_gain_tlv,
  258. 0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
  259. /* -78dB to 12dB */
  260. 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
  261. );
  262. static const DECLARE_TLV_DB_RANGE(alc_analog_gain_tlv,
  263. 0x0, 0x0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
  264. /* 0dB to 36dB */
  265. 0x01, 0x07, TLV_DB_SCALE_ITEM(0, 600, 0)
  266. );
  267. static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
  268. static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
  269. static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
  270. static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
  271. static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
  272. static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
  273. static const DECLARE_TLV_DB_SCALE(alc_gain_tlv, 0, 600, 0);
  274. /* ADC and DAC high pass filter cutoff value */
  275. static const char * const da9055_hpf_cutoff_txt[] = {
  276. "Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000"
  277. };
  278. static SOC_ENUM_SINGLE_DECL(da9055_dac_hpf_cutoff,
  279. DA9055_DAC_FILTERS1, 4, da9055_hpf_cutoff_txt);
  280. static SOC_ENUM_SINGLE_DECL(da9055_adc_hpf_cutoff,
  281. DA9055_ADC_FILTERS1, 4, da9055_hpf_cutoff_txt);
  282. /* ADC and DAC voice mode (8kHz) high pass cutoff value */
  283. static const char * const da9055_vf_cutoff_txt[] = {
  284. "2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
  285. };
  286. static SOC_ENUM_SINGLE_DECL(da9055_dac_vf_cutoff,
  287. DA9055_DAC_FILTERS1, 0, da9055_vf_cutoff_txt);
  288. static SOC_ENUM_SINGLE_DECL(da9055_adc_vf_cutoff,
  289. DA9055_ADC_FILTERS1, 0, da9055_vf_cutoff_txt);
  290. /* Gain ramping rate value */
  291. static const char * const da9055_gain_ramping_txt[] = {
  292. "nominal rate", "nominal rate * 4", "nominal rate * 8",
  293. "nominal rate / 8"
  294. };
  295. static SOC_ENUM_SINGLE_DECL(da9055_gain_ramping_rate,
  296. DA9055_GAIN_RAMP_CTRL, 0, da9055_gain_ramping_txt);
  297. /* DAC noise gate setup time value */
  298. static const char * const da9055_dac_ng_setup_time_txt[] = {
  299. "256 samples", "512 samples", "1024 samples", "2048 samples"
  300. };
  301. static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_setup_time,
  302. DA9055_DAC_NG_SETUP_TIME, 0,
  303. da9055_dac_ng_setup_time_txt);
  304. /* DAC noise gate rampup rate value */
  305. static const char * const da9055_dac_ng_rampup_txt[] = {
  306. "0.02 ms/dB", "0.16 ms/dB"
  307. };
  308. static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampup_rate,
  309. DA9055_DAC_NG_SETUP_TIME, 2,
  310. da9055_dac_ng_rampup_txt);
  311. /* DAC noise gate rampdown rate value */
  312. static const char * const da9055_dac_ng_rampdown_txt[] = {
  313. "0.64 ms/dB", "20.48 ms/dB"
  314. };
  315. static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampdown_rate,
  316. DA9055_DAC_NG_SETUP_TIME, 3,
  317. da9055_dac_ng_rampdown_txt);
  318. /* DAC soft mute rate value */
  319. static const char * const da9055_dac_soft_mute_rate_txt[] = {
  320. "1", "2", "4", "8", "16", "32", "64"
  321. };
  322. static SOC_ENUM_SINGLE_DECL(da9055_dac_soft_mute_rate,
  323. DA9055_DAC_FILTERS5, 4,
  324. da9055_dac_soft_mute_rate_txt);
  325. /* DAC routing select */
  326. static const char * const da9055_dac_src_txt[] = {
  327. "ADC output left", "ADC output right", "AIF input left",
  328. "AIF input right"
  329. };
  330. static SOC_ENUM_SINGLE_DECL(da9055_dac_l_src,
  331. DA9055_DIG_ROUTING_DAC, 0, da9055_dac_src_txt);
  332. static SOC_ENUM_SINGLE_DECL(da9055_dac_r_src,
  333. DA9055_DIG_ROUTING_DAC, 4, da9055_dac_src_txt);
  334. /* MIC PGA Left source select */
  335. static const char * const da9055_mic_l_src_txt[] = {
  336. "MIC1_P_N", "MIC1_P", "MIC1_N", "MIC2_L"
  337. };
  338. static SOC_ENUM_SINGLE_DECL(da9055_mic_l_src,
  339. DA9055_MIXIN_L_SELECT, 4, da9055_mic_l_src_txt);
  340. /* MIC PGA Right source select */
  341. static const char * const da9055_mic_r_src_txt[] = {
  342. "MIC2_R_L", "MIC2_R", "MIC2_L"
  343. };
  344. static SOC_ENUM_SINGLE_DECL(da9055_mic_r_src,
  345. DA9055_MIXIN_R_SELECT, 4, da9055_mic_r_src_txt);
  346. /* ALC Input Signal Tracking rate select */
  347. static const char * const da9055_signal_tracking_rate_txt[] = {
  348. "1/4", "1/16", "1/256", "1/65536"
  349. };
  350. static SOC_ENUM_SINGLE_DECL(da9055_integ_attack_rate,
  351. DA9055_ALC_CTRL3, 4,
  352. da9055_signal_tracking_rate_txt);
  353. static SOC_ENUM_SINGLE_DECL(da9055_integ_release_rate,
  354. DA9055_ALC_CTRL3, 6,
  355. da9055_signal_tracking_rate_txt);
  356. /* ALC Attack Rate select */
  357. static const char * const da9055_attack_rate_txt[] = {
  358. "44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs",
  359. "5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
  360. };
  361. static SOC_ENUM_SINGLE_DECL(da9055_attack_rate,
  362. DA9055_ALC_CTRL2, 0, da9055_attack_rate_txt);
  363. /* ALC Release Rate select */
  364. static const char * const da9055_release_rate_txt[] = {
  365. "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs",
  366. "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
  367. };
  368. static SOC_ENUM_SINGLE_DECL(da9055_release_rate,
  369. DA9055_ALC_CTRL2, 4, da9055_release_rate_txt);
  370. /* ALC Hold Time select */
  371. static const char * const da9055_hold_time_txt[] = {
  372. "62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
  373. "7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
  374. "253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
  375. };
  376. static SOC_ENUM_SINGLE_DECL(da9055_hold_time,
  377. DA9055_ALC_CTRL3, 0, da9055_hold_time_txt);
  378. static int da9055_get_alc_data(struct snd_soc_component *component, u8 reg_val)
  379. {
  380. int mid_data, top_data;
  381. int sum = 0;
  382. u8 iteration;
  383. for (iteration = 0; iteration < DA9055_ALC_AVG_ITERATIONS;
  384. iteration++) {
  385. /* Select the left or right channel and capture data */
  386. snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL, reg_val);
  387. /* Select middle 8 bits for read back from data register */
  388. snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL,
  389. reg_val | DA9055_ALC_DATA_MIDDLE);
  390. mid_data = snd_soc_component_read(component, DA9055_ALC_CIC_OP_LVL_DATA);
  391. /* Select top 8 bits for read back from data register */
  392. snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL,
  393. reg_val | DA9055_ALC_DATA_TOP);
  394. top_data = snd_soc_component_read(component, DA9055_ALC_CIC_OP_LVL_DATA);
  395. sum += ((mid_data << 8) | (top_data << 16));
  396. }
  397. return sum / DA9055_ALC_AVG_ITERATIONS;
  398. }
  399. static int da9055_put_alc_sw(struct snd_kcontrol *kcontrol,
  400. struct snd_ctl_elem_value *ucontrol)
  401. {
  402. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  403. u8 reg_val, adc_left, adc_right, mic_left, mic_right;
  404. int avg_left_data, avg_right_data, offset_l, offset_r;
  405. if (ucontrol->value.integer.value[0]) {
  406. /*
  407. * While enabling ALC (or ALC sync mode), calibration of the DC
  408. * offsets must be done first
  409. */
  410. /* Save current values from Mic control registers */
  411. mic_left = snd_soc_component_read(component, DA9055_MIC_L_CTRL);
  412. mic_right = snd_soc_component_read(component, DA9055_MIC_R_CTRL);
  413. /* Mute Mic PGA Left and Right */
  414. snd_soc_component_update_bits(component, DA9055_MIC_L_CTRL,
  415. DA9055_MIC_L_MUTE_EN, DA9055_MIC_L_MUTE_EN);
  416. snd_soc_component_update_bits(component, DA9055_MIC_R_CTRL,
  417. DA9055_MIC_R_MUTE_EN, DA9055_MIC_R_MUTE_EN);
  418. /* Save current values from ADC control registers */
  419. adc_left = snd_soc_component_read(component, DA9055_ADC_L_CTRL);
  420. adc_right = snd_soc_component_read(component, DA9055_ADC_R_CTRL);
  421. /* Enable ADC Left and Right */
  422. snd_soc_component_update_bits(component, DA9055_ADC_L_CTRL,
  423. DA9055_ADC_L_EN, DA9055_ADC_L_EN);
  424. snd_soc_component_update_bits(component, DA9055_ADC_R_CTRL,
  425. DA9055_ADC_R_EN, DA9055_ADC_R_EN);
  426. /* Calculate average for Left and Right data */
  427. /* Left Data */
  428. avg_left_data = da9055_get_alc_data(component,
  429. DA9055_ALC_CIC_OP_CHANNEL_LEFT);
  430. /* Right Data */
  431. avg_right_data = da9055_get_alc_data(component,
  432. DA9055_ALC_CIC_OP_CHANNEL_RIGHT);
  433. /* Calculate DC offset */
  434. offset_l = -avg_left_data;
  435. offset_r = -avg_right_data;
  436. reg_val = (offset_l & DA9055_ALC_OFFSET_15_8) >> 8;
  437. snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_L, reg_val);
  438. reg_val = (offset_l & DA9055_ALC_OFFSET_17_16) >> 16;
  439. snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_L, reg_val);
  440. reg_val = (offset_r & DA9055_ALC_OFFSET_15_8) >> 8;
  441. snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_R, reg_val);
  442. reg_val = (offset_r & DA9055_ALC_OFFSET_17_16) >> 16;
  443. snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_R, reg_val);
  444. /* Restore original values of ADC control registers */
  445. snd_soc_component_write(component, DA9055_ADC_L_CTRL, adc_left);
  446. snd_soc_component_write(component, DA9055_ADC_R_CTRL, adc_right);
  447. /* Restore original values of Mic control registers */
  448. snd_soc_component_write(component, DA9055_MIC_L_CTRL, mic_left);
  449. snd_soc_component_write(component, DA9055_MIC_R_CTRL, mic_right);
  450. }
  451. return snd_soc_put_volsw(kcontrol, ucontrol);
  452. }
  453. static const struct snd_kcontrol_new da9055_snd_controls[] = {
  454. /* Volume controls */
  455. SOC_DOUBLE_R_TLV("Mic Volume",
  456. DA9055_MIC_L_GAIN, DA9055_MIC_R_GAIN,
  457. 0, 0x7, 0, mic_vol_tlv),
  458. SOC_DOUBLE_R_TLV("Aux Volume",
  459. DA9055_AUX_L_GAIN, DA9055_AUX_R_GAIN,
  460. 0, 0x3f, 0, aux_vol_tlv),
  461. SOC_DOUBLE_R_TLV("Mixin PGA Volume",
  462. DA9055_MIXIN_L_GAIN, DA9055_MIXIN_R_GAIN,
  463. 0, 0xf, 0, mixin_gain_tlv),
  464. SOC_DOUBLE_R_TLV("ADC Volume",
  465. DA9055_ADC_L_GAIN, DA9055_ADC_R_GAIN,
  466. 0, 0x7f, 0, digital_gain_tlv),
  467. SOC_DOUBLE_R_TLV("DAC Volume",
  468. DA9055_DAC_L_GAIN, DA9055_DAC_R_GAIN,
  469. 0, 0x7f, 0, digital_gain_tlv),
  470. SOC_DOUBLE_R_TLV("Headphone Volume",
  471. DA9055_HP_L_GAIN, DA9055_HP_R_GAIN,
  472. 0, 0x3f, 0, hp_vol_tlv),
  473. SOC_SINGLE_TLV("Lineout Volume", DA9055_LINE_GAIN, 0, 0x3f, 0,
  474. lineout_vol_tlv),
  475. /* DAC Equalizer controls */
  476. SOC_SINGLE("DAC EQ Switch", DA9055_DAC_FILTERS4, 7, 1, 0),
  477. SOC_SINGLE_TLV("DAC EQ1 Volume", DA9055_DAC_FILTERS2, 0, 0xf, 0,
  478. eq_gain_tlv),
  479. SOC_SINGLE_TLV("DAC EQ2 Volume", DA9055_DAC_FILTERS2, 4, 0xf, 0,
  480. eq_gain_tlv),
  481. SOC_SINGLE_TLV("DAC EQ3 Volume", DA9055_DAC_FILTERS3, 0, 0xf, 0,
  482. eq_gain_tlv),
  483. SOC_SINGLE_TLV("DAC EQ4 Volume", DA9055_DAC_FILTERS3, 4, 0xf, 0,
  484. eq_gain_tlv),
  485. SOC_SINGLE_TLV("DAC EQ5 Volume", DA9055_DAC_FILTERS4, 0, 0xf, 0,
  486. eq_gain_tlv),
  487. /* High Pass Filter and Voice Mode controls */
  488. SOC_SINGLE("ADC HPF Switch", DA9055_ADC_FILTERS1, 7, 1, 0),
  489. SOC_ENUM("ADC HPF Cutoff", da9055_adc_hpf_cutoff),
  490. SOC_SINGLE("ADC Voice Mode Switch", DA9055_ADC_FILTERS1, 3, 1, 0),
  491. SOC_ENUM("ADC Voice Cutoff", da9055_adc_vf_cutoff),
  492. SOC_SINGLE("DAC HPF Switch", DA9055_DAC_FILTERS1, 7, 1, 0),
  493. SOC_ENUM("DAC HPF Cutoff", da9055_dac_hpf_cutoff),
  494. SOC_SINGLE("DAC Voice Mode Switch", DA9055_DAC_FILTERS1, 3, 1, 0),
  495. SOC_ENUM("DAC Voice Cutoff", da9055_dac_vf_cutoff),
  496. /* Mute controls */
  497. SOC_DOUBLE_R("Mic Switch", DA9055_MIC_L_CTRL,
  498. DA9055_MIC_R_CTRL, 6, 1, 0),
  499. SOC_DOUBLE_R("Aux Switch", DA9055_AUX_L_CTRL,
  500. DA9055_AUX_R_CTRL, 6, 1, 0),
  501. SOC_DOUBLE_R("Mixin PGA Switch", DA9055_MIXIN_L_CTRL,
  502. DA9055_MIXIN_R_CTRL, 6, 1, 0),
  503. SOC_DOUBLE_R("ADC Switch", DA9055_ADC_L_CTRL,
  504. DA9055_ADC_R_CTRL, 6, 1, 0),
  505. SOC_DOUBLE_R("Headphone Switch", DA9055_HP_L_CTRL,
  506. DA9055_HP_R_CTRL, 6, 1, 0),
  507. SOC_SINGLE("Lineout Switch", DA9055_LINE_CTRL, 6, 1, 0),
  508. SOC_SINGLE("DAC Soft Mute Switch", DA9055_DAC_FILTERS5, 7, 1, 0),
  509. SOC_ENUM("DAC Soft Mute Rate", da9055_dac_soft_mute_rate),
  510. /* Zero Cross controls */
  511. SOC_DOUBLE_R("Aux ZC Switch", DA9055_AUX_L_CTRL,
  512. DA9055_AUX_R_CTRL, 4, 1, 0),
  513. SOC_DOUBLE_R("Mixin PGA ZC Switch", DA9055_MIXIN_L_CTRL,
  514. DA9055_MIXIN_R_CTRL, 4, 1, 0),
  515. SOC_DOUBLE_R("Headphone ZC Switch", DA9055_HP_L_CTRL,
  516. DA9055_HP_R_CTRL, 4, 1, 0),
  517. SOC_SINGLE("Lineout ZC Switch", DA9055_LINE_CTRL, 4, 1, 0),
  518. /* Gain Ramping controls */
  519. SOC_DOUBLE_R("Aux Gain Ramping Switch", DA9055_AUX_L_CTRL,
  520. DA9055_AUX_R_CTRL, 5, 1, 0),
  521. SOC_DOUBLE_R("Mixin Gain Ramping Switch", DA9055_MIXIN_L_CTRL,
  522. DA9055_MIXIN_R_CTRL, 5, 1, 0),
  523. SOC_DOUBLE_R("ADC Gain Ramping Switch", DA9055_ADC_L_CTRL,
  524. DA9055_ADC_R_CTRL, 5, 1, 0),
  525. SOC_DOUBLE_R("DAC Gain Ramping Switch", DA9055_DAC_L_CTRL,
  526. DA9055_DAC_R_CTRL, 5, 1, 0),
  527. SOC_DOUBLE_R("Headphone Gain Ramping Switch", DA9055_HP_L_CTRL,
  528. DA9055_HP_R_CTRL, 5, 1, 0),
  529. SOC_SINGLE("Lineout Gain Ramping Switch", DA9055_LINE_CTRL, 5, 1, 0),
  530. SOC_ENUM("Gain Ramping Rate", da9055_gain_ramping_rate),
  531. /* DAC Noise Gate controls */
  532. SOC_SINGLE("DAC NG Switch", DA9055_DAC_NG_CTRL, 7, 1, 0),
  533. SOC_SINGLE("DAC NG ON Threshold", DA9055_DAC_NG_ON_THRESHOLD,
  534. 0, 0x7, 0),
  535. SOC_SINGLE("DAC NG OFF Threshold", DA9055_DAC_NG_OFF_THRESHOLD,
  536. 0, 0x7, 0),
  537. SOC_ENUM("DAC NG Setup Time", da9055_dac_ng_setup_time),
  538. SOC_ENUM("DAC NG Rampup Rate", da9055_dac_ng_rampup_rate),
  539. SOC_ENUM("DAC NG Rampdown Rate", da9055_dac_ng_rampdown_rate),
  540. /* DAC Invertion control */
  541. SOC_SINGLE("DAC Left Invert", DA9055_DIG_CTRL, 3, 1, 0),
  542. SOC_SINGLE("DAC Right Invert", DA9055_DIG_CTRL, 7, 1, 0),
  543. /* DMIC controls */
  544. SOC_DOUBLE_R("DMIC Switch", DA9055_MIXIN_L_SELECT,
  545. DA9055_MIXIN_R_SELECT, 7, 1, 0),
  546. /* ALC Controls */
  547. SOC_DOUBLE_EXT("ALC Switch", DA9055_ALC_CTRL1, 3, 7, 1, 0,
  548. snd_soc_get_volsw, da9055_put_alc_sw),
  549. SOC_SINGLE_EXT("ALC Sync Mode Switch", DA9055_ALC_CTRL1, 1, 1, 0,
  550. snd_soc_get_volsw, da9055_put_alc_sw),
  551. SOC_SINGLE("ALC Offset Switch", DA9055_ALC_CTRL1, 0, 1, 0),
  552. SOC_SINGLE("ALC Anticlip Mode Switch", DA9055_ALC_ANTICLIP_CTRL,
  553. 7, 1, 0),
  554. SOC_SINGLE("ALC Anticlip Level", DA9055_ALC_ANTICLIP_LEVEL,
  555. 0, 0x7f, 0),
  556. SOC_SINGLE_TLV("ALC Min Threshold Volume", DA9055_ALC_TARGET_MIN,
  557. 0, 0x3f, 1, alc_threshold_tlv),
  558. SOC_SINGLE_TLV("ALC Max Threshold Volume", DA9055_ALC_TARGET_MAX,
  559. 0, 0x3f, 1, alc_threshold_tlv),
  560. SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA9055_ALC_NOISE,
  561. 0, 0x3f, 1, alc_threshold_tlv),
  562. SOC_SINGLE_TLV("ALC Max Gain Volume", DA9055_ALC_GAIN_LIMITS,
  563. 4, 0xf, 0, alc_gain_tlv),
  564. SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA9055_ALC_GAIN_LIMITS,
  565. 0, 0xf, 0, alc_gain_tlv),
  566. SOC_SINGLE_TLV("ALC Min Analog Gain Volume",
  567. DA9055_ALC_ANA_GAIN_LIMITS,
  568. 0, 0x7, 0, alc_analog_gain_tlv),
  569. SOC_SINGLE_TLV("ALC Max Analog Gain Volume",
  570. DA9055_ALC_ANA_GAIN_LIMITS,
  571. 4, 0x7, 0, alc_analog_gain_tlv),
  572. SOC_ENUM("ALC Attack Rate", da9055_attack_rate),
  573. SOC_ENUM("ALC Release Rate", da9055_release_rate),
  574. SOC_ENUM("ALC Hold Time", da9055_hold_time),
  575. /*
  576. * Rate at which input signal envelope is tracked as the signal gets
  577. * larger
  578. */
  579. SOC_ENUM("ALC Integ Attack Rate", da9055_integ_attack_rate),
  580. /*
  581. * Rate at which input signal envelope is tracked as the signal gets
  582. * smaller
  583. */
  584. SOC_ENUM("ALC Integ Release Rate", da9055_integ_release_rate),
  585. };
  586. /* DAPM Controls */
  587. /* Mic PGA Left Source */
  588. static const struct snd_kcontrol_new da9055_mic_l_mux_controls =
  589. SOC_DAPM_ENUM("Route", da9055_mic_l_src);
  590. /* Mic PGA Right Source */
  591. static const struct snd_kcontrol_new da9055_mic_r_mux_controls =
  592. SOC_DAPM_ENUM("Route", da9055_mic_r_src);
  593. /* In Mixer Left */
  594. static const struct snd_kcontrol_new da9055_dapm_mixinl_controls[] = {
  595. SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXIN_L_SELECT, 0, 1, 0),
  596. SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_L_SELECT, 1, 1, 0),
  597. SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_L_SELECT, 2, 1, 0),
  598. };
  599. /* In Mixer Right */
  600. static const struct snd_kcontrol_new da9055_dapm_mixinr_controls[] = {
  601. SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXIN_R_SELECT, 0, 1, 0),
  602. SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_R_SELECT, 1, 1, 0),
  603. SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_R_SELECT, 2, 1, 0),
  604. SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXIN_R_SELECT, 3, 1, 0),
  605. };
  606. /* DAC Left Source */
  607. static const struct snd_kcontrol_new da9055_dac_l_mux_controls =
  608. SOC_DAPM_ENUM("Route", da9055_dac_l_src);
  609. /* DAC Right Source */
  610. static const struct snd_kcontrol_new da9055_dac_r_mux_controls =
  611. SOC_DAPM_ENUM("Route", da9055_dac_r_src);
  612. /* Out Mixer Left */
  613. static const struct snd_kcontrol_new da9055_dapm_mixoutl_controls[] = {
  614. SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXOUT_L_SELECT, 0, 1, 0),
  615. SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_L_SELECT, 1, 1, 0),
  616. SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_L_SELECT, 2, 1, 0),
  617. SOC_DAPM_SINGLE("DAC Left Switch", DA9055_MIXOUT_L_SELECT, 3, 1, 0),
  618. SOC_DAPM_SINGLE("Aux Left Invert Switch", DA9055_MIXOUT_L_SELECT,
  619. 4, 1, 0),
  620. SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_L_SELECT,
  621. 5, 1, 0),
  622. SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_L_SELECT,
  623. 6, 1, 0),
  624. };
  625. /* Out Mixer Right */
  626. static const struct snd_kcontrol_new da9055_dapm_mixoutr_controls[] = {
  627. SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXOUT_R_SELECT, 0, 1, 0),
  628. SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_R_SELECT, 1, 1, 0),
  629. SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_R_SELECT, 2, 1, 0),
  630. SOC_DAPM_SINGLE("DAC Right Switch", DA9055_MIXOUT_R_SELECT, 3, 1, 0),
  631. SOC_DAPM_SINGLE("Aux Right Invert Switch", DA9055_MIXOUT_R_SELECT,
  632. 4, 1, 0),
  633. SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_R_SELECT,
  634. 5, 1, 0),
  635. SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_R_SELECT,
  636. 6, 1, 0),
  637. };
  638. /* Headphone Output Enable */
  639. static const struct snd_kcontrol_new da9055_dapm_hp_l_control =
  640. SOC_DAPM_SINGLE("Switch", DA9055_HP_L_CTRL, 3, 1, 0);
  641. static const struct snd_kcontrol_new da9055_dapm_hp_r_control =
  642. SOC_DAPM_SINGLE("Switch", DA9055_HP_R_CTRL, 3, 1, 0);
  643. /* Lineout Output Enable */
  644. static const struct snd_kcontrol_new da9055_dapm_lineout_control =
  645. SOC_DAPM_SINGLE("Switch", DA9055_LINE_CTRL, 3, 1, 0);
  646. /* DAPM widgets */
  647. static const struct snd_soc_dapm_widget da9055_dapm_widgets[] = {
  648. /* Input Side */
  649. /* Input Lines */
  650. SND_SOC_DAPM_INPUT("MIC1"),
  651. SND_SOC_DAPM_INPUT("MIC2"),
  652. SND_SOC_DAPM_INPUT("AUXL"),
  653. SND_SOC_DAPM_INPUT("AUXR"),
  654. /* MUXs for Mic PGA source selection */
  655. SND_SOC_DAPM_MUX("Mic Left Source", SND_SOC_NOPM, 0, 0,
  656. &da9055_mic_l_mux_controls),
  657. SND_SOC_DAPM_MUX("Mic Right Source", SND_SOC_NOPM, 0, 0,
  658. &da9055_mic_r_mux_controls),
  659. /* Input PGAs */
  660. SND_SOC_DAPM_PGA("Mic Left", DA9055_MIC_L_CTRL, 7, 0, NULL, 0),
  661. SND_SOC_DAPM_PGA("Mic Right", DA9055_MIC_R_CTRL, 7, 0, NULL, 0),
  662. SND_SOC_DAPM_PGA("Aux Left", DA9055_AUX_L_CTRL, 7, 0, NULL, 0),
  663. SND_SOC_DAPM_PGA("Aux Right", DA9055_AUX_R_CTRL, 7, 0, NULL, 0),
  664. SND_SOC_DAPM_PGA("MIXIN Left", DA9055_MIXIN_L_CTRL, 7, 0, NULL, 0),
  665. SND_SOC_DAPM_PGA("MIXIN Right", DA9055_MIXIN_R_CTRL, 7, 0, NULL, 0),
  666. SND_SOC_DAPM_SUPPLY("Mic Bias", DA9055_MIC_BIAS_CTRL, 7, 0, NULL, 0),
  667. SND_SOC_DAPM_SUPPLY("AIF", DA9055_AIF_CTRL, 7, 0, NULL, 0),
  668. SND_SOC_DAPM_SUPPLY("Charge Pump", DA9055_CP_CTRL, 7, 0, NULL, 0),
  669. /* Input Mixers */
  670. SND_SOC_DAPM_MIXER("In Mixer Left", SND_SOC_NOPM, 0, 0,
  671. &da9055_dapm_mixinl_controls[0],
  672. ARRAY_SIZE(da9055_dapm_mixinl_controls)),
  673. SND_SOC_DAPM_MIXER("In Mixer Right", SND_SOC_NOPM, 0, 0,
  674. &da9055_dapm_mixinr_controls[0],
  675. ARRAY_SIZE(da9055_dapm_mixinr_controls)),
  676. /* ADCs */
  677. SND_SOC_DAPM_ADC("ADC Left", "Capture", DA9055_ADC_L_CTRL, 7, 0),
  678. SND_SOC_DAPM_ADC("ADC Right", "Capture", DA9055_ADC_R_CTRL, 7, 0),
  679. /* Output Side */
  680. /* MUXs for DAC source selection */
  681. SND_SOC_DAPM_MUX("DAC Left Source", SND_SOC_NOPM, 0, 0,
  682. &da9055_dac_l_mux_controls),
  683. SND_SOC_DAPM_MUX("DAC Right Source", SND_SOC_NOPM, 0, 0,
  684. &da9055_dac_r_mux_controls),
  685. /* AIF input */
  686. SND_SOC_DAPM_AIF_IN("AIFIN Left", "Playback", 0, SND_SOC_NOPM, 0, 0),
  687. SND_SOC_DAPM_AIF_IN("AIFIN Right", "Playback", 0, SND_SOC_NOPM, 0, 0),
  688. /* DACs */
  689. SND_SOC_DAPM_DAC("DAC Left", "Playback", DA9055_DAC_L_CTRL, 7, 0),
  690. SND_SOC_DAPM_DAC("DAC Right", "Playback", DA9055_DAC_R_CTRL, 7, 0),
  691. /* Output Mixers */
  692. SND_SOC_DAPM_MIXER("Out Mixer Left", SND_SOC_NOPM, 0, 0,
  693. &da9055_dapm_mixoutl_controls[0],
  694. ARRAY_SIZE(da9055_dapm_mixoutl_controls)),
  695. SND_SOC_DAPM_MIXER("Out Mixer Right", SND_SOC_NOPM, 0, 0,
  696. &da9055_dapm_mixoutr_controls[0],
  697. ARRAY_SIZE(da9055_dapm_mixoutr_controls)),
  698. /* Output Enable Switches */
  699. SND_SOC_DAPM_SWITCH("Headphone Left Enable", SND_SOC_NOPM, 0, 0,
  700. &da9055_dapm_hp_l_control),
  701. SND_SOC_DAPM_SWITCH("Headphone Right Enable", SND_SOC_NOPM, 0, 0,
  702. &da9055_dapm_hp_r_control),
  703. SND_SOC_DAPM_SWITCH("Lineout Enable", SND_SOC_NOPM, 0, 0,
  704. &da9055_dapm_lineout_control),
  705. /* Output PGAs */
  706. SND_SOC_DAPM_PGA("MIXOUT Left", DA9055_MIXOUT_L_CTRL, 7, 0, NULL, 0),
  707. SND_SOC_DAPM_PGA("MIXOUT Right", DA9055_MIXOUT_R_CTRL, 7, 0, NULL, 0),
  708. SND_SOC_DAPM_PGA("Lineout", DA9055_LINE_CTRL, 7, 0, NULL, 0),
  709. SND_SOC_DAPM_PGA("Headphone Left", DA9055_HP_L_CTRL, 7, 0, NULL, 0),
  710. SND_SOC_DAPM_PGA("Headphone Right", DA9055_HP_R_CTRL, 7, 0, NULL, 0),
  711. /* Output Lines */
  712. SND_SOC_DAPM_OUTPUT("HPL"),
  713. SND_SOC_DAPM_OUTPUT("HPR"),
  714. SND_SOC_DAPM_OUTPUT("LINE"),
  715. };
  716. /* DAPM audio route definition */
  717. static const struct snd_soc_dapm_route da9055_audio_map[] = {
  718. /* Dest Connecting Widget source */
  719. /* Input path */
  720. {"Mic Left Source", "MIC1_P_N", "MIC1"},
  721. {"Mic Left Source", "MIC1_P", "MIC1"},
  722. {"Mic Left Source", "MIC1_N", "MIC1"},
  723. {"Mic Left Source", "MIC2_L", "MIC2"},
  724. {"Mic Right Source", "MIC2_R_L", "MIC2"},
  725. {"Mic Right Source", "MIC2_R", "MIC2"},
  726. {"Mic Right Source", "MIC2_L", "MIC2"},
  727. {"Mic Left", NULL, "Mic Left Source"},
  728. {"Mic Right", NULL, "Mic Right Source"},
  729. {"Aux Left", NULL, "AUXL"},
  730. {"Aux Right", NULL, "AUXR"},
  731. {"In Mixer Left", "Mic Left Switch", "Mic Left"},
  732. {"In Mixer Left", "Mic Right Switch", "Mic Right"},
  733. {"In Mixer Left", "Aux Left Switch", "Aux Left"},
  734. {"In Mixer Right", "Mic Right Switch", "Mic Right"},
  735. {"In Mixer Right", "Mic Left Switch", "Mic Left"},
  736. {"In Mixer Right", "Aux Right Switch", "Aux Right"},
  737. {"In Mixer Right", "Mixin Left Switch", "MIXIN Left"},
  738. {"MIXIN Left", NULL, "In Mixer Left"},
  739. {"ADC Left", NULL, "MIXIN Left"},
  740. {"MIXIN Right", NULL, "In Mixer Right"},
  741. {"ADC Right", NULL, "MIXIN Right"},
  742. {"ADC Left", NULL, "AIF"},
  743. {"ADC Right", NULL, "AIF"},
  744. /* Output path */
  745. {"AIFIN Left", NULL, "AIF"},
  746. {"AIFIN Right", NULL, "AIF"},
  747. {"DAC Left Source", "ADC output left", "ADC Left"},
  748. {"DAC Left Source", "ADC output right", "ADC Right"},
  749. {"DAC Left Source", "AIF input left", "AIFIN Left"},
  750. {"DAC Left Source", "AIF input right", "AIFIN Right"},
  751. {"DAC Right Source", "ADC output left", "ADC Left"},
  752. {"DAC Right Source", "ADC output right", "ADC Right"},
  753. {"DAC Right Source", "AIF input left", "AIFIN Left"},
  754. {"DAC Right Source", "AIF input right", "AIFIN Right"},
  755. {"DAC Left", NULL, "DAC Left Source"},
  756. {"DAC Right", NULL, "DAC Right Source"},
  757. {"Out Mixer Left", "Aux Left Switch", "Aux Left"},
  758. {"Out Mixer Left", "Mixin Left Switch", "MIXIN Left"},
  759. {"Out Mixer Left", "Mixin Right Switch", "MIXIN Right"},
  760. {"Out Mixer Left", "Aux Left Invert Switch", "Aux Left"},
  761. {"Out Mixer Left", "Mixin Left Invert Switch", "MIXIN Left"},
  762. {"Out Mixer Left", "Mixin Right Invert Switch", "MIXIN Right"},
  763. {"Out Mixer Left", "DAC Left Switch", "DAC Left"},
  764. {"Out Mixer Right", "Aux Right Switch", "Aux Right"},
  765. {"Out Mixer Right", "Mixin Right Switch", "MIXIN Right"},
  766. {"Out Mixer Right", "Mixin Left Switch", "MIXIN Left"},
  767. {"Out Mixer Right", "Aux Right Invert Switch", "Aux Right"},
  768. {"Out Mixer Right", "Mixin Right Invert Switch", "MIXIN Right"},
  769. {"Out Mixer Right", "Mixin Left Invert Switch", "MIXIN Left"},
  770. {"Out Mixer Right", "DAC Right Switch", "DAC Right"},
  771. {"MIXOUT Left", NULL, "Out Mixer Left"},
  772. {"Headphone Left Enable", "Switch", "MIXOUT Left"},
  773. {"Headphone Left", NULL, "Headphone Left Enable"},
  774. {"Headphone Left", NULL, "Charge Pump"},
  775. {"HPL", NULL, "Headphone Left"},
  776. {"MIXOUT Right", NULL, "Out Mixer Right"},
  777. {"Headphone Right Enable", "Switch", "MIXOUT Right"},
  778. {"Headphone Right", NULL, "Headphone Right Enable"},
  779. {"Headphone Right", NULL, "Charge Pump"},
  780. {"HPR", NULL, "Headphone Right"},
  781. {"MIXOUT Right", NULL, "Out Mixer Right"},
  782. {"Lineout Enable", "Switch", "MIXOUT Right"},
  783. {"Lineout", NULL, "Lineout Enable"},
  784. {"LINE", NULL, "Lineout"},
  785. };
  786. /* Codec private data */
  787. struct da9055_priv {
  788. struct regmap *regmap;
  789. unsigned int mclk_rate;
  790. int master;
  791. struct da9055_platform_data *pdata;
  792. };
  793. static const struct reg_default da9055_reg_defaults[] = {
  794. { 0x21, 0x10 },
  795. { 0x22, 0x0A },
  796. { 0x23, 0x00 },
  797. { 0x24, 0x00 },
  798. { 0x25, 0x00 },
  799. { 0x26, 0x00 },
  800. { 0x27, 0x0C },
  801. { 0x28, 0x01 },
  802. { 0x29, 0x08 },
  803. { 0x2A, 0x32 },
  804. { 0x2B, 0x00 },
  805. { 0x30, 0x35 },
  806. { 0x31, 0x35 },
  807. { 0x32, 0x00 },
  808. { 0x33, 0x00 },
  809. { 0x34, 0x03 },
  810. { 0x35, 0x03 },
  811. { 0x36, 0x6F },
  812. { 0x37, 0x6F },
  813. { 0x38, 0x80 },
  814. { 0x39, 0x01 },
  815. { 0x3A, 0x01 },
  816. { 0x40, 0x00 },
  817. { 0x41, 0x88 },
  818. { 0x42, 0x88 },
  819. { 0x43, 0x08 },
  820. { 0x44, 0x80 },
  821. { 0x45, 0x6F },
  822. { 0x46, 0x6F },
  823. { 0x47, 0x61 },
  824. { 0x48, 0x35 },
  825. { 0x49, 0x35 },
  826. { 0x4A, 0x35 },
  827. { 0x4B, 0x00 },
  828. { 0x4C, 0x00 },
  829. { 0x60, 0x44 },
  830. { 0x61, 0x44 },
  831. { 0x62, 0x00 },
  832. { 0x63, 0x40 },
  833. { 0x64, 0x40 },
  834. { 0x65, 0x40 },
  835. { 0x66, 0x40 },
  836. { 0x67, 0x40 },
  837. { 0x68, 0x40 },
  838. { 0x69, 0x48 },
  839. { 0x6A, 0x40 },
  840. { 0x6B, 0x41 },
  841. { 0x6C, 0x40 },
  842. { 0x6D, 0x40 },
  843. { 0x6E, 0x10 },
  844. { 0x6F, 0x10 },
  845. { 0x90, 0x80 },
  846. { 0x92, 0x02 },
  847. { 0x93, 0x00 },
  848. { 0x99, 0x00 },
  849. { 0x9A, 0x00 },
  850. { 0x9B, 0x00 },
  851. { 0x9C, 0x3F },
  852. { 0x9D, 0x00 },
  853. { 0x9E, 0x3F },
  854. { 0x9F, 0xFF },
  855. { 0xA0, 0x71 },
  856. { 0xA1, 0x00 },
  857. { 0xA2, 0x00 },
  858. { 0xA6, 0x00 },
  859. { 0xA7, 0x00 },
  860. { 0xAB, 0x00 },
  861. { 0xAC, 0x00 },
  862. { 0xAD, 0x00 },
  863. { 0xAF, 0x08 },
  864. { 0xB0, 0x00 },
  865. { 0xB1, 0x00 },
  866. { 0xB2, 0x00 },
  867. };
  868. static bool da9055_volatile_register(struct device *dev,
  869. unsigned int reg)
  870. {
  871. switch (reg) {
  872. case DA9055_STATUS1:
  873. case DA9055_PLL_STATUS:
  874. case DA9055_AUX_L_GAIN_STATUS:
  875. case DA9055_AUX_R_GAIN_STATUS:
  876. case DA9055_MIC_L_GAIN_STATUS:
  877. case DA9055_MIC_R_GAIN_STATUS:
  878. case DA9055_MIXIN_L_GAIN_STATUS:
  879. case DA9055_MIXIN_R_GAIN_STATUS:
  880. case DA9055_ADC_L_GAIN_STATUS:
  881. case DA9055_ADC_R_GAIN_STATUS:
  882. case DA9055_DAC_L_GAIN_STATUS:
  883. case DA9055_DAC_R_GAIN_STATUS:
  884. case DA9055_HP_L_GAIN_STATUS:
  885. case DA9055_HP_R_GAIN_STATUS:
  886. case DA9055_LINE_GAIN_STATUS:
  887. case DA9055_ALC_CIC_OP_LVL_DATA:
  888. return true;
  889. default:
  890. return false;
  891. }
  892. }
  893. /* Set DAI word length */
  894. static int da9055_hw_params(struct snd_pcm_substream *substream,
  895. struct snd_pcm_hw_params *params,
  896. struct snd_soc_dai *dai)
  897. {
  898. struct snd_soc_component *component = dai->component;
  899. struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
  900. u8 aif_ctrl, fs;
  901. u32 sysclk;
  902. switch (params_width(params)) {
  903. case 16:
  904. aif_ctrl = DA9055_AIF_WORD_S16_LE;
  905. break;
  906. case 20:
  907. aif_ctrl = DA9055_AIF_WORD_S20_3LE;
  908. break;
  909. case 24:
  910. aif_ctrl = DA9055_AIF_WORD_S24_LE;
  911. break;
  912. case 32:
  913. aif_ctrl = DA9055_AIF_WORD_S32_LE;
  914. break;
  915. default:
  916. return -EINVAL;
  917. }
  918. /* Set AIF format */
  919. snd_soc_component_update_bits(component, DA9055_AIF_CTRL, DA9055_AIF_WORD_LENGTH_MASK,
  920. aif_ctrl);
  921. switch (params_rate(params)) {
  922. case 8000:
  923. fs = DA9055_SR_8000;
  924. sysclk = 3072000;
  925. break;
  926. case 11025:
  927. fs = DA9055_SR_11025;
  928. sysclk = 2822400;
  929. break;
  930. case 12000:
  931. fs = DA9055_SR_12000;
  932. sysclk = 3072000;
  933. break;
  934. case 16000:
  935. fs = DA9055_SR_16000;
  936. sysclk = 3072000;
  937. break;
  938. case 22050:
  939. fs = DA9055_SR_22050;
  940. sysclk = 2822400;
  941. break;
  942. case 32000:
  943. fs = DA9055_SR_32000;
  944. sysclk = 3072000;
  945. break;
  946. case 44100:
  947. fs = DA9055_SR_44100;
  948. sysclk = 2822400;
  949. break;
  950. case 48000:
  951. fs = DA9055_SR_48000;
  952. sysclk = 3072000;
  953. break;
  954. case 88200:
  955. fs = DA9055_SR_88200;
  956. sysclk = 2822400;
  957. break;
  958. case 96000:
  959. fs = DA9055_SR_96000;
  960. sysclk = 3072000;
  961. break;
  962. default:
  963. return -EINVAL;
  964. }
  965. if (da9055->mclk_rate) {
  966. /* PLL Mode, Write actual FS */
  967. snd_soc_component_write(component, DA9055_SR, fs);
  968. } else {
  969. /*
  970. * Non-PLL Mode
  971. * When PLL is bypassed, chip assumes constant MCLK of
  972. * 12.288MHz and uses sample rate value to divide this MCLK
  973. * to derive its sys clk. As sys clk has to be 256 * Fs, we
  974. * need to write constant sample rate i.e. 48KHz.
  975. */
  976. snd_soc_component_write(component, DA9055_SR, DA9055_SR_48000);
  977. }
  978. if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) {
  979. /* PLL Mode */
  980. if (!da9055->master) {
  981. /* PLL slave mode, enable PLL and also SRM */
  982. snd_soc_component_update_bits(component, DA9055_PLL_CTRL,
  983. DA9055_PLL_EN | DA9055_PLL_SRM_EN,
  984. DA9055_PLL_EN | DA9055_PLL_SRM_EN);
  985. } else {
  986. /* PLL master mode, only enable PLL */
  987. snd_soc_component_update_bits(component, DA9055_PLL_CTRL,
  988. DA9055_PLL_EN, DA9055_PLL_EN);
  989. }
  990. } else {
  991. /* Non PLL Mode, disable PLL */
  992. snd_soc_component_update_bits(component, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
  993. }
  994. return 0;
  995. }
  996. /* Set DAI mode and Format */
  997. static int da9055_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  998. {
  999. struct snd_soc_component *component = codec_dai->component;
  1000. struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
  1001. u8 aif_clk_mode, aif_ctrl, mode;
  1002. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1003. case SND_SOC_DAIFMT_CBM_CFM:
  1004. /* DA9055 in I2S Master Mode */
  1005. mode = 1;
  1006. aif_clk_mode = DA9055_AIF_CLK_EN_MASTER_MODE;
  1007. break;
  1008. case SND_SOC_DAIFMT_CBS_CFS:
  1009. /* DA9055 in I2S Slave Mode */
  1010. mode = 0;
  1011. aif_clk_mode = DA9055_AIF_CLK_EN_SLAVE_MODE;
  1012. break;
  1013. default:
  1014. return -EINVAL;
  1015. }
  1016. /* Don't allow change of mode if PLL is enabled */
  1017. if ((snd_soc_component_read(component, DA9055_PLL_CTRL) & DA9055_PLL_EN) &&
  1018. (da9055->master != mode))
  1019. return -EINVAL;
  1020. da9055->master = mode;
  1021. /* Only I2S is supported */
  1022. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1023. case SND_SOC_DAIFMT_I2S:
  1024. aif_ctrl = DA9055_AIF_FORMAT_I2S_MODE;
  1025. break;
  1026. case SND_SOC_DAIFMT_LEFT_J:
  1027. aif_ctrl = DA9055_AIF_FORMAT_LEFT_J;
  1028. break;
  1029. case SND_SOC_DAIFMT_RIGHT_J:
  1030. aif_ctrl = DA9055_AIF_FORMAT_RIGHT_J;
  1031. break;
  1032. case SND_SOC_DAIFMT_DSP_A:
  1033. aif_ctrl = DA9055_AIF_FORMAT_DSP;
  1034. break;
  1035. default:
  1036. return -EINVAL;
  1037. }
  1038. /* By default only 32 BCLK per WCLK is supported */
  1039. aif_clk_mode |= DA9055_AIF_BCLKS_PER_WCLK_32;
  1040. snd_soc_component_update_bits(component, DA9055_AIF_CLK_MODE,
  1041. (DA9055_AIF_CLK_MODE_MASK | DA9055_AIF_BCLK_MASK),
  1042. aif_clk_mode);
  1043. snd_soc_component_update_bits(component, DA9055_AIF_CTRL, DA9055_AIF_FORMAT_MASK,
  1044. aif_ctrl);
  1045. return 0;
  1046. }
  1047. static int da9055_mute(struct snd_soc_dai *dai, int mute, int direction)
  1048. {
  1049. struct snd_soc_component *component = dai->component;
  1050. if (mute) {
  1051. snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
  1052. DA9055_DAC_L_MUTE_EN, DA9055_DAC_L_MUTE_EN);
  1053. snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
  1054. DA9055_DAC_R_MUTE_EN, DA9055_DAC_R_MUTE_EN);
  1055. } else {
  1056. snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
  1057. DA9055_DAC_L_MUTE_EN, 0);
  1058. snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
  1059. DA9055_DAC_R_MUTE_EN, 0);
  1060. }
  1061. return 0;
  1062. }
  1063. #define DA9055_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1064. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1065. static int da9055_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1066. int clk_id, unsigned int freq, int dir)
  1067. {
  1068. struct snd_soc_component *component = codec_dai->component;
  1069. struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
  1070. switch (clk_id) {
  1071. case DA9055_CLKSRC_MCLK:
  1072. switch (freq) {
  1073. case 11289600:
  1074. case 12000000:
  1075. case 12288000:
  1076. case 13000000:
  1077. case 13500000:
  1078. case 14400000:
  1079. case 19200000:
  1080. case 19680000:
  1081. case 19800000:
  1082. da9055->mclk_rate = freq;
  1083. return 0;
  1084. default:
  1085. dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
  1086. freq);
  1087. return -EINVAL;
  1088. }
  1089. break;
  1090. default:
  1091. dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
  1092. return -EINVAL;
  1093. }
  1094. }
  1095. /*
  1096. * da9055_set_dai_pll : Configure the codec PLL
  1097. * @param codec_dai : Pointer to codec DAI
  1098. * @param pll_id : da9055 has only one pll, so pll_id is always zero
  1099. * @param fref : Input MCLK frequency
  1100. * @param fout : FsDM value
  1101. * @return int : Zero for success, negative error code for error
  1102. *
  1103. * Note: Supported PLL input frequencies are 11.2896MHz, 12MHz, 12.288MHz,
  1104. * 13MHz, 13.5MHz, 14.4MHz, 19.2MHz, 19.6MHz and 19.8MHz
  1105. */
  1106. static int da9055_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
  1107. int source, unsigned int fref, unsigned int fout)
  1108. {
  1109. struct snd_soc_component *component = codec_dai->component;
  1110. struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
  1111. u8 pll_frac_top, pll_frac_bot, pll_integer, cnt;
  1112. /* Disable PLL before setting the divisors */
  1113. snd_soc_component_update_bits(component, DA9055_PLL_CTRL, DA9055_PLL_EN, 0);
  1114. /* In slave mode, there is only one set of divisors */
  1115. if (!da9055->master && (fout != 2822400))
  1116. goto pll_err;
  1117. /* Search pll div array for correct divisors */
  1118. for (cnt = 0; cnt < ARRAY_SIZE(da9055_pll_div); cnt++) {
  1119. /* Check fref, mode and fout */
  1120. if ((fref == da9055_pll_div[cnt].fref) &&
  1121. (da9055->master == da9055_pll_div[cnt].mode) &&
  1122. (fout == da9055_pll_div[cnt].fout)) {
  1123. /* All match, pick up divisors */
  1124. pll_frac_top = da9055_pll_div[cnt].frac_top;
  1125. pll_frac_bot = da9055_pll_div[cnt].frac_bot;
  1126. pll_integer = da9055_pll_div[cnt].integer;
  1127. break;
  1128. }
  1129. }
  1130. if (cnt >= ARRAY_SIZE(da9055_pll_div))
  1131. goto pll_err;
  1132. /* Write PLL dividers */
  1133. snd_soc_component_write(component, DA9055_PLL_FRAC_TOP, pll_frac_top);
  1134. snd_soc_component_write(component, DA9055_PLL_FRAC_BOT, pll_frac_bot);
  1135. snd_soc_component_write(component, DA9055_PLL_INTEGER, pll_integer);
  1136. return 0;
  1137. pll_err:
  1138. dev_err(codec_dai->dev, "Error in setting up PLL\n");
  1139. return -EINVAL;
  1140. }
  1141. /* DAI operations */
  1142. static const struct snd_soc_dai_ops da9055_dai_ops = {
  1143. .hw_params = da9055_hw_params,
  1144. .set_fmt = da9055_set_dai_fmt,
  1145. .set_sysclk = da9055_set_dai_sysclk,
  1146. .set_pll = da9055_set_dai_pll,
  1147. .mute_stream = da9055_mute,
  1148. .no_capture_mute = 1,
  1149. };
  1150. static struct snd_soc_dai_driver da9055_dai = {
  1151. .name = "da9055-hifi",
  1152. /* Playback Capabilities */
  1153. .playback = {
  1154. .stream_name = "Playback",
  1155. .channels_min = 1,
  1156. .channels_max = 2,
  1157. .rates = SNDRV_PCM_RATE_8000_96000,
  1158. .formats = DA9055_FORMATS,
  1159. },
  1160. /* Capture Capabilities */
  1161. .capture = {
  1162. .stream_name = "Capture",
  1163. .channels_min = 1,
  1164. .channels_max = 2,
  1165. .rates = SNDRV_PCM_RATE_8000_96000,
  1166. .formats = DA9055_FORMATS,
  1167. },
  1168. .ops = &da9055_dai_ops,
  1169. .symmetric_rates = 1,
  1170. };
  1171. static int da9055_set_bias_level(struct snd_soc_component *component,
  1172. enum snd_soc_bias_level level)
  1173. {
  1174. switch (level) {
  1175. case SND_SOC_BIAS_ON:
  1176. case SND_SOC_BIAS_PREPARE:
  1177. break;
  1178. case SND_SOC_BIAS_STANDBY:
  1179. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  1180. /* Enable VMID reference & master bias */
  1181. snd_soc_component_update_bits(component, DA9055_REFERENCES,
  1182. DA9055_VMID_EN | DA9055_BIAS_EN,
  1183. DA9055_VMID_EN | DA9055_BIAS_EN);
  1184. }
  1185. break;
  1186. case SND_SOC_BIAS_OFF:
  1187. /* Disable VMID reference & master bias */
  1188. snd_soc_component_update_bits(component, DA9055_REFERENCES,
  1189. DA9055_VMID_EN | DA9055_BIAS_EN, 0);
  1190. break;
  1191. }
  1192. return 0;
  1193. }
  1194. static int da9055_probe(struct snd_soc_component *component)
  1195. {
  1196. struct da9055_priv *da9055 = snd_soc_component_get_drvdata(component);
  1197. /* Enable all Gain Ramps */
  1198. snd_soc_component_update_bits(component, DA9055_AUX_L_CTRL,
  1199. DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
  1200. snd_soc_component_update_bits(component, DA9055_AUX_R_CTRL,
  1201. DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
  1202. snd_soc_component_update_bits(component, DA9055_MIXIN_L_CTRL,
  1203. DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
  1204. snd_soc_component_update_bits(component, DA9055_MIXIN_R_CTRL,
  1205. DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
  1206. snd_soc_component_update_bits(component, DA9055_ADC_L_CTRL,
  1207. DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
  1208. snd_soc_component_update_bits(component, DA9055_ADC_R_CTRL,
  1209. DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
  1210. snd_soc_component_update_bits(component, DA9055_DAC_L_CTRL,
  1211. DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
  1212. snd_soc_component_update_bits(component, DA9055_DAC_R_CTRL,
  1213. DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
  1214. snd_soc_component_update_bits(component, DA9055_HP_L_CTRL,
  1215. DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
  1216. snd_soc_component_update_bits(component, DA9055_HP_R_CTRL,
  1217. DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
  1218. snd_soc_component_update_bits(component, DA9055_LINE_CTRL,
  1219. DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN);
  1220. /*
  1221. * There are two separate control bits for input and output mixers.
  1222. * One to enable corresponding amplifier and other to enable its
  1223. * output. As amplifier bits are related to power control, they are
  1224. * being managed by DAPM while other (non power related) bits are
  1225. * enabled here
  1226. */
  1227. snd_soc_component_update_bits(component, DA9055_MIXIN_L_CTRL,
  1228. DA9055_MIXIN_L_MIX_EN, DA9055_MIXIN_L_MIX_EN);
  1229. snd_soc_component_update_bits(component, DA9055_MIXIN_R_CTRL,
  1230. DA9055_MIXIN_R_MIX_EN, DA9055_MIXIN_R_MIX_EN);
  1231. snd_soc_component_update_bits(component, DA9055_MIXOUT_L_CTRL,
  1232. DA9055_MIXOUT_L_MIX_EN, DA9055_MIXOUT_L_MIX_EN);
  1233. snd_soc_component_update_bits(component, DA9055_MIXOUT_R_CTRL,
  1234. DA9055_MIXOUT_R_MIX_EN, DA9055_MIXOUT_R_MIX_EN);
  1235. /* Set this as per your system configuration */
  1236. snd_soc_component_write(component, DA9055_PLL_CTRL, DA9055_PLL_INDIV_10_20_MHZ);
  1237. /* Set platform data values */
  1238. if (da9055->pdata) {
  1239. /* set mic bias source */
  1240. if (da9055->pdata->micbias_source) {
  1241. snd_soc_component_update_bits(component, DA9055_MIXIN_R_SELECT,
  1242. DA9055_MICBIAS2_EN,
  1243. DA9055_MICBIAS2_EN);
  1244. } else {
  1245. snd_soc_component_update_bits(component, DA9055_MIXIN_R_SELECT,
  1246. DA9055_MICBIAS2_EN, 0);
  1247. }
  1248. /* set mic bias voltage */
  1249. switch (da9055->pdata->micbias) {
  1250. case DA9055_MICBIAS_2_2V:
  1251. case DA9055_MICBIAS_2_1V:
  1252. case DA9055_MICBIAS_1_8V:
  1253. case DA9055_MICBIAS_1_6V:
  1254. snd_soc_component_update_bits(component, DA9055_MIC_CONFIG,
  1255. DA9055_MICBIAS_LEVEL_MASK,
  1256. (da9055->pdata->micbias) << 4);
  1257. break;
  1258. }
  1259. }
  1260. return 0;
  1261. }
  1262. static const struct snd_soc_component_driver soc_component_dev_da9055 = {
  1263. .probe = da9055_probe,
  1264. .set_bias_level = da9055_set_bias_level,
  1265. .controls = da9055_snd_controls,
  1266. .num_controls = ARRAY_SIZE(da9055_snd_controls),
  1267. .dapm_widgets = da9055_dapm_widgets,
  1268. .num_dapm_widgets = ARRAY_SIZE(da9055_dapm_widgets),
  1269. .dapm_routes = da9055_audio_map,
  1270. .num_dapm_routes = ARRAY_SIZE(da9055_audio_map),
  1271. .idle_bias_on = 1,
  1272. .use_pmdown_time = 1,
  1273. .endianness = 1,
  1274. .non_legacy_dai_naming = 1,
  1275. };
  1276. static const struct regmap_config da9055_regmap_config = {
  1277. .reg_bits = 8,
  1278. .val_bits = 8,
  1279. .reg_defaults = da9055_reg_defaults,
  1280. .num_reg_defaults = ARRAY_SIZE(da9055_reg_defaults),
  1281. .volatile_reg = da9055_volatile_register,
  1282. .cache_type = REGCACHE_RBTREE,
  1283. };
  1284. static int da9055_i2c_probe(struct i2c_client *i2c,
  1285. const struct i2c_device_id *id)
  1286. {
  1287. struct da9055_priv *da9055;
  1288. struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev);
  1289. int ret;
  1290. da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv),
  1291. GFP_KERNEL);
  1292. if (!da9055)
  1293. return -ENOMEM;
  1294. if (pdata)
  1295. da9055->pdata = pdata;
  1296. i2c_set_clientdata(i2c, da9055);
  1297. da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config);
  1298. if (IS_ERR(da9055->regmap)) {
  1299. ret = PTR_ERR(da9055->regmap);
  1300. dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
  1301. return ret;
  1302. }
  1303. ret = devm_snd_soc_register_component(&i2c->dev,
  1304. &soc_component_dev_da9055, &da9055_dai, 1);
  1305. if (ret < 0) {
  1306. dev_err(&i2c->dev, "Failed to register da9055 component: %d\n",
  1307. ret);
  1308. }
  1309. return ret;
  1310. }
  1311. /*
  1312. * DO NOT change the device Ids. The naming is intentionally specific as both
  1313. * the CODEC and PMIC parts of this chip are instantiated separately as I2C
  1314. * devices (both have configurable I2C addresses, and are to all intents and
  1315. * purposes separate). As a result there are specific DA9055 Ids for CODEC
  1316. * and PMIC, which must be different to operate together.
  1317. */
  1318. static const struct i2c_device_id da9055_i2c_id[] = {
  1319. { "da9055-codec", 0 },
  1320. { }
  1321. };
  1322. MODULE_DEVICE_TABLE(i2c, da9055_i2c_id);
  1323. static const struct of_device_id da9055_of_match[] = {
  1324. { .compatible = "dlg,da9055-codec", },
  1325. { }
  1326. };
  1327. MODULE_DEVICE_TABLE(of, da9055_of_match);
  1328. /* I2C codec control layer */
  1329. static struct i2c_driver da9055_i2c_driver = {
  1330. .driver = {
  1331. .name = "da9055-codec",
  1332. .of_match_table = of_match_ptr(da9055_of_match),
  1333. },
  1334. .probe = da9055_i2c_probe,
  1335. .id_table = da9055_i2c_id,
  1336. };
  1337. module_i2c_driver(da9055_i2c_driver);
  1338. MODULE_DESCRIPTION("ASoC DA9055 Codec driver");
  1339. MODULE_AUTHOR("David Chen, Ashish Chavan");
  1340. MODULE_LICENSE("GPL");