da732x.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * da732x.c --- Dialog DA732X ALSA SoC Audio Driver
  4. *
  5. * Copyright (C) 2012 Dialog Semiconductor GmbH
  6. *
  7. * Author: Michal Hajduk <Michal.Hajduk@diasemi.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/i2c.h>
  15. #include <linux/regmap.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/sysfs.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include <sound/soc-dapm.h>
  24. #include <sound/initval.h>
  25. #include <sound/tlv.h>
  26. #include <asm/div64.h>
  27. #include "da732x.h"
  28. #include "da732x_reg.h"
  29. struct da732x_priv {
  30. struct regmap *regmap;
  31. unsigned int sysclk;
  32. bool pll_en;
  33. };
  34. /*
  35. * da732x register cache - default settings
  36. */
  37. static const struct reg_default da732x_reg_cache[] = {
  38. { DA732X_REG_REF1 , 0x02 },
  39. { DA732X_REG_BIAS_EN , 0x80 },
  40. { DA732X_REG_BIAS1 , 0x00 },
  41. { DA732X_REG_BIAS2 , 0x00 },
  42. { DA732X_REG_BIAS3 , 0x00 },
  43. { DA732X_REG_BIAS4 , 0x00 },
  44. { DA732X_REG_MICBIAS2 , 0x00 },
  45. { DA732X_REG_MICBIAS1 , 0x00 },
  46. { DA732X_REG_MICDET , 0x00 },
  47. { DA732X_REG_MIC1_PRE , 0x01 },
  48. { DA732X_REG_MIC1 , 0x40 },
  49. { DA732X_REG_MIC2_PRE , 0x01 },
  50. { DA732X_REG_MIC2 , 0x40 },
  51. { DA732X_REG_AUX1L , 0x75 },
  52. { DA732X_REG_AUX1R , 0x75 },
  53. { DA732X_REG_MIC3_PRE , 0x01 },
  54. { DA732X_REG_MIC3 , 0x40 },
  55. { DA732X_REG_INP_PINBIAS , 0x00 },
  56. { DA732X_REG_INP_ZC_EN , 0x00 },
  57. { DA732X_REG_INP_MUX , 0x50 },
  58. { DA732X_REG_HP_DET , 0x00 },
  59. { DA732X_REG_HPL_DAC_OFFSET , 0x00 },
  60. { DA732X_REG_HPL_DAC_OFF_CNTL , 0x00 },
  61. { DA732X_REG_HPL_OUT_OFFSET , 0x00 },
  62. { DA732X_REG_HPL , 0x40 },
  63. { DA732X_REG_HPL_VOL , 0x0F },
  64. { DA732X_REG_HPR_DAC_OFFSET , 0x00 },
  65. { DA732X_REG_HPR_DAC_OFF_CNTL , 0x00 },
  66. { DA732X_REG_HPR_OUT_OFFSET , 0x00 },
  67. { DA732X_REG_HPR , 0x40 },
  68. { DA732X_REG_HPR_VOL , 0x0F },
  69. { DA732X_REG_LIN2 , 0x4F },
  70. { DA732X_REG_LIN3 , 0x4F },
  71. { DA732X_REG_LIN4 , 0x4F },
  72. { DA732X_REG_OUT_ZC_EN , 0x00 },
  73. { DA732X_REG_HP_LIN1_GNDSEL , 0x00 },
  74. { DA732X_REG_CP_HP1 , 0x0C },
  75. { DA732X_REG_CP_HP2 , 0x03 },
  76. { DA732X_REG_CP_CTRL1 , 0x00 },
  77. { DA732X_REG_CP_CTRL2 , 0x99 },
  78. { DA732X_REG_CP_CTRL3 , 0x25 },
  79. { DA732X_REG_CP_LEVEL_MASK , 0x3F },
  80. { DA732X_REG_CP_DET , 0x00 },
  81. { DA732X_REG_CP_STATUS , 0x00 },
  82. { DA732X_REG_CP_THRESH1 , 0x00 },
  83. { DA732X_REG_CP_THRESH2 , 0x00 },
  84. { DA732X_REG_CP_THRESH3 , 0x00 },
  85. { DA732X_REG_CP_THRESH4 , 0x00 },
  86. { DA732X_REG_CP_THRESH5 , 0x00 },
  87. { DA732X_REG_CP_THRESH6 , 0x00 },
  88. { DA732X_REG_CP_THRESH7 , 0x00 },
  89. { DA732X_REG_CP_THRESH8 , 0x00 },
  90. { DA732X_REG_PLL_DIV_LO , 0x00 },
  91. { DA732X_REG_PLL_DIV_MID , 0x00 },
  92. { DA732X_REG_PLL_DIV_HI , 0x00 },
  93. { DA732X_REG_PLL_CTRL , 0x02 },
  94. { DA732X_REG_CLK_CTRL , 0xaa },
  95. { DA732X_REG_CLK_DSP , 0x07 },
  96. { DA732X_REG_CLK_EN1 , 0x00 },
  97. { DA732X_REG_CLK_EN2 , 0x00 },
  98. { DA732X_REG_CLK_EN3 , 0x00 },
  99. { DA732X_REG_CLK_EN4 , 0x00 },
  100. { DA732X_REG_CLK_EN5 , 0x00 },
  101. { DA732X_REG_AIF_MCLK , 0x00 },
  102. { DA732X_REG_AIFA1 , 0x02 },
  103. { DA732X_REG_AIFA2 , 0x00 },
  104. { DA732X_REG_AIFA3 , 0x08 },
  105. { DA732X_REG_AIFB1 , 0x02 },
  106. { DA732X_REG_AIFB2 , 0x00 },
  107. { DA732X_REG_AIFB3 , 0x08 },
  108. { DA732X_REG_PC_CTRL , 0xC0 },
  109. { DA732X_REG_DATA_ROUTE , 0x00 },
  110. { DA732X_REG_DSP_CTRL , 0x00 },
  111. { DA732X_REG_CIF_CTRL2 , 0x00 },
  112. { DA732X_REG_HANDSHAKE , 0x00 },
  113. { DA732X_REG_SPARE1_OUT , 0x00 },
  114. { DA732X_REG_SPARE2_OUT , 0x00 },
  115. { DA732X_REG_SPARE1_IN , 0x00 },
  116. { DA732X_REG_ADC1_PD , 0x00 },
  117. { DA732X_REG_ADC1_HPF , 0x00 },
  118. { DA732X_REG_ADC1_SEL , 0x00 },
  119. { DA732X_REG_ADC1_EQ12 , 0x00 },
  120. { DA732X_REG_ADC1_EQ34 , 0x00 },
  121. { DA732X_REG_ADC1_EQ5 , 0x00 },
  122. { DA732X_REG_ADC2_PD , 0x00 },
  123. { DA732X_REG_ADC2_HPF , 0x00 },
  124. { DA732X_REG_ADC2_SEL , 0x00 },
  125. { DA732X_REG_ADC2_EQ12 , 0x00 },
  126. { DA732X_REG_ADC2_EQ34 , 0x00 },
  127. { DA732X_REG_ADC2_EQ5 , 0x00 },
  128. { DA732X_REG_DAC1_HPF , 0x00 },
  129. { DA732X_REG_DAC1_L_VOL , 0x00 },
  130. { DA732X_REG_DAC1_R_VOL , 0x00 },
  131. { DA732X_REG_DAC1_SEL , 0x00 },
  132. { DA732X_REG_DAC1_SOFTMUTE , 0x00 },
  133. { DA732X_REG_DAC1_EQ12 , 0x00 },
  134. { DA732X_REG_DAC1_EQ34 , 0x00 },
  135. { DA732X_REG_DAC1_EQ5 , 0x00 },
  136. { DA732X_REG_DAC2_HPF , 0x00 },
  137. { DA732X_REG_DAC2_L_VOL , 0x00 },
  138. { DA732X_REG_DAC2_R_VOL , 0x00 },
  139. { DA732X_REG_DAC2_SEL , 0x00 },
  140. { DA732X_REG_DAC2_SOFTMUTE , 0x00 },
  141. { DA732X_REG_DAC2_EQ12 , 0x00 },
  142. { DA732X_REG_DAC2_EQ34 , 0x00 },
  143. { DA732X_REG_DAC2_EQ5 , 0x00 },
  144. { DA732X_REG_DAC3_HPF , 0x00 },
  145. { DA732X_REG_DAC3_VOL , 0x00 },
  146. { DA732X_REG_DAC3_SEL , 0x00 },
  147. { DA732X_REG_DAC3_SOFTMUTE , 0x00 },
  148. { DA732X_REG_DAC3_EQ12 , 0x00 },
  149. { DA732X_REG_DAC3_EQ34 , 0x00 },
  150. { DA732X_REG_DAC3_EQ5 , 0x00 },
  151. { DA732X_REG_BIQ_BYP , 0x00 },
  152. { DA732X_REG_DMA_CMD , 0x00 },
  153. { DA732X_REG_DMA_ADDR0 , 0x00 },
  154. { DA732X_REG_DMA_ADDR1 , 0x00 },
  155. { DA732X_REG_DMA_DATA0 , 0x00 },
  156. { DA732X_REG_DMA_DATA1 , 0x00 },
  157. { DA732X_REG_DMA_DATA2 , 0x00 },
  158. { DA732X_REG_DMA_DATA3 , 0x00 },
  159. { DA732X_REG_UNLOCK , 0x00 },
  160. };
  161. static inline int da732x_get_input_div(struct snd_soc_component *component, int sysclk)
  162. {
  163. int val;
  164. int ret;
  165. if (sysclk < DA732X_MCLK_10MHZ) {
  166. val = DA732X_MCLK_RET_0_10MHZ;
  167. ret = DA732X_MCLK_VAL_0_10MHZ;
  168. } else if ((sysclk >= DA732X_MCLK_10MHZ) &&
  169. (sysclk < DA732X_MCLK_20MHZ)) {
  170. val = DA732X_MCLK_RET_10_20MHZ;
  171. ret = DA732X_MCLK_VAL_10_20MHZ;
  172. } else if ((sysclk >= DA732X_MCLK_20MHZ) &&
  173. (sysclk < DA732X_MCLK_40MHZ)) {
  174. val = DA732X_MCLK_RET_20_40MHZ;
  175. ret = DA732X_MCLK_VAL_20_40MHZ;
  176. } else if ((sysclk >= DA732X_MCLK_40MHZ) &&
  177. (sysclk <= DA732X_MCLK_54MHZ)) {
  178. val = DA732X_MCLK_RET_40_54MHZ;
  179. ret = DA732X_MCLK_VAL_40_54MHZ;
  180. } else {
  181. return -EINVAL;
  182. }
  183. snd_soc_component_write(component, DA732X_REG_PLL_CTRL, val);
  184. return ret;
  185. }
  186. static void da732x_set_charge_pump(struct snd_soc_component *component, int state)
  187. {
  188. switch (state) {
  189. case DA732X_ENABLE_CP:
  190. snd_soc_component_write(component, DA732X_REG_CLK_EN2, DA732X_CP_CLK_EN);
  191. snd_soc_component_write(component, DA732X_REG_CP_HP2, DA732X_HP_CP_EN |
  192. DA732X_HP_CP_REG | DA732X_HP_CP_PULSESKIP);
  193. snd_soc_component_write(component, DA732X_REG_CP_CTRL1, DA732X_CP_EN |
  194. DA732X_CP_CTRL_CPVDD1);
  195. snd_soc_component_write(component, DA732X_REG_CP_CTRL2,
  196. DA732X_CP_MANAGE_MAGNITUDE | DA732X_CP_BOOST);
  197. snd_soc_component_write(component, DA732X_REG_CP_CTRL3, DA732X_CP_1MHZ);
  198. break;
  199. case DA732X_DISABLE_CP:
  200. snd_soc_component_write(component, DA732X_REG_CLK_EN2, DA732X_CP_CLK_DIS);
  201. snd_soc_component_write(component, DA732X_REG_CP_HP2, DA732X_HP_CP_DIS);
  202. snd_soc_component_write(component, DA732X_REG_CP_CTRL1, DA723X_CP_DIS);
  203. break;
  204. default:
  205. pr_err("Wrong charge pump state\n");
  206. break;
  207. }
  208. }
  209. static const DECLARE_TLV_DB_SCALE(mic_boost_tlv, DA732X_MIC_PRE_VOL_DB_MIN,
  210. DA732X_MIC_PRE_VOL_DB_INC, 0);
  211. static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, DA732X_MIC_VOL_DB_MIN,
  212. DA732X_MIC_VOL_DB_INC, 0);
  213. static const DECLARE_TLV_DB_SCALE(aux_pga_tlv, DA732X_AUX_VOL_DB_MIN,
  214. DA732X_AUX_VOL_DB_INC, 0);
  215. static const DECLARE_TLV_DB_SCALE(hp_pga_tlv, DA732X_HP_VOL_DB_MIN,
  216. DA732X_AUX_VOL_DB_INC, 0);
  217. static const DECLARE_TLV_DB_SCALE(lin2_pga_tlv, DA732X_LIN2_VOL_DB_MIN,
  218. DA732X_LIN2_VOL_DB_INC, 0);
  219. static const DECLARE_TLV_DB_SCALE(lin3_pga_tlv, DA732X_LIN3_VOL_DB_MIN,
  220. DA732X_LIN3_VOL_DB_INC, 0);
  221. static const DECLARE_TLV_DB_SCALE(lin4_pga_tlv, DA732X_LIN4_VOL_DB_MIN,
  222. DA732X_LIN4_VOL_DB_INC, 0);
  223. static const DECLARE_TLV_DB_SCALE(adc_pga_tlv, DA732X_ADC_VOL_DB_MIN,
  224. DA732X_ADC_VOL_DB_INC, 0);
  225. static const DECLARE_TLV_DB_SCALE(dac_pga_tlv, DA732X_DAC_VOL_DB_MIN,
  226. DA732X_DAC_VOL_DB_INC, 0);
  227. static const DECLARE_TLV_DB_SCALE(eq_band_pga_tlv, DA732X_EQ_BAND_VOL_DB_MIN,
  228. DA732X_EQ_BAND_VOL_DB_INC, 0);
  229. static const DECLARE_TLV_DB_SCALE(eq_overall_tlv, DA732X_EQ_OVERALL_VOL_DB_MIN,
  230. DA732X_EQ_OVERALL_VOL_DB_INC, 0);
  231. /* High Pass Filter */
  232. static const char *da732x_hpf_mode[] = {
  233. "Disable", "Music", "Voice",
  234. };
  235. static const char *da732x_hpf_music[] = {
  236. "1.8Hz", "3.75Hz", "7.5Hz", "15Hz",
  237. };
  238. static const char *da732x_hpf_voice[] = {
  239. "2.5Hz", "25Hz", "50Hz", "100Hz",
  240. "150Hz", "200Hz", "300Hz", "400Hz"
  241. };
  242. static SOC_ENUM_SINGLE_DECL(da732x_dac1_hpf_mode_enum,
  243. DA732X_REG_DAC1_HPF, DA732X_HPF_MODE_SHIFT,
  244. da732x_hpf_mode);
  245. static SOC_ENUM_SINGLE_DECL(da732x_dac2_hpf_mode_enum,
  246. DA732X_REG_DAC2_HPF, DA732X_HPF_MODE_SHIFT,
  247. da732x_hpf_mode);
  248. static SOC_ENUM_SINGLE_DECL(da732x_dac3_hpf_mode_enum,
  249. DA732X_REG_DAC3_HPF, DA732X_HPF_MODE_SHIFT,
  250. da732x_hpf_mode);
  251. static SOC_ENUM_SINGLE_DECL(da732x_adc1_hpf_mode_enum,
  252. DA732X_REG_ADC1_HPF, DA732X_HPF_MODE_SHIFT,
  253. da732x_hpf_mode);
  254. static SOC_ENUM_SINGLE_DECL(da732x_adc2_hpf_mode_enum,
  255. DA732X_REG_ADC2_HPF, DA732X_HPF_MODE_SHIFT,
  256. da732x_hpf_mode);
  257. static SOC_ENUM_SINGLE_DECL(da732x_dac1_hp_filter_enum,
  258. DA732X_REG_DAC1_HPF, DA732X_HPF_MUSIC_SHIFT,
  259. da732x_hpf_music);
  260. static SOC_ENUM_SINGLE_DECL(da732x_dac2_hp_filter_enum,
  261. DA732X_REG_DAC2_HPF, DA732X_HPF_MUSIC_SHIFT,
  262. da732x_hpf_music);
  263. static SOC_ENUM_SINGLE_DECL(da732x_dac3_hp_filter_enum,
  264. DA732X_REG_DAC3_HPF, DA732X_HPF_MUSIC_SHIFT,
  265. da732x_hpf_music);
  266. static SOC_ENUM_SINGLE_DECL(da732x_adc1_hp_filter_enum,
  267. DA732X_REG_ADC1_HPF, DA732X_HPF_MUSIC_SHIFT,
  268. da732x_hpf_music);
  269. static SOC_ENUM_SINGLE_DECL(da732x_adc2_hp_filter_enum,
  270. DA732X_REG_ADC2_HPF, DA732X_HPF_MUSIC_SHIFT,
  271. da732x_hpf_music);
  272. static SOC_ENUM_SINGLE_DECL(da732x_dac1_voice_filter_enum,
  273. DA732X_REG_DAC1_HPF, DA732X_HPF_VOICE_SHIFT,
  274. da732x_hpf_voice);
  275. static SOC_ENUM_SINGLE_DECL(da732x_dac2_voice_filter_enum,
  276. DA732X_REG_DAC2_HPF, DA732X_HPF_VOICE_SHIFT,
  277. da732x_hpf_voice);
  278. static SOC_ENUM_SINGLE_DECL(da732x_dac3_voice_filter_enum,
  279. DA732X_REG_DAC3_HPF, DA732X_HPF_VOICE_SHIFT,
  280. da732x_hpf_voice);
  281. static SOC_ENUM_SINGLE_DECL(da732x_adc1_voice_filter_enum,
  282. DA732X_REG_ADC1_HPF, DA732X_HPF_VOICE_SHIFT,
  283. da732x_hpf_voice);
  284. static SOC_ENUM_SINGLE_DECL(da732x_adc2_voice_filter_enum,
  285. DA732X_REG_ADC2_HPF, DA732X_HPF_VOICE_SHIFT,
  286. da732x_hpf_voice);
  287. static int da732x_hpf_set(struct snd_kcontrol *kcontrol,
  288. struct snd_ctl_elem_value *ucontrol)
  289. {
  290. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  291. struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value;
  292. unsigned int reg = enum_ctrl->reg;
  293. unsigned int sel = ucontrol->value.enumerated.item[0];
  294. unsigned int bits;
  295. switch (sel) {
  296. case DA732X_HPF_DISABLED:
  297. bits = DA732X_HPF_DIS;
  298. break;
  299. case DA732X_HPF_VOICE:
  300. bits = DA732X_HPF_VOICE_EN;
  301. break;
  302. case DA732X_HPF_MUSIC:
  303. bits = DA732X_HPF_MUSIC_EN;
  304. break;
  305. default:
  306. return -EINVAL;
  307. }
  308. snd_soc_component_update_bits(component, reg, DA732X_HPF_MASK, bits);
  309. return 0;
  310. }
  311. static int da732x_hpf_get(struct snd_kcontrol *kcontrol,
  312. struct snd_ctl_elem_value *ucontrol)
  313. {
  314. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  315. struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value;
  316. unsigned int reg = enum_ctrl->reg;
  317. int val;
  318. val = snd_soc_component_read(component, reg) & DA732X_HPF_MASK;
  319. switch (val) {
  320. case DA732X_HPF_VOICE_EN:
  321. ucontrol->value.enumerated.item[0] = DA732X_HPF_VOICE;
  322. break;
  323. case DA732X_HPF_MUSIC_EN:
  324. ucontrol->value.enumerated.item[0] = DA732X_HPF_MUSIC;
  325. break;
  326. default:
  327. ucontrol->value.enumerated.item[0] = DA732X_HPF_DISABLED;
  328. break;
  329. }
  330. return 0;
  331. }
  332. static const struct snd_kcontrol_new da732x_snd_controls[] = {
  333. /* Input PGAs */
  334. SOC_SINGLE_RANGE_TLV("MIC1 Boost Volume", DA732X_REG_MIC1_PRE,
  335. DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
  336. DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
  337. SOC_SINGLE_RANGE_TLV("MIC2 Boost Volume", DA732X_REG_MIC2_PRE,
  338. DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
  339. DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
  340. SOC_SINGLE_RANGE_TLV("MIC3 Boost Volume", DA732X_REG_MIC3_PRE,
  341. DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN,
  342. DA732X_MICBOOST_MAX, 0, mic_boost_tlv),
  343. /* MICs */
  344. SOC_SINGLE("MIC1 Switch", DA732X_REG_MIC1, DA732X_MIC_MUTE_SHIFT,
  345. DA732X_SWITCH_MAX, DA732X_INVERT),
  346. SOC_SINGLE_RANGE_TLV("MIC1 Volume", DA732X_REG_MIC1,
  347. DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
  348. DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
  349. SOC_SINGLE("MIC2 Switch", DA732X_REG_MIC2, DA732X_MIC_MUTE_SHIFT,
  350. DA732X_SWITCH_MAX, DA732X_INVERT),
  351. SOC_SINGLE_RANGE_TLV("MIC2 Volume", DA732X_REG_MIC2,
  352. DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
  353. DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
  354. SOC_SINGLE("MIC3 Switch", DA732X_REG_MIC3, DA732X_MIC_MUTE_SHIFT,
  355. DA732X_SWITCH_MAX, DA732X_INVERT),
  356. SOC_SINGLE_RANGE_TLV("MIC3 Volume", DA732X_REG_MIC3,
  357. DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN,
  358. DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv),
  359. /* AUXs */
  360. SOC_SINGLE("AUX1L Switch", DA732X_REG_AUX1L, DA732X_AUX_MUTE_SHIFT,
  361. DA732X_SWITCH_MAX, DA732X_INVERT),
  362. SOC_SINGLE_TLV("AUX1L Volume", DA732X_REG_AUX1L,
  363. DA732X_AUX_VOL_SHIFT, DA732X_AUX_VOL_VAL_MAX,
  364. DA732X_NO_INVERT, aux_pga_tlv),
  365. SOC_SINGLE("AUX1R Switch", DA732X_REG_AUX1R, DA732X_AUX_MUTE_SHIFT,
  366. DA732X_SWITCH_MAX, DA732X_INVERT),
  367. SOC_SINGLE_TLV("AUX1R Volume", DA732X_REG_AUX1R,
  368. DA732X_AUX_VOL_SHIFT, DA732X_AUX_VOL_VAL_MAX,
  369. DA732X_NO_INVERT, aux_pga_tlv),
  370. /* ADCs */
  371. SOC_DOUBLE_TLV("ADC1 Volume", DA732X_REG_ADC1_SEL,
  372. DA732X_ADCL_VOL_SHIFT, DA732X_ADCR_VOL_SHIFT,
  373. DA732X_ADC_VOL_VAL_MAX, DA732X_INVERT, adc_pga_tlv),
  374. SOC_DOUBLE_TLV("ADC2 Volume", DA732X_REG_ADC2_SEL,
  375. DA732X_ADCL_VOL_SHIFT, DA732X_ADCR_VOL_SHIFT,
  376. DA732X_ADC_VOL_VAL_MAX, DA732X_INVERT, adc_pga_tlv),
  377. /* DACs */
  378. SOC_DOUBLE("Digital Playback DAC12 Switch", DA732X_REG_DAC1_SEL,
  379. DA732X_DACL_MUTE_SHIFT, DA732X_DACR_MUTE_SHIFT,
  380. DA732X_SWITCH_MAX, DA732X_INVERT),
  381. SOC_DOUBLE_R_TLV("Digital Playback DAC12 Volume", DA732X_REG_DAC1_L_VOL,
  382. DA732X_REG_DAC1_R_VOL, DA732X_DAC_VOL_SHIFT,
  383. DA732X_DAC_VOL_VAL_MAX, DA732X_INVERT, dac_pga_tlv),
  384. SOC_SINGLE("Digital Playback DAC3 Switch", DA732X_REG_DAC2_SEL,
  385. DA732X_DACL_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
  386. SOC_SINGLE_TLV("Digital Playback DAC3 Volume", DA732X_REG_DAC2_L_VOL,
  387. DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
  388. DA732X_INVERT, dac_pga_tlv),
  389. SOC_SINGLE("Digital Playback DAC4 Switch", DA732X_REG_DAC2_SEL,
  390. DA732X_DACR_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
  391. SOC_SINGLE_TLV("Digital Playback DAC4 Volume", DA732X_REG_DAC2_R_VOL,
  392. DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
  393. DA732X_INVERT, dac_pga_tlv),
  394. SOC_SINGLE("Digital Playback DAC5 Switch", DA732X_REG_DAC3_SEL,
  395. DA732X_DACL_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
  396. SOC_SINGLE_TLV("Digital Playback DAC5 Volume", DA732X_REG_DAC3_VOL,
  397. DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX,
  398. DA732X_INVERT, dac_pga_tlv),
  399. /* High Pass Filters */
  400. SOC_ENUM_EXT("DAC1 High Pass Filter Mode",
  401. da732x_dac1_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
  402. SOC_ENUM("DAC1 High Pass Filter", da732x_dac1_hp_filter_enum),
  403. SOC_ENUM("DAC1 Voice Filter", da732x_dac1_voice_filter_enum),
  404. SOC_ENUM_EXT("DAC2 High Pass Filter Mode",
  405. da732x_dac2_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
  406. SOC_ENUM("DAC2 High Pass Filter", da732x_dac2_hp_filter_enum),
  407. SOC_ENUM("DAC2 Voice Filter", da732x_dac2_voice_filter_enum),
  408. SOC_ENUM_EXT("DAC3 High Pass Filter Mode",
  409. da732x_dac3_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
  410. SOC_ENUM("DAC3 High Pass Filter", da732x_dac3_hp_filter_enum),
  411. SOC_ENUM("DAC3 Filter Mode", da732x_dac3_voice_filter_enum),
  412. SOC_ENUM_EXT("ADC1 High Pass Filter Mode",
  413. da732x_adc1_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
  414. SOC_ENUM("ADC1 High Pass Filter", da732x_adc1_hp_filter_enum),
  415. SOC_ENUM("ADC1 Voice Filter", da732x_adc1_voice_filter_enum),
  416. SOC_ENUM_EXT("ADC2 High Pass Filter Mode",
  417. da732x_adc2_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set),
  418. SOC_ENUM("ADC2 High Pass Filter", da732x_adc2_hp_filter_enum),
  419. SOC_ENUM("ADC2 Voice Filter", da732x_adc2_voice_filter_enum),
  420. /* Equalizers */
  421. SOC_SINGLE("ADC1 EQ Switch", DA732X_REG_ADC1_EQ5,
  422. DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
  423. SOC_SINGLE_TLV("ADC1 EQ Band 1 Volume", DA732X_REG_ADC1_EQ12,
  424. DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  425. DA732X_INVERT, eq_band_pga_tlv),
  426. SOC_SINGLE_TLV("ADC1 EQ Band 2 Volume", DA732X_REG_ADC1_EQ12,
  427. DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  428. DA732X_INVERT, eq_band_pga_tlv),
  429. SOC_SINGLE_TLV("ADC1 EQ Band 3 Volume", DA732X_REG_ADC1_EQ34,
  430. DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  431. DA732X_INVERT, eq_band_pga_tlv),
  432. SOC_SINGLE_TLV("ADC1 EQ Band 4 Volume", DA732X_REG_ADC1_EQ34,
  433. DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  434. DA732X_INVERT, eq_band_pga_tlv),
  435. SOC_SINGLE_TLV("ADC1 EQ Band 5 Volume", DA732X_REG_ADC1_EQ5,
  436. DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  437. DA732X_INVERT, eq_band_pga_tlv),
  438. SOC_SINGLE_TLV("ADC1 EQ Overall Volume", DA732X_REG_ADC1_EQ5,
  439. DA732X_EQ_OVERALL_SHIFT, DA732X_EQ_OVERALL_VOL_VAL_MAX,
  440. DA732X_INVERT, eq_overall_tlv),
  441. SOC_SINGLE("ADC2 EQ Switch", DA732X_REG_ADC2_EQ5,
  442. DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
  443. SOC_SINGLE_TLV("ADC2 EQ Band 1 Volume", DA732X_REG_ADC2_EQ12,
  444. DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  445. DA732X_INVERT, eq_band_pga_tlv),
  446. SOC_SINGLE_TLV("ADC2 EQ Band 2 Volume", DA732X_REG_ADC2_EQ12,
  447. DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  448. DA732X_INVERT, eq_band_pga_tlv),
  449. SOC_SINGLE_TLV("ADC2 EQ Band 3 Volume", DA732X_REG_ADC2_EQ34,
  450. DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  451. DA732X_INVERT, eq_band_pga_tlv),
  452. SOC_SINGLE_TLV("ACD2 EQ Band 4 Volume", DA732X_REG_ADC2_EQ34,
  453. DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  454. DA732X_INVERT, eq_band_pga_tlv),
  455. SOC_SINGLE_TLV("ACD2 EQ Band 5 Volume", DA732X_REG_ADC2_EQ5,
  456. DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  457. DA732X_INVERT, eq_band_pga_tlv),
  458. SOC_SINGLE_TLV("ADC2 EQ Overall Volume", DA732X_REG_ADC1_EQ5,
  459. DA732X_EQ_OVERALL_SHIFT, DA732X_EQ_OVERALL_VOL_VAL_MAX,
  460. DA732X_INVERT, eq_overall_tlv),
  461. SOC_SINGLE("DAC1 EQ Switch", DA732X_REG_DAC1_EQ5,
  462. DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
  463. SOC_SINGLE_TLV("DAC1 EQ Band 1 Volume", DA732X_REG_DAC1_EQ12,
  464. DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  465. DA732X_INVERT, eq_band_pga_tlv),
  466. SOC_SINGLE_TLV("DAC1 EQ Band 2 Volume", DA732X_REG_DAC1_EQ12,
  467. DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  468. DA732X_INVERT, eq_band_pga_tlv),
  469. SOC_SINGLE_TLV("DAC1 EQ Band 3 Volume", DA732X_REG_DAC1_EQ34,
  470. DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  471. DA732X_INVERT, eq_band_pga_tlv),
  472. SOC_SINGLE_TLV("DAC1 EQ Band 4 Volume", DA732X_REG_DAC1_EQ34,
  473. DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  474. DA732X_INVERT, eq_band_pga_tlv),
  475. SOC_SINGLE_TLV("DAC1 EQ Band 5 Volume", DA732X_REG_DAC1_EQ5,
  476. DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  477. DA732X_INVERT, eq_band_pga_tlv),
  478. SOC_SINGLE("DAC2 EQ Switch", DA732X_REG_DAC2_EQ5,
  479. DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
  480. SOC_SINGLE_TLV("DAC2 EQ Band 1 Volume", DA732X_REG_DAC2_EQ12,
  481. DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  482. DA732X_INVERT, eq_band_pga_tlv),
  483. SOC_SINGLE_TLV("DAC2 EQ Band 2 Volume", DA732X_REG_DAC2_EQ12,
  484. DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  485. DA732X_INVERT, eq_band_pga_tlv),
  486. SOC_SINGLE_TLV("DAC2 EQ Band 3 Volume", DA732X_REG_DAC2_EQ34,
  487. DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  488. DA732X_INVERT, eq_band_pga_tlv),
  489. SOC_SINGLE_TLV("DAC2 EQ Band 4 Volume", DA732X_REG_DAC2_EQ34,
  490. DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  491. DA732X_INVERT, eq_band_pga_tlv),
  492. SOC_SINGLE_TLV("DAC2 EQ Band 5 Volume", DA732X_REG_DAC2_EQ5,
  493. DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  494. DA732X_INVERT, eq_band_pga_tlv),
  495. SOC_SINGLE("DAC3 EQ Switch", DA732X_REG_DAC3_EQ5,
  496. DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT),
  497. SOC_SINGLE_TLV("DAC3 EQ Band 1 Volume", DA732X_REG_DAC3_EQ12,
  498. DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  499. DA732X_INVERT, eq_band_pga_tlv),
  500. SOC_SINGLE_TLV("DAC3 EQ Band 2 Volume", DA732X_REG_DAC3_EQ12,
  501. DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  502. DA732X_INVERT, eq_band_pga_tlv),
  503. SOC_SINGLE_TLV("DAC3 EQ Band 3 Volume", DA732X_REG_DAC3_EQ34,
  504. DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  505. DA732X_INVERT, eq_band_pga_tlv),
  506. SOC_SINGLE_TLV("DAC3 EQ Band 4 Volume", DA732X_REG_DAC3_EQ34,
  507. DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  508. DA732X_INVERT, eq_band_pga_tlv),
  509. SOC_SINGLE_TLV("DAC3 EQ Band 5 Volume", DA732X_REG_DAC3_EQ5,
  510. DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX,
  511. DA732X_INVERT, eq_band_pga_tlv),
  512. /* Lineout 2 Reciever*/
  513. SOC_SINGLE("Lineout 2 Switch", DA732X_REG_LIN2, DA732X_LOUT_MUTE_SHIFT,
  514. DA732X_SWITCH_MAX, DA732X_INVERT),
  515. SOC_SINGLE_TLV("Lineout 2 Volume", DA732X_REG_LIN2,
  516. DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
  517. DA732X_NO_INVERT, lin2_pga_tlv),
  518. /* Lineout 3 SPEAKER*/
  519. SOC_SINGLE("Lineout 3 Switch", DA732X_REG_LIN3, DA732X_LOUT_MUTE_SHIFT,
  520. DA732X_SWITCH_MAX, DA732X_INVERT),
  521. SOC_SINGLE_TLV("Lineout 3 Volume", DA732X_REG_LIN3,
  522. DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
  523. DA732X_NO_INVERT, lin3_pga_tlv),
  524. /* Lineout 4 */
  525. SOC_SINGLE("Lineout 4 Switch", DA732X_REG_LIN4, DA732X_LOUT_MUTE_SHIFT,
  526. DA732X_SWITCH_MAX, DA732X_INVERT),
  527. SOC_SINGLE_TLV("Lineout 4 Volume", DA732X_REG_LIN4,
  528. DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX,
  529. DA732X_NO_INVERT, lin4_pga_tlv),
  530. /* Headphones */
  531. SOC_DOUBLE_R("Headphone Switch", DA732X_REG_HPR, DA732X_REG_HPL,
  532. DA732X_HP_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT),
  533. SOC_DOUBLE_R_TLV("Headphone Volume", DA732X_REG_HPL_VOL,
  534. DA732X_REG_HPR_VOL, DA732X_HP_VOL_SHIFT,
  535. DA732X_HP_VOL_VAL_MAX, DA732X_NO_INVERT, hp_pga_tlv),
  536. };
  537. static int da732x_adc_event(struct snd_soc_dapm_widget *w,
  538. struct snd_kcontrol *kcontrol, int event)
  539. {
  540. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  541. switch (event) {
  542. case SND_SOC_DAPM_POST_PMU:
  543. switch (w->reg) {
  544. case DA732X_REG_ADC1_PD:
  545. snd_soc_component_update_bits(component, DA732X_REG_CLK_EN3,
  546. DA732X_ADCA_BB_CLK_EN,
  547. DA732X_ADCA_BB_CLK_EN);
  548. break;
  549. case DA732X_REG_ADC2_PD:
  550. snd_soc_component_update_bits(component, DA732X_REG_CLK_EN3,
  551. DA732X_ADCC_BB_CLK_EN,
  552. DA732X_ADCC_BB_CLK_EN);
  553. break;
  554. default:
  555. return -EINVAL;
  556. }
  557. snd_soc_component_update_bits(component, w->reg, DA732X_ADC_RST_MASK,
  558. DA732X_ADC_SET_ACT);
  559. snd_soc_component_update_bits(component, w->reg, DA732X_ADC_PD_MASK,
  560. DA732X_ADC_ON);
  561. break;
  562. case SND_SOC_DAPM_POST_PMD:
  563. snd_soc_component_update_bits(component, w->reg, DA732X_ADC_PD_MASK,
  564. DA732X_ADC_OFF);
  565. snd_soc_component_update_bits(component, w->reg, DA732X_ADC_RST_MASK,
  566. DA732X_ADC_SET_RST);
  567. switch (w->reg) {
  568. case DA732X_REG_ADC1_PD:
  569. snd_soc_component_update_bits(component, DA732X_REG_CLK_EN3,
  570. DA732X_ADCA_BB_CLK_EN, 0);
  571. break;
  572. case DA732X_REG_ADC2_PD:
  573. snd_soc_component_update_bits(component, DA732X_REG_CLK_EN3,
  574. DA732X_ADCC_BB_CLK_EN, 0);
  575. break;
  576. default:
  577. return -EINVAL;
  578. }
  579. break;
  580. default:
  581. return -EINVAL;
  582. }
  583. return 0;
  584. }
  585. static int da732x_out_pga_event(struct snd_soc_dapm_widget *w,
  586. struct snd_kcontrol *kcontrol, int event)
  587. {
  588. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  589. switch (event) {
  590. case SND_SOC_DAPM_POST_PMU:
  591. snd_soc_component_update_bits(component, w->reg,
  592. (1 << w->shift) | DA732X_OUT_HIZ_EN,
  593. (1 << w->shift) | DA732X_OUT_HIZ_EN);
  594. break;
  595. case SND_SOC_DAPM_POST_PMD:
  596. snd_soc_component_update_bits(component, w->reg,
  597. (1 << w->shift) | DA732X_OUT_HIZ_EN,
  598. (1 << w->shift) | DA732X_OUT_HIZ_DIS);
  599. break;
  600. default:
  601. return -EINVAL;
  602. }
  603. return 0;
  604. }
  605. static const char *adcl_text[] = {
  606. "AUX1L", "MIC1"
  607. };
  608. static const char *adcr_text[] = {
  609. "AUX1R", "MIC2", "MIC3"
  610. };
  611. static const char *enable_text[] = {
  612. "Disabled",
  613. "Enabled"
  614. };
  615. /* ADC1LMUX */
  616. static SOC_ENUM_SINGLE_DECL(adc1l_enum,
  617. DA732X_REG_INP_MUX, DA732X_ADC1L_MUX_SEL_SHIFT,
  618. adcl_text);
  619. static const struct snd_kcontrol_new adc1l_mux =
  620. SOC_DAPM_ENUM("ADC Route", adc1l_enum);
  621. /* ADC1RMUX */
  622. static SOC_ENUM_SINGLE_DECL(adc1r_enum,
  623. DA732X_REG_INP_MUX, DA732X_ADC1R_MUX_SEL_SHIFT,
  624. adcr_text);
  625. static const struct snd_kcontrol_new adc1r_mux =
  626. SOC_DAPM_ENUM("ADC Route", adc1r_enum);
  627. /* ADC2LMUX */
  628. static SOC_ENUM_SINGLE_DECL(adc2l_enum,
  629. DA732X_REG_INP_MUX, DA732X_ADC2L_MUX_SEL_SHIFT,
  630. adcl_text);
  631. static const struct snd_kcontrol_new adc2l_mux =
  632. SOC_DAPM_ENUM("ADC Route", adc2l_enum);
  633. /* ADC2RMUX */
  634. static SOC_ENUM_SINGLE_DECL(adc2r_enum,
  635. DA732X_REG_INP_MUX, DA732X_ADC2R_MUX_SEL_SHIFT,
  636. adcr_text);
  637. static const struct snd_kcontrol_new adc2r_mux =
  638. SOC_DAPM_ENUM("ADC Route", adc2r_enum);
  639. static SOC_ENUM_SINGLE_DECL(da732x_hp_left_output,
  640. DA732X_REG_HPL, DA732X_HP_OUT_DAC_EN_SHIFT,
  641. enable_text);
  642. static const struct snd_kcontrol_new hpl_mux =
  643. SOC_DAPM_ENUM("HPL Switch", da732x_hp_left_output);
  644. static SOC_ENUM_SINGLE_DECL(da732x_hp_right_output,
  645. DA732X_REG_HPR, DA732X_HP_OUT_DAC_EN_SHIFT,
  646. enable_text);
  647. static const struct snd_kcontrol_new hpr_mux =
  648. SOC_DAPM_ENUM("HPR Switch", da732x_hp_right_output);
  649. static SOC_ENUM_SINGLE_DECL(da732x_speaker_output,
  650. DA732X_REG_LIN3, DA732X_LOUT_DAC_EN_SHIFT,
  651. enable_text);
  652. static const struct snd_kcontrol_new spk_mux =
  653. SOC_DAPM_ENUM("SPK Switch", da732x_speaker_output);
  654. static SOC_ENUM_SINGLE_DECL(da732x_lout4_output,
  655. DA732X_REG_LIN4, DA732X_LOUT_DAC_EN_SHIFT,
  656. enable_text);
  657. static const struct snd_kcontrol_new lout4_mux =
  658. SOC_DAPM_ENUM("LOUT4 Switch", da732x_lout4_output);
  659. static SOC_ENUM_SINGLE_DECL(da732x_lout2_output,
  660. DA732X_REG_LIN2, DA732X_LOUT_DAC_EN_SHIFT,
  661. enable_text);
  662. static const struct snd_kcontrol_new lout2_mux =
  663. SOC_DAPM_ENUM("LOUT2 Switch", da732x_lout2_output);
  664. static const struct snd_soc_dapm_widget da732x_dapm_widgets[] = {
  665. /* Supplies */
  666. SND_SOC_DAPM_SUPPLY("ADC1 Supply", DA732X_REG_ADC1_PD, 0,
  667. DA732X_NO_INVERT, da732x_adc_event,
  668. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  669. SND_SOC_DAPM_SUPPLY("ADC2 Supply", DA732X_REG_ADC2_PD, 0,
  670. DA732X_NO_INVERT, da732x_adc_event,
  671. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  672. SND_SOC_DAPM_SUPPLY("DAC1 CLK", DA732X_REG_CLK_EN4,
  673. DA732X_DACA_BB_CLK_SHIFT, DA732X_NO_INVERT,
  674. NULL, 0),
  675. SND_SOC_DAPM_SUPPLY("DAC2 CLK", DA732X_REG_CLK_EN4,
  676. DA732X_DACC_BB_CLK_SHIFT, DA732X_NO_INVERT,
  677. NULL, 0),
  678. SND_SOC_DAPM_SUPPLY("DAC3 CLK", DA732X_REG_CLK_EN5,
  679. DA732X_DACE_BB_CLK_SHIFT, DA732X_NO_INVERT,
  680. NULL, 0),
  681. /* Micbias */
  682. SND_SOC_DAPM_SUPPLY("MICBIAS1", DA732X_REG_MICBIAS1,
  683. DA732X_MICBIAS_EN_SHIFT,
  684. DA732X_NO_INVERT, NULL, 0),
  685. SND_SOC_DAPM_SUPPLY("MICBIAS2", DA732X_REG_MICBIAS2,
  686. DA732X_MICBIAS_EN_SHIFT,
  687. DA732X_NO_INVERT, NULL, 0),
  688. /* Inputs */
  689. SND_SOC_DAPM_INPUT("MIC1"),
  690. SND_SOC_DAPM_INPUT("MIC2"),
  691. SND_SOC_DAPM_INPUT("MIC3"),
  692. SND_SOC_DAPM_INPUT("AUX1L"),
  693. SND_SOC_DAPM_INPUT("AUX1R"),
  694. /* Outputs */
  695. SND_SOC_DAPM_OUTPUT("HPL"),
  696. SND_SOC_DAPM_OUTPUT("HPR"),
  697. SND_SOC_DAPM_OUTPUT("LOUTL"),
  698. SND_SOC_DAPM_OUTPUT("LOUTR"),
  699. SND_SOC_DAPM_OUTPUT("ClassD"),
  700. /* ADCs */
  701. SND_SOC_DAPM_ADC("ADC1L", NULL, DA732X_REG_ADC1_SEL,
  702. DA732X_ADCL_EN_SHIFT, DA732X_NO_INVERT),
  703. SND_SOC_DAPM_ADC("ADC1R", NULL, DA732X_REG_ADC1_SEL,
  704. DA732X_ADCR_EN_SHIFT, DA732X_NO_INVERT),
  705. SND_SOC_DAPM_ADC("ADC2L", NULL, DA732X_REG_ADC2_SEL,
  706. DA732X_ADCL_EN_SHIFT, DA732X_NO_INVERT),
  707. SND_SOC_DAPM_ADC("ADC2R", NULL, DA732X_REG_ADC2_SEL,
  708. DA732X_ADCR_EN_SHIFT, DA732X_NO_INVERT),
  709. /* DACs */
  710. SND_SOC_DAPM_DAC("DAC1L", NULL, DA732X_REG_DAC1_SEL,
  711. DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
  712. SND_SOC_DAPM_DAC("DAC1R", NULL, DA732X_REG_DAC1_SEL,
  713. DA732X_DACR_EN_SHIFT, DA732X_NO_INVERT),
  714. SND_SOC_DAPM_DAC("DAC2L", NULL, DA732X_REG_DAC2_SEL,
  715. DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
  716. SND_SOC_DAPM_DAC("DAC2R", NULL, DA732X_REG_DAC2_SEL,
  717. DA732X_DACR_EN_SHIFT, DA732X_NO_INVERT),
  718. SND_SOC_DAPM_DAC("DAC3", NULL, DA732X_REG_DAC3_SEL,
  719. DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT),
  720. /* Input Pgas */
  721. SND_SOC_DAPM_PGA("MIC1 PGA", DA732X_REG_MIC1, DA732X_MIC_EN_SHIFT,
  722. 0, NULL, 0),
  723. SND_SOC_DAPM_PGA("MIC2 PGA", DA732X_REG_MIC2, DA732X_MIC_EN_SHIFT,
  724. 0, NULL, 0),
  725. SND_SOC_DAPM_PGA("MIC3 PGA", DA732X_REG_MIC3, DA732X_MIC_EN_SHIFT,
  726. 0, NULL, 0),
  727. SND_SOC_DAPM_PGA("AUX1L PGA", DA732X_REG_AUX1L, DA732X_AUX_EN_SHIFT,
  728. 0, NULL, 0),
  729. SND_SOC_DAPM_PGA("AUX1R PGA", DA732X_REG_AUX1R, DA732X_AUX_EN_SHIFT,
  730. 0, NULL, 0),
  731. SND_SOC_DAPM_PGA_E("HP Left", DA732X_REG_HPL, DA732X_HP_OUT_EN_SHIFT,
  732. 0, NULL, 0, da732x_out_pga_event,
  733. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  734. SND_SOC_DAPM_PGA_E("HP Right", DA732X_REG_HPR, DA732X_HP_OUT_EN_SHIFT,
  735. 0, NULL, 0, da732x_out_pga_event,
  736. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  737. SND_SOC_DAPM_PGA_E("LIN2", DA732X_REG_LIN2, DA732X_LIN_OUT_EN_SHIFT,
  738. 0, NULL, 0, da732x_out_pga_event,
  739. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  740. SND_SOC_DAPM_PGA_E("LIN3", DA732X_REG_LIN3, DA732X_LIN_OUT_EN_SHIFT,
  741. 0, NULL, 0, da732x_out_pga_event,
  742. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  743. SND_SOC_DAPM_PGA_E("LIN4", DA732X_REG_LIN4, DA732X_LIN_OUT_EN_SHIFT,
  744. 0, NULL, 0, da732x_out_pga_event,
  745. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  746. /* MUXs */
  747. SND_SOC_DAPM_MUX("ADC1 Left MUX", SND_SOC_NOPM, 0, 0, &adc1l_mux),
  748. SND_SOC_DAPM_MUX("ADC1 Right MUX", SND_SOC_NOPM, 0, 0, &adc1r_mux),
  749. SND_SOC_DAPM_MUX("ADC2 Left MUX", SND_SOC_NOPM, 0, 0, &adc2l_mux),
  750. SND_SOC_DAPM_MUX("ADC2 Right MUX", SND_SOC_NOPM, 0, 0, &adc2r_mux),
  751. SND_SOC_DAPM_MUX("HP Left MUX", SND_SOC_NOPM, 0, 0, &hpl_mux),
  752. SND_SOC_DAPM_MUX("HP Right MUX", SND_SOC_NOPM, 0, 0, &hpr_mux),
  753. SND_SOC_DAPM_MUX("Speaker MUX", SND_SOC_NOPM, 0, 0, &spk_mux),
  754. SND_SOC_DAPM_MUX("LOUT2 MUX", SND_SOC_NOPM, 0, 0, &lout2_mux),
  755. SND_SOC_DAPM_MUX("LOUT4 MUX", SND_SOC_NOPM, 0, 0, &lout4_mux),
  756. /* AIF interfaces */
  757. SND_SOC_DAPM_AIF_OUT("AIFA Output", "AIFA Capture", 0, DA732X_REG_AIFA3,
  758. DA732X_AIF_EN_SHIFT, 0),
  759. SND_SOC_DAPM_AIF_IN("AIFA Input", "AIFA Playback", 0, DA732X_REG_AIFA3,
  760. DA732X_AIF_EN_SHIFT, 0),
  761. SND_SOC_DAPM_AIF_OUT("AIFB Output", "AIFB Capture", 0, DA732X_REG_AIFB3,
  762. DA732X_AIF_EN_SHIFT, 0),
  763. SND_SOC_DAPM_AIF_IN("AIFB Input", "AIFB Playback", 0, DA732X_REG_AIFB3,
  764. DA732X_AIF_EN_SHIFT, 0),
  765. };
  766. static const struct snd_soc_dapm_route da732x_dapm_routes[] = {
  767. /* Inputs */
  768. {"AUX1L PGA", NULL, "AUX1L"},
  769. {"AUX1R PGA", NULL, "AUX1R"},
  770. {"MIC1 PGA", NULL, "MIC1"},
  771. {"MIC2 PGA", NULL, "MIC2"},
  772. {"MIC3 PGA", NULL, "MIC3"},
  773. /* Capture Path */
  774. {"ADC1 Left MUX", "MIC1", "MIC1 PGA"},
  775. {"ADC1 Left MUX", "AUX1L", "AUX1L PGA"},
  776. {"ADC1 Right MUX", "AUX1R", "AUX1R PGA"},
  777. {"ADC1 Right MUX", "MIC2", "MIC2 PGA"},
  778. {"ADC1 Right MUX", "MIC3", "MIC3 PGA"},
  779. {"ADC2 Left MUX", "AUX1L", "AUX1L PGA"},
  780. {"ADC2 Left MUX", "MIC1", "MIC1 PGA"},
  781. {"ADC2 Right MUX", "AUX1R", "AUX1R PGA"},
  782. {"ADC2 Right MUX", "MIC2", "MIC2 PGA"},
  783. {"ADC2 Right MUX", "MIC3", "MIC3 PGA"},
  784. {"ADC1L", NULL, "ADC1 Supply"},
  785. {"ADC1R", NULL, "ADC1 Supply"},
  786. {"ADC2L", NULL, "ADC2 Supply"},
  787. {"ADC2R", NULL, "ADC2 Supply"},
  788. {"ADC1L", NULL, "ADC1 Left MUX"},
  789. {"ADC1R", NULL, "ADC1 Right MUX"},
  790. {"ADC2L", NULL, "ADC2 Left MUX"},
  791. {"ADC2R", NULL, "ADC2 Right MUX"},
  792. {"AIFA Output", NULL, "ADC1L"},
  793. {"AIFA Output", NULL, "ADC1R"},
  794. {"AIFB Output", NULL, "ADC2L"},
  795. {"AIFB Output", NULL, "ADC2R"},
  796. {"HP Left MUX", "Enabled", "AIFA Input"},
  797. {"HP Right MUX", "Enabled", "AIFA Input"},
  798. {"Speaker MUX", "Enabled", "AIFB Input"},
  799. {"LOUT2 MUX", "Enabled", "AIFB Input"},
  800. {"LOUT4 MUX", "Enabled", "AIFB Input"},
  801. {"DAC1L", NULL, "DAC1 CLK"},
  802. {"DAC1R", NULL, "DAC1 CLK"},
  803. {"DAC2L", NULL, "DAC2 CLK"},
  804. {"DAC2R", NULL, "DAC2 CLK"},
  805. {"DAC3", NULL, "DAC3 CLK"},
  806. {"DAC1L", NULL, "HP Left MUX"},
  807. {"DAC1R", NULL, "HP Right MUX"},
  808. {"DAC2L", NULL, "Speaker MUX"},
  809. {"DAC2R", NULL, "LOUT4 MUX"},
  810. {"DAC3", NULL, "LOUT2 MUX"},
  811. /* Output Pgas */
  812. {"HP Left", NULL, "DAC1L"},
  813. {"HP Right", NULL, "DAC1R"},
  814. {"LIN3", NULL, "DAC2L"},
  815. {"LIN4", NULL, "DAC2R"},
  816. {"LIN2", NULL, "DAC3"},
  817. /* Outputs */
  818. {"ClassD", NULL, "LIN3"},
  819. {"LOUTL", NULL, "LIN2"},
  820. {"LOUTR", NULL, "LIN4"},
  821. {"HPL", NULL, "HP Left"},
  822. {"HPR", NULL, "HP Right"},
  823. };
  824. static int da732x_hw_params(struct snd_pcm_substream *substream,
  825. struct snd_pcm_hw_params *params,
  826. struct snd_soc_dai *dai)
  827. {
  828. struct snd_soc_component *component = dai->component;
  829. u32 aif = 0;
  830. u32 reg_aif;
  831. u32 fs;
  832. reg_aif = dai->driver->base;
  833. switch (params_width(params)) {
  834. case 16:
  835. aif |= DA732X_AIF_WORD_16;
  836. break;
  837. case 20:
  838. aif |= DA732X_AIF_WORD_20;
  839. break;
  840. case 24:
  841. aif |= DA732X_AIF_WORD_24;
  842. break;
  843. case 32:
  844. aif |= DA732X_AIF_WORD_32;
  845. break;
  846. default:
  847. return -EINVAL;
  848. }
  849. switch (params_rate(params)) {
  850. case 8000:
  851. fs = DA732X_SR_8KHZ;
  852. break;
  853. case 11025:
  854. fs = DA732X_SR_11_025KHZ;
  855. break;
  856. case 12000:
  857. fs = DA732X_SR_12KHZ;
  858. break;
  859. case 16000:
  860. fs = DA732X_SR_16KHZ;
  861. break;
  862. case 22050:
  863. fs = DA732X_SR_22_05KHZ;
  864. break;
  865. case 24000:
  866. fs = DA732X_SR_24KHZ;
  867. break;
  868. case 32000:
  869. fs = DA732X_SR_32KHZ;
  870. break;
  871. case 44100:
  872. fs = DA732X_SR_44_1KHZ;
  873. break;
  874. case 48000:
  875. fs = DA732X_SR_48KHZ;
  876. break;
  877. case 88100:
  878. fs = DA732X_SR_88_1KHZ;
  879. break;
  880. case 96000:
  881. fs = DA732X_SR_96KHZ;
  882. break;
  883. default:
  884. return -EINVAL;
  885. }
  886. snd_soc_component_update_bits(component, reg_aif, DA732X_AIF_WORD_MASK, aif);
  887. snd_soc_component_update_bits(component, DA732X_REG_CLK_CTRL, DA732X_SR1_MASK, fs);
  888. return 0;
  889. }
  890. static int da732x_set_dai_fmt(struct snd_soc_dai *dai, u32 fmt)
  891. {
  892. struct snd_soc_component *component = dai->component;
  893. u32 aif_mclk, pc_count;
  894. u32 reg_aif1, aif1;
  895. u32 reg_aif3, aif3;
  896. switch (dai->id) {
  897. case DA732X_DAI_ID1:
  898. reg_aif1 = DA732X_REG_AIFA1;
  899. reg_aif3 = DA732X_REG_AIFA3;
  900. pc_count = DA732X_PC_PULSE_AIFA | DA732X_PC_RESYNC_NOT_AUT |
  901. DA732X_PC_SAME;
  902. break;
  903. case DA732X_DAI_ID2:
  904. reg_aif1 = DA732X_REG_AIFB1;
  905. reg_aif3 = DA732X_REG_AIFB3;
  906. pc_count = DA732X_PC_PULSE_AIFB | DA732X_PC_RESYNC_NOT_AUT |
  907. DA732X_PC_SAME;
  908. break;
  909. default:
  910. return -EINVAL;
  911. }
  912. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  913. case SND_SOC_DAIFMT_CBS_CFS:
  914. aif1 = DA732X_AIF_SLAVE;
  915. aif_mclk = DA732X_AIFM_FRAME_64 | DA732X_AIFM_SRC_SEL_AIFA;
  916. break;
  917. case SND_SOC_DAIFMT_CBM_CFM:
  918. aif1 = DA732X_AIF_CLK_FROM_SRC;
  919. aif_mclk = DA732X_CLK_GENERATION_AIF_A;
  920. break;
  921. default:
  922. return -EINVAL;
  923. }
  924. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  925. case SND_SOC_DAIFMT_I2S:
  926. aif3 = DA732X_AIF_I2S_MODE;
  927. break;
  928. case SND_SOC_DAIFMT_RIGHT_J:
  929. aif3 = DA732X_AIF_RIGHT_J_MODE;
  930. break;
  931. case SND_SOC_DAIFMT_LEFT_J:
  932. aif3 = DA732X_AIF_LEFT_J_MODE;
  933. break;
  934. case SND_SOC_DAIFMT_DSP_B:
  935. aif3 = DA732X_AIF_DSP_MODE;
  936. break;
  937. default:
  938. return -EINVAL;
  939. }
  940. /* Clock inversion */
  941. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  942. case SND_SOC_DAIFMT_DSP_B:
  943. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  944. case SND_SOC_DAIFMT_NB_NF:
  945. break;
  946. case SND_SOC_DAIFMT_IB_NF:
  947. aif3 |= DA732X_AIF_BCLK_INV;
  948. break;
  949. default:
  950. return -EINVAL;
  951. }
  952. break;
  953. case SND_SOC_DAIFMT_I2S:
  954. case SND_SOC_DAIFMT_RIGHT_J:
  955. case SND_SOC_DAIFMT_LEFT_J:
  956. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  957. case SND_SOC_DAIFMT_NB_NF:
  958. break;
  959. case SND_SOC_DAIFMT_IB_IF:
  960. aif3 |= DA732X_AIF_BCLK_INV | DA732X_AIF_WCLK_INV;
  961. break;
  962. case SND_SOC_DAIFMT_IB_NF:
  963. aif3 |= DA732X_AIF_BCLK_INV;
  964. break;
  965. case SND_SOC_DAIFMT_NB_IF:
  966. aif3 |= DA732X_AIF_WCLK_INV;
  967. break;
  968. default:
  969. return -EINVAL;
  970. }
  971. break;
  972. default:
  973. return -EINVAL;
  974. }
  975. snd_soc_component_write(component, DA732X_REG_AIF_MCLK, aif_mclk);
  976. snd_soc_component_update_bits(component, reg_aif1, DA732X_AIF1_CLK_MASK, aif1);
  977. snd_soc_component_update_bits(component, reg_aif3, DA732X_AIF_BCLK_INV |
  978. DA732X_AIF_WCLK_INV | DA732X_AIF_MODE_MASK, aif3);
  979. snd_soc_component_write(component, DA732X_REG_PC_CTRL, pc_count);
  980. return 0;
  981. }
  982. static int da732x_set_dai_pll(struct snd_soc_component *component, int pll_id,
  983. int source, unsigned int freq_in,
  984. unsigned int freq_out)
  985. {
  986. struct da732x_priv *da732x = snd_soc_component_get_drvdata(component);
  987. int fref, indiv;
  988. u8 div_lo, div_mid, div_hi;
  989. u64 frac_div;
  990. /* Disable PLL */
  991. if (freq_out == 0) {
  992. snd_soc_component_update_bits(component, DA732X_REG_PLL_CTRL,
  993. DA732X_PLL_EN, 0);
  994. da732x->pll_en = false;
  995. return 0;
  996. }
  997. if (da732x->pll_en)
  998. return -EBUSY;
  999. if (source == DA732X_SRCCLK_MCLK) {
  1000. /* Validate Sysclk rate */
  1001. switch (da732x->sysclk) {
  1002. case 11290000:
  1003. case 12288000:
  1004. case 22580000:
  1005. case 24576000:
  1006. case 45160000:
  1007. case 49152000:
  1008. snd_soc_component_write(component, DA732X_REG_PLL_CTRL,
  1009. DA732X_PLL_BYPASS);
  1010. return 0;
  1011. default:
  1012. dev_err(component->dev,
  1013. "Cannot use PLL Bypass, invalid SYSCLK rate\n");
  1014. return -EINVAL;
  1015. }
  1016. }
  1017. indiv = da732x_get_input_div(component, da732x->sysclk);
  1018. if (indiv < 0)
  1019. return indiv;
  1020. fref = (da732x->sysclk / indiv);
  1021. div_hi = freq_out / fref;
  1022. frac_div = (u64)(freq_out % fref) * 8192ULL;
  1023. do_div(frac_div, fref);
  1024. div_mid = (frac_div >> DA732X_1BYTE_SHIFT) & DA732X_U8_MASK;
  1025. div_lo = (frac_div) & DA732X_U8_MASK;
  1026. snd_soc_component_write(component, DA732X_REG_PLL_DIV_LO, div_lo);
  1027. snd_soc_component_write(component, DA732X_REG_PLL_DIV_MID, div_mid);
  1028. snd_soc_component_write(component, DA732X_REG_PLL_DIV_HI, div_hi);
  1029. snd_soc_component_update_bits(component, DA732X_REG_PLL_CTRL, DA732X_PLL_EN,
  1030. DA732X_PLL_EN);
  1031. da732x->pll_en = true;
  1032. return 0;
  1033. }
  1034. static int da732x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  1035. unsigned int freq, int dir)
  1036. {
  1037. struct snd_soc_component *component = dai->component;
  1038. struct da732x_priv *da732x = snd_soc_component_get_drvdata(component);
  1039. da732x->sysclk = freq;
  1040. return 0;
  1041. }
  1042. #define DA732X_RATES SNDRV_PCM_RATE_8000_96000
  1043. #define DA732X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  1044. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1045. static const struct snd_soc_dai_ops da732x_dai_ops = {
  1046. .hw_params = da732x_hw_params,
  1047. .set_fmt = da732x_set_dai_fmt,
  1048. .set_sysclk = da732x_set_dai_sysclk,
  1049. };
  1050. static struct snd_soc_dai_driver da732x_dai[] = {
  1051. {
  1052. .name = "DA732X_AIFA",
  1053. .id = DA732X_DAI_ID1,
  1054. .base = DA732X_REG_AIFA1,
  1055. .playback = {
  1056. .stream_name = "AIFA Playback",
  1057. .channels_min = 1,
  1058. .channels_max = 2,
  1059. .rates = DA732X_RATES,
  1060. .formats = DA732X_FORMATS,
  1061. },
  1062. .capture = {
  1063. .stream_name = "AIFA Capture",
  1064. .channels_min = 1,
  1065. .channels_max = 2,
  1066. .rates = DA732X_RATES,
  1067. .formats = DA732X_FORMATS,
  1068. },
  1069. .ops = &da732x_dai_ops,
  1070. },
  1071. {
  1072. .name = "DA732X_AIFB",
  1073. .id = DA732X_DAI_ID2,
  1074. .base = DA732X_REG_AIFB1,
  1075. .playback = {
  1076. .stream_name = "AIFB Playback",
  1077. .channels_min = 1,
  1078. .channels_max = 2,
  1079. .rates = DA732X_RATES,
  1080. .formats = DA732X_FORMATS,
  1081. },
  1082. .capture = {
  1083. .stream_name = "AIFB Capture",
  1084. .channels_min = 1,
  1085. .channels_max = 2,
  1086. .rates = DA732X_RATES,
  1087. .formats = DA732X_FORMATS,
  1088. },
  1089. .ops = &da732x_dai_ops,
  1090. },
  1091. };
  1092. static bool da732x_volatile(struct device *dev, unsigned int reg)
  1093. {
  1094. switch (reg) {
  1095. case DA732X_REG_HPL_DAC_OFF_CNTL:
  1096. case DA732X_REG_HPR_DAC_OFF_CNTL:
  1097. return true;
  1098. default:
  1099. return false;
  1100. }
  1101. }
  1102. static const struct regmap_config da732x_regmap = {
  1103. .reg_bits = 8,
  1104. .val_bits = 8,
  1105. .max_register = DA732X_MAX_REG,
  1106. .volatile_reg = da732x_volatile,
  1107. .reg_defaults = da732x_reg_cache,
  1108. .num_reg_defaults = ARRAY_SIZE(da732x_reg_cache),
  1109. .cache_type = REGCACHE_RBTREE,
  1110. };
  1111. static void da732x_dac_offset_adjust(struct snd_soc_component *component)
  1112. {
  1113. u8 offset[DA732X_HP_DACS];
  1114. u8 sign[DA732X_HP_DACS];
  1115. u8 step = DA732X_DAC_OFFSET_STEP;
  1116. /* Initialize DAC offset calibration circuits and registers */
  1117. snd_soc_component_write(component, DA732X_REG_HPL_DAC_OFFSET,
  1118. DA732X_HP_DAC_OFFSET_TRIM_VAL);
  1119. snd_soc_component_write(component, DA732X_REG_HPR_DAC_OFFSET,
  1120. DA732X_HP_DAC_OFFSET_TRIM_VAL);
  1121. snd_soc_component_write(component, DA732X_REG_HPL_DAC_OFF_CNTL,
  1122. DA732X_HP_DAC_OFF_CALIBRATION |
  1123. DA732X_HP_DAC_OFF_SCALE_STEPS);
  1124. snd_soc_component_write(component, DA732X_REG_HPR_DAC_OFF_CNTL,
  1125. DA732X_HP_DAC_OFF_CALIBRATION |
  1126. DA732X_HP_DAC_OFF_SCALE_STEPS);
  1127. /* Wait for voltage stabilization */
  1128. msleep(DA732X_WAIT_FOR_STABILIZATION);
  1129. /* Check DAC offset sign */
  1130. sign[DA732X_HPL_DAC] = (snd_soc_component_read(component, DA732X_REG_HPL_DAC_OFF_CNTL) &
  1131. DA732X_HP_DAC_OFF_CNTL_COMPO);
  1132. sign[DA732X_HPR_DAC] = (snd_soc_component_read(component, DA732X_REG_HPR_DAC_OFF_CNTL) &
  1133. DA732X_HP_DAC_OFF_CNTL_COMPO);
  1134. /* Binary search DAC offset values (both channels at once) */
  1135. offset[DA732X_HPL_DAC] = sign[DA732X_HPL_DAC] << DA732X_HP_DAC_COMPO_SHIFT;
  1136. offset[DA732X_HPR_DAC] = sign[DA732X_HPR_DAC] << DA732X_HP_DAC_COMPO_SHIFT;
  1137. do {
  1138. offset[DA732X_HPL_DAC] |= step;
  1139. offset[DA732X_HPR_DAC] |= step;
  1140. snd_soc_component_write(component, DA732X_REG_HPL_DAC_OFFSET,
  1141. ~offset[DA732X_HPL_DAC] & DA732X_HP_DAC_OFF_MASK);
  1142. snd_soc_component_write(component, DA732X_REG_HPR_DAC_OFFSET,
  1143. ~offset[DA732X_HPR_DAC] & DA732X_HP_DAC_OFF_MASK);
  1144. msleep(DA732X_WAIT_FOR_STABILIZATION);
  1145. if ((snd_soc_component_read(component, DA732X_REG_HPL_DAC_OFF_CNTL) &
  1146. DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPL_DAC])
  1147. offset[DA732X_HPL_DAC] &= ~step;
  1148. if ((snd_soc_component_read(component, DA732X_REG_HPR_DAC_OFF_CNTL) &
  1149. DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPR_DAC])
  1150. offset[DA732X_HPR_DAC] &= ~step;
  1151. step >>= 1;
  1152. } while (step);
  1153. /* Write final DAC offsets to registers */
  1154. snd_soc_component_write(component, DA732X_REG_HPL_DAC_OFFSET,
  1155. ~offset[DA732X_HPL_DAC] & DA732X_HP_DAC_OFF_MASK);
  1156. snd_soc_component_write(component, DA732X_REG_HPR_DAC_OFFSET,
  1157. ~offset[DA732X_HPR_DAC] & DA732X_HP_DAC_OFF_MASK);
  1158. /* End DAC calibration mode */
  1159. snd_soc_component_write(component, DA732X_REG_HPL_DAC_OFF_CNTL,
  1160. DA732X_HP_DAC_OFF_SCALE_STEPS);
  1161. snd_soc_component_write(component, DA732X_REG_HPR_DAC_OFF_CNTL,
  1162. DA732X_HP_DAC_OFF_SCALE_STEPS);
  1163. }
  1164. static void da732x_output_offset_adjust(struct snd_soc_component *component)
  1165. {
  1166. u8 offset[DA732X_HP_AMPS];
  1167. u8 sign[DA732X_HP_AMPS];
  1168. u8 step = DA732X_OUTPUT_OFFSET_STEP;
  1169. offset[DA732X_HPL_AMP] = DA732X_HP_OUT_TRIM_VAL;
  1170. offset[DA732X_HPR_AMP] = DA732X_HP_OUT_TRIM_VAL;
  1171. /* Initialize output offset calibration circuits and registers */
  1172. snd_soc_component_write(component, DA732X_REG_HPL_OUT_OFFSET, DA732X_HP_OUT_TRIM_VAL);
  1173. snd_soc_component_write(component, DA732X_REG_HPR_OUT_OFFSET, DA732X_HP_OUT_TRIM_VAL);
  1174. snd_soc_component_write(component, DA732X_REG_HPL,
  1175. DA732X_HP_OUT_COMP | DA732X_HP_OUT_EN);
  1176. snd_soc_component_write(component, DA732X_REG_HPR,
  1177. DA732X_HP_OUT_COMP | DA732X_HP_OUT_EN);
  1178. /* Wait for voltage stabilization */
  1179. msleep(DA732X_WAIT_FOR_STABILIZATION);
  1180. /* Check output offset sign */
  1181. sign[DA732X_HPL_AMP] = snd_soc_component_read(component, DA732X_REG_HPL) &
  1182. DA732X_HP_OUT_COMPO;
  1183. sign[DA732X_HPR_AMP] = snd_soc_component_read(component, DA732X_REG_HPR) &
  1184. DA732X_HP_OUT_COMPO;
  1185. snd_soc_component_write(component, DA732X_REG_HPL, DA732X_HP_OUT_COMP |
  1186. (sign[DA732X_HPL_AMP] >> DA732X_HP_OUT_COMPO_SHIFT) |
  1187. DA732X_HP_OUT_EN);
  1188. snd_soc_component_write(component, DA732X_REG_HPR, DA732X_HP_OUT_COMP |
  1189. (sign[DA732X_HPR_AMP] >> DA732X_HP_OUT_COMPO_SHIFT) |
  1190. DA732X_HP_OUT_EN);
  1191. /* Binary search output offset values (both channels at once) */
  1192. do {
  1193. offset[DA732X_HPL_AMP] |= step;
  1194. offset[DA732X_HPR_AMP] |= step;
  1195. snd_soc_component_write(component, DA732X_REG_HPL_OUT_OFFSET,
  1196. offset[DA732X_HPL_AMP]);
  1197. snd_soc_component_write(component, DA732X_REG_HPR_OUT_OFFSET,
  1198. offset[DA732X_HPR_AMP]);
  1199. msleep(DA732X_WAIT_FOR_STABILIZATION);
  1200. if ((snd_soc_component_read(component, DA732X_REG_HPL) &
  1201. DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPL_AMP])
  1202. offset[DA732X_HPL_AMP] &= ~step;
  1203. if ((snd_soc_component_read(component, DA732X_REG_HPR) &
  1204. DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPR_AMP])
  1205. offset[DA732X_HPR_AMP] &= ~step;
  1206. step >>= 1;
  1207. } while (step);
  1208. /* Write final DAC offsets to registers */
  1209. snd_soc_component_write(component, DA732X_REG_HPL_OUT_OFFSET, offset[DA732X_HPL_AMP]);
  1210. snd_soc_component_write(component, DA732X_REG_HPR_OUT_OFFSET, offset[DA732X_HPR_AMP]);
  1211. }
  1212. static void da732x_hp_dc_offset_cancellation(struct snd_soc_component *component)
  1213. {
  1214. /* Make sure that we have Soft Mute enabled */
  1215. snd_soc_component_write(component, DA732X_REG_DAC1_SOFTMUTE, DA732X_SOFTMUTE_EN |
  1216. DA732X_GAIN_RAMPED | DA732X_16_SAMPLES);
  1217. snd_soc_component_write(component, DA732X_REG_DAC1_SEL, DA732X_DACL_EN |
  1218. DA732X_DACR_EN | DA732X_DACL_SDM | DA732X_DACR_SDM |
  1219. DA732X_DACL_MUTE | DA732X_DACR_MUTE);
  1220. snd_soc_component_write(component, DA732X_REG_HPL, DA732X_HP_OUT_DAC_EN |
  1221. DA732X_HP_OUT_MUTE | DA732X_HP_OUT_EN);
  1222. snd_soc_component_write(component, DA732X_REG_HPR, DA732X_HP_OUT_EN |
  1223. DA732X_HP_OUT_MUTE | DA732X_HP_OUT_DAC_EN);
  1224. da732x_dac_offset_adjust(component);
  1225. da732x_output_offset_adjust(component);
  1226. snd_soc_component_write(component, DA732X_REG_DAC1_SEL, DA732X_DACS_DIS);
  1227. snd_soc_component_write(component, DA732X_REG_HPL, DA732X_HP_DIS);
  1228. snd_soc_component_write(component, DA732X_REG_HPR, DA732X_HP_DIS);
  1229. }
  1230. static int da732x_set_bias_level(struct snd_soc_component *component,
  1231. enum snd_soc_bias_level level)
  1232. {
  1233. struct da732x_priv *da732x = snd_soc_component_get_drvdata(component);
  1234. switch (level) {
  1235. case SND_SOC_BIAS_ON:
  1236. snd_soc_component_update_bits(component, DA732X_REG_BIAS_EN,
  1237. DA732X_BIAS_BOOST_MASK,
  1238. DA732X_BIAS_BOOST_100PC);
  1239. break;
  1240. case SND_SOC_BIAS_PREPARE:
  1241. break;
  1242. case SND_SOC_BIAS_STANDBY:
  1243. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  1244. /* Init Codec */
  1245. snd_soc_component_write(component, DA732X_REG_REF1,
  1246. DA732X_VMID_FASTCHG);
  1247. snd_soc_component_write(component, DA732X_REG_BIAS_EN,
  1248. DA732X_BIAS_EN);
  1249. mdelay(DA732X_STARTUP_DELAY);
  1250. /* Disable Fast Charge and enable DAC ref voltage */
  1251. snd_soc_component_write(component, DA732X_REG_REF1,
  1252. DA732X_REFBUFX2_EN);
  1253. /* Enable bypass DSP routing */
  1254. snd_soc_component_write(component, DA732X_REG_DATA_ROUTE,
  1255. DA732X_BYPASS_DSP);
  1256. /* Enable Digital subsystem */
  1257. snd_soc_component_write(component, DA732X_REG_DSP_CTRL,
  1258. DA732X_DIGITAL_EN);
  1259. snd_soc_component_write(component, DA732X_REG_SPARE1_OUT,
  1260. DA732X_HP_DRIVER_EN |
  1261. DA732X_HP_GATE_LOW |
  1262. DA732X_HP_LOOP_GAIN_CTRL);
  1263. snd_soc_component_write(component, DA732X_REG_HP_LIN1_GNDSEL,
  1264. DA732X_HP_OUT_GNDSEL);
  1265. da732x_set_charge_pump(component, DA732X_ENABLE_CP);
  1266. snd_soc_component_write(component, DA732X_REG_CLK_EN1,
  1267. DA732X_SYS3_CLK_EN | DA732X_PC_CLK_EN);
  1268. /* Enable Zero Crossing */
  1269. snd_soc_component_write(component, DA732X_REG_INP_ZC_EN,
  1270. DA732X_MIC1_PRE_ZC_EN |
  1271. DA732X_MIC1_ZC_EN |
  1272. DA732X_MIC2_PRE_ZC_EN |
  1273. DA732X_MIC2_ZC_EN |
  1274. DA732X_AUXL_ZC_EN |
  1275. DA732X_AUXR_ZC_EN |
  1276. DA732X_MIC3_PRE_ZC_EN |
  1277. DA732X_MIC3_ZC_EN);
  1278. snd_soc_component_write(component, DA732X_REG_OUT_ZC_EN,
  1279. DA732X_HPL_ZC_EN | DA732X_HPR_ZC_EN |
  1280. DA732X_LIN2_ZC_EN | DA732X_LIN3_ZC_EN |
  1281. DA732X_LIN4_ZC_EN);
  1282. da732x_hp_dc_offset_cancellation(component);
  1283. regcache_cache_only(da732x->regmap, false);
  1284. regcache_sync(da732x->regmap);
  1285. } else {
  1286. snd_soc_component_update_bits(component, DA732X_REG_BIAS_EN,
  1287. DA732X_BIAS_BOOST_MASK,
  1288. DA732X_BIAS_BOOST_50PC);
  1289. snd_soc_component_update_bits(component, DA732X_REG_PLL_CTRL,
  1290. DA732X_PLL_EN, 0);
  1291. da732x->pll_en = false;
  1292. }
  1293. break;
  1294. case SND_SOC_BIAS_OFF:
  1295. regcache_cache_only(da732x->regmap, true);
  1296. da732x_set_charge_pump(component, DA732X_DISABLE_CP);
  1297. snd_soc_component_update_bits(component, DA732X_REG_BIAS_EN, DA732X_BIAS_EN,
  1298. DA732X_BIAS_DIS);
  1299. da732x->pll_en = false;
  1300. break;
  1301. }
  1302. return 0;
  1303. }
  1304. static const struct snd_soc_component_driver soc_component_dev_da732x = {
  1305. .set_bias_level = da732x_set_bias_level,
  1306. .controls = da732x_snd_controls,
  1307. .num_controls = ARRAY_SIZE(da732x_snd_controls),
  1308. .dapm_widgets = da732x_dapm_widgets,
  1309. .num_dapm_widgets = ARRAY_SIZE(da732x_dapm_widgets),
  1310. .dapm_routes = da732x_dapm_routes,
  1311. .num_dapm_routes = ARRAY_SIZE(da732x_dapm_routes),
  1312. .set_pll = da732x_set_dai_pll,
  1313. .idle_bias_on = 1,
  1314. .use_pmdown_time = 1,
  1315. .endianness = 1,
  1316. .non_legacy_dai_naming = 1,
  1317. };
  1318. static int da732x_i2c_probe(struct i2c_client *i2c,
  1319. const struct i2c_device_id *id)
  1320. {
  1321. struct da732x_priv *da732x;
  1322. unsigned int reg;
  1323. int ret;
  1324. da732x = devm_kzalloc(&i2c->dev, sizeof(struct da732x_priv),
  1325. GFP_KERNEL);
  1326. if (!da732x)
  1327. return -ENOMEM;
  1328. i2c_set_clientdata(i2c, da732x);
  1329. da732x->regmap = devm_regmap_init_i2c(i2c, &da732x_regmap);
  1330. if (IS_ERR(da732x->regmap)) {
  1331. ret = PTR_ERR(da732x->regmap);
  1332. dev_err(&i2c->dev, "Failed to initialize regmap\n");
  1333. goto err;
  1334. }
  1335. ret = regmap_read(da732x->regmap, DA732X_REG_ID, &reg);
  1336. if (ret < 0) {
  1337. dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
  1338. goto err;
  1339. }
  1340. dev_info(&i2c->dev, "Revision: %d.%d\n",
  1341. (reg & DA732X_ID_MAJOR_MASK) >> 4,
  1342. (reg & DA732X_ID_MINOR_MASK));
  1343. ret = devm_snd_soc_register_component(&i2c->dev,
  1344. &soc_component_dev_da732x,
  1345. da732x_dai, ARRAY_SIZE(da732x_dai));
  1346. if (ret != 0)
  1347. dev_err(&i2c->dev, "Failed to register component.\n");
  1348. err:
  1349. return ret;
  1350. }
  1351. static int da732x_i2c_remove(struct i2c_client *client)
  1352. {
  1353. return 0;
  1354. }
  1355. static const struct i2c_device_id da732x_i2c_id[] = {
  1356. { "da7320", 0},
  1357. { }
  1358. };
  1359. MODULE_DEVICE_TABLE(i2c, da732x_i2c_id);
  1360. static struct i2c_driver da732x_i2c_driver = {
  1361. .driver = {
  1362. .name = "da7320",
  1363. },
  1364. .probe = da732x_i2c_probe,
  1365. .remove = da732x_i2c_remove,
  1366. .id_table = da732x_i2c_id,
  1367. };
  1368. module_i2c_driver(da732x_i2c_driver);
  1369. MODULE_DESCRIPTION("ASoC DA732X driver");
  1370. MODULE_AUTHOR("Michal Hajduk <michal.hajduk@diasemi.com>");
  1371. MODULE_LICENSE("GPL");