cs53l30.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cs53l30.c -- CS53l30 ALSA Soc Audio driver
  4. *
  5. * Copyright 2015 Cirrus Logic, Inc.
  6. *
  7. * Authors: Paul Handrigan <Paul.Handrigan@cirrus.com>,
  8. * Tim Howe <Tim.Howe@cirrus.com>
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/i2c.h>
  13. #include <linux/module.h>
  14. #include <linux/of_gpio.h>
  15. #include <linux/gpio/consumer.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <sound/pcm_params.h>
  18. #include <sound/soc.h>
  19. #include <sound/tlv.h>
  20. #include "cs53l30.h"
  21. #define CS53L30_NUM_SUPPLIES 2
  22. static const char *const cs53l30_supply_names[CS53L30_NUM_SUPPLIES] = {
  23. "VA",
  24. "VP",
  25. };
  26. struct cs53l30_private {
  27. struct regulator_bulk_data supplies[CS53L30_NUM_SUPPLIES];
  28. struct regmap *regmap;
  29. struct gpio_desc *reset_gpio;
  30. struct gpio_desc *mute_gpio;
  31. struct clk *mclk;
  32. bool use_sdout2;
  33. u32 mclk_rate;
  34. };
  35. static const struct reg_default cs53l30_reg_defaults[] = {
  36. { CS53L30_PWRCTL, CS53L30_PWRCTL_DEFAULT },
  37. { CS53L30_MCLKCTL, CS53L30_MCLKCTL_DEFAULT },
  38. { CS53L30_INT_SR_CTL, CS53L30_INT_SR_CTL_DEFAULT },
  39. { CS53L30_MICBIAS_CTL, CS53L30_MICBIAS_CTL_DEFAULT },
  40. { CS53L30_ASPCFG_CTL, CS53L30_ASPCFG_CTL_DEFAULT },
  41. { CS53L30_ASP_CTL1, CS53L30_ASP_CTL1_DEFAULT },
  42. { CS53L30_ASP_TDMTX_CTL1, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
  43. { CS53L30_ASP_TDMTX_CTL2, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
  44. { CS53L30_ASP_TDMTX_CTL3, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
  45. { CS53L30_ASP_TDMTX_CTL4, CS53L30_ASP_TDMTX_CTLx_DEFAULT },
  46. { CS53L30_ASP_TDMTX_EN1, CS53L30_ASP_TDMTX_ENx_DEFAULT },
  47. { CS53L30_ASP_TDMTX_EN2, CS53L30_ASP_TDMTX_ENx_DEFAULT },
  48. { CS53L30_ASP_TDMTX_EN3, CS53L30_ASP_TDMTX_ENx_DEFAULT },
  49. { CS53L30_ASP_TDMTX_EN4, CS53L30_ASP_TDMTX_ENx_DEFAULT },
  50. { CS53L30_ASP_TDMTX_EN5, CS53L30_ASP_TDMTX_ENx_DEFAULT },
  51. { CS53L30_ASP_TDMTX_EN6, CS53L30_ASP_TDMTX_ENx_DEFAULT },
  52. { CS53L30_ASP_CTL2, CS53L30_ASP_CTL2_DEFAULT },
  53. { CS53L30_SFT_RAMP, CS53L30_SFT_RMP_DEFAULT },
  54. { CS53L30_LRCK_CTL1, CS53L30_LRCK_CTLx_DEFAULT },
  55. { CS53L30_LRCK_CTL2, CS53L30_LRCK_CTLx_DEFAULT },
  56. { CS53L30_MUTEP_CTL1, CS53L30_MUTEP_CTL1_DEFAULT },
  57. { CS53L30_MUTEP_CTL2, CS53L30_MUTEP_CTL2_DEFAULT },
  58. { CS53L30_INBIAS_CTL1, CS53L30_INBIAS_CTL1_DEFAULT },
  59. { CS53L30_INBIAS_CTL2, CS53L30_INBIAS_CTL2_DEFAULT },
  60. { CS53L30_DMIC1_STR_CTL, CS53L30_DMIC1_STR_CTL_DEFAULT },
  61. { CS53L30_DMIC2_STR_CTL, CS53L30_DMIC2_STR_CTL_DEFAULT },
  62. { CS53L30_ADCDMIC1_CTL1, CS53L30_ADCDMICx_CTL1_DEFAULT },
  63. { CS53L30_ADCDMIC1_CTL2, CS53L30_ADCDMIC1_CTL2_DEFAULT },
  64. { CS53L30_ADC1_CTL3, CS53L30_ADCx_CTL3_DEFAULT },
  65. { CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_CTL_DEFAULT },
  66. { CS53L30_ADC1A_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
  67. { CS53L30_ADC1B_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
  68. { CS53L30_ADC1A_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
  69. { CS53L30_ADC1B_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
  70. { CS53L30_ADCDMIC2_CTL1, CS53L30_ADCDMICx_CTL1_DEFAULT },
  71. { CS53L30_ADCDMIC2_CTL2, CS53L30_ADCDMIC1_CTL2_DEFAULT },
  72. { CS53L30_ADC2_CTL3, CS53L30_ADCx_CTL3_DEFAULT },
  73. { CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_CTL_DEFAULT },
  74. { CS53L30_ADC2A_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
  75. { CS53L30_ADC2B_AFE_CTL, CS53L30_ADCxy_AFE_CTL_DEFAULT },
  76. { CS53L30_ADC2A_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
  77. { CS53L30_ADC2B_DIG_VOL, CS53L30_ADCxy_DIG_VOL_DEFAULT },
  78. { CS53L30_INT_MASK, CS53L30_DEVICE_INT_MASK },
  79. };
  80. static bool cs53l30_volatile_register(struct device *dev, unsigned int reg)
  81. {
  82. if (reg == CS53L30_IS)
  83. return true;
  84. else
  85. return false;
  86. }
  87. static bool cs53l30_writeable_register(struct device *dev, unsigned int reg)
  88. {
  89. switch (reg) {
  90. case CS53L30_DEVID_AB:
  91. case CS53L30_DEVID_CD:
  92. case CS53L30_DEVID_E:
  93. case CS53L30_REVID:
  94. case CS53L30_IS:
  95. return false;
  96. default:
  97. return true;
  98. }
  99. }
  100. static bool cs53l30_readable_register(struct device *dev, unsigned int reg)
  101. {
  102. switch (reg) {
  103. case CS53L30_DEVID_AB:
  104. case CS53L30_DEVID_CD:
  105. case CS53L30_DEVID_E:
  106. case CS53L30_REVID:
  107. case CS53L30_PWRCTL:
  108. case CS53L30_MCLKCTL:
  109. case CS53L30_INT_SR_CTL:
  110. case CS53L30_MICBIAS_CTL:
  111. case CS53L30_ASPCFG_CTL:
  112. case CS53L30_ASP_CTL1:
  113. case CS53L30_ASP_TDMTX_CTL1:
  114. case CS53L30_ASP_TDMTX_CTL2:
  115. case CS53L30_ASP_TDMTX_CTL3:
  116. case CS53L30_ASP_TDMTX_CTL4:
  117. case CS53L30_ASP_TDMTX_EN1:
  118. case CS53L30_ASP_TDMTX_EN2:
  119. case CS53L30_ASP_TDMTX_EN3:
  120. case CS53L30_ASP_TDMTX_EN4:
  121. case CS53L30_ASP_TDMTX_EN5:
  122. case CS53L30_ASP_TDMTX_EN6:
  123. case CS53L30_ASP_CTL2:
  124. case CS53L30_SFT_RAMP:
  125. case CS53L30_LRCK_CTL1:
  126. case CS53L30_LRCK_CTL2:
  127. case CS53L30_MUTEP_CTL1:
  128. case CS53L30_MUTEP_CTL2:
  129. case CS53L30_INBIAS_CTL1:
  130. case CS53L30_INBIAS_CTL2:
  131. case CS53L30_DMIC1_STR_CTL:
  132. case CS53L30_DMIC2_STR_CTL:
  133. case CS53L30_ADCDMIC1_CTL1:
  134. case CS53L30_ADCDMIC1_CTL2:
  135. case CS53L30_ADC1_CTL3:
  136. case CS53L30_ADC1_NG_CTL:
  137. case CS53L30_ADC1A_AFE_CTL:
  138. case CS53L30_ADC1B_AFE_CTL:
  139. case CS53L30_ADC1A_DIG_VOL:
  140. case CS53L30_ADC1B_DIG_VOL:
  141. case CS53L30_ADCDMIC2_CTL1:
  142. case CS53L30_ADCDMIC2_CTL2:
  143. case CS53L30_ADC2_CTL3:
  144. case CS53L30_ADC2_NG_CTL:
  145. case CS53L30_ADC2A_AFE_CTL:
  146. case CS53L30_ADC2B_AFE_CTL:
  147. case CS53L30_ADC2A_DIG_VOL:
  148. case CS53L30_ADC2B_DIG_VOL:
  149. case CS53L30_INT_MASK:
  150. return true;
  151. default:
  152. return false;
  153. }
  154. }
  155. static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2000, 0);
  156. static DECLARE_TLV_DB_SCALE(adc_ng_boost_tlv, 0, 3000, 0);
  157. static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
  158. static DECLARE_TLV_DB_SCALE(dig_tlv, -9600, 100, 1);
  159. static DECLARE_TLV_DB_SCALE(pga_preamp_tlv, 0, 10000, 0);
  160. static const char * const input1_sel_text[] = {
  161. "DMIC1 On AB In",
  162. "DMIC1 On A In",
  163. "DMIC1 On B In",
  164. "ADC1 On AB In",
  165. "ADC1 On A In",
  166. "ADC1 On B In",
  167. "DMIC1 Off ADC1 Off",
  168. };
  169. static unsigned int const input1_sel_values[] = {
  170. CS53L30_CH_TYPE,
  171. CS53L30_ADCxB_PDN | CS53L30_CH_TYPE,
  172. CS53L30_ADCxA_PDN | CS53L30_CH_TYPE,
  173. CS53L30_DMICx_PDN,
  174. CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
  175. CS53L30_ADCxA_PDN | CS53L30_DMICx_PDN,
  176. CS53L30_ADCxA_PDN | CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
  177. };
  178. static const char * const input2_sel_text[] = {
  179. "DMIC2 On AB In",
  180. "DMIC2 On A In",
  181. "DMIC2 On B In",
  182. "ADC2 On AB In",
  183. "ADC2 On A In",
  184. "ADC2 On B In",
  185. "DMIC2 Off ADC2 Off",
  186. };
  187. static unsigned int const input2_sel_values[] = {
  188. 0x0,
  189. CS53L30_ADCxB_PDN,
  190. CS53L30_ADCxA_PDN,
  191. CS53L30_DMICx_PDN,
  192. CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
  193. CS53L30_ADCxA_PDN | CS53L30_DMICx_PDN,
  194. CS53L30_ADCxA_PDN | CS53L30_ADCxB_PDN | CS53L30_DMICx_PDN,
  195. };
  196. static const char * const input1_route_sel_text[] = {
  197. "ADC1_SEL", "DMIC1_SEL",
  198. };
  199. static const struct soc_enum input1_route_sel_enum =
  200. SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, CS53L30_CH_TYPE_SHIFT,
  201. ARRAY_SIZE(input1_route_sel_text),
  202. input1_route_sel_text);
  203. static SOC_VALUE_ENUM_SINGLE_DECL(input1_sel_enum, CS53L30_ADCDMIC1_CTL1, 0,
  204. CS53L30_ADCDMICx_PDN_MASK, input1_sel_text,
  205. input1_sel_values);
  206. static const struct snd_kcontrol_new input1_route_sel_mux =
  207. SOC_DAPM_ENUM("Input 1 Route", input1_route_sel_enum);
  208. static const char * const input2_route_sel_text[] = {
  209. "ADC2_SEL", "DMIC2_SEL",
  210. };
  211. /* Note: CS53L30_ADCDMIC1_CTL1 CH_TYPE controls inputs 1 and 2 */
  212. static const struct soc_enum input2_route_sel_enum =
  213. SOC_ENUM_SINGLE(CS53L30_ADCDMIC1_CTL1, 0,
  214. ARRAY_SIZE(input2_route_sel_text),
  215. input2_route_sel_text);
  216. static SOC_VALUE_ENUM_SINGLE_DECL(input2_sel_enum, CS53L30_ADCDMIC2_CTL1, 0,
  217. CS53L30_ADCDMICx_PDN_MASK, input2_sel_text,
  218. input2_sel_values);
  219. static const struct snd_kcontrol_new input2_route_sel_mux =
  220. SOC_DAPM_ENUM("Input 2 Route", input2_route_sel_enum);
  221. /*
  222. * TB = 6144*(MCLK(int) scaling factor)/MCLK(internal)
  223. * TB - Time base
  224. * NOTE: If MCLK_INT_SCALE = 0, then TB=1
  225. */
  226. static const char * const cs53l30_ng_delay_text[] = {
  227. "TB*50ms", "TB*100ms", "TB*150ms", "TB*200ms",
  228. };
  229. static const struct soc_enum adc1_ng_delay_enum =
  230. SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_DELAY_SHIFT,
  231. ARRAY_SIZE(cs53l30_ng_delay_text),
  232. cs53l30_ng_delay_text);
  233. static const struct soc_enum adc2_ng_delay_enum =
  234. SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_DELAY_SHIFT,
  235. ARRAY_SIZE(cs53l30_ng_delay_text),
  236. cs53l30_ng_delay_text);
  237. /* The noise gate threshold selected will depend on NG Boost */
  238. static const char * const cs53l30_ng_thres_text[] = {
  239. "-64dB/-34dB", "-66dB/-36dB", "-70dB/-40dB", "-73dB/-43dB",
  240. "-76dB/-46dB", "-82dB/-52dB", "-58dB", "-64dB",
  241. };
  242. static const struct soc_enum adc1_ng_thres_enum =
  243. SOC_ENUM_SINGLE(CS53L30_ADC1_NG_CTL, CS53L30_ADCx_NG_THRESH_SHIFT,
  244. ARRAY_SIZE(cs53l30_ng_thres_text),
  245. cs53l30_ng_thres_text);
  246. static const struct soc_enum adc2_ng_thres_enum =
  247. SOC_ENUM_SINGLE(CS53L30_ADC2_NG_CTL, CS53L30_ADCx_NG_THRESH_SHIFT,
  248. ARRAY_SIZE(cs53l30_ng_thres_text),
  249. cs53l30_ng_thres_text);
  250. /* Corner frequencies are with an Fs of 48kHz. */
  251. static const char * const hpf_corner_freq_text[] = {
  252. "1.86Hz", "120Hz", "235Hz", "466Hz",
  253. };
  254. static const struct soc_enum adc1_hpf_enum =
  255. SOC_ENUM_SINGLE(CS53L30_ADC1_CTL3, CS53L30_ADCx_HPF_CF_SHIFT,
  256. ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text);
  257. static const struct soc_enum adc2_hpf_enum =
  258. SOC_ENUM_SINGLE(CS53L30_ADC2_CTL3, CS53L30_ADCx_HPF_CF_SHIFT,
  259. ARRAY_SIZE(hpf_corner_freq_text), hpf_corner_freq_text);
  260. static const struct snd_kcontrol_new cs53l30_snd_controls[] = {
  261. SOC_SINGLE("Digital Soft-Ramp Switch", CS53L30_SFT_RAMP,
  262. CS53L30_DIGSFT_SHIFT, 1, 0),
  263. SOC_SINGLE("ADC1 Noise Gate Ganging Switch", CS53L30_ADC1_CTL3,
  264. CS53L30_ADCx_NG_ALL_SHIFT, 1, 0),
  265. SOC_SINGLE("ADC2 Noise Gate Ganging Switch", CS53L30_ADC2_CTL3,
  266. CS53L30_ADCx_NG_ALL_SHIFT, 1, 0),
  267. SOC_SINGLE("ADC1A Noise Gate Enable Switch", CS53L30_ADC1_NG_CTL,
  268. CS53L30_ADCxA_NG_SHIFT, 1, 0),
  269. SOC_SINGLE("ADC1B Noise Gate Enable Switch", CS53L30_ADC1_NG_CTL,
  270. CS53L30_ADCxB_NG_SHIFT, 1, 0),
  271. SOC_SINGLE("ADC2A Noise Gate Enable Switch", CS53L30_ADC2_NG_CTL,
  272. CS53L30_ADCxA_NG_SHIFT, 1, 0),
  273. SOC_SINGLE("ADC2B Noise Gate Enable Switch", CS53L30_ADC2_NG_CTL,
  274. CS53L30_ADCxB_NG_SHIFT, 1, 0),
  275. SOC_SINGLE("ADC1 Notch Filter Switch", CS53L30_ADCDMIC1_CTL2,
  276. CS53L30_ADCx_NOTCH_DIS_SHIFT, 1, 1),
  277. SOC_SINGLE("ADC2 Notch Filter Switch", CS53L30_ADCDMIC2_CTL2,
  278. CS53L30_ADCx_NOTCH_DIS_SHIFT, 1, 1),
  279. SOC_SINGLE("ADC1A Invert Switch", CS53L30_ADCDMIC1_CTL2,
  280. CS53L30_ADCxA_INV_SHIFT, 1, 0),
  281. SOC_SINGLE("ADC1B Invert Switch", CS53L30_ADCDMIC1_CTL2,
  282. CS53L30_ADCxB_INV_SHIFT, 1, 0),
  283. SOC_SINGLE("ADC2A Invert Switch", CS53L30_ADCDMIC2_CTL2,
  284. CS53L30_ADCxA_INV_SHIFT, 1, 0),
  285. SOC_SINGLE("ADC2B Invert Switch", CS53L30_ADCDMIC2_CTL2,
  286. CS53L30_ADCxB_INV_SHIFT, 1, 0),
  287. SOC_SINGLE_TLV("ADC1A Digital Boost Volume", CS53L30_ADCDMIC1_CTL2,
  288. CS53L30_ADCxA_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
  289. SOC_SINGLE_TLV("ADC1B Digital Boost Volume", CS53L30_ADCDMIC1_CTL2,
  290. CS53L30_ADCxB_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
  291. SOC_SINGLE_TLV("ADC2A Digital Boost Volume", CS53L30_ADCDMIC2_CTL2,
  292. CS53L30_ADCxA_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
  293. SOC_SINGLE_TLV("ADC2B Digital Boost Volume", CS53L30_ADCDMIC2_CTL2,
  294. CS53L30_ADCxB_DIG_BOOST_SHIFT, 1, 0, adc_boost_tlv),
  295. SOC_SINGLE_TLV("ADC1 NG Boost Volume", CS53L30_ADC1_NG_CTL,
  296. CS53L30_ADCx_NG_BOOST_SHIFT, 1, 0, adc_ng_boost_tlv),
  297. SOC_SINGLE_TLV("ADC2 NG Boost Volume", CS53L30_ADC2_NG_CTL,
  298. CS53L30_ADCx_NG_BOOST_SHIFT, 1, 0, adc_ng_boost_tlv),
  299. SOC_DOUBLE_R_TLV("ADC1 Preamplifier Volume", CS53L30_ADC1A_AFE_CTL,
  300. CS53L30_ADC1B_AFE_CTL, CS53L30_ADCxy_PREAMP_SHIFT,
  301. 2, 0, pga_preamp_tlv),
  302. SOC_DOUBLE_R_TLV("ADC2 Preamplifier Volume", CS53L30_ADC2A_AFE_CTL,
  303. CS53L30_ADC2B_AFE_CTL, CS53L30_ADCxy_PREAMP_SHIFT,
  304. 2, 0, pga_preamp_tlv),
  305. SOC_ENUM("Input 1 Channel Select", input1_sel_enum),
  306. SOC_ENUM("Input 2 Channel Select", input2_sel_enum),
  307. SOC_ENUM("ADC1 HPF Select", adc1_hpf_enum),
  308. SOC_ENUM("ADC2 HPF Select", adc2_hpf_enum),
  309. SOC_ENUM("ADC1 NG Threshold", adc1_ng_thres_enum),
  310. SOC_ENUM("ADC2 NG Threshold", adc2_ng_thres_enum),
  311. SOC_ENUM("ADC1 NG Delay", adc1_ng_delay_enum),
  312. SOC_ENUM("ADC2 NG Delay", adc2_ng_delay_enum),
  313. SOC_SINGLE_SX_TLV("ADC1A PGA Volume",
  314. CS53L30_ADC1A_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
  315. SOC_SINGLE_SX_TLV("ADC1B PGA Volume",
  316. CS53L30_ADC1B_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
  317. SOC_SINGLE_SX_TLV("ADC2A PGA Volume",
  318. CS53L30_ADC2A_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
  319. SOC_SINGLE_SX_TLV("ADC2B PGA Volume",
  320. CS53L30_ADC2B_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
  321. SOC_SINGLE_SX_TLV("ADC1A Digital Volume",
  322. CS53L30_ADC1A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
  323. SOC_SINGLE_SX_TLV("ADC1B Digital Volume",
  324. CS53L30_ADC1B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
  325. SOC_SINGLE_SX_TLV("ADC2A Digital Volume",
  326. CS53L30_ADC2A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
  327. SOC_SINGLE_SX_TLV("ADC2B Digital Volume",
  328. CS53L30_ADC2B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
  329. };
  330. static const struct snd_soc_dapm_widget cs53l30_dapm_widgets[] = {
  331. SND_SOC_DAPM_INPUT("IN1_DMIC1"),
  332. SND_SOC_DAPM_INPUT("IN2"),
  333. SND_SOC_DAPM_INPUT("IN3_DMIC2"),
  334. SND_SOC_DAPM_INPUT("IN4"),
  335. SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS53L30_MICBIAS_CTL,
  336. CS53L30_MIC1_BIAS_PDN_SHIFT, 1, NULL, 0),
  337. SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS53L30_MICBIAS_CTL,
  338. CS53L30_MIC2_BIAS_PDN_SHIFT, 1, NULL, 0),
  339. SND_SOC_DAPM_SUPPLY("MIC3 Bias", CS53L30_MICBIAS_CTL,
  340. CS53L30_MIC3_BIAS_PDN_SHIFT, 1, NULL, 0),
  341. SND_SOC_DAPM_SUPPLY("MIC4 Bias", CS53L30_MICBIAS_CTL,
  342. CS53L30_MIC4_BIAS_PDN_SHIFT, 1, NULL, 0),
  343. SND_SOC_DAPM_AIF_OUT("ASP_SDOUT1", NULL, 0, CS53L30_ASP_CTL1,
  344. CS53L30_ASP_SDOUTx_PDN_SHIFT, 1),
  345. SND_SOC_DAPM_AIF_OUT("ASP_SDOUT2", NULL, 0, CS53L30_ASP_CTL2,
  346. CS53L30_ASP_SDOUTx_PDN_SHIFT, 1),
  347. SND_SOC_DAPM_MUX("Input Mux 1", SND_SOC_NOPM, 0, 0,
  348. &input1_route_sel_mux),
  349. SND_SOC_DAPM_MUX("Input Mux 2", SND_SOC_NOPM, 0, 0,
  350. &input2_route_sel_mux),
  351. SND_SOC_DAPM_ADC("ADC1A", NULL, CS53L30_ADCDMIC1_CTL1,
  352. CS53L30_ADCxA_PDN_SHIFT, 1),
  353. SND_SOC_DAPM_ADC("ADC1B", NULL, CS53L30_ADCDMIC1_CTL1,
  354. CS53L30_ADCxB_PDN_SHIFT, 1),
  355. SND_SOC_DAPM_ADC("ADC2A", NULL, CS53L30_ADCDMIC2_CTL1,
  356. CS53L30_ADCxA_PDN_SHIFT, 1),
  357. SND_SOC_DAPM_ADC("ADC2B", NULL, CS53L30_ADCDMIC2_CTL1,
  358. CS53L30_ADCxB_PDN_SHIFT, 1),
  359. SND_SOC_DAPM_ADC("DMIC1", NULL, CS53L30_ADCDMIC1_CTL1,
  360. CS53L30_DMICx_PDN_SHIFT, 1),
  361. SND_SOC_DAPM_ADC("DMIC2", NULL, CS53L30_ADCDMIC2_CTL1,
  362. CS53L30_DMICx_PDN_SHIFT, 1),
  363. };
  364. static const struct snd_soc_dapm_route cs53l30_dapm_routes[] = {
  365. /* ADC Input Paths */
  366. {"ADC1A", NULL, "IN1_DMIC1"},
  367. {"Input Mux 1", "ADC1_SEL", "ADC1A"},
  368. {"ADC1B", NULL, "IN2"},
  369. {"ADC2A", NULL, "IN3_DMIC2"},
  370. {"Input Mux 2", "ADC2_SEL", "ADC2A"},
  371. {"ADC2B", NULL, "IN4"},
  372. /* MIC Bias Paths */
  373. {"ADC1A", NULL, "MIC1 Bias"},
  374. {"ADC1B", NULL, "MIC2 Bias"},
  375. {"ADC2A", NULL, "MIC3 Bias"},
  376. {"ADC2B", NULL, "MIC4 Bias"},
  377. /* DMIC Paths */
  378. {"DMIC1", NULL, "IN1_DMIC1"},
  379. {"Input Mux 1", "DMIC1_SEL", "DMIC1"},
  380. {"DMIC2", NULL, "IN3_DMIC2"},
  381. {"Input Mux 2", "DMIC2_SEL", "DMIC2"},
  382. };
  383. static const struct snd_soc_dapm_route cs53l30_dapm_routes_sdout1[] = {
  384. /* Output Paths when using SDOUT1 only */
  385. {"ASP_SDOUT1", NULL, "ADC1A" },
  386. {"ASP_SDOUT1", NULL, "Input Mux 1"},
  387. {"ASP_SDOUT1", NULL, "ADC1B"},
  388. {"ASP_SDOUT1", NULL, "ADC2A"},
  389. {"ASP_SDOUT1", NULL, "Input Mux 2"},
  390. {"ASP_SDOUT1", NULL, "ADC2B"},
  391. {"Capture", NULL, "ASP_SDOUT1"},
  392. };
  393. static const struct snd_soc_dapm_route cs53l30_dapm_routes_sdout2[] = {
  394. /* Output Paths when using both SDOUT1 and SDOUT2 */
  395. {"ASP_SDOUT1", NULL, "ADC1A" },
  396. {"ASP_SDOUT1", NULL, "Input Mux 1"},
  397. {"ASP_SDOUT1", NULL, "ADC1B"},
  398. {"ASP_SDOUT2", NULL, "ADC2A"},
  399. {"ASP_SDOUT2", NULL, "Input Mux 2"},
  400. {"ASP_SDOUT2", NULL, "ADC2B"},
  401. {"Capture", NULL, "ASP_SDOUT1"},
  402. {"Capture", NULL, "ASP_SDOUT2"},
  403. };
  404. struct cs53l30_mclk_div {
  405. u32 mclk_rate;
  406. u32 srate;
  407. u8 asp_rate;
  408. u8 internal_fs_ratio;
  409. u8 mclk_int_scale;
  410. };
  411. static const struct cs53l30_mclk_div cs53l30_mclk_coeffs[] = {
  412. /* NOTE: Enable MCLK_INT_SCALE to save power. */
  413. /* MCLK, Sample Rate, asp_rate, internal_fs_ratio, mclk_int_scale */
  414. {5644800, 11025, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  415. {5644800, 22050, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  416. {5644800, 44100, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  417. {6000000, 8000, 0x1, 0, CS53L30_MCLK_INT_SCALE},
  418. {6000000, 11025, 0x2, 0, CS53L30_MCLK_INT_SCALE},
  419. {6000000, 12000, 0x4, 0, CS53L30_MCLK_INT_SCALE},
  420. {6000000, 16000, 0x5, 0, CS53L30_MCLK_INT_SCALE},
  421. {6000000, 22050, 0x6, 0, CS53L30_MCLK_INT_SCALE},
  422. {6000000, 24000, 0x8, 0, CS53L30_MCLK_INT_SCALE},
  423. {6000000, 32000, 0x9, 0, CS53L30_MCLK_INT_SCALE},
  424. {6000000, 44100, 0xA, 0, CS53L30_MCLK_INT_SCALE},
  425. {6000000, 48000, 0xC, 0, CS53L30_MCLK_INT_SCALE},
  426. {6144000, 8000, 0x1, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  427. {6144000, 11025, 0x2, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  428. {6144000, 12000, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  429. {6144000, 16000, 0x5, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  430. {6144000, 22050, 0x6, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  431. {6144000, 24000, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  432. {6144000, 32000, 0x9, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  433. {6144000, 44100, 0xA, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  434. {6144000, 48000, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  435. {6400000, 8000, 0x1, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  436. {6400000, 11025, 0x2, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  437. {6400000, 12000, 0x4, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  438. {6400000, 16000, 0x5, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  439. {6400000, 22050, 0x6, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  440. {6400000, 24000, 0x8, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  441. {6400000, 32000, 0x9, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  442. {6400000, 44100, 0xA, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  443. {6400000, 48000, 0xC, CS53L30_INTRNL_FS_RATIO, CS53L30_MCLK_INT_SCALE},
  444. };
  445. struct cs53l30_mclkx_div {
  446. u32 mclkx;
  447. u8 ratio;
  448. u8 mclkdiv;
  449. };
  450. static const struct cs53l30_mclkx_div cs53l30_mclkx_coeffs[] = {
  451. {5644800, 1, CS53L30_MCLK_DIV_BY_1},
  452. {6000000, 1, CS53L30_MCLK_DIV_BY_1},
  453. {6144000, 1, CS53L30_MCLK_DIV_BY_1},
  454. {11289600, 2, CS53L30_MCLK_DIV_BY_2},
  455. {12288000, 2, CS53L30_MCLK_DIV_BY_2},
  456. {12000000, 2, CS53L30_MCLK_DIV_BY_2},
  457. {19200000, 3, CS53L30_MCLK_DIV_BY_3},
  458. };
  459. static int cs53l30_get_mclkx_coeff(int mclkx)
  460. {
  461. int i;
  462. for (i = 0; i < ARRAY_SIZE(cs53l30_mclkx_coeffs); i++) {
  463. if (cs53l30_mclkx_coeffs[i].mclkx == mclkx)
  464. return i;
  465. }
  466. return -EINVAL;
  467. }
  468. static int cs53l30_get_mclk_coeff(int mclk_rate, int srate)
  469. {
  470. int i;
  471. for (i = 0; i < ARRAY_SIZE(cs53l30_mclk_coeffs); i++) {
  472. if (cs53l30_mclk_coeffs[i].mclk_rate == mclk_rate &&
  473. cs53l30_mclk_coeffs[i].srate == srate)
  474. return i;
  475. }
  476. return -EINVAL;
  477. }
  478. static int cs53l30_set_sysclk(struct snd_soc_dai *dai,
  479. int clk_id, unsigned int freq, int dir)
  480. {
  481. struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
  482. int mclkx_coeff;
  483. u32 mclk_rate;
  484. /* MCLKX -> MCLK */
  485. mclkx_coeff = cs53l30_get_mclkx_coeff(freq);
  486. if (mclkx_coeff < 0)
  487. return mclkx_coeff;
  488. mclk_rate = cs53l30_mclkx_coeffs[mclkx_coeff].mclkx /
  489. cs53l30_mclkx_coeffs[mclkx_coeff].ratio;
  490. regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
  491. CS53L30_MCLK_DIV_MASK,
  492. cs53l30_mclkx_coeffs[mclkx_coeff].mclkdiv);
  493. priv->mclk_rate = mclk_rate;
  494. return 0;
  495. }
  496. static int cs53l30_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  497. {
  498. struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
  499. u8 aspcfg = 0, aspctl1 = 0;
  500. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  501. case SND_SOC_DAIFMT_CBM_CFM:
  502. aspcfg |= CS53L30_ASP_MS;
  503. break;
  504. case SND_SOC_DAIFMT_CBS_CFS:
  505. break;
  506. default:
  507. return -EINVAL;
  508. }
  509. /* DAI mode */
  510. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  511. case SND_SOC_DAIFMT_I2S:
  512. /* Set TDM_PDN to turn off TDM mode -- Reset default */
  513. aspctl1 |= CS53L30_ASP_TDM_PDN;
  514. break;
  515. case SND_SOC_DAIFMT_DSP_A:
  516. /*
  517. * Clear TDM_PDN to turn on TDM mode; Use ASP_SCLK_INV = 0
  518. * with SHIFT_LEFT = 1 combination as Figure 4-13 shows in
  519. * the CS53L30 datasheet
  520. */
  521. aspctl1 |= CS53L30_SHIFT_LEFT;
  522. break;
  523. default:
  524. return -EINVAL;
  525. }
  526. /* Check to see if the SCLK is inverted */
  527. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  528. case SND_SOC_DAIFMT_IB_NF:
  529. case SND_SOC_DAIFMT_IB_IF:
  530. aspcfg ^= CS53L30_ASP_SCLK_INV;
  531. break;
  532. default:
  533. break;
  534. }
  535. regmap_update_bits(priv->regmap, CS53L30_ASPCFG_CTL,
  536. CS53L30_ASP_MS | CS53L30_ASP_SCLK_INV, aspcfg);
  537. regmap_update_bits(priv->regmap, CS53L30_ASP_CTL1,
  538. CS53L30_ASP_TDM_PDN | CS53L30_SHIFT_LEFT, aspctl1);
  539. return 0;
  540. }
  541. static int cs53l30_pcm_hw_params(struct snd_pcm_substream *substream,
  542. struct snd_pcm_hw_params *params,
  543. struct snd_soc_dai *dai)
  544. {
  545. struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
  546. int srate = params_rate(params);
  547. int mclk_coeff;
  548. /* MCLK -> srate */
  549. mclk_coeff = cs53l30_get_mclk_coeff(priv->mclk_rate, srate);
  550. if (mclk_coeff < 0)
  551. return -EINVAL;
  552. regmap_update_bits(priv->regmap, CS53L30_INT_SR_CTL,
  553. CS53L30_INTRNL_FS_RATIO_MASK,
  554. cs53l30_mclk_coeffs[mclk_coeff].internal_fs_ratio);
  555. regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
  556. CS53L30_MCLK_INT_SCALE_MASK,
  557. cs53l30_mclk_coeffs[mclk_coeff].mclk_int_scale);
  558. regmap_update_bits(priv->regmap, CS53L30_ASPCFG_CTL,
  559. CS53L30_ASP_RATE_MASK,
  560. cs53l30_mclk_coeffs[mclk_coeff].asp_rate);
  561. return 0;
  562. }
  563. static int cs53l30_set_bias_level(struct snd_soc_component *component,
  564. enum snd_soc_bias_level level)
  565. {
  566. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  567. struct cs53l30_private *priv = snd_soc_component_get_drvdata(component);
  568. unsigned int reg;
  569. int i, inter_max_check, ret;
  570. switch (level) {
  571. case SND_SOC_BIAS_ON:
  572. break;
  573. case SND_SOC_BIAS_PREPARE:
  574. if (dapm->bias_level == SND_SOC_BIAS_STANDBY)
  575. regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
  576. CS53L30_PDN_LP_MASK, 0);
  577. break;
  578. case SND_SOC_BIAS_STANDBY:
  579. if (dapm->bias_level == SND_SOC_BIAS_OFF) {
  580. ret = clk_prepare_enable(priv->mclk);
  581. if (ret) {
  582. dev_err(component->dev,
  583. "failed to enable MCLK: %d\n", ret);
  584. return ret;
  585. }
  586. regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
  587. CS53L30_MCLK_DIS_MASK, 0);
  588. regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
  589. CS53L30_PDN_ULP_MASK, 0);
  590. msleep(50);
  591. } else {
  592. regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
  593. CS53L30_PDN_ULP_MASK,
  594. CS53L30_PDN_ULP);
  595. }
  596. break;
  597. case SND_SOC_BIAS_OFF:
  598. regmap_update_bits(priv->regmap, CS53L30_INT_MASK,
  599. CS53L30_PDN_DONE, 0);
  600. /*
  601. * If digital softramp is set, the amount of time required
  602. * for power down increases and depends on the digital
  603. * volume setting.
  604. */
  605. /* Set the max possible time if digsft is set */
  606. regmap_read(priv->regmap, CS53L30_SFT_RAMP, &reg);
  607. if (reg & CS53L30_DIGSFT_MASK)
  608. inter_max_check = CS53L30_PDN_POLL_MAX;
  609. else
  610. inter_max_check = 10;
  611. regmap_update_bits(priv->regmap, CS53L30_PWRCTL,
  612. CS53L30_PDN_ULP_MASK,
  613. CS53L30_PDN_ULP);
  614. /* PDN_DONE will take a min of 20ms to be set.*/
  615. msleep(20);
  616. /* Clr status */
  617. regmap_read(priv->regmap, CS53L30_IS, &reg);
  618. for (i = 0; i < inter_max_check; i++) {
  619. if (inter_max_check < 10) {
  620. usleep_range(1000, 1100);
  621. regmap_read(priv->regmap, CS53L30_IS, &reg);
  622. if (reg & CS53L30_PDN_DONE)
  623. break;
  624. } else {
  625. usleep_range(10000, 10100);
  626. regmap_read(priv->regmap, CS53L30_IS, &reg);
  627. if (reg & CS53L30_PDN_DONE)
  628. break;
  629. }
  630. }
  631. /* PDN_DONE is set. We now can disable the MCLK */
  632. regmap_update_bits(priv->regmap, CS53L30_INT_MASK,
  633. CS53L30_PDN_DONE, CS53L30_PDN_DONE);
  634. regmap_update_bits(priv->regmap, CS53L30_MCLKCTL,
  635. CS53L30_MCLK_DIS_MASK,
  636. CS53L30_MCLK_DIS);
  637. clk_disable_unprepare(priv->mclk);
  638. break;
  639. }
  640. return 0;
  641. }
  642. static int cs53l30_set_tristate(struct snd_soc_dai *dai, int tristate)
  643. {
  644. struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
  645. u8 val = tristate ? CS53L30_ASP_3ST : 0;
  646. return regmap_update_bits(priv->regmap, CS53L30_ASP_CTL1,
  647. CS53L30_ASP_3ST_MASK, val);
  648. }
  649. static unsigned int const cs53l30_src_rates[] = {
  650. 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
  651. };
  652. static const struct snd_pcm_hw_constraint_list src_constraints = {
  653. .count = ARRAY_SIZE(cs53l30_src_rates),
  654. .list = cs53l30_src_rates,
  655. };
  656. static int cs53l30_pcm_startup(struct snd_pcm_substream *substream,
  657. struct snd_soc_dai *dai)
  658. {
  659. snd_pcm_hw_constraint_list(substream->runtime, 0,
  660. SNDRV_PCM_HW_PARAM_RATE, &src_constraints);
  661. return 0;
  662. }
  663. /*
  664. * Note: CS53L30 counts the slot number per byte while ASoC counts the slot
  665. * number per slot_width. So there is a difference between the slots of ASoC
  666. * and the slots of CS53L30.
  667. */
  668. static int cs53l30_set_dai_tdm_slot(struct snd_soc_dai *dai,
  669. unsigned int tx_mask, unsigned int rx_mask,
  670. int slots, int slot_width)
  671. {
  672. struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
  673. unsigned int loc[CS53L30_TDM_SLOT_MAX] = {48, 48, 48, 48};
  674. unsigned int slot_next, slot_step;
  675. u64 tx_enable = 0;
  676. int i;
  677. if (!rx_mask) {
  678. dev_err(dai->dev, "rx masks must not be 0\n");
  679. return -EINVAL;
  680. }
  681. /* Assuming slot_width is not supposed to be greater than 64 */
  682. if (slots <= 0 || slot_width <= 0 || slot_width > 64) {
  683. dev_err(dai->dev, "invalid slot number or slot width\n");
  684. return -EINVAL;
  685. }
  686. if (slot_width & 0x7) {
  687. dev_err(dai->dev, "slot width must count in byte\n");
  688. return -EINVAL;
  689. }
  690. /* How many bytes in each ASoC slot */
  691. slot_step = slot_width >> 3;
  692. for (i = 0; rx_mask && i < CS53L30_TDM_SLOT_MAX; i++) {
  693. /* Find the first slot from LSB */
  694. slot_next = __ffs(rx_mask);
  695. /* Save the slot location by converting to CS53L30 slot */
  696. loc[i] = slot_next * slot_step;
  697. /* Create the mask of CS53L30 slot */
  698. tx_enable |= (u64)((u64)(1 << slot_step) - 1) << (u64)loc[i];
  699. /* Clear this slot from rx_mask */
  700. rx_mask &= ~(1 << slot_next);
  701. }
  702. /* Error out to avoid slot shift */
  703. if (rx_mask && i == CS53L30_TDM_SLOT_MAX) {
  704. dev_err(dai->dev, "rx_mask exceeds max slot number: %d\n",
  705. CS53L30_TDM_SLOT_MAX);
  706. return -EINVAL;
  707. }
  708. /* Validate the last active CS53L30 slot */
  709. slot_next = loc[i - 1] + slot_step - 1;
  710. if (slot_next > 47) {
  711. dev_err(dai->dev, "slot selection out of bounds: %u\n",
  712. slot_next);
  713. return -EINVAL;
  714. }
  715. for (i = 0; i < CS53L30_TDM_SLOT_MAX && loc[i] != 48; i++) {
  716. regmap_update_bits(priv->regmap, CS53L30_ASP_TDMTX_CTL(i),
  717. CS53L30_ASP_CHx_TX_LOC_MASK, loc[i]);
  718. dev_dbg(dai->dev, "loc[%d]=%x\n", i, loc[i]);
  719. }
  720. for (i = 0; i < CS53L30_ASP_TDMTX_ENx_MAX && tx_enable; i++) {
  721. regmap_write(priv->regmap, CS53L30_ASP_TDMTX_ENx(i),
  722. tx_enable & 0xff);
  723. tx_enable >>= 8;
  724. dev_dbg(dai->dev, "en_reg=%x, tx_enable=%llx\n",
  725. CS53L30_ASP_TDMTX_ENx(i), tx_enable & 0xff);
  726. }
  727. return 0;
  728. }
  729. static int cs53l30_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
  730. {
  731. struct cs53l30_private *priv = snd_soc_component_get_drvdata(dai->component);
  732. gpiod_set_value_cansleep(priv->mute_gpio, mute);
  733. return 0;
  734. }
  735. /* SNDRV_PCM_RATE_KNOT -> 12000, 24000 Hz, limit with constraint list */
  736. #define CS53L30_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT)
  737. #define CS53L30_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  738. SNDRV_PCM_FMTBIT_S24_LE)
  739. static const struct snd_soc_dai_ops cs53l30_ops = {
  740. .startup = cs53l30_pcm_startup,
  741. .hw_params = cs53l30_pcm_hw_params,
  742. .set_fmt = cs53l30_set_dai_fmt,
  743. .set_sysclk = cs53l30_set_sysclk,
  744. .set_tristate = cs53l30_set_tristate,
  745. .set_tdm_slot = cs53l30_set_dai_tdm_slot,
  746. .mute_stream = cs53l30_mute_stream,
  747. };
  748. static struct snd_soc_dai_driver cs53l30_dai = {
  749. .name = "cs53l30",
  750. .capture = {
  751. .stream_name = "Capture",
  752. .channels_min = 1,
  753. .channels_max = 4,
  754. .rates = CS53L30_RATES,
  755. .formats = CS53L30_FORMATS,
  756. },
  757. .ops = &cs53l30_ops,
  758. .symmetric_rates = 1,
  759. };
  760. static int cs53l30_component_probe(struct snd_soc_component *component)
  761. {
  762. struct cs53l30_private *priv = snd_soc_component_get_drvdata(component);
  763. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  764. if (priv->use_sdout2)
  765. snd_soc_dapm_add_routes(dapm, cs53l30_dapm_routes_sdout2,
  766. ARRAY_SIZE(cs53l30_dapm_routes_sdout2));
  767. else
  768. snd_soc_dapm_add_routes(dapm, cs53l30_dapm_routes_sdout1,
  769. ARRAY_SIZE(cs53l30_dapm_routes_sdout1));
  770. return 0;
  771. }
  772. static const struct snd_soc_component_driver cs53l30_driver = {
  773. .probe = cs53l30_component_probe,
  774. .set_bias_level = cs53l30_set_bias_level,
  775. .controls = cs53l30_snd_controls,
  776. .num_controls = ARRAY_SIZE(cs53l30_snd_controls),
  777. .dapm_widgets = cs53l30_dapm_widgets,
  778. .num_dapm_widgets = ARRAY_SIZE(cs53l30_dapm_widgets),
  779. .dapm_routes = cs53l30_dapm_routes,
  780. .num_dapm_routes = ARRAY_SIZE(cs53l30_dapm_routes),
  781. .use_pmdown_time = 1,
  782. .endianness = 1,
  783. .non_legacy_dai_naming = 1,
  784. };
  785. static struct regmap_config cs53l30_regmap = {
  786. .reg_bits = 8,
  787. .val_bits = 8,
  788. .max_register = CS53L30_MAX_REGISTER,
  789. .reg_defaults = cs53l30_reg_defaults,
  790. .num_reg_defaults = ARRAY_SIZE(cs53l30_reg_defaults),
  791. .volatile_reg = cs53l30_volatile_register,
  792. .writeable_reg = cs53l30_writeable_register,
  793. .readable_reg = cs53l30_readable_register,
  794. .cache_type = REGCACHE_RBTREE,
  795. };
  796. static int cs53l30_i2c_probe(struct i2c_client *client,
  797. const struct i2c_device_id *id)
  798. {
  799. const struct device_node *np = client->dev.of_node;
  800. struct device *dev = &client->dev;
  801. struct cs53l30_private *cs53l30;
  802. unsigned int devid = 0;
  803. unsigned int reg;
  804. int ret = 0, i;
  805. u8 val;
  806. cs53l30 = devm_kzalloc(dev, sizeof(*cs53l30), GFP_KERNEL);
  807. if (!cs53l30)
  808. return -ENOMEM;
  809. for (i = 0; i < ARRAY_SIZE(cs53l30->supplies); i++)
  810. cs53l30->supplies[i].supply = cs53l30_supply_names[i];
  811. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs53l30->supplies),
  812. cs53l30->supplies);
  813. if (ret) {
  814. dev_err(dev, "failed to get supplies: %d\n", ret);
  815. return ret;
  816. }
  817. ret = regulator_bulk_enable(ARRAY_SIZE(cs53l30->supplies),
  818. cs53l30->supplies);
  819. if (ret) {
  820. dev_err(dev, "failed to enable supplies: %d\n", ret);
  821. return ret;
  822. }
  823. /* Reset the Device */
  824. cs53l30->reset_gpio = devm_gpiod_get_optional(dev, "reset",
  825. GPIOD_OUT_LOW);
  826. if (IS_ERR(cs53l30->reset_gpio)) {
  827. ret = PTR_ERR(cs53l30->reset_gpio);
  828. goto error;
  829. }
  830. gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
  831. i2c_set_clientdata(client, cs53l30);
  832. cs53l30->mclk_rate = 0;
  833. cs53l30->regmap = devm_regmap_init_i2c(client, &cs53l30_regmap);
  834. if (IS_ERR(cs53l30->regmap)) {
  835. ret = PTR_ERR(cs53l30->regmap);
  836. dev_err(dev, "regmap_init() failed: %d\n", ret);
  837. goto error;
  838. }
  839. /* Initialize codec */
  840. ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_AB, &reg);
  841. devid = reg << 12;
  842. ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_CD, &reg);
  843. devid |= reg << 4;
  844. ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_E, &reg);
  845. devid |= (reg & 0xF0) >> 4;
  846. if (devid != CS53L30_DEVID) {
  847. ret = -ENODEV;
  848. dev_err(dev, "Device ID (%X). Expected %X\n",
  849. devid, CS53L30_DEVID);
  850. goto error;
  851. }
  852. ret = regmap_read(cs53l30->regmap, CS53L30_REVID, &reg);
  853. if (ret < 0) {
  854. dev_err(dev, "failed to get Revision ID: %d\n", ret);
  855. goto error;
  856. }
  857. /* Check if MCLK provided */
  858. cs53l30->mclk = devm_clk_get(dev, "mclk");
  859. if (IS_ERR(cs53l30->mclk)) {
  860. if (PTR_ERR(cs53l30->mclk) != -ENOENT) {
  861. ret = PTR_ERR(cs53l30->mclk);
  862. goto error;
  863. }
  864. /* Otherwise mark the mclk pointer to NULL */
  865. cs53l30->mclk = NULL;
  866. }
  867. /* Fetch the MUTE control */
  868. cs53l30->mute_gpio = devm_gpiod_get_optional(dev, "mute",
  869. GPIOD_OUT_HIGH);
  870. if (IS_ERR(cs53l30->mute_gpio)) {
  871. ret = PTR_ERR(cs53l30->mute_gpio);
  872. goto error;
  873. }
  874. if (cs53l30->mute_gpio) {
  875. /* Enable MUTE controls via MUTE pin */
  876. regmap_write(cs53l30->regmap, CS53L30_MUTEP_CTL1,
  877. CS53L30_MUTEP_CTL1_MUTEALL);
  878. /* Flip the polarity of MUTE pin */
  879. if (gpiod_is_active_low(cs53l30->mute_gpio))
  880. regmap_update_bits(cs53l30->regmap, CS53L30_MUTEP_CTL2,
  881. CS53L30_MUTE_PIN_POLARITY, 0);
  882. }
  883. if (!of_property_read_u8(np, "cirrus,micbias-lvl", &val))
  884. regmap_update_bits(cs53l30->regmap, CS53L30_MICBIAS_CTL,
  885. CS53L30_MIC_BIAS_CTRL_MASK, val);
  886. if (of_property_read_bool(np, "cirrus,use-sdout2"))
  887. cs53l30->use_sdout2 = true;
  888. dev_info(dev, "Cirrus Logic CS53L30, Revision: %02X\n", reg & 0xFF);
  889. ret = devm_snd_soc_register_component(dev, &cs53l30_driver, &cs53l30_dai, 1);
  890. if (ret) {
  891. dev_err(dev, "failed to register component: %d\n", ret);
  892. goto error;
  893. }
  894. return 0;
  895. error:
  896. regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
  897. cs53l30->supplies);
  898. return ret;
  899. }
  900. static int cs53l30_i2c_remove(struct i2c_client *client)
  901. {
  902. struct cs53l30_private *cs53l30 = i2c_get_clientdata(client);
  903. /* Hold down reset */
  904. gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
  905. regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
  906. cs53l30->supplies);
  907. return 0;
  908. }
  909. #ifdef CONFIG_PM
  910. static int cs53l30_runtime_suspend(struct device *dev)
  911. {
  912. struct cs53l30_private *cs53l30 = dev_get_drvdata(dev);
  913. regcache_cache_only(cs53l30->regmap, true);
  914. /* Hold down reset */
  915. gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
  916. regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
  917. cs53l30->supplies);
  918. return 0;
  919. }
  920. static int cs53l30_runtime_resume(struct device *dev)
  921. {
  922. struct cs53l30_private *cs53l30 = dev_get_drvdata(dev);
  923. int ret;
  924. ret = regulator_bulk_enable(ARRAY_SIZE(cs53l30->supplies),
  925. cs53l30->supplies);
  926. if (ret) {
  927. dev_err(dev, "failed to enable supplies: %d\n", ret);
  928. return ret;
  929. }
  930. gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
  931. regcache_cache_only(cs53l30->regmap, false);
  932. ret = regcache_sync(cs53l30->regmap);
  933. if (ret) {
  934. dev_err(dev, "failed to synchronize regcache: %d\n", ret);
  935. return ret;
  936. }
  937. return 0;
  938. }
  939. #endif
  940. static const struct dev_pm_ops cs53l30_runtime_pm = {
  941. SET_RUNTIME_PM_OPS(cs53l30_runtime_suspend, cs53l30_runtime_resume,
  942. NULL)
  943. };
  944. static const struct of_device_id cs53l30_of_match[] = {
  945. { .compatible = "cirrus,cs53l30", },
  946. {},
  947. };
  948. MODULE_DEVICE_TABLE(of, cs53l30_of_match);
  949. static const struct i2c_device_id cs53l30_id[] = {
  950. { "cs53l30", 0 },
  951. {}
  952. };
  953. MODULE_DEVICE_TABLE(i2c, cs53l30_id);
  954. static struct i2c_driver cs53l30_i2c_driver = {
  955. .driver = {
  956. .name = "cs53l30",
  957. .of_match_table = cs53l30_of_match,
  958. .pm = &cs53l30_runtime_pm,
  959. },
  960. .id_table = cs53l30_id,
  961. .probe = cs53l30_i2c_probe,
  962. .remove = cs53l30_i2c_remove,
  963. };
  964. module_i2c_driver(cs53l30_i2c_driver);
  965. MODULE_DESCRIPTION("ASoC CS53L30 driver");
  966. MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <Paul.Handrigan@cirrus.com>");
  967. MODULE_LICENSE("GPL");