cs43130.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * ALSA SoC CS43130 codec driver
  4. *
  5. * Copyright 2017 Cirrus Logic, Inc.
  6. *
  7. * Author: Li Xu <li.xu@cirrus.com>
  8. */
  9. #ifndef __CS43130_H__
  10. #define __CS43130_H__
  11. /* CS43130 registers addresses */
  12. /* all reg address is shifted by a byte for control byte to be LSB */
  13. #define CS43130_FIRSTREG 0x010000
  14. #define CS43130_LASTREG 0x190000
  15. #define CS43130_CHIP_ID 0x00043130
  16. #define CS4399_CHIP_ID 0x00043990
  17. #define CS43131_CHIP_ID 0x00043131
  18. #define CS43198_CHIP_ID 0x00043198
  19. #define CS43130_DEVID_AB 0x010000 /* Device ID A & B [RO] */
  20. #define CS43130_DEVID_CD 0x010001 /* Device ID C & D [RO] */
  21. #define CS43130_DEVID_E 0x010002 /* Device ID E [RO] */
  22. #define CS43130_FAB_ID 0x010003 /* Fab ID [RO] */
  23. #define CS43130_REV_ID 0x010004 /* Revision ID [RO] */
  24. #define CS43130_SUBREV_ID 0x010005 /* Subrevision ID */
  25. #define CS43130_SYS_CLK_CTL_1 0x010006 /* System Clocking Ctl 1 */
  26. #define CS43130_SP_SRATE 0x01000B /* Serial Port Sample Rate */
  27. #define CS43130_SP_BITSIZE 0x01000C /* Serial Port Bit Size */
  28. #define CS43130_PAD_INT_CFG 0x01000D /* Pad Interface Config */
  29. #define CS43130_DXD1 0x010010 /* DXD1 */
  30. #define CS43130_DXD7 0x010025 /* DXD7 */
  31. #define CS43130_DXD19 0x010026 /* DXD19 */
  32. #define CS43130_DXD17 0x010027 /* DXD17 */
  33. #define CS43130_DXD18 0x010028 /* DXD18 */
  34. #define CS43130_DXD12 0x01002C /* DXD12 */
  35. #define CS43130_DXD8 0x01002E /* DXD8 */
  36. #define CS43130_PWDN_CTL 0x020000 /* Power Down Ctl */
  37. #define CS43130_DXD2 0x020019 /* DXD2 */
  38. #define CS43130_CRYSTAL_SET 0x020052 /* Crystal Setting */
  39. #define CS43130_PLL_SET_1 0x030001 /* PLL Setting 1 */
  40. #define CS43130_PLL_SET_2 0x030002 /* PLL Setting 2 */
  41. #define CS43130_PLL_SET_3 0x030003 /* PLL Setting 3 */
  42. #define CS43130_PLL_SET_4 0x030004 /* PLL Setting 4 */
  43. #define CS43130_PLL_SET_5 0x030005 /* PLL Setting 5 */
  44. #define CS43130_PLL_SET_6 0x030008 /* PLL Setting 6 */
  45. #define CS43130_PLL_SET_7 0x03000A /* PLL Setting 7 */
  46. #define CS43130_PLL_SET_8 0x03001B /* PLL Setting 8 */
  47. #define CS43130_PLL_SET_9 0x040002 /* PLL Setting 9 */
  48. #define CS43130_PLL_SET_10 0x040003 /* PLL Setting 10 */
  49. #define CS43130_CLKOUT_CTL 0x040004 /* CLKOUT Ctl */
  50. #define CS43130_ASP_NUM_1 0x040010 /* ASP Numerator 1 */
  51. #define CS43130_ASP_NUM_2 0x040011 /* ASP Numerator 2 */
  52. #define CS43130_ASP_DEN_1 0x040012 /* ASP Denominator 1 */
  53. #define CS43130_ASP_DEN_2 0x040013 /* ASP Denominator 2 */
  54. #define CS43130_ASP_LRCK_HI_TIME_1 0x040014 /* ASP LRCK High Time 1 */
  55. #define CS43130_ASP_LRCK_HI_TIME_2 0x040015 /* ASP LRCK High Time 2 */
  56. #define CS43130_ASP_LRCK_PERIOD_1 0x040016 /* ASP LRCK Period 1 */
  57. #define CS43130_ASP_LRCK_PERIOD_2 0x040017 /* ASP LRCK Period 2 */
  58. #define CS43130_ASP_CLOCK_CONF 0x040018 /* ASP Clock Config */
  59. #define CS43130_ASP_FRAME_CONF 0x040019 /* ASP Frame Config */
  60. #define CS43130_XSP_NUM_1 0x040020 /* XSP Numerator 1 */
  61. #define CS43130_XSP_NUM_2 0x040021 /* XSP Numerator 2 */
  62. #define CS43130_XSP_DEN_1 0x040022 /* XSP Denominator 1 */
  63. #define CS43130_XSP_DEN_2 0x040023 /* XSP Denominator 2 */
  64. #define CS43130_XSP_LRCK_HI_TIME_1 0x040024 /* XSP LRCK High Time 1 */
  65. #define CS43130_XSP_LRCK_HI_TIME_2 0x040025 /* XSP LRCK High Time 2 */
  66. #define CS43130_XSP_LRCK_PERIOD_1 0x040026 /* XSP LRCK Period 1 */
  67. #define CS43130_XSP_LRCK_PERIOD_2 0x040027 /* XSP LRCK Period 2 */
  68. #define CS43130_XSP_CLOCK_CONF 0x040028 /* XSP Clock Config */
  69. #define CS43130_XSP_FRAME_CONF 0x040029 /* XSP Frame Config */
  70. #define CS43130_ASP_CH_1_LOC 0x050000 /* ASP Chan 1 Location */
  71. #define CS43130_ASP_CH_2_LOC 0x050001 /* ASP Chan 2 Location */
  72. #define CS43130_ASP_CH_1_SZ_EN 0x05000A /* ASP Chan 1 Size, Enable */
  73. #define CS43130_ASP_CH_2_SZ_EN 0x05000B /* ASP Chan 2 Size, Enable */
  74. #define CS43130_XSP_CH_1_LOC 0x060000 /* XSP Chan 1 Location */
  75. #define CS43130_XSP_CH_2_LOC 0x060001 /* XSP Chan 2 Location */
  76. #define CS43130_XSP_CH_1_SZ_EN 0x06000A /* XSP Chan 1 Size, Enable */
  77. #define CS43130_XSP_CH_2_SZ_EN 0x06000B /* XSP Chan 2 Size, Enable */
  78. #define CS43130_DSD_VOL_B 0x070000 /* DSD Volume B */
  79. #define CS43130_DSD_VOL_A 0x070001 /* DSD Volume A */
  80. #define CS43130_DSD_PATH_CTL_1 0x070002 /* DSD Proc Path Sig Ctl 1 */
  81. #define CS43130_DSD_INT_CFG 0x070003 /* DSD Interface Config */
  82. #define CS43130_DSD_PATH_CTL_2 0x070004 /* DSD Proc Path Sig Ctl 2 */
  83. #define CS43130_DSD_PCM_MIX_CTL 0x070005 /* DSD and PCM Mixing Ctl */
  84. #define CS43130_DSD_PATH_CTL_3 0x070006 /* DSD Proc Path Sig Ctl 3 */
  85. #define CS43130_HP_OUT_CTL_1 0x080000 /* HP Output Ctl 1 */
  86. #define CS43130_DXD16 0x080024 /* DXD16 */
  87. #define CS43130_DXD13 0x080032 /* DXD13 */
  88. #define CS43130_PCM_FILT_OPT 0x090000 /* PCM Filter Option */
  89. #define CS43130_PCM_VOL_B 0x090001 /* PCM Volume B */
  90. #define CS43130_PCM_VOL_A 0x090002 /* PCM Volume A */
  91. #define CS43130_PCM_PATH_CTL_1 0x090003 /* PCM Path Signal Ctl 1 */
  92. #define CS43130_PCM_PATH_CTL_2 0x090004 /* PCM Path Signal Ctl 2 */
  93. #define CS43130_DXD6 0x090097 /* DXD6 */
  94. #define CS43130_CLASS_H_CTL 0x0B0000 /* Class H Ctl */
  95. #define CS43130_DXD15 0x0B0005 /* DXD15 */
  96. #define CS43130_DXD14 0x0B0006 /* DXD14 */
  97. #define CS43130_DXD3 0x0C0002 /* DXD3 */
  98. #define CS43130_DXD10 0x0C0003 /* DXD10 */
  99. #define CS43130_DXD11 0x0C0005 /* DXD11 */
  100. #define CS43130_DXD9 0x0C0006 /* DXD9 */
  101. #define CS43130_DXD4 0x0C0009 /* DXD4 */
  102. #define CS43130_DXD5 0x0C000E /* DXD5 */
  103. #define CS43130_HP_DETECT 0x0D0000 /* HP Detect */
  104. #define CS43130_HP_STATUS 0x0D0001 /* HP Status [RO] */
  105. #define CS43130_HP_LOAD_1 0x0E0000 /* HP Load 1 */
  106. #define CS43130_HP_MEAS_LOAD_1 0x0E0003 /* HP Load Measurement 1 */
  107. #define CS43130_HP_MEAS_LOAD_2 0x0E0004 /* HP Load Measurement 2 */
  108. #define CS43130_HP_DC_STAT_1 0x0E000D /* HP DC Load Status 0 [RO] */
  109. #define CS43130_HP_DC_STAT_2 0x0E000E /* HP DC Load Status 1 [RO] */
  110. #define CS43130_HP_AC_STAT_1 0x0E0010 /* HP AC Load Status 0 [RO] */
  111. #define CS43130_HP_AC_STAT_2 0x0E0011 /* HP AC Load Status 1 [RO] */
  112. #define CS43130_HP_LOAD_STAT 0x0E001A /* HP Load Status [RO] */
  113. #define CS43130_INT_STATUS_1 0x0F0000 /* Interrupt Status 1 */
  114. #define CS43130_INT_STATUS_2 0x0F0001 /* Interrupt Status 2 */
  115. #define CS43130_INT_STATUS_3 0x0F0002 /* Interrupt Status 3 */
  116. #define CS43130_INT_STATUS_4 0x0F0003 /* Interrupt Status 4 */
  117. #define CS43130_INT_STATUS_5 0x0F0004 /* Interrupt Status 5 */
  118. #define CS43130_INT_MASK_1 0x0F0010 /* Interrupt Mask 1 */
  119. #define CS43130_INT_MASK_2 0x0F0011 /* Interrupt Mask 2 */
  120. #define CS43130_INT_MASK_3 0x0F0012 /* Interrupt Mask 3 */
  121. #define CS43130_INT_MASK_4 0x0F0013 /* Interrupt Mask 4 */
  122. #define CS43130_INT_MASK_5 0x0F0014 /* Interrupt Mask 5 */
  123. #define CS43130_MCLK_SRC_SEL_MASK 0x03
  124. #define CS43130_MCLK_SRC_SEL_SHIFT 0
  125. #define CS43130_MCLK_INT_MASK 0x04
  126. #define CS43130_MCLK_INT_SHIFT 2
  127. #define CS43130_CH_BITSIZE_MASK 0x03
  128. #define CS43130_CH_EN_MASK 0x04
  129. #define CS43130_CH_EN_SHIFT 2
  130. #define CS43130_ASP_BITSIZE_MASK 0x03
  131. #define CS43130_XSP_BITSIZE_MASK 0x0C
  132. #define CS43130_XSP_BITSIZE_SHIFT 2
  133. #define CS43130_SP_BITSIZE_ASP_SHIFT 0
  134. #define CS43130_HP_DETECT_CTRL_SHIFT 6
  135. #define CS43130_HP_DETECT_CTRL_MASK (0x03 << CS43130_HP_DETECT_CTRL_SHIFT)
  136. #define CS43130_HP_DETECT_INV_SHIFT 5
  137. #define CS43130_HP_DETECT_INV_MASK (1 << CS43130_HP_DETECT_INV_SHIFT)
  138. /* CS43130_INT_MASK_1 */
  139. #define CS43130_HP_PLUG_INT_SHIFT 6
  140. #define CS43130_HP_PLUG_INT (1 << CS43130_HP_PLUG_INT_SHIFT)
  141. #define CS43130_HP_UNPLUG_INT_SHIFT 5
  142. #define CS43130_HP_UNPLUG_INT (1 << CS43130_HP_UNPLUG_INT_SHIFT)
  143. #define CS43130_XTAL_RDY_INT_SHIFT 4
  144. #define CS43130_XTAL_RDY_INT_MASK 0x10
  145. #define CS43130_XTAL_RDY_INT (1 << CS43130_XTAL_RDY_INT_SHIFT)
  146. #define CS43130_XTAL_ERR_INT_SHIFT 3
  147. #define CS43130_XTAL_ERR_INT (1 << CS43130_XTAL_ERR_INT_SHIFT)
  148. #define CS43130_PLL_RDY_INT_MASK 0x04
  149. #define CS43130_PLL_RDY_INT_SHIFT 2
  150. #define CS43130_PLL_RDY_INT (1 << CS43130_PLL_RDY_INT_SHIFT)
  151. /* CS43130_INT_MASK_4 */
  152. #define CS43130_INT_MASK_ALL 0xFF
  153. #define CS43130_HPLOAD_NO_DC_INT_SHIFT 7
  154. #define CS43130_HPLOAD_NO_DC_INT (1 << CS43130_HPLOAD_NO_DC_INT_SHIFT)
  155. #define CS43130_HPLOAD_UNPLUG_INT_SHIFT 6
  156. #define CS43130_HPLOAD_UNPLUG_INT (1 << CS43130_HPLOAD_UNPLUG_INT_SHIFT)
  157. #define CS43130_HPLOAD_OOR_INT_SHIFT 4
  158. #define CS43130_HPLOAD_OOR_INT (1 << CS43130_HPLOAD_OOR_INT_SHIFT)
  159. #define CS43130_HPLOAD_AC_INT_SHIFT 3
  160. #define CS43130_HPLOAD_AC_INT (1 << CS43130_HPLOAD_AC_INT_SHIFT)
  161. #define CS43130_HPLOAD_DC_INT_SHIFT 2
  162. #define CS43130_HPLOAD_DC_INT (1 << CS43130_HPLOAD_DC_INT_SHIFT)
  163. #define CS43130_HPLOAD_OFF_INT_SHIFT 1
  164. #define CS43130_HPLOAD_OFF_INT (1 << CS43130_HPLOAD_OFF_INT_SHIFT)
  165. #define CS43130_HPLOAD_ON_INT 1
  166. /* CS43130_HP_LOAD_1 */
  167. #define CS43130_HPLOAD_EN_SHIFT 7
  168. #define CS43130_HPLOAD_EN (1 << CS43130_HPLOAD_EN_SHIFT)
  169. #define CS43130_HPLOAD_CHN_SEL_SHIFT 4
  170. #define CS43130_HPLOAD_CHN_SEL (1 << CS43130_HPLOAD_CHN_SEL_SHIFT)
  171. #define CS43130_HPLOAD_AC_START_SHIFT 1
  172. #define CS43130_HPLOAD_AC_START (1 << CS43130_HPLOAD_AC_START_SHIFT)
  173. #define CS43130_HPLOAD_DC_START 1
  174. /* Reg CS43130_SP_BITSIZE */
  175. #define CS43130_SP_BIT_SIZE_8 0x03
  176. #define CS43130_SP_BIT_SIZE_16 0x02
  177. #define CS43130_SP_BIT_SIZE_24 0x01
  178. #define CS43130_SP_BIT_SIZE_32 0x00
  179. /* Reg CS43130_SP_CH_SZ_EN */
  180. #define CS43130_CH_BIT_SIZE_8 0x00
  181. #define CS43130_CH_BIT_SIZE_16 0x01
  182. #define CS43130_CH_BIT_SIZE_24 0x02
  183. #define CS43130_CH_BIT_SIZE_32 0x03
  184. /* PLL */
  185. #define CS43130_PLL_START_MASK 0x01
  186. #define CS43130_PLL_MODE_MASK 0x02
  187. #define CS43130_PLL_MODE_SHIFT 1
  188. #define CS43130_PLL_REF_PREDIV_MASK 0x3
  189. #define CS43130_SP_STP_MASK 0x10
  190. #define CS43130_SP_STP_SHIFT 4
  191. #define CS43130_SP_5050_MASK 0x08
  192. #define CS43130_SP_5050_SHIFT 3
  193. #define CS43130_SP_FSD_MASK 0x07
  194. #define CS43130_SP_MODE_MASK 0x10
  195. #define CS43130_SP_MODE_SHIFT 4
  196. #define CS43130_SP_SCPOL_OUT_MASK 0x08
  197. #define CS43130_SP_SCPOL_OUT_SHIFT 3
  198. #define CS43130_SP_SCPOL_IN_MASK 0x04
  199. #define CS43130_SP_SCPOL_IN_SHIFT 2
  200. #define CS43130_SP_LCPOL_OUT_MASK 0x02
  201. #define CS43130_SP_LCPOL_OUT_SHIFT 1
  202. #define CS43130_SP_LCPOL_IN_MASK 0x01
  203. #define CS43130_SP_LCPOL_IN_SHIFT 0
  204. /* Reg CS43130_PWDN_CTL */
  205. #define CS43130_PDN_XSP_MASK 0x80
  206. #define CS43130_PDN_XSP_SHIFT 7
  207. #define CS43130_PDN_ASP_MASK 0x40
  208. #define CS43130_PDN_ASP_SHIFT 6
  209. #define CS43130_PDN_DSPIF_MASK 0x20
  210. #define CS43130_PDN_DSDIF_SHIFT 5
  211. #define CS43130_PDN_HP_MASK 0x10
  212. #define CS43130_PDN_HP_SHIFT 4
  213. #define CS43130_PDN_XTAL_MASK 0x08
  214. #define CS43130_PDN_XTAL_SHIFT 3
  215. #define CS43130_PDN_PLL_MASK 0x04
  216. #define CS43130_PDN_PLL_SHIFT 2
  217. #define CS43130_PDN_CLKOUT_MASK 0x02
  218. #define CS43130_PDN_CLKOUT_SHIFT 1
  219. /* Reg CS43130_HP_OUT_CTL_1 */
  220. #define CS43130_HP_IN_EN_SHIFT 3
  221. #define CS43130_HP_IN_EN_MASK 0x08
  222. /* Reg CS43130_PAD_INT_CFG */
  223. #define CS43130_ASP_3ST_MASK 0x01
  224. #define CS43130_XSP_3ST_MASK 0x02
  225. /* Reg CS43130_PLL_SET_2 */
  226. #define CS43130_PLL_DIV_DATA_MASK 0x000000FF
  227. #define CS43130_PLL_DIV_FRAC_0_DATA_SHIFT 0
  228. /* Reg CS43130_PLL_SET_3 */
  229. #define CS43130_PLL_DIV_FRAC_1_DATA_SHIFT 8
  230. /* Reg CS43130_PLL_SET_4 */
  231. #define CS43130_PLL_DIV_FRAC_2_DATA_SHIFT 16
  232. /* Reg CS43130_SP_DEN_1 */
  233. #define CS43130_SP_M_LSB_DATA_MASK 0x00FF
  234. #define CS43130_SP_M_LSB_DATA_SHIFT 0
  235. /* Reg CS43130_SP_DEN_2 */
  236. #define CS43130_SP_M_MSB_DATA_MASK 0xFF00
  237. #define CS43130_SP_M_MSB_DATA_SHIFT 8
  238. /* Reg CS43130_SP_NUM_1 */
  239. #define CS43130_SP_N_LSB_DATA_MASK 0x00FF
  240. #define CS43130_SP_N_LSB_DATA_SHIFT 0
  241. /* Reg CS43130_SP_NUM_2 */
  242. #define CS43130_SP_N_MSB_DATA_MASK 0xFF00
  243. #define CS43130_SP_N_MSB_DATA_SHIFT 8
  244. /* Reg CS43130_SP_LRCK_HI_TIME_1 */
  245. #define CS43130_SP_LCHI_DATA_MASK 0x00FF
  246. #define CS43130_SP_LCHI_LSB_DATA_SHIFT 0
  247. /* Reg CS43130_SP_LRCK_HI_TIME_2 */
  248. #define CS43130_SP_LCHI_MSB_DATA_SHIFT 8
  249. /* Reg CS43130_SP_LRCK_PERIOD_1 */
  250. #define CS43130_SP_LCPR_DATA_MASK 0x00FF
  251. #define CS43130_SP_LCPR_LSB_DATA_SHIFT 0
  252. /* Reg CS43130_SP_LRCK_PERIOD_2 */
  253. #define CS43130_SP_LCPR_MSB_DATA_SHIFT 8
  254. #define CS43130_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
  255. SNDRV_PCM_FMTBIT_S16_LE | \
  256. SNDRV_PCM_FMTBIT_S24_LE | \
  257. SNDRV_PCM_FMTBIT_S32_LE)
  258. #define CS43130_DOP_FORMATS (SNDRV_PCM_FMTBIT_DSD_U16_LE | \
  259. SNDRV_PCM_FMTBIT_DSD_U16_BE | \
  260. SNDRV_PCM_FMTBIT_S24_LE)
  261. /* Reg CS43130_CRYSTAL_SET */
  262. #define CS43130_XTAL_IBIAS_MASK 0x07
  263. /* Reg CS43130_PATH_CTL_1 */
  264. #define CS43130_MUTE_MASK 0x03
  265. #define CS43130_MUTE_EN 0x03
  266. /* Reg CS43130_DSD_INT_CFG */
  267. #define CS43130_DSD_MASTER 0x04
  268. /* Reg CS43130_DSD_PATH_CTL_2 */
  269. #define CS43130_DSD_SRC_MASK 0x60
  270. #define CS43130_DSD_SRC_SHIFT 5
  271. #define CS43130_DSD_EN_SHIFT 4
  272. #define CS43130_DSD_SPEED_MASK 0x04
  273. #define CS43130_DSD_SPEED_SHIFT 2
  274. /* Reg CS43130_DSD_PCM_MIX_CTL */
  275. #define CS43130_MIX_PCM_PREP_SHIFT 1
  276. #define CS43130_MIX_PCM_PREP_MASK 0x02
  277. #define CS43130_MIX_PCM_DSD_SHIFT 0
  278. #define CS43130_MIX_PCM_DSD_MASK 0x01
  279. /* Reg CS43130_HP_MEAS_LOAD */
  280. #define CS43130_HP_MEAS_LOAD_MASK 0x000000FF
  281. #define CS43130_HP_MEAS_LOAD_1_SHIFT 0
  282. #define CS43130_HP_MEAS_LOAD_2_SHIFT 8
  283. #define CS43130_MCLK_22M 22579200
  284. #define CS43130_MCLK_24M 24576000
  285. #define CS43130_LINEOUT_LOAD 5000
  286. #define CS43130_JACK_LINEOUT (SND_JACK_MECHANICAL | SND_JACK_LINEOUT)
  287. #define CS43130_JACK_HEADPHONE (SND_JACK_MECHANICAL | \
  288. SND_JACK_HEADPHONE)
  289. #define CS43130_JACK_MASK (SND_JACK_MECHANICAL | \
  290. SND_JACK_LINEOUT | \
  291. SND_JACK_HEADPHONE)
  292. enum cs43130_dsd_src {
  293. CS43130_DSD_SRC_DSD = 0,
  294. CS43130_DSD_SRC_ASP = 2,
  295. CS43130_DSD_SRC_XSP = 3,
  296. };
  297. enum cs43130_asp_rate {
  298. CS43130_ASP_SPRATE_32K = 0,
  299. CS43130_ASP_SPRATE_44_1K,
  300. CS43130_ASP_SPRATE_48K,
  301. CS43130_ASP_SPRATE_88_2K,
  302. CS43130_ASP_SPRATE_96K,
  303. CS43130_ASP_SPRATE_176_4K,
  304. CS43130_ASP_SPRATE_192K,
  305. CS43130_ASP_SPRATE_352_8K,
  306. CS43130_ASP_SPRATE_384K,
  307. };
  308. enum cs43130_mclk_src_sel {
  309. CS43130_MCLK_SRC_EXT = 0,
  310. CS43130_MCLK_SRC_PLL,
  311. CS43130_MCLK_SRC_RCO
  312. };
  313. enum cs43130_mclk_int_freq {
  314. CS43130_MCLK_24P5 = 0,
  315. CS43130_MCLK_22P5,
  316. };
  317. enum cs43130_xtal_ibias {
  318. CS43130_XTAL_UNUSED = -1,
  319. CS43130_XTAL_IBIAS_15UA = 2,
  320. CS43130_XTAL_IBIAS_12_5UA = 4,
  321. CS43130_XTAL_IBIAS_7_5UA = 6,
  322. };
  323. enum cs43130_dai_id {
  324. CS43130_ASP_PCM_DAI = 0,
  325. CS43130_ASP_DOP_DAI,
  326. CS43130_XSP_DOP_DAI,
  327. CS43130_XSP_DSD_DAI,
  328. CS43130_DAI_ID_MAX,
  329. };
  330. struct cs43130_clk_gen {
  331. unsigned int mclk_int;
  332. int fs;
  333. u16 den;
  334. u16 num;
  335. };
  336. /* frm_size = 16 */
  337. static const struct cs43130_clk_gen cs43130_16_clk_gen[] = {
  338. {22579200, 32000, 441, 10,},
  339. {22579200, 44100, 32, 1,},
  340. {22579200, 48000, 147, 5,},
  341. {22579200, 88200, 16, 1,},
  342. {22579200, 96000, 147, 10,},
  343. {22579200, 176400, 8, 1,},
  344. {22579200, 192000, 147, 20,},
  345. {22579200, 352800, 4, 1,},
  346. {22579200, 384000, 147, 40,},
  347. {24576000, 32000, 48, 1,},
  348. {24576000, 44100, 5120, 147,},
  349. {24576000, 48000, 32, 1,},
  350. {24576000, 88200, 2560, 147,},
  351. {24576000, 96000, 16, 1,},
  352. {24576000, 176400, 1280, 147,},
  353. {24576000, 192000, 8, 1,},
  354. {24576000, 352800, 640, 147,},
  355. {24576000, 384000, 4, 1,},
  356. };
  357. /* frm_size = 32 */
  358. static const struct cs43130_clk_gen cs43130_32_clk_gen[] = {
  359. {22579200, 32000, 441, 20,},
  360. {22579200, 44100, 16, 1,},
  361. {22579200, 48000, 147, 10,},
  362. {22579200, 88200, 8, 1,},
  363. {22579200, 96000, 147, 20,},
  364. {22579200, 176400, 4, 1,},
  365. {22579200, 192000, 147, 40,},
  366. {22579200, 352800, 2, 1,},
  367. {22579200, 384000, 147, 80,},
  368. {24576000, 32000, 24, 1,},
  369. {24576000, 44100, 2560, 147,},
  370. {24576000, 48000, 16, 1,},
  371. {24576000, 88200, 1280, 147,},
  372. {24576000, 96000, 8, 1,},
  373. {24576000, 176400, 640, 147,},
  374. {24576000, 192000, 4, 1,},
  375. {24576000, 352800, 320, 147,},
  376. {24576000, 384000, 2, 1,},
  377. };
  378. /* frm_size = 48 */
  379. static const struct cs43130_clk_gen cs43130_48_clk_gen[] = {
  380. {22579200, 32000, 147, 100,},
  381. {22579200, 44100, 32, 3,},
  382. {22579200, 48000, 49, 5,},
  383. {22579200, 88200, 16, 3,},
  384. {22579200, 96000, 49, 10,},
  385. {22579200, 176400, 8, 3,},
  386. {22579200, 192000, 49, 20,},
  387. {22579200, 352800, 4, 3,},
  388. {22579200, 384000, 49, 40,},
  389. {24576000, 32000, 16, 1,},
  390. {24576000, 44100, 5120, 441,},
  391. {24576000, 48000, 32, 3,},
  392. {24576000, 88200, 2560, 441,},
  393. {24576000, 96000, 16, 3,},
  394. {24576000, 176400, 1280, 441,},
  395. {24576000, 192000, 8, 3,},
  396. {24576000, 352800, 640, 441,},
  397. {24576000, 384000, 4, 3,},
  398. };
  399. /* frm_size = 64 */
  400. static const struct cs43130_clk_gen cs43130_64_clk_gen[] = {
  401. {22579200, 32000, 441, 40,},
  402. {22579200, 44100, 8, 1,},
  403. {22579200, 48000, 147, 20,},
  404. {22579200, 88200, 4, 1,},
  405. {22579200, 96000, 147, 40,},
  406. {22579200, 176400, 2, 1,},
  407. {22579200, 192000, 147, 80,},
  408. {22579200, 352800, 1, 1,},
  409. {24576000, 32000, 12, 1,},
  410. {24576000, 44100, 1280, 147,},
  411. {24576000, 48000, 8, 1,},
  412. {24576000, 88200, 640, 147,},
  413. {24576000, 96000, 4, 1,},
  414. {24576000, 176400, 320, 147,},
  415. {24576000, 192000, 2, 1,},
  416. {24576000, 352800, 160, 147,},
  417. {24576000, 384000, 1, 1,},
  418. };
  419. struct cs43130_bitwidth_map {
  420. unsigned int bitwidth;
  421. u8 sp_bit;
  422. u8 ch_bit;
  423. };
  424. struct cs43130_rate_map {
  425. int fs;
  426. int val;
  427. };
  428. #define HP_LEFT 0
  429. #define HP_RIGHT 1
  430. #define CS43130_AC_FREQ 10
  431. #define CS43130_DC_THRESHOLD 2
  432. #define CS43130_NUM_SUPPLIES 5
  433. static const char *const cs43130_supply_names[CS43130_NUM_SUPPLIES] = {
  434. "VA",
  435. "VP",
  436. "VCP",
  437. "VD",
  438. "VL",
  439. };
  440. #define CS43130_NUM_INT 5 /* number of interrupt status reg */
  441. struct cs43130_dai {
  442. unsigned int sclk;
  443. unsigned int dai_format;
  444. unsigned int dai_mode;
  445. };
  446. struct cs43130_private {
  447. struct snd_soc_component *component;
  448. struct regmap *regmap;
  449. struct regulator_bulk_data supplies[CS43130_NUM_SUPPLIES];
  450. struct gpio_desc *reset_gpio;
  451. unsigned int dev_id; /* codec device ID */
  452. int xtal_ibias;
  453. /* shared by both DAIs */
  454. struct mutex clk_mutex;
  455. int clk_req;
  456. bool pll_bypass;
  457. struct completion xtal_rdy;
  458. struct completion pll_rdy;
  459. unsigned int mclk;
  460. unsigned int mclk_int;
  461. int mclk_int_src;
  462. /* DAI specific */
  463. struct cs43130_dai dais[CS43130_DAI_ID_MAX];
  464. /* HP load specific */
  465. bool dc_meas;
  466. bool ac_meas;
  467. bool hpload_done;
  468. struct completion hpload_evt;
  469. unsigned int hpload_stat;
  470. u16 hpload_dc[2];
  471. u16 dc_threshold[CS43130_DC_THRESHOLD];
  472. u16 ac_freq[CS43130_AC_FREQ];
  473. u16 hpload_ac[CS43130_AC_FREQ][2];
  474. struct workqueue_struct *wq;
  475. struct work_struct work;
  476. struct snd_soc_jack jack;
  477. };
  478. #endif /* __CS43130_H__ */