cs43130.c 72 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cs43130.c -- CS43130 ALSA Soc Audio driver
  4. *
  5. * Copyright 2017 Cirrus Logic, Inc.
  6. *
  7. * Authors: Li Xu <li.xu@cirrus.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/gpio/consumer.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm.h>
  18. #include <linux/i2c.h>
  19. #include <linux/of_device.h>
  20. #include <linux/regmap.h>
  21. #include <linux/slab.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include <linux/of_gpio.h>
  30. #include <linux/regulator/consumer.h>
  31. #include <linux/pm_runtime.h>
  32. #include <linux/of_irq.h>
  33. #include <linux/completion.h>
  34. #include <linux/mutex.h>
  35. #include <linux/workqueue.h>
  36. #include <sound/jack.h>
  37. #include "cs43130.h"
  38. static const struct reg_default cs43130_reg_defaults[] = {
  39. {CS43130_SYS_CLK_CTL_1, 0x06},
  40. {CS43130_SP_SRATE, 0x01},
  41. {CS43130_SP_BITSIZE, 0x05},
  42. {CS43130_PAD_INT_CFG, 0x03},
  43. {CS43130_PWDN_CTL, 0xFE},
  44. {CS43130_CRYSTAL_SET, 0x04},
  45. {CS43130_PLL_SET_1, 0x00},
  46. {CS43130_PLL_SET_2, 0x00},
  47. {CS43130_PLL_SET_3, 0x00},
  48. {CS43130_PLL_SET_4, 0x00},
  49. {CS43130_PLL_SET_5, 0x40},
  50. {CS43130_PLL_SET_6, 0x10},
  51. {CS43130_PLL_SET_7, 0x80},
  52. {CS43130_PLL_SET_8, 0x03},
  53. {CS43130_PLL_SET_9, 0x02},
  54. {CS43130_PLL_SET_10, 0x02},
  55. {CS43130_CLKOUT_CTL, 0x00},
  56. {CS43130_ASP_NUM_1, 0x01},
  57. {CS43130_ASP_NUM_2, 0x00},
  58. {CS43130_ASP_DEN_1, 0x08},
  59. {CS43130_ASP_DEN_2, 0x00},
  60. {CS43130_ASP_LRCK_HI_TIME_1, 0x1F},
  61. {CS43130_ASP_LRCK_HI_TIME_2, 0x00},
  62. {CS43130_ASP_LRCK_PERIOD_1, 0x3F},
  63. {CS43130_ASP_LRCK_PERIOD_2, 0x00},
  64. {CS43130_ASP_CLOCK_CONF, 0x0C},
  65. {CS43130_ASP_FRAME_CONF, 0x0A},
  66. {CS43130_XSP_NUM_1, 0x01},
  67. {CS43130_XSP_NUM_2, 0x00},
  68. {CS43130_XSP_DEN_1, 0x02},
  69. {CS43130_XSP_DEN_2, 0x00},
  70. {CS43130_XSP_LRCK_HI_TIME_1, 0x1F},
  71. {CS43130_XSP_LRCK_HI_TIME_2, 0x00},
  72. {CS43130_XSP_LRCK_PERIOD_1, 0x3F},
  73. {CS43130_XSP_LRCK_PERIOD_2, 0x00},
  74. {CS43130_XSP_CLOCK_CONF, 0x0C},
  75. {CS43130_XSP_FRAME_CONF, 0x0A},
  76. {CS43130_ASP_CH_1_LOC, 0x00},
  77. {CS43130_ASP_CH_2_LOC, 0x00},
  78. {CS43130_ASP_CH_1_SZ_EN, 0x06},
  79. {CS43130_ASP_CH_2_SZ_EN, 0x0E},
  80. {CS43130_XSP_CH_1_LOC, 0x00},
  81. {CS43130_XSP_CH_2_LOC, 0x00},
  82. {CS43130_XSP_CH_1_SZ_EN, 0x06},
  83. {CS43130_XSP_CH_2_SZ_EN, 0x0E},
  84. {CS43130_DSD_VOL_B, 0x78},
  85. {CS43130_DSD_VOL_A, 0x78},
  86. {CS43130_DSD_PATH_CTL_1, 0xA8},
  87. {CS43130_DSD_INT_CFG, 0x00},
  88. {CS43130_DSD_PATH_CTL_2, 0x02},
  89. {CS43130_DSD_PCM_MIX_CTL, 0x00},
  90. {CS43130_DSD_PATH_CTL_3, 0x40},
  91. {CS43130_HP_OUT_CTL_1, 0x30},
  92. {CS43130_PCM_FILT_OPT, 0x02},
  93. {CS43130_PCM_VOL_B, 0x78},
  94. {CS43130_PCM_VOL_A, 0x78},
  95. {CS43130_PCM_PATH_CTL_1, 0xA8},
  96. {CS43130_PCM_PATH_CTL_2, 0x00},
  97. {CS43130_CLASS_H_CTL, 0x1E},
  98. {CS43130_HP_DETECT, 0x04},
  99. {CS43130_HP_LOAD_1, 0x00},
  100. {CS43130_HP_MEAS_LOAD_1, 0x00},
  101. {CS43130_HP_MEAS_LOAD_2, 0x00},
  102. {CS43130_INT_MASK_1, 0xFF},
  103. {CS43130_INT_MASK_2, 0xFF},
  104. {CS43130_INT_MASK_3, 0xFF},
  105. {CS43130_INT_MASK_4, 0xFF},
  106. {CS43130_INT_MASK_5, 0xFF},
  107. };
  108. static bool cs43130_volatile_register(struct device *dev, unsigned int reg)
  109. {
  110. switch (reg) {
  111. case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
  112. case CS43130_HP_DC_STAT_1 ... CS43130_HP_DC_STAT_2:
  113. case CS43130_HP_AC_STAT_1 ... CS43130_HP_AC_STAT_2:
  114. return true;
  115. default:
  116. return false;
  117. }
  118. }
  119. static bool cs43130_readable_register(struct device *dev, unsigned int reg)
  120. {
  121. switch (reg) {
  122. case CS43130_DEVID_AB ... CS43130_SYS_CLK_CTL_1:
  123. case CS43130_SP_SRATE ... CS43130_PAD_INT_CFG:
  124. case CS43130_PWDN_CTL:
  125. case CS43130_CRYSTAL_SET:
  126. case CS43130_PLL_SET_1 ... CS43130_PLL_SET_5:
  127. case CS43130_PLL_SET_6:
  128. case CS43130_PLL_SET_7:
  129. case CS43130_PLL_SET_8:
  130. case CS43130_PLL_SET_9:
  131. case CS43130_PLL_SET_10:
  132. case CS43130_CLKOUT_CTL:
  133. case CS43130_ASP_NUM_1 ... CS43130_ASP_FRAME_CONF:
  134. case CS43130_XSP_NUM_1 ... CS43130_XSP_FRAME_CONF:
  135. case CS43130_ASP_CH_1_LOC:
  136. case CS43130_ASP_CH_2_LOC:
  137. case CS43130_ASP_CH_1_SZ_EN:
  138. case CS43130_ASP_CH_2_SZ_EN:
  139. case CS43130_XSP_CH_1_LOC:
  140. case CS43130_XSP_CH_2_LOC:
  141. case CS43130_XSP_CH_1_SZ_EN:
  142. case CS43130_XSP_CH_2_SZ_EN:
  143. case CS43130_DSD_VOL_B ... CS43130_DSD_PATH_CTL_3:
  144. case CS43130_HP_OUT_CTL_1:
  145. case CS43130_PCM_FILT_OPT ... CS43130_PCM_PATH_CTL_2:
  146. case CS43130_CLASS_H_CTL:
  147. case CS43130_HP_DETECT:
  148. case CS43130_HP_STATUS:
  149. case CS43130_HP_LOAD_1:
  150. case CS43130_HP_MEAS_LOAD_1:
  151. case CS43130_HP_MEAS_LOAD_2:
  152. case CS43130_HP_DC_STAT_1:
  153. case CS43130_HP_DC_STAT_2:
  154. case CS43130_HP_AC_STAT_1:
  155. case CS43130_HP_AC_STAT_2:
  156. case CS43130_HP_LOAD_STAT:
  157. case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
  158. case CS43130_INT_MASK_1 ... CS43130_INT_MASK_5:
  159. return true;
  160. default:
  161. return false;
  162. }
  163. }
  164. static bool cs43130_precious_register(struct device *dev, unsigned int reg)
  165. {
  166. switch (reg) {
  167. case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
  168. return true;
  169. default:
  170. return false;
  171. }
  172. }
  173. struct cs43130_pll_params {
  174. unsigned int pll_in;
  175. u8 sclk_prediv;
  176. u8 pll_div_int;
  177. u32 pll_div_frac;
  178. u8 pll_mode;
  179. u8 pll_divout;
  180. unsigned int pll_out;
  181. u8 pll_cal_ratio;
  182. };
  183. static const struct cs43130_pll_params pll_ratio_table[] = {
  184. {9600000, 0x02, 0x49, 0x800000, 0x00, 0x08, 22579200, 151},
  185. {9600000, 0x02, 0x50, 0x000000, 0x00, 0x08, 24576000, 164},
  186. {11289600, 0x02, 0X40, 0, 0x01, 0x08, 22579200, 128},
  187. {11289600, 0x02, 0x44, 0x06F700, 0x0, 0x08, 24576000, 139},
  188. {12000000, 0x02, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120},
  189. {12000000, 0x02, 0x40, 0x000000, 0x00, 0x08, 24576000, 131},
  190. {12288000, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118},
  191. {12288000, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128},
  192. {13000000, 0x02, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111},
  193. {13000000, 0x02, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121},
  194. {19200000, 0x03, 0x49, 0x800000, 0x00, 0x08, 22579200, 151},
  195. {19200000, 0x03, 0x50, 0x000000, 0x00, 0x08, 24576000, 164},
  196. {22579200, 0, 0, 0, 0, 0, 22579200, 0},
  197. {22579200, 0x03, 0x44, 0x06F700, 0x00, 0x08, 24576000, 139},
  198. {24000000, 0x03, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120},
  199. {24000000, 0x03, 0x40, 0x000000, 0x00, 0x08, 24576000, 131},
  200. {24576000, 0x03, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118},
  201. {24576000, 0, 0, 0, 0, 0, 24576000, 0},
  202. {26000000, 0x03, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111},
  203. {26000000, 0x03, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121},
  204. };
  205. static const struct cs43130_pll_params *cs43130_get_pll_table(
  206. unsigned int freq_in, unsigned int freq_out)
  207. {
  208. int i;
  209. for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
  210. if (pll_ratio_table[i].pll_in == freq_in &&
  211. pll_ratio_table[i].pll_out == freq_out)
  212. return &pll_ratio_table[i];
  213. }
  214. return NULL;
  215. }
  216. static int cs43130_pll_config(struct snd_soc_component *component)
  217. {
  218. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  219. const struct cs43130_pll_params *pll_entry;
  220. dev_dbg(component->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n",
  221. cs43130->mclk, cs43130->mclk_int);
  222. pll_entry = cs43130_get_pll_table(cs43130->mclk, cs43130->mclk_int);
  223. if (!pll_entry)
  224. return -EINVAL;
  225. if (pll_entry->pll_cal_ratio == 0) {
  226. regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
  227. CS43130_PLL_START_MASK, 0);
  228. cs43130->pll_bypass = true;
  229. return 0;
  230. }
  231. cs43130->pll_bypass = false;
  232. regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_2,
  233. CS43130_PLL_DIV_DATA_MASK,
  234. pll_entry->pll_div_frac >>
  235. CS43130_PLL_DIV_FRAC_0_DATA_SHIFT);
  236. regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_3,
  237. CS43130_PLL_DIV_DATA_MASK,
  238. pll_entry->pll_div_frac >>
  239. CS43130_PLL_DIV_FRAC_1_DATA_SHIFT);
  240. regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_4,
  241. CS43130_PLL_DIV_DATA_MASK,
  242. pll_entry->pll_div_frac >>
  243. CS43130_PLL_DIV_FRAC_2_DATA_SHIFT);
  244. regmap_write(cs43130->regmap, CS43130_PLL_SET_5,
  245. pll_entry->pll_div_int);
  246. regmap_write(cs43130->regmap, CS43130_PLL_SET_6, pll_entry->pll_divout);
  247. regmap_write(cs43130->regmap, CS43130_PLL_SET_7,
  248. pll_entry->pll_cal_ratio);
  249. regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8,
  250. CS43130_PLL_MODE_MASK,
  251. pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT);
  252. regmap_write(cs43130->regmap, CS43130_PLL_SET_9,
  253. pll_entry->sclk_prediv);
  254. regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
  255. CS43130_PLL_START_MASK, 1);
  256. return 0;
  257. }
  258. static int cs43130_set_pll(struct snd_soc_component *component, int pll_id, int source,
  259. unsigned int freq_in, unsigned int freq_out)
  260. {
  261. int ret = 0;
  262. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  263. switch (freq_in) {
  264. case 9600000:
  265. case 11289600:
  266. case 12000000:
  267. case 12288000:
  268. case 13000000:
  269. case 19200000:
  270. case 22579200:
  271. case 24000000:
  272. case 24576000:
  273. case 26000000:
  274. cs43130->mclk = freq_in;
  275. break;
  276. default:
  277. dev_err(component->dev,
  278. "unsupported pll input reference clock:%d\n", freq_in);
  279. return -EINVAL;
  280. }
  281. switch (freq_out) {
  282. case 22579200:
  283. cs43130->mclk_int = freq_out;
  284. break;
  285. case 24576000:
  286. cs43130->mclk_int = freq_out;
  287. break;
  288. default:
  289. dev_err(component->dev,
  290. "unsupported pll output ref clock: %u\n", freq_out);
  291. return -EINVAL;
  292. }
  293. ret = cs43130_pll_config(component);
  294. dev_dbg(component->dev, "cs43130->pll_bypass = %d", cs43130->pll_bypass);
  295. return ret;
  296. }
  297. static int cs43130_change_clksrc(struct snd_soc_component *component,
  298. enum cs43130_mclk_src_sel src)
  299. {
  300. int ret;
  301. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  302. int mclk_int_decoded;
  303. if (src == cs43130->mclk_int_src) {
  304. /* clk source has not changed */
  305. return 0;
  306. }
  307. switch (cs43130->mclk_int) {
  308. case CS43130_MCLK_22M:
  309. mclk_int_decoded = CS43130_MCLK_22P5;
  310. break;
  311. case CS43130_MCLK_24M:
  312. mclk_int_decoded = CS43130_MCLK_24P5;
  313. break;
  314. default:
  315. dev_err(component->dev, "Invalid MCLK INT freq: %u\n", cs43130->mclk_int);
  316. return -EINVAL;
  317. }
  318. switch (src) {
  319. case CS43130_MCLK_SRC_EXT:
  320. cs43130->pll_bypass = true;
  321. cs43130->mclk_int_src = CS43130_MCLK_SRC_EXT;
  322. if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
  323. regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
  324. CS43130_PDN_XTAL_MASK,
  325. 1 << CS43130_PDN_XTAL_SHIFT);
  326. } else {
  327. reinit_completion(&cs43130->xtal_rdy);
  328. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  329. CS43130_XTAL_RDY_INT_MASK, 0);
  330. regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
  331. CS43130_PDN_XTAL_MASK, 0);
  332. ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
  333. msecs_to_jiffies(100));
  334. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  335. CS43130_XTAL_RDY_INT_MASK,
  336. 1 << CS43130_XTAL_RDY_INT_SHIFT);
  337. if (ret == 0) {
  338. dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n");
  339. return -ETIMEDOUT;
  340. }
  341. }
  342. regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
  343. CS43130_MCLK_SRC_SEL_MASK,
  344. src << CS43130_MCLK_SRC_SEL_SHIFT);
  345. regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
  346. CS43130_MCLK_INT_MASK,
  347. mclk_int_decoded << CS43130_MCLK_INT_SHIFT);
  348. usleep_range(150, 200);
  349. regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
  350. CS43130_PDN_PLL_MASK,
  351. 1 << CS43130_PDN_PLL_SHIFT);
  352. break;
  353. case CS43130_MCLK_SRC_PLL:
  354. cs43130->pll_bypass = false;
  355. cs43130->mclk_int_src = CS43130_MCLK_SRC_PLL;
  356. if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
  357. regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
  358. CS43130_PDN_XTAL_MASK,
  359. 1 << CS43130_PDN_XTAL_SHIFT);
  360. } else {
  361. reinit_completion(&cs43130->xtal_rdy);
  362. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  363. CS43130_XTAL_RDY_INT_MASK, 0);
  364. regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
  365. CS43130_PDN_XTAL_MASK, 0);
  366. ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
  367. msecs_to_jiffies(100));
  368. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  369. CS43130_XTAL_RDY_INT_MASK,
  370. 1 << CS43130_XTAL_RDY_INT_SHIFT);
  371. if (ret == 0) {
  372. dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n");
  373. return -ETIMEDOUT;
  374. }
  375. }
  376. reinit_completion(&cs43130->pll_rdy);
  377. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  378. CS43130_PLL_RDY_INT_MASK, 0);
  379. regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
  380. CS43130_PDN_PLL_MASK, 0);
  381. ret = wait_for_completion_timeout(&cs43130->pll_rdy,
  382. msecs_to_jiffies(100));
  383. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  384. CS43130_PLL_RDY_INT_MASK,
  385. 1 << CS43130_PLL_RDY_INT_SHIFT);
  386. if (ret == 0) {
  387. dev_err(component->dev, "Timeout waiting for PLL_READY interrupt\n");
  388. return -ETIMEDOUT;
  389. }
  390. regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
  391. CS43130_MCLK_SRC_SEL_MASK,
  392. src << CS43130_MCLK_SRC_SEL_SHIFT);
  393. regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
  394. CS43130_MCLK_INT_MASK,
  395. mclk_int_decoded << CS43130_MCLK_INT_SHIFT);
  396. usleep_range(150, 200);
  397. break;
  398. case CS43130_MCLK_SRC_RCO:
  399. cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;
  400. regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
  401. CS43130_MCLK_SRC_SEL_MASK,
  402. src << CS43130_MCLK_SRC_SEL_SHIFT);
  403. regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
  404. CS43130_MCLK_INT_MASK,
  405. CS43130_MCLK_22P5 << CS43130_MCLK_INT_SHIFT);
  406. usleep_range(150, 200);
  407. regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
  408. CS43130_PDN_XTAL_MASK,
  409. 1 << CS43130_PDN_XTAL_SHIFT);
  410. regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
  411. CS43130_PDN_PLL_MASK,
  412. 1 << CS43130_PDN_PLL_SHIFT);
  413. break;
  414. default:
  415. dev_err(component->dev, "Invalid MCLK source value\n");
  416. return -EINVAL;
  417. }
  418. return 0;
  419. }
  420. static const struct cs43130_bitwidth_map cs43130_bitwidth_table[] = {
  421. {8, CS43130_SP_BIT_SIZE_8, CS43130_CH_BIT_SIZE_8},
  422. {16, CS43130_SP_BIT_SIZE_16, CS43130_CH_BIT_SIZE_16},
  423. {24, CS43130_SP_BIT_SIZE_24, CS43130_CH_BIT_SIZE_24},
  424. {32, CS43130_SP_BIT_SIZE_32, CS43130_CH_BIT_SIZE_32},
  425. };
  426. static const struct cs43130_bitwidth_map *cs43130_get_bitwidth_table(
  427. unsigned int bitwidth)
  428. {
  429. int i;
  430. for (i = 0; i < ARRAY_SIZE(cs43130_bitwidth_table); i++) {
  431. if (cs43130_bitwidth_table[i].bitwidth == bitwidth)
  432. return &cs43130_bitwidth_table[i];
  433. }
  434. return NULL;
  435. }
  436. static int cs43130_set_bitwidth(int dai_id, unsigned int bitwidth_dai,
  437. struct regmap *regmap)
  438. {
  439. const struct cs43130_bitwidth_map *bw_map;
  440. bw_map = cs43130_get_bitwidth_table(bitwidth_dai);
  441. if (!bw_map)
  442. return -EINVAL;
  443. switch (dai_id) {
  444. case CS43130_ASP_PCM_DAI:
  445. case CS43130_ASP_DOP_DAI:
  446. regmap_update_bits(regmap, CS43130_ASP_CH_1_SZ_EN,
  447. CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
  448. regmap_update_bits(regmap, CS43130_ASP_CH_2_SZ_EN,
  449. CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
  450. regmap_update_bits(regmap, CS43130_SP_BITSIZE,
  451. CS43130_ASP_BITSIZE_MASK, bw_map->sp_bit);
  452. break;
  453. case CS43130_XSP_DOP_DAI:
  454. regmap_update_bits(regmap, CS43130_XSP_CH_1_SZ_EN,
  455. CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
  456. regmap_update_bits(regmap, CS43130_XSP_CH_2_SZ_EN,
  457. CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
  458. regmap_update_bits(regmap, CS43130_SP_BITSIZE,
  459. CS43130_XSP_BITSIZE_MASK, bw_map->sp_bit <<
  460. CS43130_XSP_BITSIZE_SHIFT);
  461. break;
  462. default:
  463. return -EINVAL;
  464. }
  465. return 0;
  466. }
  467. static const struct cs43130_rate_map cs43130_rate_table[] = {
  468. {32000, CS43130_ASP_SPRATE_32K},
  469. {44100, CS43130_ASP_SPRATE_44_1K},
  470. {48000, CS43130_ASP_SPRATE_48K},
  471. {88200, CS43130_ASP_SPRATE_88_2K},
  472. {96000, CS43130_ASP_SPRATE_96K},
  473. {176400, CS43130_ASP_SPRATE_176_4K},
  474. {192000, CS43130_ASP_SPRATE_192K},
  475. {352800, CS43130_ASP_SPRATE_352_8K},
  476. {384000, CS43130_ASP_SPRATE_384K},
  477. };
  478. static const struct cs43130_rate_map *cs43130_get_rate_table(int fs)
  479. {
  480. int i;
  481. for (i = 0; i < ARRAY_SIZE(cs43130_rate_table); i++) {
  482. if (cs43130_rate_table[i].fs == fs)
  483. return &cs43130_rate_table[i];
  484. }
  485. return NULL;
  486. }
  487. static const struct cs43130_clk_gen *cs43130_get_clk_gen(int mclk_int, int fs,
  488. const struct cs43130_clk_gen *clk_gen_table, int len_clk_gen_table)
  489. {
  490. int i;
  491. for (i = 0; i < len_clk_gen_table; i++) {
  492. if (clk_gen_table[i].mclk_int == mclk_int &&
  493. clk_gen_table[i].fs == fs)
  494. return &clk_gen_table[i];
  495. }
  496. return NULL;
  497. }
  498. static int cs43130_set_sp_fmt(int dai_id, unsigned int bitwidth_sclk,
  499. struct snd_pcm_hw_params *params,
  500. struct cs43130_private *cs43130)
  501. {
  502. u16 frm_size;
  503. u16 hi_size;
  504. u8 frm_delay;
  505. u8 frm_phase;
  506. u8 frm_data;
  507. u8 sclk_edge;
  508. u8 lrck_edge;
  509. u8 clk_data;
  510. u8 loc_ch1;
  511. u8 loc_ch2;
  512. u8 dai_mode_val;
  513. const struct cs43130_clk_gen *clk_gen;
  514. switch (cs43130->dais[dai_id].dai_format) {
  515. case SND_SOC_DAIFMT_I2S:
  516. hi_size = bitwidth_sclk;
  517. frm_delay = 2;
  518. frm_phase = 0;
  519. break;
  520. case SND_SOC_DAIFMT_LEFT_J:
  521. hi_size = bitwidth_sclk;
  522. frm_delay = 2;
  523. frm_phase = 1;
  524. break;
  525. case SND_SOC_DAIFMT_DSP_A:
  526. hi_size = 1;
  527. frm_delay = 2;
  528. frm_phase = 1;
  529. break;
  530. case SND_SOC_DAIFMT_DSP_B:
  531. hi_size = 1;
  532. frm_delay = 0;
  533. frm_phase = 1;
  534. break;
  535. default:
  536. return -EINVAL;
  537. }
  538. switch (cs43130->dais[dai_id].dai_mode) {
  539. case SND_SOC_DAIFMT_CBS_CFS:
  540. dai_mode_val = 0;
  541. break;
  542. case SND_SOC_DAIFMT_CBM_CFM:
  543. dai_mode_val = 1;
  544. break;
  545. default:
  546. return -EINVAL;
  547. }
  548. frm_size = bitwidth_sclk * params_channels(params);
  549. sclk_edge = 1;
  550. lrck_edge = 0;
  551. loc_ch1 = 0;
  552. loc_ch2 = bitwidth_sclk * (params_channels(params) - 1);
  553. frm_data = frm_delay & CS43130_SP_FSD_MASK;
  554. frm_data |= (frm_phase << CS43130_SP_STP_SHIFT) & CS43130_SP_STP_MASK;
  555. clk_data = lrck_edge & CS43130_SP_LCPOL_IN_MASK;
  556. clk_data |= (lrck_edge << CS43130_SP_LCPOL_OUT_SHIFT) &
  557. CS43130_SP_LCPOL_OUT_MASK;
  558. clk_data |= (sclk_edge << CS43130_SP_SCPOL_IN_SHIFT) &
  559. CS43130_SP_SCPOL_IN_MASK;
  560. clk_data |= (sclk_edge << CS43130_SP_SCPOL_OUT_SHIFT) &
  561. CS43130_SP_SCPOL_OUT_MASK;
  562. clk_data |= (dai_mode_val << CS43130_SP_MODE_SHIFT) &
  563. CS43130_SP_MODE_MASK;
  564. switch (dai_id) {
  565. case CS43130_ASP_PCM_DAI:
  566. case CS43130_ASP_DOP_DAI:
  567. regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1,
  568. CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
  569. CS43130_SP_LCPR_LSB_DATA_SHIFT);
  570. regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2,
  571. CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
  572. CS43130_SP_LCPR_MSB_DATA_SHIFT);
  573. regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1,
  574. CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
  575. CS43130_SP_LCHI_LSB_DATA_SHIFT);
  576. regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2,
  577. CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
  578. CS43130_SP_LCHI_MSB_DATA_SHIFT);
  579. regmap_write(cs43130->regmap, CS43130_ASP_FRAME_CONF, frm_data);
  580. regmap_write(cs43130->regmap, CS43130_ASP_CH_1_LOC, loc_ch1);
  581. regmap_write(cs43130->regmap, CS43130_ASP_CH_2_LOC, loc_ch2);
  582. regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN,
  583. CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
  584. regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN,
  585. CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
  586. regmap_write(cs43130->regmap, CS43130_ASP_CLOCK_CONF, clk_data);
  587. break;
  588. case CS43130_XSP_DOP_DAI:
  589. regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1,
  590. CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
  591. CS43130_SP_LCPR_LSB_DATA_SHIFT);
  592. regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2,
  593. CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
  594. CS43130_SP_LCPR_MSB_DATA_SHIFT);
  595. regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1,
  596. CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
  597. CS43130_SP_LCHI_LSB_DATA_SHIFT);
  598. regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2,
  599. CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
  600. CS43130_SP_LCHI_MSB_DATA_SHIFT);
  601. regmap_write(cs43130->regmap, CS43130_XSP_FRAME_CONF, frm_data);
  602. regmap_write(cs43130->regmap, CS43130_XSP_CH_1_LOC, loc_ch1);
  603. regmap_write(cs43130->regmap, CS43130_XSP_CH_2_LOC, loc_ch2);
  604. regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_1_SZ_EN,
  605. CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
  606. regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_2_SZ_EN,
  607. CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
  608. regmap_write(cs43130->regmap, CS43130_XSP_CLOCK_CONF, clk_data);
  609. break;
  610. default:
  611. return -EINVAL;
  612. }
  613. switch (frm_size) {
  614. case 16:
  615. clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
  616. params_rate(params),
  617. cs43130_16_clk_gen,
  618. ARRAY_SIZE(cs43130_16_clk_gen));
  619. break;
  620. case 32:
  621. clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
  622. params_rate(params),
  623. cs43130_32_clk_gen,
  624. ARRAY_SIZE(cs43130_32_clk_gen));
  625. break;
  626. case 48:
  627. clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
  628. params_rate(params),
  629. cs43130_48_clk_gen,
  630. ARRAY_SIZE(cs43130_48_clk_gen));
  631. break;
  632. case 64:
  633. clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
  634. params_rate(params),
  635. cs43130_64_clk_gen,
  636. ARRAY_SIZE(cs43130_64_clk_gen));
  637. break;
  638. default:
  639. return -EINVAL;
  640. }
  641. if (!clk_gen)
  642. return -EINVAL;
  643. switch (dai_id) {
  644. case CS43130_ASP_PCM_DAI:
  645. case CS43130_ASP_DOP_DAI:
  646. regmap_write(cs43130->regmap, CS43130_ASP_DEN_1,
  647. (clk_gen->den & CS43130_SP_M_LSB_DATA_MASK) >>
  648. CS43130_SP_M_LSB_DATA_SHIFT);
  649. regmap_write(cs43130->regmap, CS43130_ASP_DEN_2,
  650. (clk_gen->den & CS43130_SP_M_MSB_DATA_MASK) >>
  651. CS43130_SP_M_MSB_DATA_SHIFT);
  652. regmap_write(cs43130->regmap, CS43130_ASP_NUM_1,
  653. (clk_gen->num & CS43130_SP_N_LSB_DATA_MASK) >>
  654. CS43130_SP_N_LSB_DATA_SHIFT);
  655. regmap_write(cs43130->regmap, CS43130_ASP_NUM_2,
  656. (clk_gen->num & CS43130_SP_N_MSB_DATA_MASK) >>
  657. CS43130_SP_N_MSB_DATA_SHIFT);
  658. break;
  659. case CS43130_XSP_DOP_DAI:
  660. regmap_write(cs43130->regmap, CS43130_XSP_DEN_1,
  661. (clk_gen->den & CS43130_SP_M_LSB_DATA_MASK) >>
  662. CS43130_SP_M_LSB_DATA_SHIFT);
  663. regmap_write(cs43130->regmap, CS43130_XSP_DEN_2,
  664. (clk_gen->den & CS43130_SP_M_MSB_DATA_MASK) >>
  665. CS43130_SP_M_MSB_DATA_SHIFT);
  666. regmap_write(cs43130->regmap, CS43130_XSP_NUM_1,
  667. (clk_gen->num & CS43130_SP_N_LSB_DATA_MASK) >>
  668. CS43130_SP_N_LSB_DATA_SHIFT);
  669. regmap_write(cs43130->regmap, CS43130_XSP_NUM_2,
  670. (clk_gen->num & CS43130_SP_N_MSB_DATA_MASK) >>
  671. CS43130_SP_N_MSB_DATA_SHIFT);
  672. break;
  673. default:
  674. return -EINVAL;
  675. }
  676. return 0;
  677. }
  678. static int cs43130_pcm_dsd_mix(bool en, struct regmap *regmap)
  679. {
  680. if (en) {
  681. regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
  682. CS43130_MIX_PCM_PREP_MASK,
  683. 1 << CS43130_MIX_PCM_PREP_SHIFT);
  684. usleep_range(6000, 6050);
  685. regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
  686. CS43130_MIX_PCM_DSD_MASK,
  687. 1 << CS43130_MIX_PCM_DSD_SHIFT);
  688. } else {
  689. regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
  690. CS43130_MIX_PCM_DSD_MASK,
  691. 0 << CS43130_MIX_PCM_DSD_SHIFT);
  692. usleep_range(1600, 1650);
  693. regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
  694. CS43130_MIX_PCM_PREP_MASK,
  695. 0 << CS43130_MIX_PCM_PREP_SHIFT);
  696. }
  697. return 0;
  698. }
  699. static int cs43130_dsd_hw_params(struct snd_pcm_substream *substream,
  700. struct snd_pcm_hw_params *params,
  701. struct snd_soc_dai *dai)
  702. {
  703. struct snd_soc_component *component = dai->component;
  704. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  705. unsigned int required_clk;
  706. u8 dsd_speed;
  707. mutex_lock(&cs43130->clk_mutex);
  708. if (!cs43130->clk_req) {
  709. /* no DAI is currently using clk */
  710. if (!(CS43130_MCLK_22M % params_rate(params)))
  711. required_clk = CS43130_MCLK_22M;
  712. else
  713. required_clk = CS43130_MCLK_24M;
  714. cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
  715. if (cs43130->pll_bypass)
  716. cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);
  717. else
  718. cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);
  719. }
  720. cs43130->clk_req++;
  721. if (cs43130->clk_req == 2)
  722. cs43130_pcm_dsd_mix(true, cs43130->regmap);
  723. mutex_unlock(&cs43130->clk_mutex);
  724. switch (params_rate(params)) {
  725. case 176400:
  726. dsd_speed = 0;
  727. break;
  728. case 352800:
  729. dsd_speed = 1;
  730. break;
  731. default:
  732. dev_err(component->dev, "Rate(%u) not supported\n",
  733. params_rate(params));
  734. return -EINVAL;
  735. }
  736. if (cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
  737. regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
  738. CS43130_DSD_MASTER, CS43130_DSD_MASTER);
  739. else
  740. regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
  741. CS43130_DSD_MASTER, 0);
  742. regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
  743. CS43130_DSD_SPEED_MASK,
  744. dsd_speed << CS43130_DSD_SPEED_SHIFT);
  745. regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
  746. CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_DSD <<
  747. CS43130_DSD_SRC_SHIFT);
  748. return 0;
  749. }
  750. static int cs43130_hw_params(struct snd_pcm_substream *substream,
  751. struct snd_pcm_hw_params *params,
  752. struct snd_soc_dai *dai)
  753. {
  754. struct snd_soc_component *component = dai->component;
  755. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  756. const struct cs43130_rate_map *rate_map;
  757. unsigned int sclk = cs43130->dais[dai->id].sclk;
  758. unsigned int bitwidth_sclk;
  759. unsigned int bitwidth_dai = (unsigned int)(params_width(params));
  760. unsigned int required_clk;
  761. u8 dsd_speed;
  762. mutex_lock(&cs43130->clk_mutex);
  763. if (!cs43130->clk_req) {
  764. /* no DAI is currently using clk */
  765. if (!(CS43130_MCLK_22M % params_rate(params)))
  766. required_clk = CS43130_MCLK_22M;
  767. else
  768. required_clk = CS43130_MCLK_24M;
  769. cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
  770. if (cs43130->pll_bypass)
  771. cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);
  772. else
  773. cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);
  774. }
  775. cs43130->clk_req++;
  776. if (cs43130->clk_req == 2)
  777. cs43130_pcm_dsd_mix(true, cs43130->regmap);
  778. mutex_unlock(&cs43130->clk_mutex);
  779. switch (dai->id) {
  780. case CS43130_ASP_DOP_DAI:
  781. case CS43130_XSP_DOP_DAI:
  782. /* DoP bitwidth is always 24-bit */
  783. bitwidth_dai = 24;
  784. sclk = params_rate(params) * bitwidth_dai *
  785. params_channels(params);
  786. switch (params_rate(params)) {
  787. case 176400:
  788. dsd_speed = 0;
  789. break;
  790. case 352800:
  791. dsd_speed = 1;
  792. break;
  793. default:
  794. dev_err(component->dev, "Rate(%u) not supported\n",
  795. params_rate(params));
  796. return -EINVAL;
  797. }
  798. regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
  799. CS43130_DSD_SPEED_MASK,
  800. dsd_speed << CS43130_DSD_SPEED_SHIFT);
  801. break;
  802. case CS43130_ASP_PCM_DAI:
  803. rate_map = cs43130_get_rate_table(params_rate(params));
  804. if (!rate_map)
  805. return -EINVAL;
  806. regmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val);
  807. break;
  808. default:
  809. dev_err(component->dev, "Invalid DAI (%d)\n", dai->id);
  810. return -EINVAL;
  811. }
  812. switch (dai->id) {
  813. case CS43130_ASP_DOP_DAI:
  814. regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
  815. CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_ASP <<
  816. CS43130_DSD_SRC_SHIFT);
  817. break;
  818. case CS43130_XSP_DOP_DAI:
  819. regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
  820. CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_XSP <<
  821. CS43130_DSD_SRC_SHIFT);
  822. break;
  823. }
  824. if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
  825. /* Calculate SCLK in master mode if unassigned */
  826. sclk = params_rate(params) * bitwidth_dai *
  827. params_channels(params);
  828. if (!sclk) {
  829. /* at this point, SCLK must be set */
  830. dev_err(component->dev, "SCLK freq is not set\n");
  831. return -EINVAL;
  832. }
  833. bitwidth_sclk = (sclk / params_rate(params)) / params_channels(params);
  834. if (bitwidth_sclk < bitwidth_dai) {
  835. dev_err(component->dev, "Format not supported: SCLK freq is too low\n");
  836. return -EINVAL;
  837. }
  838. dev_dbg(component->dev,
  839. "sclk = %u, fs = %d, bitwidth_dai = %u\n",
  840. sclk, params_rate(params), bitwidth_dai);
  841. dev_dbg(component->dev,
  842. "bitwidth_sclk = %u, num_ch = %u\n",
  843. bitwidth_sclk, params_channels(params));
  844. cs43130_set_bitwidth(dai->id, bitwidth_dai, cs43130->regmap);
  845. cs43130_set_sp_fmt(dai->id, bitwidth_sclk, params, cs43130);
  846. return 0;
  847. }
  848. static int cs43130_hw_free(struct snd_pcm_substream *substream,
  849. struct snd_soc_dai *dai)
  850. {
  851. struct snd_soc_component *component = dai->component;
  852. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  853. mutex_lock(&cs43130->clk_mutex);
  854. cs43130->clk_req--;
  855. if (!cs43130->clk_req) {
  856. /* no DAI is currently using clk */
  857. cs43130_change_clksrc(component, CS43130_MCLK_SRC_RCO);
  858. cs43130_pcm_dsd_mix(false, cs43130->regmap);
  859. }
  860. mutex_unlock(&cs43130->clk_mutex);
  861. return 0;
  862. }
  863. static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1);
  864. static const char * const pcm_ch_text[] = {
  865. "Left-Right Ch",
  866. "Left-Left Ch",
  867. "Right-Left Ch",
  868. "Right-Right Ch",
  869. };
  870. static const struct reg_sequence pcm_ch_en_seq[] = {
  871. {CS43130_DXD1, 0x99},
  872. {0x180005, 0x8C},
  873. {0x180007, 0xAB},
  874. {0x180015, 0x31},
  875. {0x180017, 0xB2},
  876. {0x180025, 0x30},
  877. {0x180027, 0x84},
  878. {0x180035, 0x9C},
  879. {0x180037, 0xAE},
  880. {0x18000D, 0x24},
  881. {0x18000F, 0xA3},
  882. {0x18001D, 0x05},
  883. {0x18001F, 0xD4},
  884. {0x18002D, 0x0B},
  885. {0x18002F, 0xC7},
  886. {0x18003D, 0x71},
  887. {0x18003F, 0xE7},
  888. {CS43130_DXD1, 0},
  889. };
  890. static const struct reg_sequence pcm_ch_dis_seq[] = {
  891. {CS43130_DXD1, 0x99},
  892. {0x180005, 0x24},
  893. {0x180007, 0xA3},
  894. {0x180015, 0x05},
  895. {0x180017, 0xD4},
  896. {0x180025, 0x0B},
  897. {0x180027, 0xC7},
  898. {0x180035, 0x71},
  899. {0x180037, 0xE7},
  900. {0x18000D, 0x8C},
  901. {0x18000F, 0xAB},
  902. {0x18001D, 0x31},
  903. {0x18001F, 0xB2},
  904. {0x18002D, 0x30},
  905. {0x18002F, 0x84},
  906. {0x18003D, 0x9C},
  907. {0x18003F, 0xAE},
  908. {CS43130_DXD1, 0},
  909. };
  910. static int cs43130_pcm_ch_get(struct snd_kcontrol *kcontrol,
  911. struct snd_ctl_elem_value *ucontrol)
  912. {
  913. return snd_soc_get_enum_double(kcontrol, ucontrol);
  914. }
  915. static int cs43130_pcm_ch_put(struct snd_kcontrol *kcontrol,
  916. struct snd_ctl_elem_value *ucontrol)
  917. {
  918. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  919. unsigned int *item = ucontrol->value.enumerated.item;
  920. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  921. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  922. unsigned int val;
  923. if (item[0] >= e->items)
  924. return -EINVAL;
  925. val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
  926. switch (cs43130->dev_id) {
  927. case CS43131_CHIP_ID:
  928. case CS43198_CHIP_ID:
  929. if (val >= 2)
  930. regmap_multi_reg_write(cs43130->regmap, pcm_ch_en_seq,
  931. ARRAY_SIZE(pcm_ch_en_seq));
  932. else
  933. regmap_multi_reg_write(cs43130->regmap, pcm_ch_dis_seq,
  934. ARRAY_SIZE(pcm_ch_dis_seq));
  935. break;
  936. }
  937. return snd_soc_put_enum_double(kcontrol, ucontrol);
  938. }
  939. static SOC_ENUM_SINGLE_DECL(pcm_ch_enum, CS43130_PCM_PATH_CTL_2, 0,
  940. pcm_ch_text);
  941. static const char * const pcm_spd_texts[] = {
  942. "Fast",
  943. "Slow",
  944. };
  945. static SOC_ENUM_SINGLE_DECL(pcm_spd_enum, CS43130_PCM_FILT_OPT, 7,
  946. pcm_spd_texts);
  947. static const char * const dsd_texts[] = {
  948. "Off",
  949. "BCKA Mode",
  950. "BCKD Mode",
  951. };
  952. static const unsigned int dsd_values[] = {
  953. CS43130_DSD_SRC_DSD,
  954. CS43130_DSD_SRC_ASP,
  955. CS43130_DSD_SRC_XSP,
  956. };
  957. static SOC_VALUE_ENUM_SINGLE_DECL(dsd_enum, CS43130_DSD_INT_CFG, 0, 0x03,
  958. dsd_texts, dsd_values);
  959. static const struct snd_kcontrol_new cs43130_snd_controls[] = {
  960. SOC_DOUBLE_R_TLV("Master Playback Volume",
  961. CS43130_PCM_VOL_A, CS43130_PCM_VOL_B, 0, 0xFF, 1,
  962. pcm_vol_tlv),
  963. SOC_DOUBLE_R_TLV("Master DSD Playback Volume",
  964. CS43130_DSD_VOL_A, CS43130_DSD_VOL_B, 0, 0xFF, 1,
  965. pcm_vol_tlv),
  966. SOC_ENUM_EXT("PCM Ch Select", pcm_ch_enum, cs43130_pcm_ch_get,
  967. cs43130_pcm_ch_put),
  968. SOC_ENUM("PCM Filter Speed", pcm_spd_enum),
  969. SOC_SINGLE("PCM Phase Compensation", CS43130_PCM_FILT_OPT, 6, 1, 0),
  970. SOC_SINGLE("PCM Nonoversample Emulate", CS43130_PCM_FILT_OPT, 5, 1, 0),
  971. SOC_SINGLE("PCM High-pass Filter", CS43130_PCM_FILT_OPT, 1, 1, 0),
  972. SOC_SINGLE("PCM De-emphasis Filter", CS43130_PCM_FILT_OPT, 0, 1, 0),
  973. SOC_ENUM("DSD Phase Modulation", dsd_enum),
  974. };
  975. static const struct reg_sequence pcm_seq[] = {
  976. {CS43130_DXD1, 0x99},
  977. {CS43130_DXD7, 0x01},
  978. {CS43130_DXD8, 0},
  979. {CS43130_DXD9, 0x01},
  980. {CS43130_DXD3, 0x12},
  981. {CS43130_DXD4, 0},
  982. {CS43130_DXD10, 0x28},
  983. {CS43130_DXD11, 0x28},
  984. {CS43130_DXD1, 0},
  985. };
  986. static const struct reg_sequence dsd_seq[] = {
  987. {CS43130_DXD1, 0x99},
  988. {CS43130_DXD7, 0x01},
  989. {CS43130_DXD8, 0},
  990. {CS43130_DXD9, 0x01},
  991. {CS43130_DXD3, 0x12},
  992. {CS43130_DXD4, 0},
  993. {CS43130_DXD10, 0x1E},
  994. {CS43130_DXD11, 0x20},
  995. {CS43130_DXD1, 0},
  996. };
  997. static const struct reg_sequence pop_free_seq[] = {
  998. {CS43130_DXD1, 0x99},
  999. {CS43130_DXD12, 0x0A},
  1000. {CS43130_DXD1, 0},
  1001. };
  1002. static const struct reg_sequence pop_free_seq2[] = {
  1003. {CS43130_DXD1, 0x99},
  1004. {CS43130_DXD13, 0x20},
  1005. {CS43130_DXD1, 0},
  1006. };
  1007. static const struct reg_sequence mute_seq[] = {
  1008. {CS43130_DXD1, 0x99},
  1009. {CS43130_DXD3, 0x12},
  1010. {CS43130_DXD5, 0x02},
  1011. {CS43130_DXD4, 0x12},
  1012. {CS43130_DXD1, 0},
  1013. };
  1014. static const struct reg_sequence unmute_seq[] = {
  1015. {CS43130_DXD1, 0x99},
  1016. {CS43130_DXD3, 0x10},
  1017. {CS43130_DXD5, 0},
  1018. {CS43130_DXD4, 0x16},
  1019. {CS43130_DXD1, 0},
  1020. };
  1021. static int cs43130_dsd_event(struct snd_soc_dapm_widget *w,
  1022. struct snd_kcontrol *kcontrol, int event)
  1023. {
  1024. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1025. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  1026. switch (event) {
  1027. case SND_SOC_DAPM_PRE_PMU:
  1028. switch (cs43130->dev_id) {
  1029. case CS43130_CHIP_ID:
  1030. case CS4399_CHIP_ID:
  1031. regmap_multi_reg_write(cs43130->regmap, dsd_seq,
  1032. ARRAY_SIZE(dsd_seq));
  1033. break;
  1034. }
  1035. break;
  1036. case SND_SOC_DAPM_POST_PMU:
  1037. regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_1,
  1038. CS43130_MUTE_MASK, 0);
  1039. switch (cs43130->dev_id) {
  1040. case CS43130_CHIP_ID:
  1041. case CS4399_CHIP_ID:
  1042. regmap_multi_reg_write(cs43130->regmap, unmute_seq,
  1043. ARRAY_SIZE(unmute_seq));
  1044. break;
  1045. }
  1046. break;
  1047. case SND_SOC_DAPM_PRE_PMD:
  1048. switch (cs43130->dev_id) {
  1049. case CS43130_CHIP_ID:
  1050. case CS4399_CHIP_ID:
  1051. regmap_multi_reg_write(cs43130->regmap, mute_seq,
  1052. ARRAY_SIZE(mute_seq));
  1053. regmap_update_bits(cs43130->regmap,
  1054. CS43130_DSD_PATH_CTL_1,
  1055. CS43130_MUTE_MASK, CS43130_MUTE_EN);
  1056. /*
  1057. * DSD Power Down Sequence
  1058. * According to Design, 130ms is preferred.
  1059. */
  1060. msleep(130);
  1061. break;
  1062. case CS43131_CHIP_ID:
  1063. case CS43198_CHIP_ID:
  1064. regmap_update_bits(cs43130->regmap,
  1065. CS43130_DSD_PATH_CTL_1,
  1066. CS43130_MUTE_MASK, CS43130_MUTE_EN);
  1067. break;
  1068. }
  1069. break;
  1070. default:
  1071. dev_err(component->dev, "Invalid event = 0x%x\n", event);
  1072. return -EINVAL;
  1073. }
  1074. return 0;
  1075. }
  1076. static int cs43130_pcm_event(struct snd_soc_dapm_widget *w,
  1077. struct snd_kcontrol *kcontrol, int event)
  1078. {
  1079. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1080. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  1081. switch (event) {
  1082. case SND_SOC_DAPM_PRE_PMU:
  1083. switch (cs43130->dev_id) {
  1084. case CS43130_CHIP_ID:
  1085. case CS4399_CHIP_ID:
  1086. regmap_multi_reg_write(cs43130->regmap, pcm_seq,
  1087. ARRAY_SIZE(pcm_seq));
  1088. break;
  1089. }
  1090. break;
  1091. case SND_SOC_DAPM_POST_PMU:
  1092. regmap_update_bits(cs43130->regmap, CS43130_PCM_PATH_CTL_1,
  1093. CS43130_MUTE_MASK, 0);
  1094. switch (cs43130->dev_id) {
  1095. case CS43130_CHIP_ID:
  1096. case CS4399_CHIP_ID:
  1097. regmap_multi_reg_write(cs43130->regmap, unmute_seq,
  1098. ARRAY_SIZE(unmute_seq));
  1099. break;
  1100. }
  1101. break;
  1102. case SND_SOC_DAPM_PRE_PMD:
  1103. switch (cs43130->dev_id) {
  1104. case CS43130_CHIP_ID:
  1105. case CS4399_CHIP_ID:
  1106. regmap_multi_reg_write(cs43130->regmap, mute_seq,
  1107. ARRAY_SIZE(mute_seq));
  1108. regmap_update_bits(cs43130->regmap,
  1109. CS43130_PCM_PATH_CTL_1,
  1110. CS43130_MUTE_MASK, CS43130_MUTE_EN);
  1111. /*
  1112. * PCM Power Down Sequence
  1113. * According to Design, 130ms is preferred.
  1114. */
  1115. msleep(130);
  1116. break;
  1117. case CS43131_CHIP_ID:
  1118. case CS43198_CHIP_ID:
  1119. regmap_update_bits(cs43130->regmap,
  1120. CS43130_PCM_PATH_CTL_1,
  1121. CS43130_MUTE_MASK, CS43130_MUTE_EN);
  1122. break;
  1123. }
  1124. break;
  1125. default:
  1126. dev_err(component->dev, "Invalid event = 0x%x\n", event);
  1127. return -EINVAL;
  1128. }
  1129. return 0;
  1130. }
  1131. static const struct reg_sequence dac_postpmu_seq[] = {
  1132. {CS43130_DXD9, 0x0C},
  1133. {CS43130_DXD3, 0x10},
  1134. {CS43130_DXD4, 0x20},
  1135. };
  1136. static const struct reg_sequence dac_postpmd_seq[] = {
  1137. {CS43130_DXD1, 0x99},
  1138. {CS43130_DXD6, 0x01},
  1139. {CS43130_DXD1, 0},
  1140. };
  1141. static int cs43130_dac_event(struct snd_soc_dapm_widget *w,
  1142. struct snd_kcontrol *kcontrol, int event)
  1143. {
  1144. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1145. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  1146. switch (event) {
  1147. case SND_SOC_DAPM_PRE_PMU:
  1148. switch (cs43130->dev_id) {
  1149. case CS43130_CHIP_ID:
  1150. case CS4399_CHIP_ID:
  1151. regmap_multi_reg_write(cs43130->regmap, pop_free_seq,
  1152. ARRAY_SIZE(pop_free_seq));
  1153. break;
  1154. case CS43131_CHIP_ID:
  1155. case CS43198_CHIP_ID:
  1156. regmap_multi_reg_write(cs43130->regmap, pop_free_seq2,
  1157. ARRAY_SIZE(pop_free_seq2));
  1158. break;
  1159. }
  1160. break;
  1161. case SND_SOC_DAPM_POST_PMU:
  1162. usleep_range(10000, 10050);
  1163. regmap_write(cs43130->regmap, CS43130_DXD1, 0x99);
  1164. switch (cs43130->dev_id) {
  1165. case CS43130_CHIP_ID:
  1166. case CS4399_CHIP_ID:
  1167. regmap_multi_reg_write(cs43130->regmap, dac_postpmu_seq,
  1168. ARRAY_SIZE(dac_postpmu_seq));
  1169. /*
  1170. * Per datasheet, Sec. PCM Power-Up Sequence.
  1171. * According to Design, CS43130_DXD12 must be 0 to meet
  1172. * THDN and Dynamic Range spec.
  1173. */
  1174. msleep(1000);
  1175. regmap_write(cs43130->regmap, CS43130_DXD12, 0);
  1176. break;
  1177. case CS43131_CHIP_ID:
  1178. case CS43198_CHIP_ID:
  1179. usleep_range(12000, 12010);
  1180. regmap_write(cs43130->regmap, CS43130_DXD13, 0);
  1181. break;
  1182. }
  1183. regmap_write(cs43130->regmap, CS43130_DXD1, 0);
  1184. break;
  1185. case SND_SOC_DAPM_POST_PMD:
  1186. switch (cs43130->dev_id) {
  1187. case CS43130_CHIP_ID:
  1188. case CS4399_CHIP_ID:
  1189. regmap_multi_reg_write(cs43130->regmap, dac_postpmd_seq,
  1190. ARRAY_SIZE(dac_postpmd_seq));
  1191. break;
  1192. }
  1193. break;
  1194. default:
  1195. dev_err(component->dev, "Invalid DAC event = 0x%x\n", event);
  1196. return -EINVAL;
  1197. }
  1198. return 0;
  1199. }
  1200. static const struct reg_sequence hpin_prepmd_seq[] = {
  1201. {CS43130_DXD1, 0x99},
  1202. {CS43130_DXD15, 0x64},
  1203. {CS43130_DXD14, 0},
  1204. {CS43130_DXD2, 0},
  1205. {CS43130_DXD1, 0},
  1206. };
  1207. static const struct reg_sequence hpin_postpmu_seq[] = {
  1208. {CS43130_DXD1, 0x99},
  1209. {CS43130_DXD2, 1},
  1210. {CS43130_DXD14, 0xDC},
  1211. {CS43130_DXD15, 0xE4},
  1212. {CS43130_DXD1, 0},
  1213. };
  1214. static int cs43130_hpin_event(struct snd_soc_dapm_widget *w,
  1215. struct snd_kcontrol *kcontrol, int event)
  1216. {
  1217. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1218. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  1219. switch (event) {
  1220. case SND_SOC_DAPM_POST_PMD:
  1221. regmap_multi_reg_write(cs43130->regmap, hpin_prepmd_seq,
  1222. ARRAY_SIZE(hpin_prepmd_seq));
  1223. break;
  1224. case SND_SOC_DAPM_PRE_PMU:
  1225. regmap_multi_reg_write(cs43130->regmap, hpin_postpmu_seq,
  1226. ARRAY_SIZE(hpin_postpmu_seq));
  1227. break;
  1228. default:
  1229. dev_err(component->dev, "Invalid HPIN event = 0x%x\n", event);
  1230. return -EINVAL;
  1231. }
  1232. return 0;
  1233. }
  1234. static const struct snd_soc_dapm_widget digital_hp_widgets[] = {
  1235. SND_SOC_DAPM_OUTPUT("HPOUTA"),
  1236. SND_SOC_DAPM_OUTPUT("HPOUTB"),
  1237. SND_SOC_DAPM_AIF_IN_E("ASPIN PCM", NULL, 0, CS43130_PWDN_CTL,
  1238. CS43130_PDN_ASP_SHIFT, 1, cs43130_pcm_event,
  1239. (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1240. SND_SOC_DAPM_PRE_PMD)),
  1241. SND_SOC_DAPM_AIF_IN_E("ASPIN DoP", NULL, 0, CS43130_PWDN_CTL,
  1242. CS43130_PDN_ASP_SHIFT, 1, cs43130_dsd_event,
  1243. (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1244. SND_SOC_DAPM_PRE_PMD)),
  1245. SND_SOC_DAPM_AIF_IN_E("XSPIN DoP", NULL, 0, CS43130_PWDN_CTL,
  1246. CS43130_PDN_XSP_SHIFT, 1, cs43130_dsd_event,
  1247. (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1248. SND_SOC_DAPM_PRE_PMD)),
  1249. SND_SOC_DAPM_AIF_IN_E("XSPIN DSD", NULL, 0, CS43130_PWDN_CTL,
  1250. CS43130_PDN_DSDIF_SHIFT, 1, cs43130_dsd_event,
  1251. (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1252. SND_SOC_DAPM_PRE_PMD)),
  1253. SND_SOC_DAPM_DAC("DSD", NULL, CS43130_DSD_PATH_CTL_2,
  1254. CS43130_DSD_EN_SHIFT, 0),
  1255. SND_SOC_DAPM_DAC_E("HiFi DAC", NULL, CS43130_PWDN_CTL,
  1256. CS43130_PDN_HP_SHIFT, 1, cs43130_dac_event,
  1257. (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1258. SND_SOC_DAPM_POST_PMD)),
  1259. };
  1260. static const struct snd_soc_dapm_widget analog_hp_widgets[] = {
  1261. SND_SOC_DAPM_DAC_E("Analog Playback", NULL, CS43130_HP_OUT_CTL_1,
  1262. CS43130_HP_IN_EN_SHIFT, 0, cs43130_hpin_event,
  1263. (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)),
  1264. };
  1265. static struct snd_soc_dapm_widget all_hp_widgets[
  1266. ARRAY_SIZE(digital_hp_widgets) +
  1267. ARRAY_SIZE(analog_hp_widgets)];
  1268. static const struct snd_soc_dapm_route digital_hp_routes[] = {
  1269. {"ASPIN PCM", NULL, "ASP PCM Playback"},
  1270. {"ASPIN DoP", NULL, "ASP DoP Playback"},
  1271. {"XSPIN DoP", NULL, "XSP DoP Playback"},
  1272. {"XSPIN DSD", NULL, "XSP DSD Playback"},
  1273. {"DSD", NULL, "ASPIN DoP"},
  1274. {"DSD", NULL, "XSPIN DoP"},
  1275. {"DSD", NULL, "XSPIN DSD"},
  1276. {"HiFi DAC", NULL, "ASPIN PCM"},
  1277. {"HiFi DAC", NULL, "DSD"},
  1278. {"HPOUTA", NULL, "HiFi DAC"},
  1279. {"HPOUTB", NULL, "HiFi DAC"},
  1280. };
  1281. static const struct snd_soc_dapm_route analog_hp_routes[] = {
  1282. {"HPOUTA", NULL, "Analog Playback"},
  1283. {"HPOUTB", NULL, "Analog Playback"},
  1284. };
  1285. static struct snd_soc_dapm_route all_hp_routes[
  1286. ARRAY_SIZE(digital_hp_routes) +
  1287. ARRAY_SIZE(analog_hp_routes)];
  1288. static const unsigned int cs43130_asp_src_rates[] = {
  1289. 32000, 44100, 48000, 88200, 96000, 176400, 192000, 352800, 384000
  1290. };
  1291. static const struct snd_pcm_hw_constraint_list cs43130_asp_constraints = {
  1292. .count = ARRAY_SIZE(cs43130_asp_src_rates),
  1293. .list = cs43130_asp_src_rates,
  1294. };
  1295. static int cs43130_pcm_startup(struct snd_pcm_substream *substream,
  1296. struct snd_soc_dai *dai)
  1297. {
  1298. return snd_pcm_hw_constraint_list(substream->runtime, 0,
  1299. SNDRV_PCM_HW_PARAM_RATE,
  1300. &cs43130_asp_constraints);
  1301. }
  1302. static const unsigned int cs43130_dop_src_rates[] = {
  1303. 176400, 352800,
  1304. };
  1305. static const struct snd_pcm_hw_constraint_list cs43130_dop_constraints = {
  1306. .count = ARRAY_SIZE(cs43130_dop_src_rates),
  1307. .list = cs43130_dop_src_rates,
  1308. };
  1309. static int cs43130_dop_startup(struct snd_pcm_substream *substream,
  1310. struct snd_soc_dai *dai)
  1311. {
  1312. return snd_pcm_hw_constraint_list(substream->runtime, 0,
  1313. SNDRV_PCM_HW_PARAM_RATE,
  1314. &cs43130_dop_constraints);
  1315. }
  1316. static int cs43130_pcm_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  1317. {
  1318. struct snd_soc_component *component = codec_dai->component;
  1319. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  1320. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1321. case SND_SOC_DAIFMT_CBS_CFS:
  1322. cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS;
  1323. break;
  1324. case SND_SOC_DAIFMT_CBM_CFM:
  1325. cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM;
  1326. break;
  1327. default:
  1328. dev_err(component->dev, "unsupported mode\n");
  1329. return -EINVAL;
  1330. }
  1331. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1332. case SND_SOC_DAIFMT_I2S:
  1333. cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_I2S;
  1334. break;
  1335. case SND_SOC_DAIFMT_LEFT_J:
  1336. cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_LEFT_J;
  1337. break;
  1338. case SND_SOC_DAIFMT_DSP_A:
  1339. cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_A;
  1340. break;
  1341. case SND_SOC_DAIFMT_DSP_B:
  1342. cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_B;
  1343. break;
  1344. default:
  1345. dev_err(component->dev,
  1346. "unsupported audio format\n");
  1347. return -EINVAL;
  1348. }
  1349. dev_dbg(component->dev, "dai_id = %d, dai_mode = %u, dai_format = %u\n",
  1350. codec_dai->id,
  1351. cs43130->dais[codec_dai->id].dai_mode,
  1352. cs43130->dais[codec_dai->id].dai_format);
  1353. return 0;
  1354. }
  1355. static int cs43130_dsd_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  1356. {
  1357. struct snd_soc_component *component = codec_dai->component;
  1358. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  1359. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1360. case SND_SOC_DAIFMT_CBS_CFS:
  1361. cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS;
  1362. break;
  1363. case SND_SOC_DAIFMT_CBM_CFM:
  1364. cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM;
  1365. break;
  1366. default:
  1367. dev_err(component->dev, "Unsupported DAI format.\n");
  1368. return -EINVAL;
  1369. }
  1370. dev_dbg(component->dev, "dai_mode = 0x%x\n",
  1371. cs43130->dais[codec_dai->id].dai_mode);
  1372. return 0;
  1373. }
  1374. static int cs43130_set_sysclk(struct snd_soc_dai *codec_dai,
  1375. int clk_id, unsigned int freq, int dir)
  1376. {
  1377. struct snd_soc_component *component = codec_dai->component;
  1378. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  1379. cs43130->dais[codec_dai->id].sclk = freq;
  1380. dev_dbg(component->dev, "dai_id = %d, sclk = %u\n", codec_dai->id,
  1381. cs43130->dais[codec_dai->id].sclk);
  1382. return 0;
  1383. }
  1384. static const struct snd_soc_dai_ops cs43130_pcm_ops = {
  1385. .startup = cs43130_pcm_startup,
  1386. .hw_params = cs43130_hw_params,
  1387. .hw_free = cs43130_hw_free,
  1388. .set_sysclk = cs43130_set_sysclk,
  1389. .set_fmt = cs43130_pcm_set_fmt,
  1390. };
  1391. static const struct snd_soc_dai_ops cs43130_dop_ops = {
  1392. .startup = cs43130_dop_startup,
  1393. .hw_params = cs43130_hw_params,
  1394. .hw_free = cs43130_hw_free,
  1395. .set_sysclk = cs43130_set_sysclk,
  1396. .set_fmt = cs43130_pcm_set_fmt,
  1397. };
  1398. static const struct snd_soc_dai_ops cs43130_dsd_ops = {
  1399. .startup = cs43130_dop_startup,
  1400. .hw_params = cs43130_dsd_hw_params,
  1401. .hw_free = cs43130_hw_free,
  1402. .set_fmt = cs43130_dsd_set_fmt,
  1403. };
  1404. static struct snd_soc_dai_driver cs43130_dai[] = {
  1405. {
  1406. .name = "cs43130-asp-pcm",
  1407. .id = CS43130_ASP_PCM_DAI,
  1408. .playback = {
  1409. .stream_name = "ASP PCM Playback",
  1410. .channels_min = 1,
  1411. .channels_max = 2,
  1412. .rates = SNDRV_PCM_RATE_KNOT,
  1413. .formats = CS43130_PCM_FORMATS,
  1414. },
  1415. .ops = &cs43130_pcm_ops,
  1416. .symmetric_rates = 1,
  1417. },
  1418. {
  1419. .name = "cs43130-asp-dop",
  1420. .id = CS43130_ASP_DOP_DAI,
  1421. .playback = {
  1422. .stream_name = "ASP DoP Playback",
  1423. .channels_min = 1,
  1424. .channels_max = 2,
  1425. .rates = SNDRV_PCM_RATE_KNOT,
  1426. .formats = CS43130_DOP_FORMATS,
  1427. },
  1428. .ops = &cs43130_dop_ops,
  1429. .symmetric_rates = 1,
  1430. },
  1431. {
  1432. .name = "cs43130-xsp-dop",
  1433. .id = CS43130_XSP_DOP_DAI,
  1434. .playback = {
  1435. .stream_name = "XSP DoP Playback",
  1436. .channels_min = 1,
  1437. .channels_max = 2,
  1438. .rates = SNDRV_PCM_RATE_KNOT,
  1439. .formats = CS43130_DOP_FORMATS,
  1440. },
  1441. .ops = &cs43130_dop_ops,
  1442. .symmetric_rates = 1,
  1443. },
  1444. {
  1445. .name = "cs43130-xsp-dsd",
  1446. .id = CS43130_XSP_DSD_DAI,
  1447. .playback = {
  1448. .stream_name = "XSP DSD Playback",
  1449. .channels_min = 1,
  1450. .channels_max = 2,
  1451. .rates = SNDRV_PCM_RATE_KNOT,
  1452. .formats = CS43130_DOP_FORMATS,
  1453. },
  1454. .ops = &cs43130_dsd_ops,
  1455. },
  1456. };
  1457. static int cs43130_component_set_sysclk(struct snd_soc_component *component,
  1458. int clk_id, int source, unsigned int freq,
  1459. int dir)
  1460. {
  1461. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  1462. dev_dbg(component->dev, "clk_id = %d, source = %d, freq = %d, dir = %d\n",
  1463. clk_id, source, freq, dir);
  1464. switch (freq) {
  1465. case CS43130_MCLK_22M:
  1466. case CS43130_MCLK_24M:
  1467. cs43130->mclk = freq;
  1468. break;
  1469. default:
  1470. dev_err(component->dev, "Invalid MCLK INT freq: %u\n", freq);
  1471. return -EINVAL;
  1472. }
  1473. if (source == CS43130_MCLK_SRC_EXT) {
  1474. cs43130->pll_bypass = true;
  1475. } else {
  1476. dev_err(component->dev, "Invalid MCLK source\n");
  1477. return -EINVAL;
  1478. }
  1479. return 0;
  1480. }
  1481. static inline u16 cs43130_get_ac_reg_val(u16 ac_freq)
  1482. {
  1483. /* AC freq is counted in 5.94Hz step. */
  1484. return ac_freq / 6;
  1485. }
  1486. static int cs43130_show_dc(struct device *dev, char *buf, u8 ch)
  1487. {
  1488. struct i2c_client *client = to_i2c_client(dev);
  1489. struct cs43130_private *cs43130 = i2c_get_clientdata(client);
  1490. if (!cs43130->hpload_done)
  1491. return scnprintf(buf, PAGE_SIZE, "NO_HPLOAD\n");
  1492. else
  1493. return scnprintf(buf, PAGE_SIZE, "%u\n",
  1494. cs43130->hpload_dc[ch]);
  1495. }
  1496. static ssize_t cs43130_show_dc_l(struct device *dev,
  1497. struct device_attribute *attr, char *buf)
  1498. {
  1499. return cs43130_show_dc(dev, buf, HP_LEFT);
  1500. }
  1501. static ssize_t cs43130_show_dc_r(struct device *dev,
  1502. struct device_attribute *attr, char *buf)
  1503. {
  1504. return cs43130_show_dc(dev, buf, HP_RIGHT);
  1505. }
  1506. static u16 const cs43130_ac_freq[CS43130_AC_FREQ] = {
  1507. 24,
  1508. 43,
  1509. 93,
  1510. 200,
  1511. 431,
  1512. 928,
  1513. 2000,
  1514. 4309,
  1515. 9283,
  1516. 20000,
  1517. };
  1518. static int cs43130_show_ac(struct device *dev, char *buf, u8 ch)
  1519. {
  1520. int i, j = 0, tmp;
  1521. struct i2c_client *client = to_i2c_client(dev);
  1522. struct cs43130_private *cs43130 = i2c_get_clientdata(client);
  1523. if (cs43130->hpload_done && cs43130->ac_meas) {
  1524. for (i = 0; i < ARRAY_SIZE(cs43130_ac_freq); i++) {
  1525. tmp = scnprintf(buf + j, PAGE_SIZE - j, "%u\n",
  1526. cs43130->hpload_ac[i][ch]);
  1527. if (!tmp)
  1528. break;
  1529. j += tmp;
  1530. }
  1531. return j;
  1532. } else {
  1533. return scnprintf(buf, PAGE_SIZE, "NO_HPLOAD\n");
  1534. }
  1535. }
  1536. static ssize_t cs43130_show_ac_l(struct device *dev,
  1537. struct device_attribute *attr, char *buf)
  1538. {
  1539. return cs43130_show_ac(dev, buf, HP_LEFT);
  1540. }
  1541. static ssize_t cs43130_show_ac_r(struct device *dev,
  1542. struct device_attribute *attr, char *buf)
  1543. {
  1544. return cs43130_show_ac(dev, buf, HP_RIGHT);
  1545. }
  1546. static DEVICE_ATTR(hpload_dc_l, 0444, cs43130_show_dc_l, NULL);
  1547. static DEVICE_ATTR(hpload_dc_r, 0444, cs43130_show_dc_r, NULL);
  1548. static DEVICE_ATTR(hpload_ac_l, 0444, cs43130_show_ac_l, NULL);
  1549. static DEVICE_ATTR(hpload_ac_r, 0444, cs43130_show_ac_r, NULL);
  1550. static struct attribute *hpload_attrs[] = {
  1551. &dev_attr_hpload_dc_l.attr,
  1552. &dev_attr_hpload_dc_r.attr,
  1553. &dev_attr_hpload_ac_l.attr,
  1554. &dev_attr_hpload_ac_r.attr,
  1555. };
  1556. ATTRIBUTE_GROUPS(hpload);
  1557. static struct reg_sequence hp_en_cal_seq[] = {
  1558. {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL},
  1559. {CS43130_HP_MEAS_LOAD_1, 0},
  1560. {CS43130_HP_MEAS_LOAD_2, 0},
  1561. {CS43130_INT_MASK_4, 0},
  1562. {CS43130_DXD1, 0x99},
  1563. {CS43130_DXD16, 0xBB},
  1564. {CS43130_DXD12, 0x01},
  1565. {CS43130_DXD19, 0xCB},
  1566. {CS43130_DXD17, 0x95},
  1567. {CS43130_DXD18, 0x0B},
  1568. {CS43130_DXD1, 0},
  1569. {CS43130_HP_LOAD_1, 0x80},
  1570. };
  1571. static struct reg_sequence hp_en_cal_seq2[] = {
  1572. {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL},
  1573. {CS43130_HP_MEAS_LOAD_1, 0},
  1574. {CS43130_HP_MEAS_LOAD_2, 0},
  1575. {CS43130_INT_MASK_4, 0},
  1576. {CS43130_HP_LOAD_1, 0x80},
  1577. };
  1578. static struct reg_sequence hp_dis_cal_seq[] = {
  1579. {CS43130_HP_LOAD_1, 0x80},
  1580. {CS43130_DXD1, 0x99},
  1581. {CS43130_DXD12, 0},
  1582. {CS43130_DXD1, 0},
  1583. {CS43130_HP_LOAD_1, 0},
  1584. };
  1585. static struct reg_sequence hp_dis_cal_seq2[] = {
  1586. {CS43130_HP_LOAD_1, 0x80},
  1587. {CS43130_HP_LOAD_1, 0},
  1588. };
  1589. static struct reg_sequence hp_dc_ch_l_seq[] = {
  1590. {CS43130_DXD1, 0x99},
  1591. {CS43130_DXD19, 0x0A},
  1592. {CS43130_DXD17, 0x93},
  1593. {CS43130_DXD18, 0x0A},
  1594. {CS43130_DXD1, 0},
  1595. {CS43130_HP_LOAD_1, 0x80},
  1596. {CS43130_HP_LOAD_1, 0x81},
  1597. };
  1598. static struct reg_sequence hp_dc_ch_l_seq2[] = {
  1599. {CS43130_HP_LOAD_1, 0x80},
  1600. {CS43130_HP_LOAD_1, 0x81},
  1601. };
  1602. static struct reg_sequence hp_dc_ch_r_seq[] = {
  1603. {CS43130_DXD1, 0x99},
  1604. {CS43130_DXD19, 0x8A},
  1605. {CS43130_DXD17, 0x15},
  1606. {CS43130_DXD18, 0x06},
  1607. {CS43130_DXD1, 0},
  1608. {CS43130_HP_LOAD_1, 0x90},
  1609. {CS43130_HP_LOAD_1, 0x91},
  1610. };
  1611. static struct reg_sequence hp_dc_ch_r_seq2[] = {
  1612. {CS43130_HP_LOAD_1, 0x90},
  1613. {CS43130_HP_LOAD_1, 0x91},
  1614. };
  1615. static struct reg_sequence hp_ac_ch_l_seq[] = {
  1616. {CS43130_DXD1, 0x99},
  1617. {CS43130_DXD19, 0x0A},
  1618. {CS43130_DXD17, 0x93},
  1619. {CS43130_DXD18, 0x0A},
  1620. {CS43130_DXD1, 0},
  1621. {CS43130_HP_LOAD_1, 0x80},
  1622. {CS43130_HP_LOAD_1, 0x82},
  1623. };
  1624. static struct reg_sequence hp_ac_ch_l_seq2[] = {
  1625. {CS43130_HP_LOAD_1, 0x80},
  1626. {CS43130_HP_LOAD_1, 0x82},
  1627. };
  1628. static struct reg_sequence hp_ac_ch_r_seq[] = {
  1629. {CS43130_DXD1, 0x99},
  1630. {CS43130_DXD19, 0x8A},
  1631. {CS43130_DXD17, 0x15},
  1632. {CS43130_DXD18, 0x06},
  1633. {CS43130_DXD1, 0},
  1634. {CS43130_HP_LOAD_1, 0x90},
  1635. {CS43130_HP_LOAD_1, 0x92},
  1636. };
  1637. static struct reg_sequence hp_ac_ch_r_seq2[] = {
  1638. {CS43130_HP_LOAD_1, 0x90},
  1639. {CS43130_HP_LOAD_1, 0x92},
  1640. };
  1641. static struct reg_sequence hp_cln_seq[] = {
  1642. {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL},
  1643. {CS43130_HP_MEAS_LOAD_1, 0},
  1644. {CS43130_HP_MEAS_LOAD_2, 0},
  1645. };
  1646. struct reg_sequences {
  1647. struct reg_sequence *seq;
  1648. int size;
  1649. unsigned int msk;
  1650. };
  1651. static struct reg_sequences hpload_seq1[] = {
  1652. {
  1653. .seq = hp_en_cal_seq,
  1654. .size = ARRAY_SIZE(hp_en_cal_seq),
  1655. .msk = CS43130_HPLOAD_ON_INT,
  1656. },
  1657. {
  1658. .seq = hp_dc_ch_l_seq,
  1659. .size = ARRAY_SIZE(hp_dc_ch_l_seq),
  1660. .msk = CS43130_HPLOAD_DC_INT,
  1661. },
  1662. {
  1663. .seq = hp_ac_ch_l_seq,
  1664. .size = ARRAY_SIZE(hp_ac_ch_l_seq),
  1665. .msk = CS43130_HPLOAD_AC_INT,
  1666. },
  1667. {
  1668. .seq = hp_dis_cal_seq,
  1669. .size = ARRAY_SIZE(hp_dis_cal_seq),
  1670. .msk = CS43130_HPLOAD_OFF_INT,
  1671. },
  1672. {
  1673. .seq = hp_en_cal_seq,
  1674. .size = ARRAY_SIZE(hp_en_cal_seq),
  1675. .msk = CS43130_HPLOAD_ON_INT,
  1676. },
  1677. {
  1678. .seq = hp_dc_ch_r_seq,
  1679. .size = ARRAY_SIZE(hp_dc_ch_r_seq),
  1680. .msk = CS43130_HPLOAD_DC_INT,
  1681. },
  1682. {
  1683. .seq = hp_ac_ch_r_seq,
  1684. .size = ARRAY_SIZE(hp_ac_ch_r_seq),
  1685. .msk = CS43130_HPLOAD_AC_INT,
  1686. },
  1687. };
  1688. static struct reg_sequences hpload_seq2[] = {
  1689. {
  1690. .seq = hp_en_cal_seq2,
  1691. .size = ARRAY_SIZE(hp_en_cal_seq2),
  1692. .msk = CS43130_HPLOAD_ON_INT,
  1693. },
  1694. {
  1695. .seq = hp_dc_ch_l_seq2,
  1696. .size = ARRAY_SIZE(hp_dc_ch_l_seq2),
  1697. .msk = CS43130_HPLOAD_DC_INT,
  1698. },
  1699. {
  1700. .seq = hp_ac_ch_l_seq2,
  1701. .size = ARRAY_SIZE(hp_ac_ch_l_seq2),
  1702. .msk = CS43130_HPLOAD_AC_INT,
  1703. },
  1704. {
  1705. .seq = hp_dis_cal_seq2,
  1706. .size = ARRAY_SIZE(hp_dis_cal_seq2),
  1707. .msk = CS43130_HPLOAD_OFF_INT,
  1708. },
  1709. {
  1710. .seq = hp_en_cal_seq2,
  1711. .size = ARRAY_SIZE(hp_en_cal_seq2),
  1712. .msk = CS43130_HPLOAD_ON_INT,
  1713. },
  1714. {
  1715. .seq = hp_dc_ch_r_seq2,
  1716. .size = ARRAY_SIZE(hp_dc_ch_r_seq2),
  1717. .msk = CS43130_HPLOAD_DC_INT,
  1718. },
  1719. {
  1720. .seq = hp_ac_ch_r_seq2,
  1721. .size = ARRAY_SIZE(hp_ac_ch_r_seq2),
  1722. .msk = CS43130_HPLOAD_AC_INT,
  1723. },
  1724. };
  1725. static int cs43130_update_hpload(unsigned int msk, int ac_idx,
  1726. struct cs43130_private *cs43130)
  1727. {
  1728. bool left_ch = true;
  1729. unsigned int reg;
  1730. u32 addr;
  1731. u16 impedance;
  1732. struct snd_soc_component *component = cs43130->component;
  1733. switch (msk) {
  1734. case CS43130_HPLOAD_DC_INT:
  1735. case CS43130_HPLOAD_AC_INT:
  1736. break;
  1737. default:
  1738. return 0;
  1739. }
  1740. regmap_read(cs43130->regmap, CS43130_HP_LOAD_1, &reg);
  1741. if (reg & CS43130_HPLOAD_CHN_SEL)
  1742. left_ch = false;
  1743. if (msk == CS43130_HPLOAD_DC_INT)
  1744. addr = CS43130_HP_DC_STAT_1;
  1745. else
  1746. addr = CS43130_HP_AC_STAT_1;
  1747. regmap_read(cs43130->regmap, addr, &reg);
  1748. impedance = reg >> 3;
  1749. regmap_read(cs43130->regmap, addr + 1, &reg);
  1750. impedance |= reg << 5;
  1751. if (msk == CS43130_HPLOAD_DC_INT) {
  1752. if (left_ch)
  1753. cs43130->hpload_dc[HP_LEFT] = impedance;
  1754. else
  1755. cs43130->hpload_dc[HP_RIGHT] = impedance;
  1756. dev_dbg(component->dev, "HP DC impedance (Ch %u): %u\n", !left_ch,
  1757. impedance);
  1758. } else {
  1759. if (left_ch)
  1760. cs43130->hpload_ac[ac_idx][HP_LEFT] = impedance;
  1761. else
  1762. cs43130->hpload_ac[ac_idx][HP_RIGHT] = impedance;
  1763. dev_dbg(component->dev, "HP AC (%u Hz) impedance (Ch %u): %u\n",
  1764. cs43130->ac_freq[ac_idx], !left_ch, impedance);
  1765. }
  1766. return 0;
  1767. }
  1768. static int cs43130_hpload_proc(struct cs43130_private *cs43130,
  1769. struct reg_sequence *seq, int seq_size,
  1770. unsigned int rslt_msk, int ac_idx)
  1771. {
  1772. int ret;
  1773. unsigned int msk;
  1774. u16 ac_reg_val;
  1775. struct snd_soc_component *component = cs43130->component;
  1776. reinit_completion(&cs43130->hpload_evt);
  1777. if (rslt_msk == CS43130_HPLOAD_AC_INT) {
  1778. ac_reg_val = cs43130_get_ac_reg_val(cs43130->ac_freq[ac_idx]);
  1779. regmap_update_bits(cs43130->regmap, CS43130_HP_LOAD_1,
  1780. CS43130_HPLOAD_AC_START, 0);
  1781. regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_1,
  1782. CS43130_HP_MEAS_LOAD_MASK,
  1783. ac_reg_val >> CS43130_HP_MEAS_LOAD_1_SHIFT);
  1784. regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_2,
  1785. CS43130_HP_MEAS_LOAD_MASK,
  1786. ac_reg_val >> CS43130_HP_MEAS_LOAD_2_SHIFT);
  1787. }
  1788. regmap_multi_reg_write(cs43130->regmap, seq,
  1789. seq_size);
  1790. ret = wait_for_completion_timeout(&cs43130->hpload_evt,
  1791. msecs_to_jiffies(1000));
  1792. regmap_read(cs43130->regmap, CS43130_INT_MASK_4, &msk);
  1793. if (!ret) {
  1794. dev_err(component->dev, "Timeout waiting for HPLOAD interrupt\n");
  1795. return -1;
  1796. }
  1797. dev_dbg(component->dev, "HP load stat: %x, INT_MASK_4: %x\n",
  1798. cs43130->hpload_stat, msk);
  1799. if ((cs43130->hpload_stat & (CS43130_HPLOAD_NO_DC_INT |
  1800. CS43130_HPLOAD_UNPLUG_INT |
  1801. CS43130_HPLOAD_OOR_INT)) ||
  1802. !(cs43130->hpload_stat & rslt_msk)) {
  1803. dev_dbg(component->dev, "HP load measure failed\n");
  1804. return -1;
  1805. }
  1806. return 0;
  1807. }
  1808. static const struct reg_sequence hv_seq[][2] = {
  1809. {
  1810. {CS43130_CLASS_H_CTL, 0x1C},
  1811. {CS43130_HP_OUT_CTL_1, 0x10},
  1812. },
  1813. {
  1814. {CS43130_CLASS_H_CTL, 0x1E},
  1815. {CS43130_HP_OUT_CTL_1, 0x20},
  1816. },
  1817. {
  1818. {CS43130_CLASS_H_CTL, 0x1E},
  1819. {CS43130_HP_OUT_CTL_1, 0x30},
  1820. },
  1821. };
  1822. static int cs43130_set_hv(struct regmap *regmap, u16 hpload_dc,
  1823. const u16 *dc_threshold)
  1824. {
  1825. int i;
  1826. for (i = 0; i < CS43130_DC_THRESHOLD; i++) {
  1827. if (hpload_dc <= dc_threshold[i])
  1828. break;
  1829. }
  1830. regmap_multi_reg_write(regmap, hv_seq[i], ARRAY_SIZE(hv_seq[i]));
  1831. return 0;
  1832. }
  1833. static void cs43130_imp_meas(struct work_struct *wk)
  1834. {
  1835. unsigned int reg, seq_size;
  1836. int i, ret, ac_idx;
  1837. struct cs43130_private *cs43130;
  1838. struct snd_soc_component *component;
  1839. struct reg_sequences *hpload_seq;
  1840. cs43130 = container_of(wk, struct cs43130_private, work);
  1841. component = cs43130->component;
  1842. if (!cs43130->mclk)
  1843. return;
  1844. cs43130->hpload_done = false;
  1845. mutex_lock(&cs43130->clk_mutex);
  1846. if (!cs43130->clk_req) {
  1847. /* clk not in use */
  1848. cs43130_set_pll(component, 0, 0, cs43130->mclk, CS43130_MCLK_22M);
  1849. if (cs43130->pll_bypass)
  1850. cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);
  1851. else
  1852. cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);
  1853. }
  1854. cs43130->clk_req++;
  1855. mutex_unlock(&cs43130->clk_mutex);
  1856. regmap_read(cs43130->regmap, CS43130_INT_STATUS_4, &reg);
  1857. switch (cs43130->dev_id) {
  1858. case CS43130_CHIP_ID:
  1859. hpload_seq = hpload_seq1;
  1860. seq_size = ARRAY_SIZE(hpload_seq1);
  1861. break;
  1862. case CS43131_CHIP_ID:
  1863. hpload_seq = hpload_seq2;
  1864. seq_size = ARRAY_SIZE(hpload_seq2);
  1865. break;
  1866. default:
  1867. WARN(1, "Invalid dev_id for meas: %d", cs43130->dev_id);
  1868. return;
  1869. }
  1870. i = 0;
  1871. ac_idx = 0;
  1872. while (i < seq_size) {
  1873. ret = cs43130_hpload_proc(cs43130, hpload_seq[i].seq,
  1874. hpload_seq[i].size,
  1875. hpload_seq[i].msk, ac_idx);
  1876. if (ret < 0)
  1877. goto exit;
  1878. cs43130_update_hpload(hpload_seq[i].msk, ac_idx, cs43130);
  1879. if (cs43130->ac_meas &&
  1880. hpload_seq[i].msk == CS43130_HPLOAD_AC_INT &&
  1881. ac_idx < CS43130_AC_FREQ - 1) {
  1882. ac_idx++;
  1883. } else {
  1884. ac_idx = 0;
  1885. i++;
  1886. }
  1887. }
  1888. cs43130->hpload_done = true;
  1889. if (cs43130->hpload_dc[HP_LEFT] >= CS43130_LINEOUT_LOAD)
  1890. snd_soc_jack_report(&cs43130->jack, CS43130_JACK_LINEOUT,
  1891. CS43130_JACK_MASK);
  1892. else
  1893. snd_soc_jack_report(&cs43130->jack, CS43130_JACK_HEADPHONE,
  1894. CS43130_JACK_MASK);
  1895. dev_dbg(component->dev, "Set HP output control. DC threshold\n");
  1896. for (i = 0; i < CS43130_DC_THRESHOLD; i++)
  1897. dev_dbg(component->dev, "DC threshold[%d]: %u.\n", i,
  1898. cs43130->dc_threshold[i]);
  1899. cs43130_set_hv(cs43130->regmap, cs43130->hpload_dc[HP_LEFT],
  1900. cs43130->dc_threshold);
  1901. exit:
  1902. switch (cs43130->dev_id) {
  1903. case CS43130_CHIP_ID:
  1904. cs43130_hpload_proc(cs43130, hp_dis_cal_seq,
  1905. ARRAY_SIZE(hp_dis_cal_seq),
  1906. CS43130_HPLOAD_OFF_INT, ac_idx);
  1907. break;
  1908. case CS43131_CHIP_ID:
  1909. cs43130_hpload_proc(cs43130, hp_dis_cal_seq2,
  1910. ARRAY_SIZE(hp_dis_cal_seq2),
  1911. CS43130_HPLOAD_OFF_INT, ac_idx);
  1912. break;
  1913. }
  1914. regmap_multi_reg_write(cs43130->regmap, hp_cln_seq,
  1915. ARRAY_SIZE(hp_cln_seq));
  1916. mutex_lock(&cs43130->clk_mutex);
  1917. cs43130->clk_req--;
  1918. /* clk not in use */
  1919. if (!cs43130->clk_req)
  1920. cs43130_change_clksrc(component, CS43130_MCLK_SRC_RCO);
  1921. mutex_unlock(&cs43130->clk_mutex);
  1922. }
  1923. static irqreturn_t cs43130_irq_thread(int irq, void *data)
  1924. {
  1925. struct cs43130_private *cs43130 = (struct cs43130_private *)data;
  1926. struct snd_soc_component *component = cs43130->component;
  1927. unsigned int stickies[CS43130_NUM_INT];
  1928. unsigned int irq_occurrence = 0;
  1929. unsigned int masks[CS43130_NUM_INT];
  1930. int i, j;
  1931. for (i = 0; i < ARRAY_SIZE(stickies); i++) {
  1932. regmap_read(cs43130->regmap, CS43130_INT_STATUS_1 + i,
  1933. &stickies[i]);
  1934. regmap_read(cs43130->regmap, CS43130_INT_MASK_1 + i,
  1935. &masks[i]);
  1936. }
  1937. for (i = 0; i < ARRAY_SIZE(stickies); i++) {
  1938. stickies[i] = stickies[i] & (~masks[i]);
  1939. for (j = 0; j < 8; j++)
  1940. irq_occurrence += (stickies[i] >> j) & 1;
  1941. }
  1942. dev_dbg(component->dev, "number of interrupts occurred (%u)\n",
  1943. irq_occurrence);
  1944. if (!irq_occurrence)
  1945. return IRQ_NONE;
  1946. if (stickies[0] & CS43130_XTAL_RDY_INT) {
  1947. complete(&cs43130->xtal_rdy);
  1948. return IRQ_HANDLED;
  1949. }
  1950. if (stickies[0] & CS43130_PLL_RDY_INT) {
  1951. complete(&cs43130->pll_rdy);
  1952. return IRQ_HANDLED;
  1953. }
  1954. if (stickies[3] & CS43130_HPLOAD_NO_DC_INT) {
  1955. cs43130->hpload_stat = stickies[3];
  1956. dev_err(component->dev,
  1957. "DC load has not completed before AC load (%x)\n",
  1958. cs43130->hpload_stat);
  1959. complete(&cs43130->hpload_evt);
  1960. return IRQ_HANDLED;
  1961. }
  1962. if (stickies[3] & CS43130_HPLOAD_UNPLUG_INT) {
  1963. cs43130->hpload_stat = stickies[3];
  1964. dev_err(component->dev, "HP unplugged during measurement (%x)\n",
  1965. cs43130->hpload_stat);
  1966. complete(&cs43130->hpload_evt);
  1967. return IRQ_HANDLED;
  1968. }
  1969. if (stickies[3] & CS43130_HPLOAD_OOR_INT) {
  1970. cs43130->hpload_stat = stickies[3];
  1971. dev_err(component->dev, "HP load out of range (%x)\n",
  1972. cs43130->hpload_stat);
  1973. complete(&cs43130->hpload_evt);
  1974. return IRQ_HANDLED;
  1975. }
  1976. if (stickies[3] & CS43130_HPLOAD_AC_INT) {
  1977. cs43130->hpload_stat = stickies[3];
  1978. dev_dbg(component->dev, "HP AC load measurement done (%x)\n",
  1979. cs43130->hpload_stat);
  1980. complete(&cs43130->hpload_evt);
  1981. return IRQ_HANDLED;
  1982. }
  1983. if (stickies[3] & CS43130_HPLOAD_DC_INT) {
  1984. cs43130->hpload_stat = stickies[3];
  1985. dev_dbg(component->dev, "HP DC load measurement done (%x)\n",
  1986. cs43130->hpload_stat);
  1987. complete(&cs43130->hpload_evt);
  1988. return IRQ_HANDLED;
  1989. }
  1990. if (stickies[3] & CS43130_HPLOAD_ON_INT) {
  1991. cs43130->hpload_stat = stickies[3];
  1992. dev_dbg(component->dev, "HP load state machine on done (%x)\n",
  1993. cs43130->hpload_stat);
  1994. complete(&cs43130->hpload_evt);
  1995. return IRQ_HANDLED;
  1996. }
  1997. if (stickies[3] & CS43130_HPLOAD_OFF_INT) {
  1998. cs43130->hpload_stat = stickies[3];
  1999. dev_dbg(component->dev, "HP load state machine off done (%x)\n",
  2000. cs43130->hpload_stat);
  2001. complete(&cs43130->hpload_evt);
  2002. return IRQ_HANDLED;
  2003. }
  2004. if (stickies[0] & CS43130_XTAL_ERR_INT) {
  2005. dev_err(component->dev, "Crystal err: clock is not running\n");
  2006. return IRQ_HANDLED;
  2007. }
  2008. if (stickies[0] & CS43130_HP_UNPLUG_INT) {
  2009. dev_dbg(component->dev, "HP unplugged\n");
  2010. cs43130->hpload_done = false;
  2011. snd_soc_jack_report(&cs43130->jack, 0, CS43130_JACK_MASK);
  2012. return IRQ_HANDLED;
  2013. }
  2014. if (stickies[0] & CS43130_HP_PLUG_INT) {
  2015. if (cs43130->dc_meas && !cs43130->hpload_done &&
  2016. !work_busy(&cs43130->work)) {
  2017. dev_dbg(component->dev, "HP load queue work\n");
  2018. queue_work(cs43130->wq, &cs43130->work);
  2019. }
  2020. snd_soc_jack_report(&cs43130->jack, SND_JACK_MECHANICAL,
  2021. CS43130_JACK_MASK);
  2022. return IRQ_HANDLED;
  2023. }
  2024. return IRQ_NONE;
  2025. }
  2026. static int cs43130_probe(struct snd_soc_component *component)
  2027. {
  2028. int ret;
  2029. struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
  2030. struct snd_soc_card *card = component->card;
  2031. unsigned int reg;
  2032. cs43130->component = component;
  2033. if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) {
  2034. regmap_update_bits(cs43130->regmap, CS43130_CRYSTAL_SET,
  2035. CS43130_XTAL_IBIAS_MASK,
  2036. cs43130->xtal_ibias);
  2037. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  2038. CS43130_XTAL_ERR_INT, 0);
  2039. }
  2040. ret = snd_soc_card_jack_new(card, "Headphone", CS43130_JACK_MASK,
  2041. &cs43130->jack, NULL, 0);
  2042. if (ret < 0) {
  2043. dev_err(component->dev, "Cannot create jack\n");
  2044. return ret;
  2045. }
  2046. cs43130->hpload_done = false;
  2047. if (cs43130->dc_meas) {
  2048. ret = sysfs_create_groups(&component->dev->kobj, hpload_groups);
  2049. if (ret)
  2050. return ret;
  2051. cs43130->wq = create_singlethread_workqueue("cs43130_hp");
  2052. if (!cs43130->wq) {
  2053. sysfs_remove_groups(&component->dev->kobj, hpload_groups);
  2054. return -ENOMEM;
  2055. }
  2056. INIT_WORK(&cs43130->work, cs43130_imp_meas);
  2057. }
  2058. regmap_read(cs43130->regmap, CS43130_INT_STATUS_1, &reg);
  2059. regmap_read(cs43130->regmap, CS43130_HP_STATUS, &reg);
  2060. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  2061. CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT, 0);
  2062. regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
  2063. CS43130_HP_DETECT_CTRL_MASK, 0);
  2064. regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
  2065. CS43130_HP_DETECT_CTRL_MASK,
  2066. CS43130_HP_DETECT_CTRL_MASK);
  2067. return 0;
  2068. }
  2069. static struct snd_soc_component_driver soc_component_dev_cs43130 = {
  2070. .probe = cs43130_probe,
  2071. .controls = cs43130_snd_controls,
  2072. .num_controls = ARRAY_SIZE(cs43130_snd_controls),
  2073. .set_sysclk = cs43130_component_set_sysclk,
  2074. .set_pll = cs43130_set_pll,
  2075. .idle_bias_on = 1,
  2076. .use_pmdown_time = 1,
  2077. .endianness = 1,
  2078. .non_legacy_dai_naming = 1,
  2079. };
  2080. static const struct regmap_config cs43130_regmap = {
  2081. .reg_bits = 24,
  2082. .pad_bits = 8,
  2083. .val_bits = 8,
  2084. .max_register = CS43130_LASTREG,
  2085. .reg_defaults = cs43130_reg_defaults,
  2086. .num_reg_defaults = ARRAY_SIZE(cs43130_reg_defaults),
  2087. .readable_reg = cs43130_readable_register,
  2088. .precious_reg = cs43130_precious_register,
  2089. .volatile_reg = cs43130_volatile_register,
  2090. .cache_type = REGCACHE_RBTREE,
  2091. /* needed for regcache_sync */
  2092. .use_single_read = true,
  2093. .use_single_write = true,
  2094. };
  2095. static u16 const cs43130_dc_threshold[CS43130_DC_THRESHOLD] = {
  2096. 50,
  2097. 120,
  2098. };
  2099. static int cs43130_handle_device_data(struct i2c_client *i2c_client,
  2100. struct cs43130_private *cs43130)
  2101. {
  2102. struct device_node *np = i2c_client->dev.of_node;
  2103. unsigned int val;
  2104. int i;
  2105. if (of_property_read_u32(np, "cirrus,xtal-ibias", &val) < 0) {
  2106. /* Crystal is unused. System clock is used for external MCLK */
  2107. cs43130->xtal_ibias = CS43130_XTAL_UNUSED;
  2108. return 0;
  2109. }
  2110. switch (val) {
  2111. case 1:
  2112. cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA;
  2113. break;
  2114. case 2:
  2115. cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA;
  2116. break;
  2117. case 3:
  2118. cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA;
  2119. break;
  2120. default:
  2121. dev_err(&i2c_client->dev,
  2122. "Invalid cirrus,xtal-ibias value: %d\n", val);
  2123. return -EINVAL;
  2124. }
  2125. cs43130->dc_meas = of_property_read_bool(np, "cirrus,dc-measure");
  2126. cs43130->ac_meas = of_property_read_bool(np, "cirrus,ac-measure");
  2127. if (of_property_read_u16_array(np, "cirrus,ac-freq", cs43130->ac_freq,
  2128. CS43130_AC_FREQ) < 0) {
  2129. for (i = 0; i < CS43130_AC_FREQ; i++)
  2130. cs43130->ac_freq[i] = cs43130_ac_freq[i];
  2131. }
  2132. if (of_property_read_u16_array(np, "cirrus,dc-threshold",
  2133. cs43130->dc_threshold,
  2134. CS43130_DC_THRESHOLD) < 0) {
  2135. for (i = 0; i < CS43130_DC_THRESHOLD; i++)
  2136. cs43130->dc_threshold[i] = cs43130_dc_threshold[i];
  2137. }
  2138. return 0;
  2139. }
  2140. static int cs43130_i2c_probe(struct i2c_client *client,
  2141. const struct i2c_device_id *id)
  2142. {
  2143. struct cs43130_private *cs43130;
  2144. int ret;
  2145. unsigned int devid = 0;
  2146. unsigned int reg;
  2147. int i;
  2148. cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL);
  2149. if (!cs43130)
  2150. return -ENOMEM;
  2151. i2c_set_clientdata(client, cs43130);
  2152. cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap);
  2153. if (IS_ERR(cs43130->regmap)) {
  2154. ret = PTR_ERR(cs43130->regmap);
  2155. return ret;
  2156. }
  2157. if (client->dev.of_node) {
  2158. ret = cs43130_handle_device_data(client, cs43130);
  2159. if (ret != 0)
  2160. return ret;
  2161. }
  2162. for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++)
  2163. cs43130->supplies[i].supply = cs43130_supply_names[i];
  2164. ret = devm_regulator_bulk_get(&client->dev,
  2165. ARRAY_SIZE(cs43130->supplies),
  2166. cs43130->supplies);
  2167. if (ret != 0) {
  2168. dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
  2169. return ret;
  2170. }
  2171. ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies),
  2172. cs43130->supplies);
  2173. if (ret != 0) {
  2174. dev_err(&client->dev, "Failed to enable supplies: %d\n", ret);
  2175. return ret;
  2176. }
  2177. cs43130->reset_gpio = devm_gpiod_get_optional(&client->dev,
  2178. "reset", GPIOD_OUT_LOW);
  2179. if (IS_ERR(cs43130->reset_gpio))
  2180. return PTR_ERR(cs43130->reset_gpio);
  2181. gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
  2182. usleep_range(2000, 2050);
  2183. ret = regmap_read(cs43130->regmap, CS43130_DEVID_AB, &reg);
  2184. devid = (reg & 0xFF) << 12;
  2185. ret = regmap_read(cs43130->regmap, CS43130_DEVID_CD, &reg);
  2186. devid |= (reg & 0xFF) << 4;
  2187. ret = regmap_read(cs43130->regmap, CS43130_DEVID_E, &reg);
  2188. devid |= (reg & 0xF0) >> 4;
  2189. switch (devid) {
  2190. case CS43130_CHIP_ID:
  2191. case CS4399_CHIP_ID:
  2192. case CS43131_CHIP_ID:
  2193. case CS43198_CHIP_ID:
  2194. break;
  2195. default:
  2196. dev_err(&client->dev,
  2197. "CS43130 Device ID %X. Expected ID %X, %X, %X or %X\n",
  2198. devid, CS43130_CHIP_ID, CS4399_CHIP_ID,
  2199. CS43131_CHIP_ID, CS43198_CHIP_ID);
  2200. ret = -ENODEV;
  2201. goto err;
  2202. }
  2203. cs43130->dev_id = devid;
  2204. ret = regmap_read(cs43130->regmap, CS43130_REV_ID, &reg);
  2205. if (ret < 0) {
  2206. dev_err(&client->dev, "Get Revision ID failed\n");
  2207. goto err;
  2208. }
  2209. dev_info(&client->dev,
  2210. "Cirrus Logic CS43130 (%x), Revision: %02X\n", devid,
  2211. reg & 0xFF);
  2212. mutex_init(&cs43130->clk_mutex);
  2213. init_completion(&cs43130->xtal_rdy);
  2214. init_completion(&cs43130->pll_rdy);
  2215. init_completion(&cs43130->hpload_evt);
  2216. ret = devm_request_threaded_irq(&client->dev, client->irq,
  2217. NULL, cs43130_irq_thread,
  2218. IRQF_ONESHOT | IRQF_TRIGGER_LOW,
  2219. "cs43130", cs43130);
  2220. if (ret != 0) {
  2221. dev_err(&client->dev, "Failed to request IRQ: %d\n", ret);
  2222. return ret;
  2223. }
  2224. cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;
  2225. pm_runtime_set_autosuspend_delay(&client->dev, 100);
  2226. pm_runtime_use_autosuspend(&client->dev);
  2227. pm_runtime_set_active(&client->dev);
  2228. pm_runtime_enable(&client->dev);
  2229. switch (cs43130->dev_id) {
  2230. case CS43130_CHIP_ID:
  2231. case CS43131_CHIP_ID:
  2232. memcpy(all_hp_widgets, digital_hp_widgets,
  2233. sizeof(digital_hp_widgets));
  2234. memcpy(all_hp_widgets + ARRAY_SIZE(digital_hp_widgets),
  2235. analog_hp_widgets, sizeof(analog_hp_widgets));
  2236. memcpy(all_hp_routes, digital_hp_routes,
  2237. sizeof(digital_hp_routes));
  2238. memcpy(all_hp_routes + ARRAY_SIZE(digital_hp_routes),
  2239. analog_hp_routes, sizeof(analog_hp_routes));
  2240. soc_component_dev_cs43130.dapm_widgets =
  2241. all_hp_widgets;
  2242. soc_component_dev_cs43130.num_dapm_widgets =
  2243. ARRAY_SIZE(all_hp_widgets);
  2244. soc_component_dev_cs43130.dapm_routes =
  2245. all_hp_routes;
  2246. soc_component_dev_cs43130.num_dapm_routes =
  2247. ARRAY_SIZE(all_hp_routes);
  2248. break;
  2249. case CS43198_CHIP_ID:
  2250. case CS4399_CHIP_ID:
  2251. soc_component_dev_cs43130.dapm_widgets =
  2252. digital_hp_widgets;
  2253. soc_component_dev_cs43130.num_dapm_widgets =
  2254. ARRAY_SIZE(digital_hp_widgets);
  2255. soc_component_dev_cs43130.dapm_routes =
  2256. digital_hp_routes;
  2257. soc_component_dev_cs43130.num_dapm_routes =
  2258. ARRAY_SIZE(digital_hp_routes);
  2259. break;
  2260. }
  2261. ret = devm_snd_soc_register_component(&client->dev,
  2262. &soc_component_dev_cs43130,
  2263. cs43130_dai, ARRAY_SIZE(cs43130_dai));
  2264. if (ret < 0) {
  2265. dev_err(&client->dev,
  2266. "snd_soc_register_component failed with ret = %d\n", ret);
  2267. goto err;
  2268. }
  2269. regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
  2270. CS43130_ASP_3ST_MASK, 0);
  2271. regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
  2272. CS43130_XSP_3ST_MASK, 0);
  2273. return 0;
  2274. err:
  2275. return ret;
  2276. }
  2277. static int cs43130_i2c_remove(struct i2c_client *client)
  2278. {
  2279. struct cs43130_private *cs43130 = i2c_get_clientdata(client);
  2280. if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
  2281. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  2282. CS43130_XTAL_ERR_INT,
  2283. 1 << CS43130_XTAL_ERR_INT_SHIFT);
  2284. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  2285. CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT,
  2286. CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT);
  2287. if (cs43130->dc_meas) {
  2288. cancel_work_sync(&cs43130->work);
  2289. flush_workqueue(cs43130->wq);
  2290. device_remove_file(&client->dev, &dev_attr_hpload_dc_l);
  2291. device_remove_file(&client->dev, &dev_attr_hpload_dc_r);
  2292. device_remove_file(&client->dev, &dev_attr_hpload_ac_l);
  2293. device_remove_file(&client->dev, &dev_attr_hpload_ac_r);
  2294. }
  2295. gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
  2296. pm_runtime_disable(&client->dev);
  2297. regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
  2298. return 0;
  2299. }
  2300. static int __maybe_unused cs43130_runtime_suspend(struct device *dev)
  2301. {
  2302. struct cs43130_private *cs43130 = dev_get_drvdata(dev);
  2303. if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
  2304. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  2305. CS43130_XTAL_ERR_INT,
  2306. 1 << CS43130_XTAL_ERR_INT_SHIFT);
  2307. regcache_cache_only(cs43130->regmap, true);
  2308. regcache_mark_dirty(cs43130->regmap);
  2309. gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
  2310. regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
  2311. return 0;
  2312. }
  2313. static int __maybe_unused cs43130_runtime_resume(struct device *dev)
  2314. {
  2315. struct cs43130_private *cs43130 = dev_get_drvdata(dev);
  2316. int ret;
  2317. ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES, cs43130->supplies);
  2318. if (ret != 0) {
  2319. dev_err(dev, "Failed to enable supplies: %d\n", ret);
  2320. return ret;
  2321. }
  2322. regcache_cache_only(cs43130->regmap, false);
  2323. gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
  2324. usleep_range(2000, 2050);
  2325. ret = regcache_sync(cs43130->regmap);
  2326. if (ret != 0) {
  2327. dev_err(dev, "Failed to restore register cache\n");
  2328. goto err;
  2329. }
  2330. if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
  2331. regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
  2332. CS43130_XTAL_ERR_INT, 0);
  2333. return 0;
  2334. err:
  2335. regcache_cache_only(cs43130->regmap, true);
  2336. regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
  2337. return ret;
  2338. }
  2339. static const struct dev_pm_ops cs43130_runtime_pm = {
  2340. SET_RUNTIME_PM_OPS(cs43130_runtime_suspend, cs43130_runtime_resume,
  2341. NULL)
  2342. };
  2343. static const struct of_device_id cs43130_of_match[] = {
  2344. {.compatible = "cirrus,cs43130",},
  2345. {.compatible = "cirrus,cs4399",},
  2346. {.compatible = "cirrus,cs43131",},
  2347. {.compatible = "cirrus,cs43198",},
  2348. {},
  2349. };
  2350. MODULE_DEVICE_TABLE(of, cs43130_of_match);
  2351. static const struct i2c_device_id cs43130_i2c_id[] = {
  2352. {"cs43130", 0},
  2353. {"cs4399", 0},
  2354. {"cs43131", 0},
  2355. {"cs43198", 0},
  2356. {}
  2357. };
  2358. MODULE_DEVICE_TABLE(i2c, cs43130_i2c_id);
  2359. static struct i2c_driver cs43130_i2c_driver = {
  2360. .driver = {
  2361. .name = "cs43130",
  2362. .of_match_table = cs43130_of_match,
  2363. .pm = &cs43130_runtime_pm,
  2364. },
  2365. .id_table = cs43130_i2c_id,
  2366. .probe = cs43130_i2c_probe,
  2367. .remove = cs43130_i2c_remove,
  2368. };
  2369. module_i2c_driver(cs43130_i2c_driver);
  2370. MODULE_AUTHOR("Li Xu <li.xu@cirrus.com>");
  2371. MODULE_DESCRIPTION("Cirrus Logic CS43130 ALSA SoC Codec Driver");
  2372. MODULE_LICENSE("GPL");