cs42l73.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cs42l73.c -- CS42L73 ALSA Soc Audio driver
  4. *
  5. * Copyright 2011 Cirrus Logic, Inc.
  6. *
  7. * Authors: Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>
  8. * Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/delay.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/regmap.h>
  19. #include <linux/slab.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <sound/soc-dapm.h>
  25. #include <sound/initval.h>
  26. #include <sound/tlv.h>
  27. #include <sound/cs42l73.h>
  28. #include "cs42l73.h"
  29. struct sp_config {
  30. u8 spc, mmcc, spfs;
  31. u32 srate;
  32. };
  33. struct cs42l73_private {
  34. struct cs42l73_platform_data pdata;
  35. struct sp_config config[3];
  36. struct regmap *regmap;
  37. u32 sysclk;
  38. u8 mclksel;
  39. u32 mclk;
  40. int shutdwn_delay;
  41. };
  42. static const struct reg_default cs42l73_reg_defaults[] = {
  43. { 6, 0xF1 }, /* r06 - Power Ctl 1 */
  44. { 7, 0xDF }, /* r07 - Power Ctl 2 */
  45. { 8, 0x3F }, /* r08 - Power Ctl 3 */
  46. { 9, 0x50 }, /* r09 - Charge Pump Freq */
  47. { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
  48. { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
  49. { 12, 0x00 }, /* r0C - Aux PCM Ctl */
  50. { 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */
  51. { 14, 0x00 }, /* r0E - Audio PCM Ctl */
  52. { 15, 0x15 }, /* r0F - Audio PCM Master Clock Ctl */
  53. { 16, 0x00 }, /* r10 - Voice PCM Ctl */
  54. { 17, 0x15 }, /* r11 - Voice PCM Master Clock Ctl */
  55. { 18, 0x00 }, /* r12 - Voice/Aux Sample Rate */
  56. { 19, 0x06 }, /* r13 - Misc I/O Path Ctl */
  57. { 20, 0x00 }, /* r14 - ADC Input Path Ctl */
  58. { 21, 0x00 }, /* r15 - MICA Preamp, PGA Volume */
  59. { 22, 0x00 }, /* r16 - MICB Preamp, PGA Volume */
  60. { 23, 0x00 }, /* r17 - Input Path A Digital Volume */
  61. { 24, 0x00 }, /* r18 - Input Path B Digital Volume */
  62. { 25, 0x00 }, /* r19 - Playback Digital Ctl */
  63. { 26, 0x00 }, /* r1A - HP/LO Left Digital Volume */
  64. { 27, 0x00 }, /* r1B - HP/LO Right Digital Volume */
  65. { 28, 0x00 }, /* r1C - Speakerphone Digital Volume */
  66. { 29, 0x00 }, /* r1D - Ear/SPKLO Digital Volume */
  67. { 30, 0x00 }, /* r1E - HP Left Analog Volume */
  68. { 31, 0x00 }, /* r1F - HP Right Analog Volume */
  69. { 32, 0x00 }, /* r20 - LO Left Analog Volume */
  70. { 33, 0x00 }, /* r21 - LO Right Analog Volume */
  71. { 34, 0x00 }, /* r22 - Stereo Input Path Advisory Volume */
  72. { 35, 0x00 }, /* r23 - Aux PCM Input Advisory Volume */
  73. { 36, 0x00 }, /* r24 - Audio PCM Input Advisory Volume */
  74. { 37, 0x00 }, /* r25 - Voice PCM Input Advisory Volume */
  75. { 38, 0x00 }, /* r26 - Limiter Attack Rate HP/LO */
  76. { 39, 0x7F }, /* r27 - Limter Ctl, Release Rate HP/LO */
  77. { 40, 0x00 }, /* r28 - Limter Threshold HP/LO */
  78. { 41, 0x00 }, /* r29 - Limiter Attack Rate Speakerphone */
  79. { 42, 0x3F }, /* r2A - Limter Ctl, Release Rate Speakerphone */
  80. { 43, 0x00 }, /* r2B - Limter Threshold Speakerphone */
  81. { 44, 0x00 }, /* r2C - Limiter Attack Rate Ear/SPKLO */
  82. { 45, 0x3F }, /* r2D - Limter Ctl, Release Rate Ear/SPKLO */
  83. { 46, 0x00 }, /* r2E - Limter Threshold Ear/SPKLO */
  84. { 47, 0x00 }, /* r2F - ALC Enable, Attack Rate Left/Right */
  85. { 48, 0x3F }, /* r30 - ALC Release Rate Left/Right */
  86. { 49, 0x00 }, /* r31 - ALC Threshold Left/Right */
  87. { 50, 0x00 }, /* r32 - Noise Gate Ctl Left/Right */
  88. { 51, 0x00 }, /* r33 - ALC/NG Misc Ctl */
  89. { 52, 0x18 }, /* r34 - Mixer Ctl */
  90. { 53, 0x3F }, /* r35 - HP/LO Left Mixer Input Path Volume */
  91. { 54, 0x3F }, /* r36 - HP/LO Right Mixer Input Path Volume */
  92. { 55, 0x3F }, /* r37 - HP/LO Left Mixer Aux PCM Volume */
  93. { 56, 0x3F }, /* r38 - HP/LO Right Mixer Aux PCM Volume */
  94. { 57, 0x3F }, /* r39 - HP/LO Left Mixer Audio PCM Volume */
  95. { 58, 0x3F }, /* r3A - HP/LO Right Mixer Audio PCM Volume */
  96. { 59, 0x3F }, /* r3B - HP/LO Left Mixer Voice PCM Mono Volume */
  97. { 60, 0x3F }, /* r3C - HP/LO Right Mixer Voice PCM Mono Volume */
  98. { 61, 0x3F }, /* r3D - Aux PCM Left Mixer Input Path Volume */
  99. { 62, 0x3F }, /* r3E - Aux PCM Right Mixer Input Path Volume */
  100. { 63, 0x3F }, /* r3F - Aux PCM Left Mixer Volume */
  101. { 64, 0x3F }, /* r40 - Aux PCM Left Mixer Volume */
  102. { 65, 0x3F }, /* r41 - Aux PCM Left Mixer Audio PCM L Volume */
  103. { 66, 0x3F }, /* r42 - Aux PCM Right Mixer Audio PCM R Volume */
  104. { 67, 0x3F }, /* r43 - Aux PCM Left Mixer Voice PCM Volume */
  105. { 68, 0x3F }, /* r44 - Aux PCM Right Mixer Voice PCM Volume */
  106. { 69, 0x3F }, /* r45 - Audio PCM Left Input Path Volume */
  107. { 70, 0x3F }, /* r46 - Audio PCM Right Input Path Volume */
  108. { 71, 0x3F }, /* r47 - Audio PCM Left Mixer Aux PCM L Volume */
  109. { 72, 0x3F }, /* r48 - Audio PCM Right Mixer Aux PCM R Volume */
  110. { 73, 0x3F }, /* r49 - Audio PCM Left Mixer Volume */
  111. { 74, 0x3F }, /* r4A - Audio PCM Right Mixer Volume */
  112. { 75, 0x3F }, /* r4B - Audio PCM Left Mixer Voice PCM Volume */
  113. { 76, 0x3F }, /* r4C - Audio PCM Right Mixer Voice PCM Volume */
  114. { 77, 0x3F }, /* r4D - Voice PCM Left Input Path Volume */
  115. { 78, 0x3F }, /* r4E - Voice PCM Right Input Path Volume */
  116. { 79, 0x3F }, /* r4F - Voice PCM Left Mixer Aux PCM L Volume */
  117. { 80, 0x3F }, /* r50 - Voice PCM Right Mixer Aux PCM R Volume */
  118. { 81, 0x3F }, /* r51 - Voice PCM Left Mixer Audio PCM L Volume */
  119. { 82, 0x3F }, /* r52 - Voice PCM Right Mixer Audio PCM R Volume */
  120. { 83, 0x3F }, /* r53 - Voice PCM Left Mixer Voice PCM Volume */
  121. { 84, 0x3F }, /* r54 - Voice PCM Right Mixer Voice PCM Volume */
  122. { 85, 0xAA }, /* r55 - Mono Mixer Ctl */
  123. { 86, 0x3F }, /* r56 - SPK Mono Mixer Input Path Volume */
  124. { 87, 0x3F }, /* r57 - SPK Mono Mixer Aux PCM Mono/L/R Volume */
  125. { 88, 0x3F }, /* r58 - SPK Mono Mixer Audio PCM Mono/L/R Volume */
  126. { 89, 0x3F }, /* r59 - SPK Mono Mixer Voice PCM Mono Volume */
  127. { 90, 0x3F }, /* r5A - SPKLO Mono Mixer Input Path Mono Volume */
  128. { 91, 0x3F }, /* r5B - SPKLO Mono Mixer Aux Mono/L/R Volume */
  129. { 92, 0x3F }, /* r5C - SPKLO Mono Mixer Audio Mono/L/R Volume */
  130. { 93, 0x3F }, /* r5D - SPKLO Mono Mixer Voice Mono Volume */
  131. { 94, 0x00 }, /* r5E - Interrupt Mask 1 */
  132. { 95, 0x00 }, /* r5F - Interrupt Mask 2 */
  133. };
  134. static bool cs42l73_volatile_register(struct device *dev, unsigned int reg)
  135. {
  136. switch (reg) {
  137. case CS42L73_IS1:
  138. case CS42L73_IS2:
  139. return true;
  140. default:
  141. return false;
  142. }
  143. }
  144. static bool cs42l73_readable_register(struct device *dev, unsigned int reg)
  145. {
  146. switch (reg) {
  147. case CS42L73_DEVID_AB ... CS42L73_DEVID_E:
  148. case CS42L73_REVID ... CS42L73_IM2:
  149. return true;
  150. default:
  151. return false;
  152. }
  153. }
  154. static const DECLARE_TLV_DB_RANGE(hpaloa_tlv,
  155. 0, 13, TLV_DB_SCALE_ITEM(-7600, 200, 0),
  156. 14, 75, TLV_DB_SCALE_ITEM(-4900, 100, 0)
  157. );
  158. static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2500, 0);
  159. static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
  160. static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
  161. static DECLARE_TLV_DB_SCALE(micpga_tlv, -600, 50, 0);
  162. static const DECLARE_TLV_DB_RANGE(limiter_tlv,
  163. 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
  164. 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
  165. );
  166. static const DECLARE_TLV_DB_SCALE(attn_tlv, -6300, 100, 1);
  167. static const char * const cs42l73_pgaa_text[] = { "Line A", "Mic 1" };
  168. static const char * const cs42l73_pgab_text[] = { "Line B", "Mic 2" };
  169. static SOC_ENUM_SINGLE_DECL(pgaa_enum,
  170. CS42L73_ADCIPC, 3,
  171. cs42l73_pgaa_text);
  172. static SOC_ENUM_SINGLE_DECL(pgab_enum,
  173. CS42L73_ADCIPC, 7,
  174. cs42l73_pgab_text);
  175. static const struct snd_kcontrol_new pgaa_mux =
  176. SOC_DAPM_ENUM("Left Analog Input Capture Mux", pgaa_enum);
  177. static const struct snd_kcontrol_new pgab_mux =
  178. SOC_DAPM_ENUM("Right Analog Input Capture Mux", pgab_enum);
  179. static const struct snd_kcontrol_new input_left_mixer[] = {
  180. SOC_DAPM_SINGLE("ADC Left Input", CS42L73_PWRCTL1,
  181. 5, 1, 1),
  182. SOC_DAPM_SINGLE("DMIC Left Input", CS42L73_PWRCTL1,
  183. 4, 1, 1),
  184. };
  185. static const struct snd_kcontrol_new input_right_mixer[] = {
  186. SOC_DAPM_SINGLE("ADC Right Input", CS42L73_PWRCTL1,
  187. 7, 1, 1),
  188. SOC_DAPM_SINGLE("DMIC Right Input", CS42L73_PWRCTL1,
  189. 6, 1, 1),
  190. };
  191. static const char * const cs42l73_ng_delay_text[] = {
  192. "50ms", "100ms", "150ms", "200ms" };
  193. static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
  194. CS42L73_NGCAB, 0,
  195. cs42l73_ng_delay_text);
  196. static const char * const cs42l73_mono_mix_texts[] = {
  197. "Left", "Right", "Mono Mix"};
  198. static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 };
  199. static const struct soc_enum spk_asp_enum =
  200. SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 6, 3,
  201. ARRAY_SIZE(cs42l73_mono_mix_texts),
  202. cs42l73_mono_mix_texts,
  203. cs42l73_mono_mix_values);
  204. static const struct snd_kcontrol_new spk_asp_mixer =
  205. SOC_DAPM_ENUM("Route", spk_asp_enum);
  206. static const struct soc_enum spk_xsp_enum =
  207. SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 4, 3,
  208. ARRAY_SIZE(cs42l73_mono_mix_texts),
  209. cs42l73_mono_mix_texts,
  210. cs42l73_mono_mix_values);
  211. static const struct snd_kcontrol_new spk_xsp_mixer =
  212. SOC_DAPM_ENUM("Route", spk_xsp_enum);
  213. static const struct soc_enum esl_asp_enum =
  214. SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 2, 3,
  215. ARRAY_SIZE(cs42l73_mono_mix_texts),
  216. cs42l73_mono_mix_texts,
  217. cs42l73_mono_mix_values);
  218. static const struct snd_kcontrol_new esl_asp_mixer =
  219. SOC_DAPM_ENUM("Route", esl_asp_enum);
  220. static const struct soc_enum esl_xsp_enum =
  221. SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 3,
  222. ARRAY_SIZE(cs42l73_mono_mix_texts),
  223. cs42l73_mono_mix_texts,
  224. cs42l73_mono_mix_values);
  225. static const struct snd_kcontrol_new esl_xsp_mixer =
  226. SOC_DAPM_ENUM("Route", esl_xsp_enum);
  227. static const char * const cs42l73_ip_swap_text[] = {
  228. "Stereo", "Mono A", "Mono B", "Swap A-B"};
  229. static SOC_ENUM_SINGLE_DECL(ip_swap_enum,
  230. CS42L73_MIOPC, 6,
  231. cs42l73_ip_swap_text);
  232. static const char * const cs42l73_spo_mixer_text[] = {"Mono", "Stereo"};
  233. static SOC_ENUM_SINGLE_DECL(vsp_output_mux_enum,
  234. CS42L73_MIXERCTL, 5,
  235. cs42l73_spo_mixer_text);
  236. static SOC_ENUM_SINGLE_DECL(xsp_output_mux_enum,
  237. CS42L73_MIXERCTL, 4,
  238. cs42l73_spo_mixer_text);
  239. static const struct snd_kcontrol_new hp_amp_ctl =
  240. SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 0, 1, 1);
  241. static const struct snd_kcontrol_new lo_amp_ctl =
  242. SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 1, 1, 1);
  243. static const struct snd_kcontrol_new spk_amp_ctl =
  244. SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 2, 1, 1);
  245. static const struct snd_kcontrol_new spklo_amp_ctl =
  246. SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 4, 1, 1);
  247. static const struct snd_kcontrol_new ear_amp_ctl =
  248. SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 3, 1, 1);
  249. static const struct snd_kcontrol_new cs42l73_snd_controls[] = {
  250. SOC_DOUBLE_R_SX_TLV("Headphone Analog Playback Volume",
  251. CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0,
  252. 0x41, 0x4B, hpaloa_tlv),
  253. SOC_DOUBLE_R_SX_TLV("LineOut Analog Playback Volume", CS42L73_LOAAVOL,
  254. CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv),
  255. SOC_DOUBLE_R_SX_TLV("Input PGA Analog Volume", CS42L73_MICAPREPGAAVOL,
  256. CS42L73_MICBPREPGABVOL, 0, 0x34,
  257. 0x24, micpga_tlv),
  258. SOC_DOUBLE_R("MIC Preamp Switch", CS42L73_MICAPREPGAAVOL,
  259. CS42L73_MICBPREPGABVOL, 6, 1, 1),
  260. SOC_DOUBLE_R_SX_TLV("Input Path Digital Volume", CS42L73_IPADVOL,
  261. CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv),
  262. SOC_DOUBLE_R_SX_TLV("HL Digital Playback Volume",
  263. CS42L73_HLADVOL, CS42L73_HLBDVOL,
  264. 0, 0x34, 0xE4, hl_tlv),
  265. SOC_SINGLE_TLV("ADC A Boost Volume",
  266. CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv),
  267. SOC_SINGLE_TLV("ADC B Boost Volume",
  268. CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv),
  269. SOC_SINGLE_SX_TLV("Speakerphone Digital Volume",
  270. CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv),
  271. SOC_SINGLE_SX_TLV("Ear Speaker Digital Volume",
  272. CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv),
  273. SOC_DOUBLE_R("Headphone Analog Playback Switch", CS42L73_HPAAVOL,
  274. CS42L73_HPBAVOL, 7, 1, 1),
  275. SOC_DOUBLE_R("LineOut Analog Playback Switch", CS42L73_LOAAVOL,
  276. CS42L73_LOBAVOL, 7, 1, 1),
  277. SOC_DOUBLE("Input Path Digital Switch", CS42L73_ADCIPC, 0, 4, 1, 1),
  278. SOC_DOUBLE("HL Digital Playback Switch", CS42L73_PBDC, 0,
  279. 1, 1, 1),
  280. SOC_SINGLE("Speakerphone Digital Playback Switch", CS42L73_PBDC, 2, 1,
  281. 1),
  282. SOC_SINGLE("Ear Speaker Digital Playback Switch", CS42L73_PBDC, 3, 1,
  283. 1),
  284. SOC_SINGLE("PGA Soft-Ramp Switch", CS42L73_MIOPC, 3, 1, 0),
  285. SOC_SINGLE("Analog Zero Cross Switch", CS42L73_MIOPC, 2, 1, 0),
  286. SOC_SINGLE("Digital Soft-Ramp Switch", CS42L73_MIOPC, 1, 1, 0),
  287. SOC_SINGLE("Analog Output Soft-Ramp Switch", CS42L73_MIOPC, 0, 1, 0),
  288. SOC_DOUBLE("ADC Signal Polarity Switch", CS42L73_ADCIPC, 1, 5, 1,
  289. 0),
  290. SOC_SINGLE("HL Limiter Attack Rate", CS42L73_LIMARATEHL, 0, 0x3F,
  291. 0),
  292. SOC_SINGLE("HL Limiter Release Rate", CS42L73_LIMRRATEHL, 0,
  293. 0x3F, 0),
  294. SOC_SINGLE("HL Limiter Switch", CS42L73_LIMRRATEHL, 7, 1, 0),
  295. SOC_SINGLE("HL Limiter All Channels Switch", CS42L73_LIMRRATEHL, 6, 1,
  296. 0),
  297. SOC_SINGLE_TLV("HL Limiter Max Threshold Volume", CS42L73_LMAXHL, 5, 7,
  298. 1, limiter_tlv),
  299. SOC_SINGLE_TLV("HL Limiter Cushion Volume", CS42L73_LMAXHL, 2, 7, 1,
  300. limiter_tlv),
  301. SOC_SINGLE("SPK Limiter Attack Rate Volume", CS42L73_LIMARATESPK, 0,
  302. 0x3F, 0),
  303. SOC_SINGLE("SPK Limiter Release Rate Volume", CS42L73_LIMRRATESPK, 0,
  304. 0x3F, 0),
  305. SOC_SINGLE("SPK Limiter Switch", CS42L73_LIMRRATESPK, 7, 1, 0),
  306. SOC_SINGLE("SPK Limiter All Channels Switch", CS42L73_LIMRRATESPK,
  307. 6, 1, 0),
  308. SOC_SINGLE_TLV("SPK Limiter Max Threshold Volume", CS42L73_LMAXSPK, 5,
  309. 7, 1, limiter_tlv),
  310. SOC_SINGLE_TLV("SPK Limiter Cushion Volume", CS42L73_LMAXSPK, 2, 7, 1,
  311. limiter_tlv),
  312. SOC_SINGLE("ESL Limiter Attack Rate Volume", CS42L73_LIMARATEESL, 0,
  313. 0x3F, 0),
  314. SOC_SINGLE("ESL Limiter Release Rate Volume", CS42L73_LIMRRATEESL, 0,
  315. 0x3F, 0),
  316. SOC_SINGLE("ESL Limiter Switch", CS42L73_LIMRRATEESL, 7, 1, 0),
  317. SOC_SINGLE_TLV("ESL Limiter Max Threshold Volume", CS42L73_LMAXESL, 5,
  318. 7, 1, limiter_tlv),
  319. SOC_SINGLE_TLV("ESL Limiter Cushion Volume", CS42L73_LMAXESL, 2, 7, 1,
  320. limiter_tlv),
  321. SOC_SINGLE("ALC Attack Rate Volume", CS42L73_ALCARATE, 0, 0x3F, 0),
  322. SOC_SINGLE("ALC Release Rate Volume", CS42L73_ALCRRATE, 0, 0x3F, 0),
  323. SOC_DOUBLE("ALC Switch", CS42L73_ALCARATE, 6, 7, 1, 0),
  324. SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L73_ALCMINMAX, 5, 7, 0,
  325. limiter_tlv),
  326. SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L73_ALCMINMAX, 2, 7, 0,
  327. limiter_tlv),
  328. SOC_DOUBLE("NG Enable Switch", CS42L73_NGCAB, 6, 7, 1, 0),
  329. SOC_SINGLE("NG Boost Switch", CS42L73_NGCAB, 5, 1, 0),
  330. /*
  331. NG Threshold depends on NG_BOOTSAB, which selects
  332. between two threshold scales in decibels.
  333. Set linear values for now ..
  334. */
  335. SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0),
  336. SOC_ENUM("NG Delay", ng_delay_enum),
  337. SOC_DOUBLE_R_TLV("XSP-IP Volume",
  338. CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1,
  339. attn_tlv),
  340. SOC_DOUBLE_R_TLV("XSP-XSP Volume",
  341. CS42L73_XSPAXSPAA, CS42L73_XSPBXSPBA, 0, 0x3F, 1,
  342. attn_tlv),
  343. SOC_DOUBLE_R_TLV("XSP-ASP Volume",
  344. CS42L73_XSPAASPAA, CS42L73_XSPAASPBA, 0, 0x3F, 1,
  345. attn_tlv),
  346. SOC_DOUBLE_R_TLV("XSP-VSP Volume",
  347. CS42L73_XSPAVSPMA, CS42L73_XSPBVSPMA, 0, 0x3F, 1,
  348. attn_tlv),
  349. SOC_DOUBLE_R_TLV("ASP-IP Volume",
  350. CS42L73_ASPAIPAA, CS42L73_ASPBIPBA, 0, 0x3F, 1,
  351. attn_tlv),
  352. SOC_DOUBLE_R_TLV("ASP-XSP Volume",
  353. CS42L73_ASPAXSPAA, CS42L73_ASPBXSPBA, 0, 0x3F, 1,
  354. attn_tlv),
  355. SOC_DOUBLE_R_TLV("ASP-ASP Volume",
  356. CS42L73_ASPAASPAA, CS42L73_ASPBASPBA, 0, 0x3F, 1,
  357. attn_tlv),
  358. SOC_DOUBLE_R_TLV("ASP-VSP Volume",
  359. CS42L73_ASPAVSPMA, CS42L73_ASPBVSPMA, 0, 0x3F, 1,
  360. attn_tlv),
  361. SOC_DOUBLE_R_TLV("VSP-IP Volume",
  362. CS42L73_VSPAIPAA, CS42L73_VSPBIPBA, 0, 0x3F, 1,
  363. attn_tlv),
  364. SOC_DOUBLE_R_TLV("VSP-XSP Volume",
  365. CS42L73_VSPAXSPAA, CS42L73_VSPBXSPBA, 0, 0x3F, 1,
  366. attn_tlv),
  367. SOC_DOUBLE_R_TLV("VSP-ASP Volume",
  368. CS42L73_VSPAASPAA, CS42L73_VSPBASPBA, 0, 0x3F, 1,
  369. attn_tlv),
  370. SOC_DOUBLE_R_TLV("VSP-VSP Volume",
  371. CS42L73_VSPAVSPMA, CS42L73_VSPBVSPMA, 0, 0x3F, 1,
  372. attn_tlv),
  373. SOC_DOUBLE_R_TLV("HL-IP Volume",
  374. CS42L73_HLAIPAA, CS42L73_HLBIPBA, 0, 0x3F, 1,
  375. attn_tlv),
  376. SOC_DOUBLE_R_TLV("HL-XSP Volume",
  377. CS42L73_HLAXSPAA, CS42L73_HLBXSPBA, 0, 0x3F, 1,
  378. attn_tlv),
  379. SOC_DOUBLE_R_TLV("HL-ASP Volume",
  380. CS42L73_HLAASPAA, CS42L73_HLBASPBA, 0, 0x3F, 1,
  381. attn_tlv),
  382. SOC_DOUBLE_R_TLV("HL-VSP Volume",
  383. CS42L73_HLAVSPMA, CS42L73_HLBVSPMA, 0, 0x3F, 1,
  384. attn_tlv),
  385. SOC_SINGLE_TLV("SPK-IP Mono Volume",
  386. CS42L73_SPKMIPMA, 0, 0x3F, 1, attn_tlv),
  387. SOC_SINGLE_TLV("SPK-XSP Mono Volume",
  388. CS42L73_SPKMXSPA, 0, 0x3F, 1, attn_tlv),
  389. SOC_SINGLE_TLV("SPK-ASP Mono Volume",
  390. CS42L73_SPKMASPA, 0, 0x3F, 1, attn_tlv),
  391. SOC_SINGLE_TLV("SPK-VSP Mono Volume",
  392. CS42L73_SPKMVSPMA, 0, 0x3F, 1, attn_tlv),
  393. SOC_SINGLE_TLV("ESL-IP Mono Volume",
  394. CS42L73_ESLMIPMA, 0, 0x3F, 1, attn_tlv),
  395. SOC_SINGLE_TLV("ESL-XSP Mono Volume",
  396. CS42L73_ESLMXSPA, 0, 0x3F, 1, attn_tlv),
  397. SOC_SINGLE_TLV("ESL-ASP Mono Volume",
  398. CS42L73_ESLMASPA, 0, 0x3F, 1, attn_tlv),
  399. SOC_SINGLE_TLV("ESL-VSP Mono Volume",
  400. CS42L73_ESLMVSPMA, 0, 0x3F, 1, attn_tlv),
  401. SOC_ENUM("IP Digital Swap/Mono Select", ip_swap_enum),
  402. SOC_ENUM("VSPOUT Mono/Stereo Select", vsp_output_mux_enum),
  403. SOC_ENUM("XSPOUT Mono/Stereo Select", xsp_output_mux_enum),
  404. };
  405. static int cs42l73_spklo_spk_amp_event(struct snd_soc_dapm_widget *w,
  406. struct snd_kcontrol *kcontrol, int event)
  407. {
  408. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  409. struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
  410. switch (event) {
  411. case SND_SOC_DAPM_POST_PMD:
  412. /* 150 ms delay between setting PDN and MCLKDIS */
  413. priv->shutdwn_delay = 150;
  414. break;
  415. default:
  416. pr_err("Invalid event = 0x%x\n", event);
  417. }
  418. return 0;
  419. }
  420. static int cs42l73_ear_amp_event(struct snd_soc_dapm_widget *w,
  421. struct snd_kcontrol *kcontrol, int event)
  422. {
  423. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  424. struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
  425. switch (event) {
  426. case SND_SOC_DAPM_POST_PMD:
  427. /* 50 ms delay between setting PDN and MCLKDIS */
  428. if (priv->shutdwn_delay < 50)
  429. priv->shutdwn_delay = 50;
  430. break;
  431. default:
  432. pr_err("Invalid event = 0x%x\n", event);
  433. }
  434. return 0;
  435. }
  436. static int cs42l73_hp_amp_event(struct snd_soc_dapm_widget *w,
  437. struct snd_kcontrol *kcontrol, int event)
  438. {
  439. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  440. struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
  441. switch (event) {
  442. case SND_SOC_DAPM_POST_PMD:
  443. /* 30 ms delay between setting PDN and MCLKDIS */
  444. if (priv->shutdwn_delay < 30)
  445. priv->shutdwn_delay = 30;
  446. break;
  447. default:
  448. pr_err("Invalid event = 0x%x\n", event);
  449. }
  450. return 0;
  451. }
  452. static const struct snd_soc_dapm_widget cs42l73_dapm_widgets[] = {
  453. SND_SOC_DAPM_INPUT("DMICA"),
  454. SND_SOC_DAPM_INPUT("DMICB"),
  455. SND_SOC_DAPM_INPUT("LINEINA"),
  456. SND_SOC_DAPM_INPUT("LINEINB"),
  457. SND_SOC_DAPM_INPUT("MIC1"),
  458. SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS42L73_PWRCTL2, 6, 1, NULL, 0),
  459. SND_SOC_DAPM_INPUT("MIC2"),
  460. SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0),
  461. SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL, 0,
  462. CS42L73_PWRCTL2, 1, 1),
  463. SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL, 0,
  464. CS42L73_PWRCTL2, 1, 1),
  465. SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL, 0,
  466. CS42L73_PWRCTL2, 3, 1),
  467. SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL, 0,
  468. CS42L73_PWRCTL2, 3, 1),
  469. SND_SOC_DAPM_AIF_OUT("VSPINOUT", NULL, 0,
  470. CS42L73_PWRCTL2, 4, 1),
  471. SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0),
  472. SND_SOC_DAPM_PGA("PGA Right", SND_SOC_NOPM, 0, 0, NULL, 0),
  473. SND_SOC_DAPM_MUX("PGA Left Mux", SND_SOC_NOPM, 0, 0, &pgaa_mux),
  474. SND_SOC_DAPM_MUX("PGA Right Mux", SND_SOC_NOPM, 0, 0, &pgab_mux),
  475. SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L73_PWRCTL1, 7, 1),
  476. SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L73_PWRCTL1, 5, 1),
  477. SND_SOC_DAPM_ADC("DMIC Left", NULL, CS42L73_PWRCTL1, 6, 1),
  478. SND_SOC_DAPM_ADC("DMIC Right", NULL, CS42L73_PWRCTL1, 4, 1),
  479. SND_SOC_DAPM_MIXER_NAMED_CTL("Input Left Capture", SND_SOC_NOPM,
  480. 0, 0, input_left_mixer,
  481. ARRAY_SIZE(input_left_mixer)),
  482. SND_SOC_DAPM_MIXER_NAMED_CTL("Input Right Capture", SND_SOC_NOPM,
  483. 0, 0, input_right_mixer,
  484. ARRAY_SIZE(input_right_mixer)),
  485. SND_SOC_DAPM_MIXER("ASPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  486. SND_SOC_DAPM_MIXER("ASPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  487. SND_SOC_DAPM_MIXER("XSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  488. SND_SOC_DAPM_MIXER("XSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  489. SND_SOC_DAPM_MIXER("VSP Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  490. SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0,
  491. CS42L73_PWRCTL2, 0, 1),
  492. SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0,
  493. CS42L73_PWRCTL2, 0, 1),
  494. SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0,
  495. CS42L73_PWRCTL2, 0, 1),
  496. SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0,
  497. CS42L73_PWRCTL2, 2, 1),
  498. SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0,
  499. CS42L73_PWRCTL2, 2, 1),
  500. SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0,
  501. CS42L73_PWRCTL2, 2, 1),
  502. SND_SOC_DAPM_AIF_IN("VSPINOUT", NULL, 0,
  503. CS42L73_PWRCTL2, 4, 1),
  504. SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  505. SND_SOC_DAPM_MIXER("HL Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  506. SND_SOC_DAPM_MIXER("SPK Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  507. SND_SOC_DAPM_MIXER("ESL Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  508. SND_SOC_DAPM_MUX("ESL-XSP Mux", SND_SOC_NOPM,
  509. 0, 0, &esl_xsp_mixer),
  510. SND_SOC_DAPM_MUX("ESL-ASP Mux", SND_SOC_NOPM,
  511. 0, 0, &esl_asp_mixer),
  512. SND_SOC_DAPM_MUX("SPK-ASP Mux", SND_SOC_NOPM,
  513. 0, 0, &spk_asp_mixer),
  514. SND_SOC_DAPM_MUX("SPK-XSP Mux", SND_SOC_NOPM,
  515. 0, 0, &spk_xsp_mixer),
  516. SND_SOC_DAPM_PGA("HL Left DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  517. SND_SOC_DAPM_PGA("HL Right DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  518. SND_SOC_DAPM_PGA("SPK DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  519. SND_SOC_DAPM_PGA("ESL DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  520. SND_SOC_DAPM_SWITCH_E("HP Amp", CS42L73_PWRCTL3, 0, 1,
  521. &hp_amp_ctl, cs42l73_hp_amp_event,
  522. SND_SOC_DAPM_POST_PMD),
  523. SND_SOC_DAPM_SWITCH("LO Amp", CS42L73_PWRCTL3, 1, 1,
  524. &lo_amp_ctl),
  525. SND_SOC_DAPM_SWITCH_E("SPK Amp", CS42L73_PWRCTL3, 2, 1,
  526. &spk_amp_ctl, cs42l73_spklo_spk_amp_event,
  527. SND_SOC_DAPM_POST_PMD),
  528. SND_SOC_DAPM_SWITCH_E("EAR Amp", CS42L73_PWRCTL3, 3, 1,
  529. &ear_amp_ctl, cs42l73_ear_amp_event,
  530. SND_SOC_DAPM_POST_PMD),
  531. SND_SOC_DAPM_SWITCH_E("SPKLO Amp", CS42L73_PWRCTL3, 4, 1,
  532. &spklo_amp_ctl, cs42l73_spklo_spk_amp_event,
  533. SND_SOC_DAPM_POST_PMD),
  534. SND_SOC_DAPM_OUTPUT("HPOUTA"),
  535. SND_SOC_DAPM_OUTPUT("HPOUTB"),
  536. SND_SOC_DAPM_OUTPUT("LINEOUTA"),
  537. SND_SOC_DAPM_OUTPUT("LINEOUTB"),
  538. SND_SOC_DAPM_OUTPUT("EAROUT"),
  539. SND_SOC_DAPM_OUTPUT("SPKOUT"),
  540. SND_SOC_DAPM_OUTPUT("SPKLINEOUT"),
  541. };
  542. static const struct snd_soc_dapm_route cs42l73_audio_map[] = {
  543. /* SPKLO EARSPK Paths */
  544. {"EAROUT", NULL, "EAR Amp"},
  545. {"SPKLINEOUT", NULL, "SPKLO Amp"},
  546. {"EAR Amp", "Switch", "ESL DAC"},
  547. {"SPKLO Amp", "Switch", "ESL DAC"},
  548. {"ESL DAC", "ESL-ASP Mono Volume", "ESL Mixer"},
  549. {"ESL DAC", "ESL-XSP Mono Volume", "ESL Mixer"},
  550. {"ESL DAC", "ESL-VSP Mono Volume", "VSPINOUT"},
  551. /* Loopback */
  552. {"ESL DAC", "ESL-IP Mono Volume", "Input Left Capture"},
  553. {"ESL DAC", "ESL-IP Mono Volume", "Input Right Capture"},
  554. {"ESL Mixer", NULL, "ESL-ASP Mux"},
  555. {"ESL Mixer", NULL, "ESL-XSP Mux"},
  556. {"ESL-ASP Mux", "Left", "ASPINL"},
  557. {"ESL-ASP Mux", "Right", "ASPINR"},
  558. {"ESL-ASP Mux", "Mono Mix", "ASPINM"},
  559. {"ESL-XSP Mux", "Left", "XSPINL"},
  560. {"ESL-XSP Mux", "Right", "XSPINR"},
  561. {"ESL-XSP Mux", "Mono Mix", "XSPINM"},
  562. /* Speakerphone Paths */
  563. {"SPKOUT", NULL, "SPK Amp"},
  564. {"SPK Amp", "Switch", "SPK DAC"},
  565. {"SPK DAC", "SPK-ASP Mono Volume", "SPK Mixer"},
  566. {"SPK DAC", "SPK-XSP Mono Volume", "SPK Mixer"},
  567. {"SPK DAC", "SPK-VSP Mono Volume", "VSPINOUT"},
  568. /* Loopback */
  569. {"SPK DAC", "SPK-IP Mono Volume", "Input Left Capture"},
  570. {"SPK DAC", "SPK-IP Mono Volume", "Input Right Capture"},
  571. {"SPK Mixer", NULL, "SPK-ASP Mux"},
  572. {"SPK Mixer", NULL, "SPK-XSP Mux"},
  573. {"SPK-ASP Mux", "Left", "ASPINL"},
  574. {"SPK-ASP Mux", "Mono Mix", "ASPINM"},
  575. {"SPK-ASP Mux", "Right", "ASPINR"},
  576. {"SPK-XSP Mux", "Left", "XSPINL"},
  577. {"SPK-XSP Mux", "Mono Mix", "XSPINM"},
  578. {"SPK-XSP Mux", "Right", "XSPINR"},
  579. /* HP LineOUT Paths */
  580. {"HPOUTA", NULL, "HP Amp"},
  581. {"HPOUTB", NULL, "HP Amp"},
  582. {"LINEOUTA", NULL, "LO Amp"},
  583. {"LINEOUTB", NULL, "LO Amp"},
  584. {"HP Amp", "Switch", "HL Left DAC"},
  585. {"HP Amp", "Switch", "HL Right DAC"},
  586. {"LO Amp", "Switch", "HL Left DAC"},
  587. {"LO Amp", "Switch", "HL Right DAC"},
  588. {"HL Left DAC", "HL-XSP Volume", "HL Left Mixer"},
  589. {"HL Right DAC", "HL-XSP Volume", "HL Right Mixer"},
  590. {"HL Left DAC", "HL-ASP Volume", "HL Left Mixer"},
  591. {"HL Right DAC", "HL-ASP Volume", "HL Right Mixer"},
  592. {"HL Left DAC", "HL-VSP Volume", "HL Left Mixer"},
  593. {"HL Right DAC", "HL-VSP Volume", "HL Right Mixer"},
  594. /* Loopback */
  595. {"HL Left DAC", "HL-IP Volume", "HL Left Mixer"},
  596. {"HL Right DAC", "HL-IP Volume", "HL Right Mixer"},
  597. {"HL Left Mixer", NULL, "Input Left Capture"},
  598. {"HL Right Mixer", NULL, "Input Right Capture"},
  599. {"HL Left Mixer", NULL, "ASPINL"},
  600. {"HL Right Mixer", NULL, "ASPINR"},
  601. {"HL Left Mixer", NULL, "XSPINL"},
  602. {"HL Right Mixer", NULL, "XSPINR"},
  603. {"HL Left Mixer", NULL, "VSPINOUT"},
  604. {"HL Right Mixer", NULL, "VSPINOUT"},
  605. {"ASPINL", NULL, "ASP Playback"},
  606. {"ASPINM", NULL, "ASP Playback"},
  607. {"ASPINR", NULL, "ASP Playback"},
  608. {"XSPINL", NULL, "XSP Playback"},
  609. {"XSPINM", NULL, "XSP Playback"},
  610. {"XSPINR", NULL, "XSP Playback"},
  611. {"VSPINOUT", NULL, "VSP Playback"},
  612. /* Capture Paths */
  613. {"MIC1", NULL, "MIC1 Bias"},
  614. {"PGA Left Mux", "Mic 1", "MIC1"},
  615. {"MIC2", NULL, "MIC2 Bias"},
  616. {"PGA Right Mux", "Mic 2", "MIC2"},
  617. {"PGA Left Mux", "Line A", "LINEINA"},
  618. {"PGA Right Mux", "Line B", "LINEINB"},
  619. {"PGA Left", NULL, "PGA Left Mux"},
  620. {"PGA Right", NULL, "PGA Right Mux"},
  621. {"ADC Left", NULL, "PGA Left"},
  622. {"ADC Right", NULL, "PGA Right"},
  623. {"DMIC Left", NULL, "DMICA"},
  624. {"DMIC Right", NULL, "DMICB"},
  625. {"Input Left Capture", "ADC Left Input", "ADC Left"},
  626. {"Input Right Capture", "ADC Right Input", "ADC Right"},
  627. {"Input Left Capture", "DMIC Left Input", "DMIC Left"},
  628. {"Input Right Capture", "DMIC Right Input", "DMIC Right"},
  629. /* Audio Capture */
  630. {"ASPL Output Mixer", NULL, "Input Left Capture"},
  631. {"ASPR Output Mixer", NULL, "Input Right Capture"},
  632. {"ASPOUTL", "ASP-IP Volume", "ASPL Output Mixer"},
  633. {"ASPOUTR", "ASP-IP Volume", "ASPR Output Mixer"},
  634. /* Auxillary Capture */
  635. {"XSPL Output Mixer", NULL, "Input Left Capture"},
  636. {"XSPR Output Mixer", NULL, "Input Right Capture"},
  637. {"XSPOUTL", "XSP-IP Volume", "XSPL Output Mixer"},
  638. {"XSPOUTR", "XSP-IP Volume", "XSPR Output Mixer"},
  639. {"XSPOUTL", NULL, "XSPL Output Mixer"},
  640. {"XSPOUTR", NULL, "XSPR Output Mixer"},
  641. /* Voice Capture */
  642. {"VSP Output Mixer", NULL, "Input Left Capture"},
  643. {"VSP Output Mixer", NULL, "Input Right Capture"},
  644. {"VSPINOUT", "VSP-IP Volume", "VSP Output Mixer"},
  645. {"VSPINOUT", NULL, "VSP Output Mixer"},
  646. {"ASP Capture", NULL, "ASPOUTL"},
  647. {"ASP Capture", NULL, "ASPOUTR"},
  648. {"XSP Capture", NULL, "XSPOUTL"},
  649. {"XSP Capture", NULL, "XSPOUTR"},
  650. {"VSP Capture", NULL, "VSPINOUT"},
  651. };
  652. struct cs42l73_mclk_div {
  653. u32 mclk;
  654. u32 srate;
  655. u8 mmcc;
  656. };
  657. static const struct cs42l73_mclk_div cs42l73_mclk_coeffs[] = {
  658. /* MCLK, Sample Rate, xMMCC[5:0] */
  659. {5644800, 11025, 0x30},
  660. {5644800, 22050, 0x20},
  661. {5644800, 44100, 0x10},
  662. {6000000, 8000, 0x39},
  663. {6000000, 11025, 0x33},
  664. {6000000, 12000, 0x31},
  665. {6000000, 16000, 0x29},
  666. {6000000, 22050, 0x23},
  667. {6000000, 24000, 0x21},
  668. {6000000, 32000, 0x19},
  669. {6000000, 44100, 0x13},
  670. {6000000, 48000, 0x11},
  671. {6144000, 8000, 0x38},
  672. {6144000, 12000, 0x30},
  673. {6144000, 16000, 0x28},
  674. {6144000, 24000, 0x20},
  675. {6144000, 32000, 0x18},
  676. {6144000, 48000, 0x10},
  677. {6500000, 8000, 0x3C},
  678. {6500000, 11025, 0x35},
  679. {6500000, 12000, 0x34},
  680. {6500000, 16000, 0x2C},
  681. {6500000, 22050, 0x25},
  682. {6500000, 24000, 0x24},
  683. {6500000, 32000, 0x1C},
  684. {6500000, 44100, 0x15},
  685. {6500000, 48000, 0x14},
  686. {6400000, 8000, 0x3E},
  687. {6400000, 11025, 0x37},
  688. {6400000, 12000, 0x36},
  689. {6400000, 16000, 0x2E},
  690. {6400000, 22050, 0x27},
  691. {6400000, 24000, 0x26},
  692. {6400000, 32000, 0x1E},
  693. {6400000, 44100, 0x17},
  694. {6400000, 48000, 0x16},
  695. };
  696. struct cs42l73_mclkx_div {
  697. u32 mclkx;
  698. u8 ratio;
  699. u8 mclkdiv;
  700. };
  701. static const struct cs42l73_mclkx_div cs42l73_mclkx_coeffs[] = {
  702. {5644800, 1, 0}, /* 5644800 */
  703. {6000000, 1, 0}, /* 6000000 */
  704. {6144000, 1, 0}, /* 6144000 */
  705. {11289600, 2, 2}, /* 5644800 */
  706. {12288000, 2, 2}, /* 6144000 */
  707. {12000000, 2, 2}, /* 6000000 */
  708. {13000000, 2, 2}, /* 6500000 */
  709. {19200000, 3, 3}, /* 6400000 */
  710. {24000000, 4, 4}, /* 6000000 */
  711. {26000000, 4, 4}, /* 6500000 */
  712. {38400000, 6, 5} /* 6400000 */
  713. };
  714. static int cs42l73_get_mclkx_coeff(int mclkx)
  715. {
  716. int i;
  717. for (i = 0; i < ARRAY_SIZE(cs42l73_mclkx_coeffs); i++) {
  718. if (cs42l73_mclkx_coeffs[i].mclkx == mclkx)
  719. return i;
  720. }
  721. return -EINVAL;
  722. }
  723. static int cs42l73_get_mclk_coeff(int mclk, int srate)
  724. {
  725. int i;
  726. for (i = 0; i < ARRAY_SIZE(cs42l73_mclk_coeffs); i++) {
  727. if (cs42l73_mclk_coeffs[i].mclk == mclk &&
  728. cs42l73_mclk_coeffs[i].srate == srate)
  729. return i;
  730. }
  731. return -EINVAL;
  732. }
  733. static int cs42l73_set_mclk(struct snd_soc_dai *dai, unsigned int freq)
  734. {
  735. struct snd_soc_component *component = dai->component;
  736. struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
  737. int mclkx_coeff;
  738. u32 mclk = 0;
  739. u8 dmmcc = 0;
  740. /* MCLKX -> MCLK */
  741. mclkx_coeff = cs42l73_get_mclkx_coeff(freq);
  742. if (mclkx_coeff < 0)
  743. return mclkx_coeff;
  744. mclk = cs42l73_mclkx_coeffs[mclkx_coeff].mclkx /
  745. cs42l73_mclkx_coeffs[mclkx_coeff].ratio;
  746. dev_dbg(component->dev, "MCLK%u %u <-> internal MCLK %u\n",
  747. priv->mclksel + 1, cs42l73_mclkx_coeffs[mclkx_coeff].mclkx,
  748. mclk);
  749. dmmcc = (priv->mclksel << 4) |
  750. (cs42l73_mclkx_coeffs[mclkx_coeff].mclkdiv << 1);
  751. snd_soc_component_write(component, CS42L73_DMMCC, dmmcc);
  752. priv->sysclk = mclkx_coeff;
  753. priv->mclk = mclk;
  754. return 0;
  755. }
  756. static int cs42l73_set_sysclk(struct snd_soc_dai *dai,
  757. int clk_id, unsigned int freq, int dir)
  758. {
  759. struct snd_soc_component *component = dai->component;
  760. struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
  761. switch (clk_id) {
  762. case CS42L73_CLKID_MCLK1:
  763. break;
  764. case CS42L73_CLKID_MCLK2:
  765. break;
  766. default:
  767. return -EINVAL;
  768. }
  769. if ((cs42l73_set_mclk(dai, freq)) < 0) {
  770. dev_err(component->dev, "Unable to set MCLK for dai %s\n",
  771. dai->name);
  772. return -EINVAL;
  773. }
  774. priv->mclksel = clk_id;
  775. return 0;
  776. }
  777. static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  778. {
  779. struct snd_soc_component *component = codec_dai->component;
  780. struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
  781. u8 id = codec_dai->id;
  782. unsigned int inv, format;
  783. u8 spc, mmcc;
  784. spc = snd_soc_component_read(component, CS42L73_SPC(id));
  785. mmcc = snd_soc_component_read(component, CS42L73_MMCC(id));
  786. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  787. case SND_SOC_DAIFMT_CBM_CFM:
  788. mmcc |= CS42L73_MS_MASTER;
  789. break;
  790. case SND_SOC_DAIFMT_CBS_CFS:
  791. mmcc &= ~CS42L73_MS_MASTER;
  792. break;
  793. default:
  794. return -EINVAL;
  795. }
  796. format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  797. inv = (fmt & SND_SOC_DAIFMT_INV_MASK);
  798. switch (format) {
  799. case SND_SOC_DAIFMT_I2S:
  800. spc &= ~CS42L73_SPDIF_PCM;
  801. break;
  802. case SND_SOC_DAIFMT_DSP_A:
  803. case SND_SOC_DAIFMT_DSP_B:
  804. if (mmcc & CS42L73_MS_MASTER) {
  805. dev_err(component->dev,
  806. "PCM format in slave mode only\n");
  807. return -EINVAL;
  808. }
  809. if (id == CS42L73_ASP) {
  810. dev_err(component->dev,
  811. "PCM format is not supported on ASP port\n");
  812. return -EINVAL;
  813. }
  814. spc |= CS42L73_SPDIF_PCM;
  815. break;
  816. default:
  817. return -EINVAL;
  818. }
  819. if (spc & CS42L73_SPDIF_PCM) {
  820. /* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */
  821. spc &= ~(CS42L73_PCM_MODE_MASK | CS42L73_PCM_BIT_ORDER);
  822. switch (format) {
  823. case SND_SOC_DAIFMT_DSP_B:
  824. if (inv == SND_SOC_DAIFMT_IB_IF)
  825. spc |= CS42L73_PCM_MODE0;
  826. if (inv == SND_SOC_DAIFMT_IB_NF)
  827. spc |= CS42L73_PCM_MODE1;
  828. break;
  829. case SND_SOC_DAIFMT_DSP_A:
  830. if (inv == SND_SOC_DAIFMT_IB_IF)
  831. spc |= CS42L73_PCM_MODE1;
  832. break;
  833. default:
  834. return -EINVAL;
  835. }
  836. }
  837. priv->config[id].spc = spc;
  838. priv->config[id].mmcc = mmcc;
  839. return 0;
  840. }
  841. static const unsigned int cs42l73_asrc_rates[] = {
  842. 8000, 11025, 12000, 16000, 22050,
  843. 24000, 32000, 44100, 48000
  844. };
  845. static unsigned int cs42l73_get_xspfs_coeff(u32 rate)
  846. {
  847. int i;
  848. for (i = 0; i < ARRAY_SIZE(cs42l73_asrc_rates); i++) {
  849. if (cs42l73_asrc_rates[i] == rate)
  850. return i + 1;
  851. }
  852. return 0; /* 0 = Don't know */
  853. }
  854. static void cs42l73_update_asrc(struct snd_soc_component *component, int id, int srate)
  855. {
  856. u8 spfs = 0;
  857. if (srate > 0)
  858. spfs = cs42l73_get_xspfs_coeff(srate);
  859. switch (id) {
  860. case CS42L73_XSP:
  861. snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0x0f, spfs);
  862. break;
  863. case CS42L73_ASP:
  864. snd_soc_component_update_bits(component, CS42L73_ASPC, 0x3c, spfs << 2);
  865. break;
  866. case CS42L73_VSP:
  867. snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0xf0, spfs << 4);
  868. break;
  869. default:
  870. break;
  871. }
  872. }
  873. static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
  874. struct snd_pcm_hw_params *params,
  875. struct snd_soc_dai *dai)
  876. {
  877. struct snd_soc_component *component = dai->component;
  878. struct cs42l73_private *priv = snd_soc_component_get_drvdata(component);
  879. int id = dai->id;
  880. int mclk_coeff;
  881. int srate = params_rate(params);
  882. if (priv->config[id].mmcc & CS42L73_MS_MASTER) {
  883. /* CS42L73 Master */
  884. /* MCLK -> srate */
  885. mclk_coeff =
  886. cs42l73_get_mclk_coeff(priv->mclk, srate);
  887. if (mclk_coeff < 0)
  888. return -EINVAL;
  889. dev_dbg(component->dev,
  890. "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n",
  891. id, priv->mclk, srate,
  892. cs42l73_mclk_coeffs[mclk_coeff].mmcc);
  893. priv->config[id].mmcc &= 0xC0;
  894. priv->config[id].mmcc |= cs42l73_mclk_coeffs[mclk_coeff].mmcc;
  895. priv->config[id].spc &= 0xFC;
  896. /* Use SCLK=64*Fs if internal MCLK >= 6.4MHz */
  897. if (priv->mclk >= 6400000)
  898. priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
  899. else
  900. priv->config[id].spc |= CS42L73_MCK_SCLK_MCLK;
  901. } else {
  902. /* CS42L73 Slave */
  903. priv->config[id].spc &= 0xFC;
  904. priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
  905. }
  906. /* Update ASRCs */
  907. priv->config[id].srate = srate;
  908. snd_soc_component_write(component, CS42L73_SPC(id), priv->config[id].spc);
  909. snd_soc_component_write(component, CS42L73_MMCC(id), priv->config[id].mmcc);
  910. cs42l73_update_asrc(component, id, srate);
  911. return 0;
  912. }
  913. static int cs42l73_set_bias_level(struct snd_soc_component *component,
  914. enum snd_soc_bias_level level)
  915. {
  916. struct cs42l73_private *cs42l73 = snd_soc_component_get_drvdata(component);
  917. switch (level) {
  918. case SND_SOC_BIAS_ON:
  919. snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 0);
  920. snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 0);
  921. break;
  922. case SND_SOC_BIAS_PREPARE:
  923. break;
  924. case SND_SOC_BIAS_STANDBY:
  925. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  926. regcache_cache_only(cs42l73->regmap, false);
  927. regcache_sync(cs42l73->regmap);
  928. }
  929. snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 1);
  930. break;
  931. case SND_SOC_BIAS_OFF:
  932. snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 1);
  933. if (cs42l73->shutdwn_delay > 0) {
  934. mdelay(cs42l73->shutdwn_delay);
  935. cs42l73->shutdwn_delay = 0;
  936. } else {
  937. mdelay(15); /* Min amount of time requred to power
  938. * down.
  939. */
  940. }
  941. snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 1);
  942. break;
  943. }
  944. return 0;
  945. }
  946. static int cs42l73_set_tristate(struct snd_soc_dai *dai, int tristate)
  947. {
  948. struct snd_soc_component *component = dai->component;
  949. int id = dai->id;
  950. return snd_soc_component_update_bits(component, CS42L73_SPC(id), CS42L73_SP_3ST,
  951. tristate << 7);
  952. }
  953. static const struct snd_pcm_hw_constraint_list constraints_12_24 = {
  954. .count = ARRAY_SIZE(cs42l73_asrc_rates),
  955. .list = cs42l73_asrc_rates,
  956. };
  957. static int cs42l73_pcm_startup(struct snd_pcm_substream *substream,
  958. struct snd_soc_dai *dai)
  959. {
  960. snd_pcm_hw_constraint_list(substream->runtime, 0,
  961. SNDRV_PCM_HW_PARAM_RATE,
  962. &constraints_12_24);
  963. return 0;
  964. }
  965. #define CS42L73_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  966. SNDRV_PCM_FMTBIT_S24_LE)
  967. static const struct snd_soc_dai_ops cs42l73_ops = {
  968. .startup = cs42l73_pcm_startup,
  969. .hw_params = cs42l73_pcm_hw_params,
  970. .set_fmt = cs42l73_set_dai_fmt,
  971. .set_sysclk = cs42l73_set_sysclk,
  972. .set_tristate = cs42l73_set_tristate,
  973. };
  974. static struct snd_soc_dai_driver cs42l73_dai[] = {
  975. {
  976. .name = "cs42l73-xsp",
  977. .id = CS42L73_XSP,
  978. .playback = {
  979. .stream_name = "XSP Playback",
  980. .channels_min = 1,
  981. .channels_max = 2,
  982. .rates = SNDRV_PCM_RATE_KNOT,
  983. .formats = CS42L73_FORMATS,
  984. },
  985. .capture = {
  986. .stream_name = "XSP Capture",
  987. .channels_min = 1,
  988. .channels_max = 2,
  989. .rates = SNDRV_PCM_RATE_KNOT,
  990. .formats = CS42L73_FORMATS,
  991. },
  992. .ops = &cs42l73_ops,
  993. .symmetric_rates = 1,
  994. },
  995. {
  996. .name = "cs42l73-asp",
  997. .id = CS42L73_ASP,
  998. .playback = {
  999. .stream_name = "ASP Playback",
  1000. .channels_min = 2,
  1001. .channels_max = 2,
  1002. .rates = SNDRV_PCM_RATE_KNOT,
  1003. .formats = CS42L73_FORMATS,
  1004. },
  1005. .capture = {
  1006. .stream_name = "ASP Capture",
  1007. .channels_min = 2,
  1008. .channels_max = 2,
  1009. .rates = SNDRV_PCM_RATE_KNOT,
  1010. .formats = CS42L73_FORMATS,
  1011. },
  1012. .ops = &cs42l73_ops,
  1013. .symmetric_rates = 1,
  1014. },
  1015. {
  1016. .name = "cs42l73-vsp",
  1017. .id = CS42L73_VSP,
  1018. .playback = {
  1019. .stream_name = "VSP Playback",
  1020. .channels_min = 1,
  1021. .channels_max = 2,
  1022. .rates = SNDRV_PCM_RATE_KNOT,
  1023. .formats = CS42L73_FORMATS,
  1024. },
  1025. .capture = {
  1026. .stream_name = "VSP Capture",
  1027. .channels_min = 1,
  1028. .channels_max = 2,
  1029. .rates = SNDRV_PCM_RATE_KNOT,
  1030. .formats = CS42L73_FORMATS,
  1031. },
  1032. .ops = &cs42l73_ops,
  1033. .symmetric_rates = 1,
  1034. }
  1035. };
  1036. static int cs42l73_probe(struct snd_soc_component *component)
  1037. {
  1038. struct cs42l73_private *cs42l73 = snd_soc_component_get_drvdata(component);
  1039. /* Set Charge Pump Frequency */
  1040. if (cs42l73->pdata.chgfreq)
  1041. snd_soc_component_update_bits(component, CS42L73_CPFCHC,
  1042. CS42L73_CHARGEPUMP_MASK,
  1043. cs42l73->pdata.chgfreq << 4);
  1044. /* MCLK1 as master clk */
  1045. cs42l73->mclksel = CS42L73_CLKID_MCLK1;
  1046. cs42l73->mclk = 0;
  1047. return 0;
  1048. }
  1049. static const struct snd_soc_component_driver soc_component_dev_cs42l73 = {
  1050. .probe = cs42l73_probe,
  1051. .set_bias_level = cs42l73_set_bias_level,
  1052. .controls = cs42l73_snd_controls,
  1053. .num_controls = ARRAY_SIZE(cs42l73_snd_controls),
  1054. .dapm_widgets = cs42l73_dapm_widgets,
  1055. .num_dapm_widgets = ARRAY_SIZE(cs42l73_dapm_widgets),
  1056. .dapm_routes = cs42l73_audio_map,
  1057. .num_dapm_routes = ARRAY_SIZE(cs42l73_audio_map),
  1058. .suspend_bias_off = 1,
  1059. .idle_bias_on = 1,
  1060. .use_pmdown_time = 1,
  1061. .endianness = 1,
  1062. .non_legacy_dai_naming = 1,
  1063. };
  1064. static const struct regmap_config cs42l73_regmap = {
  1065. .reg_bits = 8,
  1066. .val_bits = 8,
  1067. .max_register = CS42L73_MAX_REGISTER,
  1068. .reg_defaults = cs42l73_reg_defaults,
  1069. .num_reg_defaults = ARRAY_SIZE(cs42l73_reg_defaults),
  1070. .volatile_reg = cs42l73_volatile_register,
  1071. .readable_reg = cs42l73_readable_register,
  1072. .cache_type = REGCACHE_RBTREE,
  1073. };
  1074. static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
  1075. const struct i2c_device_id *id)
  1076. {
  1077. struct cs42l73_private *cs42l73;
  1078. struct cs42l73_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
  1079. int ret;
  1080. unsigned int devid = 0;
  1081. unsigned int reg;
  1082. u32 val32;
  1083. cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l73), GFP_KERNEL);
  1084. if (!cs42l73)
  1085. return -ENOMEM;
  1086. cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap);
  1087. if (IS_ERR(cs42l73->regmap)) {
  1088. ret = PTR_ERR(cs42l73->regmap);
  1089. dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
  1090. return ret;
  1091. }
  1092. if (pdata) {
  1093. cs42l73->pdata = *pdata;
  1094. } else {
  1095. pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
  1096. GFP_KERNEL);
  1097. if (!pdata)
  1098. return -ENOMEM;
  1099. if (i2c_client->dev.of_node) {
  1100. if (of_property_read_u32(i2c_client->dev.of_node,
  1101. "chgfreq", &val32) >= 0)
  1102. pdata->chgfreq = val32;
  1103. }
  1104. pdata->reset_gpio = of_get_named_gpio(i2c_client->dev.of_node,
  1105. "reset-gpio", 0);
  1106. cs42l73->pdata = *pdata;
  1107. }
  1108. i2c_set_clientdata(i2c_client, cs42l73);
  1109. if (cs42l73->pdata.reset_gpio) {
  1110. ret = devm_gpio_request_one(&i2c_client->dev,
  1111. cs42l73->pdata.reset_gpio,
  1112. GPIOF_OUT_INIT_HIGH,
  1113. "CS42L73 /RST");
  1114. if (ret < 0) {
  1115. dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
  1116. cs42l73->pdata.reset_gpio, ret);
  1117. return ret;
  1118. }
  1119. gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0);
  1120. gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 1);
  1121. }
  1122. /* initialize codec */
  1123. ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_AB, &reg);
  1124. devid = (reg & 0xFF) << 12;
  1125. ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_CD, &reg);
  1126. devid |= (reg & 0xFF) << 4;
  1127. ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_E, &reg);
  1128. devid |= (reg & 0xF0) >> 4;
  1129. if (devid != CS42L73_DEVID) {
  1130. ret = -ENODEV;
  1131. dev_err(&i2c_client->dev,
  1132. "CS42L73 Device ID (%X). Expected %X\n",
  1133. devid, CS42L73_DEVID);
  1134. return ret;
  1135. }
  1136. ret = regmap_read(cs42l73->regmap, CS42L73_REVID, &reg);
  1137. if (ret < 0) {
  1138. dev_err(&i2c_client->dev, "Get Revision ID failed\n");
  1139. return ret;
  1140. }
  1141. dev_info(&i2c_client->dev,
  1142. "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF);
  1143. ret = devm_snd_soc_register_component(&i2c_client->dev,
  1144. &soc_component_dev_cs42l73, cs42l73_dai,
  1145. ARRAY_SIZE(cs42l73_dai));
  1146. if (ret < 0)
  1147. return ret;
  1148. return 0;
  1149. }
  1150. static const struct of_device_id cs42l73_of_match[] = {
  1151. { .compatible = "cirrus,cs42l73", },
  1152. {},
  1153. };
  1154. MODULE_DEVICE_TABLE(of, cs42l73_of_match);
  1155. static const struct i2c_device_id cs42l73_id[] = {
  1156. {"cs42l73", 0},
  1157. {}
  1158. };
  1159. MODULE_DEVICE_TABLE(i2c, cs42l73_id);
  1160. static struct i2c_driver cs42l73_i2c_driver = {
  1161. .driver = {
  1162. .name = "cs42l73",
  1163. .of_match_table = cs42l73_of_match,
  1164. },
  1165. .id_table = cs42l73_id,
  1166. .probe = cs42l73_i2c_probe,
  1167. };
  1168. module_i2c_driver(cs42l73_i2c_driver);
  1169. MODULE_DESCRIPTION("ASoC CS42L73 driver");
  1170. MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
  1171. MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
  1172. MODULE_LICENSE("GPL");