cs42l51.c 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cs42l51.c
  4. *
  5. * ASoC Driver for Cirrus Logic CS42L51 codecs
  6. *
  7. * Copyright (c) 2010 Arnaud Patard <apatard@mandriva.com>
  8. *
  9. * Based on cs4270.c - Copyright (c) Freescale Semiconductor
  10. *
  11. * For now:
  12. * - Only I2C is support. Not SPI
  13. * - master mode *NOT* supported
  14. */
  15. #include <linux/clk.h>
  16. #include <linux/module.h>
  17. #include <linux/slab.h>
  18. #include <sound/core.h>
  19. #include <sound/soc.h>
  20. #include <sound/tlv.h>
  21. #include <sound/initval.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/pcm.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/regmap.h>
  26. #include <linux/regulator/consumer.h>
  27. #include "cs42l51.h"
  28. enum master_slave_mode {
  29. MODE_SLAVE,
  30. MODE_SLAVE_AUTO,
  31. MODE_MASTER,
  32. };
  33. static const char * const cs42l51_supply_names[] = {
  34. "VL",
  35. "VD",
  36. "VA",
  37. "VAHP",
  38. };
  39. struct cs42l51_private {
  40. unsigned int mclk;
  41. struct clk *mclk_handle;
  42. unsigned int audio_mode; /* The mode (I2S or left-justified) */
  43. enum master_slave_mode func;
  44. struct regulator_bulk_data supplies[ARRAY_SIZE(cs42l51_supply_names)];
  45. struct gpio_desc *reset_gpio;
  46. struct regmap *regmap;
  47. };
  48. #define CS42L51_FORMATS ( \
  49. SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
  50. SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
  51. SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
  52. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE)
  53. static int cs42l51_get_chan_mix(struct snd_kcontrol *kcontrol,
  54. struct snd_ctl_elem_value *ucontrol)
  55. {
  56. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  57. unsigned long value = snd_soc_component_read(component, CS42L51_PCM_MIXER)&3;
  58. switch (value) {
  59. default:
  60. case 0:
  61. ucontrol->value.enumerated.item[0] = 0;
  62. break;
  63. /* same value : (L+R)/2 and (R+L)/2 */
  64. case 1:
  65. case 2:
  66. ucontrol->value.enumerated.item[0] = 1;
  67. break;
  68. case 3:
  69. ucontrol->value.enumerated.item[0] = 2;
  70. break;
  71. }
  72. return 0;
  73. }
  74. #define CHAN_MIX_NORMAL 0x00
  75. #define CHAN_MIX_BOTH 0x55
  76. #define CHAN_MIX_SWAP 0xFF
  77. static int cs42l51_set_chan_mix(struct snd_kcontrol *kcontrol,
  78. struct snd_ctl_elem_value *ucontrol)
  79. {
  80. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  81. unsigned char val;
  82. switch (ucontrol->value.enumerated.item[0]) {
  83. default:
  84. case 0:
  85. val = CHAN_MIX_NORMAL;
  86. break;
  87. case 1:
  88. val = CHAN_MIX_BOTH;
  89. break;
  90. case 2:
  91. val = CHAN_MIX_SWAP;
  92. break;
  93. }
  94. snd_soc_component_write(component, CS42L51_PCM_MIXER, val);
  95. return 1;
  96. }
  97. static const DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -5150, 50, 0);
  98. static const DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0);
  99. static const DECLARE_TLV_DB_SCALE(aout_tlv, -10200, 50, 0);
  100. static const DECLARE_TLV_DB_SCALE(boost_tlv, 1600, 1600, 0);
  101. static const DECLARE_TLV_DB_SCALE(adc_boost_tlv, 2000, 2000, 0);
  102. static const char *chan_mix[] = {
  103. "L R",
  104. "L+R",
  105. "R L",
  106. };
  107. static const DECLARE_TLV_DB_SCALE(pga_tlv, -300, 50, 0);
  108. static const DECLARE_TLV_DB_SCALE(adc_att_tlv, -9600, 100, 0);
  109. static SOC_ENUM_SINGLE_EXT_DECL(cs42l51_chan_mix, chan_mix);
  110. static const struct snd_kcontrol_new cs42l51_snd_controls[] = {
  111. SOC_DOUBLE_R_SX_TLV("PCM Playback Volume",
  112. CS42L51_PCMA_VOL, CS42L51_PCMB_VOL,
  113. 0, 0x19, 0x7F, adc_pcm_tlv),
  114. SOC_DOUBLE_R("PCM Playback Switch",
  115. CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 7, 1, 1),
  116. SOC_DOUBLE_R_SX_TLV("Analog Playback Volume",
  117. CS42L51_AOUTA_VOL, CS42L51_AOUTB_VOL,
  118. 0, 0x34, 0xE4, aout_tlv),
  119. SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
  120. CS42L51_ADCA_VOL, CS42L51_ADCB_VOL,
  121. 0, 0x19, 0x7F, adc_pcm_tlv),
  122. SOC_DOUBLE_R("ADC Mixer Switch",
  123. CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 7, 1, 1),
  124. SOC_DOUBLE_R_SX_TLV("ADC Attenuator Volume",
  125. CS42L51_ADCA_ATT, CS42L51_ADCB_ATT,
  126. 0, 0xA0, 96, adc_att_tlv),
  127. SOC_DOUBLE_R_SX_TLV("PGA Volume",
  128. CS42L51_ALC_PGA_CTL, CS42L51_ALC_PGB_CTL,
  129. 0, 0x1A, 30, pga_tlv),
  130. SOC_SINGLE("Playback Deemphasis Switch", CS42L51_DAC_CTL, 3, 1, 0),
  131. SOC_SINGLE("Auto-Mute Switch", CS42L51_DAC_CTL, 2, 1, 0),
  132. SOC_SINGLE("Soft Ramp Switch", CS42L51_DAC_CTL, 1, 1, 0),
  133. SOC_SINGLE("Zero Cross Switch", CS42L51_DAC_CTL, 0, 0, 0),
  134. SOC_DOUBLE_TLV("Mic Boost Volume",
  135. CS42L51_MIC_CTL, 0, 1, 1, 0, boost_tlv),
  136. SOC_DOUBLE_TLV("ADC Boost Volume",
  137. CS42L51_MIC_CTL, 5, 6, 1, 0, adc_boost_tlv),
  138. SOC_SINGLE_TLV("Bass Volume", CS42L51_TONE_CTL, 0, 0xf, 1, tone_tlv),
  139. SOC_SINGLE_TLV("Treble Volume", CS42L51_TONE_CTL, 4, 0xf, 1, tone_tlv),
  140. SOC_ENUM_EXT("PCM channel mixer",
  141. cs42l51_chan_mix,
  142. cs42l51_get_chan_mix, cs42l51_set_chan_mix),
  143. };
  144. /*
  145. * to power down, one must:
  146. * 1.) Enable the PDN bit
  147. * 2.) enable power-down for the select channels
  148. * 3.) disable the PDN bit.
  149. */
  150. static int cs42l51_pdn_event(struct snd_soc_dapm_widget *w,
  151. struct snd_kcontrol *kcontrol, int event)
  152. {
  153. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  154. switch (event) {
  155. case SND_SOC_DAPM_PRE_PMD:
  156. snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
  157. CS42L51_POWER_CTL1_PDN,
  158. CS42L51_POWER_CTL1_PDN);
  159. break;
  160. default:
  161. case SND_SOC_DAPM_POST_PMD:
  162. snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
  163. CS42L51_POWER_CTL1_PDN, 0);
  164. break;
  165. }
  166. return 0;
  167. }
  168. static const char *cs42l51_dac_names[] = {"Direct PCM",
  169. "DSP PCM", "ADC"};
  170. static SOC_ENUM_SINGLE_DECL(cs42l51_dac_mux_enum,
  171. CS42L51_DAC_CTL, 6, cs42l51_dac_names);
  172. static const struct snd_kcontrol_new cs42l51_dac_mux_controls =
  173. SOC_DAPM_ENUM("Route", cs42l51_dac_mux_enum);
  174. static const char *cs42l51_adcl_names[] = {"AIN1 Left", "AIN2 Left",
  175. "MIC Left", "MIC+preamp Left"};
  176. static SOC_ENUM_SINGLE_DECL(cs42l51_adcl_mux_enum,
  177. CS42L51_ADC_INPUT, 4, cs42l51_adcl_names);
  178. static const struct snd_kcontrol_new cs42l51_adcl_mux_controls =
  179. SOC_DAPM_ENUM("Route", cs42l51_adcl_mux_enum);
  180. static const char *cs42l51_adcr_names[] = {"AIN1 Right", "AIN2 Right",
  181. "MIC Right", "MIC+preamp Right"};
  182. static SOC_ENUM_SINGLE_DECL(cs42l51_adcr_mux_enum,
  183. CS42L51_ADC_INPUT, 6, cs42l51_adcr_names);
  184. static const struct snd_kcontrol_new cs42l51_adcr_mux_controls =
  185. SOC_DAPM_ENUM("Route", cs42l51_adcr_mux_enum);
  186. static const struct snd_soc_dapm_widget cs42l51_dapm_widgets[] = {
  187. SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L51_MIC_POWER_CTL, 1, 1, NULL,
  188. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  189. SND_SOC_DAPM_PGA_E("Left PGA", CS42L51_POWER_CTL1, 3, 1, NULL, 0,
  190. cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
  191. SND_SOC_DAPM_PGA_E("Right PGA", CS42L51_POWER_CTL1, 4, 1, NULL, 0,
  192. cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
  193. SND_SOC_DAPM_ADC_E("Left ADC", "Left HiFi Capture",
  194. CS42L51_POWER_CTL1, 1, 1,
  195. cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
  196. SND_SOC_DAPM_ADC_E("Right ADC", "Right HiFi Capture",
  197. CS42L51_POWER_CTL1, 2, 1,
  198. cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
  199. SND_SOC_DAPM_DAC_E("Left DAC", NULL, CS42L51_POWER_CTL1, 5, 1,
  200. cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
  201. SND_SOC_DAPM_DAC_E("Right DAC", NULL, CS42L51_POWER_CTL1, 6, 1,
  202. cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
  203. /* analog/mic */
  204. SND_SOC_DAPM_INPUT("AIN1L"),
  205. SND_SOC_DAPM_INPUT("AIN1R"),
  206. SND_SOC_DAPM_INPUT("AIN2L"),
  207. SND_SOC_DAPM_INPUT("AIN2R"),
  208. SND_SOC_DAPM_INPUT("MICL"),
  209. SND_SOC_DAPM_INPUT("MICR"),
  210. SND_SOC_DAPM_MIXER("Mic Preamp Left",
  211. CS42L51_MIC_POWER_CTL, 2, 1, NULL, 0),
  212. SND_SOC_DAPM_MIXER("Mic Preamp Right",
  213. CS42L51_MIC_POWER_CTL, 3, 1, NULL, 0),
  214. /* HP */
  215. SND_SOC_DAPM_OUTPUT("HPL"),
  216. SND_SOC_DAPM_OUTPUT("HPR"),
  217. /* mux */
  218. SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
  219. &cs42l51_dac_mux_controls),
  220. SND_SOC_DAPM_MUX("PGA-ADC Mux Left", SND_SOC_NOPM, 0, 0,
  221. &cs42l51_adcl_mux_controls),
  222. SND_SOC_DAPM_MUX("PGA-ADC Mux Right", SND_SOC_NOPM, 0, 0,
  223. &cs42l51_adcr_mux_controls),
  224. };
  225. static int mclk_event(struct snd_soc_dapm_widget *w,
  226. struct snd_kcontrol *kcontrol, int event)
  227. {
  228. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  229. struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(comp);
  230. switch (event) {
  231. case SND_SOC_DAPM_PRE_PMU:
  232. return clk_prepare_enable(cs42l51->mclk_handle);
  233. case SND_SOC_DAPM_POST_PMD:
  234. /* Delay mclk shutdown to fulfill power-down sequence requirements */
  235. msleep(20);
  236. clk_disable_unprepare(cs42l51->mclk_handle);
  237. break;
  238. }
  239. return 0;
  240. }
  241. static const struct snd_soc_dapm_widget cs42l51_dapm_mclk_widgets[] = {
  242. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, mclk_event,
  243. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  244. };
  245. static const struct snd_soc_dapm_route cs42l51_routes[] = {
  246. {"HPL", NULL, "Left DAC"},
  247. {"HPR", NULL, "Right DAC"},
  248. {"Right DAC", NULL, "DAC Mux"},
  249. {"Left DAC", NULL, "DAC Mux"},
  250. {"DAC Mux", "Direct PCM", "Playback"},
  251. {"DAC Mux", "DSP PCM", "Playback"},
  252. {"Left ADC", NULL, "Left PGA"},
  253. {"Right ADC", NULL, "Right PGA"},
  254. {"Mic Preamp Left", NULL, "MICL"},
  255. {"Mic Preamp Right", NULL, "MICR"},
  256. {"PGA-ADC Mux Left", "AIN1 Left", "AIN1L" },
  257. {"PGA-ADC Mux Left", "AIN2 Left", "AIN2L" },
  258. {"PGA-ADC Mux Left", "MIC Left", "MICL" },
  259. {"PGA-ADC Mux Left", "MIC+preamp Left", "Mic Preamp Left" },
  260. {"PGA-ADC Mux Right", "AIN1 Right", "AIN1R" },
  261. {"PGA-ADC Mux Right", "AIN2 Right", "AIN2R" },
  262. {"PGA-ADC Mux Right", "MIC Right", "MICR" },
  263. {"PGA-ADC Mux Right", "MIC+preamp Right", "Mic Preamp Right" },
  264. {"Left PGA", NULL, "PGA-ADC Mux Left"},
  265. {"Right PGA", NULL, "PGA-ADC Mux Right"},
  266. };
  267. static int cs42l51_set_dai_fmt(struct snd_soc_dai *codec_dai,
  268. unsigned int format)
  269. {
  270. struct snd_soc_component *component = codec_dai->component;
  271. struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
  272. switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
  273. case SND_SOC_DAIFMT_I2S:
  274. case SND_SOC_DAIFMT_LEFT_J:
  275. case SND_SOC_DAIFMT_RIGHT_J:
  276. cs42l51->audio_mode = format & SND_SOC_DAIFMT_FORMAT_MASK;
  277. break;
  278. default:
  279. dev_err(component->dev, "invalid DAI format\n");
  280. return -EINVAL;
  281. }
  282. switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
  283. case SND_SOC_DAIFMT_CBM_CFM:
  284. cs42l51->func = MODE_MASTER;
  285. break;
  286. case SND_SOC_DAIFMT_CBS_CFS:
  287. cs42l51->func = MODE_SLAVE_AUTO;
  288. break;
  289. default:
  290. dev_err(component->dev, "Unknown master/slave configuration\n");
  291. return -EINVAL;
  292. }
  293. return 0;
  294. }
  295. struct cs42l51_ratios {
  296. unsigned int ratio;
  297. unsigned char speed_mode;
  298. unsigned char mclk;
  299. };
  300. static struct cs42l51_ratios slave_ratios[] = {
  301. { 512, CS42L51_QSM_MODE, 0 }, { 768, CS42L51_QSM_MODE, 0 },
  302. { 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
  303. { 2048, CS42L51_QSM_MODE, 0 }, { 3072, CS42L51_QSM_MODE, 0 },
  304. { 256, CS42L51_HSM_MODE, 0 }, { 384, CS42L51_HSM_MODE, 0 },
  305. { 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 },
  306. { 1024, CS42L51_HSM_MODE, 0 }, { 1536, CS42L51_HSM_MODE, 0 },
  307. { 128, CS42L51_SSM_MODE, 0 }, { 192, CS42L51_SSM_MODE, 0 },
  308. { 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 },
  309. { 512, CS42L51_SSM_MODE, 0 }, { 768, CS42L51_SSM_MODE, 0 },
  310. { 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 },
  311. { 256, CS42L51_DSM_MODE, 0 }, { 384, CS42L51_DSM_MODE, 0 },
  312. };
  313. static struct cs42l51_ratios slave_auto_ratios[] = {
  314. { 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
  315. { 2048, CS42L51_QSM_MODE, 1 }, { 3072, CS42L51_QSM_MODE, 1 },
  316. { 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 },
  317. { 1024, CS42L51_HSM_MODE, 1 }, { 1536, CS42L51_HSM_MODE, 1 },
  318. { 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 },
  319. { 512, CS42L51_SSM_MODE, 1 }, { 768, CS42L51_SSM_MODE, 1 },
  320. { 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 },
  321. { 256, CS42L51_DSM_MODE, 1 }, { 384, CS42L51_DSM_MODE, 1 },
  322. };
  323. /*
  324. * Master mode mclk/fs ratios.
  325. * Recommended configurations are SSM for 4-50khz and DSM for 50-100kHz ranges
  326. * The table below provides support of following ratios:
  327. * 128: SSM (%128) with div2 disabled
  328. * 256: SSM (%128) with div2 enabled
  329. * In both cases, if sampling rate is above 50kHz, SSM is overridden
  330. * with DSM (%128) configuration
  331. */
  332. static struct cs42l51_ratios master_ratios[] = {
  333. { 128, CS42L51_SSM_MODE, 0 }, { 256, CS42L51_SSM_MODE, 1 },
  334. };
  335. static int cs42l51_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  336. int clk_id, unsigned int freq, int dir)
  337. {
  338. struct snd_soc_component *component = codec_dai->component;
  339. struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
  340. cs42l51->mclk = freq;
  341. return 0;
  342. }
  343. static int cs42l51_hw_params(struct snd_pcm_substream *substream,
  344. struct snd_pcm_hw_params *params,
  345. struct snd_soc_dai *dai)
  346. {
  347. struct snd_soc_component *component = dai->component;
  348. struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
  349. int ret;
  350. unsigned int i;
  351. unsigned int rate;
  352. unsigned int ratio;
  353. struct cs42l51_ratios *ratios = NULL;
  354. int nr_ratios = 0;
  355. int intf_ctl, power_ctl, fmt, mode;
  356. switch (cs42l51->func) {
  357. case MODE_MASTER:
  358. ratios = master_ratios;
  359. nr_ratios = ARRAY_SIZE(master_ratios);
  360. break;
  361. case MODE_SLAVE:
  362. ratios = slave_ratios;
  363. nr_ratios = ARRAY_SIZE(slave_ratios);
  364. break;
  365. case MODE_SLAVE_AUTO:
  366. ratios = slave_auto_ratios;
  367. nr_ratios = ARRAY_SIZE(slave_auto_ratios);
  368. break;
  369. }
  370. /* Figure out which MCLK/LRCK ratio to use */
  371. rate = params_rate(params); /* Sampling rate, in Hz */
  372. ratio = cs42l51->mclk / rate; /* MCLK/LRCK ratio */
  373. for (i = 0; i < nr_ratios; i++) {
  374. if (ratios[i].ratio == ratio)
  375. break;
  376. }
  377. if (i == nr_ratios) {
  378. /* We did not find a matching ratio */
  379. dev_err(component->dev, "could not find matching ratio\n");
  380. return -EINVAL;
  381. }
  382. intf_ctl = snd_soc_component_read(component, CS42L51_INTF_CTL);
  383. power_ctl = snd_soc_component_read(component, CS42L51_MIC_POWER_CTL);
  384. intf_ctl &= ~(CS42L51_INTF_CTL_MASTER | CS42L51_INTF_CTL_ADC_I2S
  385. | CS42L51_INTF_CTL_DAC_FORMAT(7));
  386. power_ctl &= ~(CS42L51_MIC_POWER_CTL_SPEED(3)
  387. | CS42L51_MIC_POWER_CTL_MCLK_DIV2);
  388. switch (cs42l51->func) {
  389. case MODE_MASTER:
  390. intf_ctl |= CS42L51_INTF_CTL_MASTER;
  391. mode = ratios[i].speed_mode;
  392. /* Force DSM mode if sampling rate is above 50kHz */
  393. if (rate > 50000)
  394. mode = CS42L51_DSM_MODE;
  395. power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(mode);
  396. /*
  397. * Auto detect mode is not applicable for master mode and has to
  398. * be disabled. Otherwise SPEED[1:0] bits will be ignored.
  399. */
  400. power_ctl &= ~CS42L51_MIC_POWER_CTL_AUTO;
  401. break;
  402. case MODE_SLAVE:
  403. power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(ratios[i].speed_mode);
  404. break;
  405. case MODE_SLAVE_AUTO:
  406. power_ctl |= CS42L51_MIC_POWER_CTL_AUTO;
  407. break;
  408. }
  409. switch (cs42l51->audio_mode) {
  410. case SND_SOC_DAIFMT_I2S:
  411. intf_ctl |= CS42L51_INTF_CTL_ADC_I2S;
  412. intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_I2S);
  413. break;
  414. case SND_SOC_DAIFMT_LEFT_J:
  415. intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_LJ24);
  416. break;
  417. case SND_SOC_DAIFMT_RIGHT_J:
  418. switch (params_width(params)) {
  419. case 16:
  420. fmt = CS42L51_DAC_DIF_RJ16;
  421. break;
  422. case 18:
  423. fmt = CS42L51_DAC_DIF_RJ18;
  424. break;
  425. case 20:
  426. fmt = CS42L51_DAC_DIF_RJ20;
  427. break;
  428. case 24:
  429. fmt = CS42L51_DAC_DIF_RJ24;
  430. break;
  431. default:
  432. dev_err(component->dev, "unknown format\n");
  433. return -EINVAL;
  434. }
  435. intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(fmt);
  436. break;
  437. default:
  438. dev_err(component->dev, "unknown format\n");
  439. return -EINVAL;
  440. }
  441. if (ratios[i].mclk)
  442. power_ctl |= CS42L51_MIC_POWER_CTL_MCLK_DIV2;
  443. ret = snd_soc_component_write(component, CS42L51_INTF_CTL, intf_ctl);
  444. if (ret < 0)
  445. return ret;
  446. ret = snd_soc_component_write(component, CS42L51_MIC_POWER_CTL, power_ctl);
  447. if (ret < 0)
  448. return ret;
  449. return 0;
  450. }
  451. static int cs42l51_dai_mute(struct snd_soc_dai *dai, int mute, int direction)
  452. {
  453. struct snd_soc_component *component = dai->component;
  454. int reg;
  455. int mask = CS42L51_DAC_OUT_CTL_DACA_MUTE|CS42L51_DAC_OUT_CTL_DACB_MUTE;
  456. reg = snd_soc_component_read(component, CS42L51_DAC_OUT_CTL);
  457. if (mute)
  458. reg |= mask;
  459. else
  460. reg &= ~mask;
  461. return snd_soc_component_write(component, CS42L51_DAC_OUT_CTL, reg);
  462. }
  463. static int cs42l51_of_xlate_dai_id(struct snd_soc_component *component,
  464. struct device_node *endpoint)
  465. {
  466. /* return dai id 0, whatever the endpoint index */
  467. return 0;
  468. }
  469. static const struct snd_soc_dai_ops cs42l51_dai_ops = {
  470. .hw_params = cs42l51_hw_params,
  471. .set_sysclk = cs42l51_set_dai_sysclk,
  472. .set_fmt = cs42l51_set_dai_fmt,
  473. .mute_stream = cs42l51_dai_mute,
  474. .no_capture_mute = 1,
  475. };
  476. static struct snd_soc_dai_driver cs42l51_dai = {
  477. .name = "cs42l51-hifi",
  478. .playback = {
  479. .stream_name = "Playback",
  480. .channels_min = 1,
  481. .channels_max = 2,
  482. .rates = SNDRV_PCM_RATE_8000_96000,
  483. .formats = CS42L51_FORMATS,
  484. },
  485. .capture = {
  486. .stream_name = "Capture",
  487. .channels_min = 1,
  488. .channels_max = 2,
  489. .rates = SNDRV_PCM_RATE_8000_96000,
  490. .formats = CS42L51_FORMATS,
  491. },
  492. .ops = &cs42l51_dai_ops,
  493. };
  494. static int cs42l51_component_probe(struct snd_soc_component *component)
  495. {
  496. int ret, reg;
  497. struct snd_soc_dapm_context *dapm;
  498. struct cs42l51_private *cs42l51;
  499. cs42l51 = snd_soc_component_get_drvdata(component);
  500. dapm = snd_soc_component_get_dapm(component);
  501. if (cs42l51->mclk_handle)
  502. snd_soc_dapm_new_controls(dapm, cs42l51_dapm_mclk_widgets, 1);
  503. /*
  504. * DAC configuration
  505. * - Use signal processor
  506. * - auto mute
  507. * - vol changes immediate
  508. * - no de-emphasize
  509. */
  510. reg = CS42L51_DAC_CTL_DATA_SEL(1)
  511. | CS42L51_DAC_CTL_AMUTE | CS42L51_DAC_CTL_DACSZ(0);
  512. ret = snd_soc_component_write(component, CS42L51_DAC_CTL, reg);
  513. if (ret < 0)
  514. return ret;
  515. return 0;
  516. }
  517. static const struct snd_soc_component_driver soc_component_device_cs42l51 = {
  518. .probe = cs42l51_component_probe,
  519. .controls = cs42l51_snd_controls,
  520. .num_controls = ARRAY_SIZE(cs42l51_snd_controls),
  521. .dapm_widgets = cs42l51_dapm_widgets,
  522. .num_dapm_widgets = ARRAY_SIZE(cs42l51_dapm_widgets),
  523. .dapm_routes = cs42l51_routes,
  524. .num_dapm_routes = ARRAY_SIZE(cs42l51_routes),
  525. .of_xlate_dai_id = cs42l51_of_xlate_dai_id,
  526. .idle_bias_on = 1,
  527. .use_pmdown_time = 1,
  528. .endianness = 1,
  529. .non_legacy_dai_naming = 1,
  530. };
  531. static bool cs42l51_writeable_reg(struct device *dev, unsigned int reg)
  532. {
  533. switch (reg) {
  534. case CS42L51_POWER_CTL1:
  535. case CS42L51_MIC_POWER_CTL:
  536. case CS42L51_INTF_CTL:
  537. case CS42L51_MIC_CTL:
  538. case CS42L51_ADC_CTL:
  539. case CS42L51_ADC_INPUT:
  540. case CS42L51_DAC_OUT_CTL:
  541. case CS42L51_DAC_CTL:
  542. case CS42L51_ALC_PGA_CTL:
  543. case CS42L51_ALC_PGB_CTL:
  544. case CS42L51_ADCA_ATT:
  545. case CS42L51_ADCB_ATT:
  546. case CS42L51_ADCA_VOL:
  547. case CS42L51_ADCB_VOL:
  548. case CS42L51_PCMA_VOL:
  549. case CS42L51_PCMB_VOL:
  550. case CS42L51_BEEP_FREQ:
  551. case CS42L51_BEEP_VOL:
  552. case CS42L51_BEEP_CONF:
  553. case CS42L51_TONE_CTL:
  554. case CS42L51_AOUTA_VOL:
  555. case CS42L51_AOUTB_VOL:
  556. case CS42L51_PCM_MIXER:
  557. case CS42L51_LIMIT_THRES_DIS:
  558. case CS42L51_LIMIT_REL:
  559. case CS42L51_LIMIT_ATT:
  560. case CS42L51_ALC_EN:
  561. case CS42L51_ALC_REL:
  562. case CS42L51_ALC_THRES:
  563. case CS42L51_NOISE_CONF:
  564. case CS42L51_CHARGE_FREQ:
  565. return true;
  566. default:
  567. return false;
  568. }
  569. }
  570. static bool cs42l51_volatile_reg(struct device *dev, unsigned int reg)
  571. {
  572. switch (reg) {
  573. case CS42L51_STATUS:
  574. return true;
  575. default:
  576. return false;
  577. }
  578. }
  579. static bool cs42l51_readable_reg(struct device *dev, unsigned int reg)
  580. {
  581. switch (reg) {
  582. case CS42L51_CHIP_REV_ID:
  583. case CS42L51_POWER_CTL1:
  584. case CS42L51_MIC_POWER_CTL:
  585. case CS42L51_INTF_CTL:
  586. case CS42L51_MIC_CTL:
  587. case CS42L51_ADC_CTL:
  588. case CS42L51_ADC_INPUT:
  589. case CS42L51_DAC_OUT_CTL:
  590. case CS42L51_DAC_CTL:
  591. case CS42L51_ALC_PGA_CTL:
  592. case CS42L51_ALC_PGB_CTL:
  593. case CS42L51_ADCA_ATT:
  594. case CS42L51_ADCB_ATT:
  595. case CS42L51_ADCA_VOL:
  596. case CS42L51_ADCB_VOL:
  597. case CS42L51_PCMA_VOL:
  598. case CS42L51_PCMB_VOL:
  599. case CS42L51_BEEP_FREQ:
  600. case CS42L51_BEEP_VOL:
  601. case CS42L51_BEEP_CONF:
  602. case CS42L51_TONE_CTL:
  603. case CS42L51_AOUTA_VOL:
  604. case CS42L51_AOUTB_VOL:
  605. case CS42L51_PCM_MIXER:
  606. case CS42L51_LIMIT_THRES_DIS:
  607. case CS42L51_LIMIT_REL:
  608. case CS42L51_LIMIT_ATT:
  609. case CS42L51_ALC_EN:
  610. case CS42L51_ALC_REL:
  611. case CS42L51_ALC_THRES:
  612. case CS42L51_NOISE_CONF:
  613. case CS42L51_STATUS:
  614. case CS42L51_CHARGE_FREQ:
  615. return true;
  616. default:
  617. return false;
  618. }
  619. }
  620. const struct regmap_config cs42l51_regmap = {
  621. .reg_bits = 8,
  622. .reg_stride = 1,
  623. .val_bits = 8,
  624. .use_single_write = true,
  625. .readable_reg = cs42l51_readable_reg,
  626. .volatile_reg = cs42l51_volatile_reg,
  627. .writeable_reg = cs42l51_writeable_reg,
  628. .max_register = CS42L51_CHARGE_FREQ,
  629. .cache_type = REGCACHE_RBTREE,
  630. };
  631. EXPORT_SYMBOL_GPL(cs42l51_regmap);
  632. int cs42l51_probe(struct device *dev, struct regmap *regmap)
  633. {
  634. struct cs42l51_private *cs42l51;
  635. unsigned int val;
  636. int ret, i;
  637. if (IS_ERR(regmap))
  638. return PTR_ERR(regmap);
  639. cs42l51 = devm_kzalloc(dev, sizeof(struct cs42l51_private),
  640. GFP_KERNEL);
  641. if (!cs42l51)
  642. return -ENOMEM;
  643. dev_set_drvdata(dev, cs42l51);
  644. cs42l51->regmap = regmap;
  645. cs42l51->mclk_handle = devm_clk_get(dev, "MCLK");
  646. if (IS_ERR(cs42l51->mclk_handle)) {
  647. if (PTR_ERR(cs42l51->mclk_handle) != -ENOENT)
  648. return PTR_ERR(cs42l51->mclk_handle);
  649. cs42l51->mclk_handle = NULL;
  650. }
  651. for (i = 0; i < ARRAY_SIZE(cs42l51->supplies); i++)
  652. cs42l51->supplies[i].supply = cs42l51_supply_names[i];
  653. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs42l51->supplies),
  654. cs42l51->supplies);
  655. if (ret != 0) {
  656. dev_err(dev, "Failed to request supplies: %d\n", ret);
  657. return ret;
  658. }
  659. ret = regulator_bulk_enable(ARRAY_SIZE(cs42l51->supplies),
  660. cs42l51->supplies);
  661. if (ret != 0) {
  662. dev_err(dev, "Failed to enable supplies: %d\n", ret);
  663. return ret;
  664. }
  665. cs42l51->reset_gpio = devm_gpiod_get_optional(dev, "reset",
  666. GPIOD_OUT_LOW);
  667. if (IS_ERR(cs42l51->reset_gpio))
  668. return PTR_ERR(cs42l51->reset_gpio);
  669. if (cs42l51->reset_gpio) {
  670. dev_dbg(dev, "Release reset gpio\n");
  671. gpiod_set_value_cansleep(cs42l51->reset_gpio, 0);
  672. mdelay(2);
  673. }
  674. /* Verify that we have a CS42L51 */
  675. ret = regmap_read(regmap, CS42L51_CHIP_REV_ID, &val);
  676. if (ret < 0) {
  677. dev_err(dev, "failed to read I2C\n");
  678. goto error;
  679. }
  680. if ((val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) &&
  681. (val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) {
  682. dev_err(dev, "Invalid chip id: %x\n", val);
  683. ret = -ENODEV;
  684. goto error;
  685. }
  686. dev_info(dev, "Cirrus Logic CS42L51, Revision: %02X\n",
  687. val & CS42L51_CHIP_REV_MASK);
  688. ret = devm_snd_soc_register_component(dev,
  689. &soc_component_device_cs42l51, &cs42l51_dai, 1);
  690. if (ret < 0)
  691. goto error;
  692. return 0;
  693. error:
  694. regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
  695. cs42l51->supplies);
  696. return ret;
  697. }
  698. EXPORT_SYMBOL_GPL(cs42l51_probe);
  699. int cs42l51_remove(struct device *dev)
  700. {
  701. struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
  702. gpiod_set_value_cansleep(cs42l51->reset_gpio, 1);
  703. return regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
  704. cs42l51->supplies);
  705. }
  706. EXPORT_SYMBOL_GPL(cs42l51_remove);
  707. int __maybe_unused cs42l51_suspend(struct device *dev)
  708. {
  709. struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
  710. regcache_cache_only(cs42l51->regmap, true);
  711. regcache_mark_dirty(cs42l51->regmap);
  712. return 0;
  713. }
  714. EXPORT_SYMBOL_GPL(cs42l51_suspend);
  715. int __maybe_unused cs42l51_resume(struct device *dev)
  716. {
  717. struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
  718. regcache_cache_only(cs42l51->regmap, false);
  719. return regcache_sync(cs42l51->regmap);
  720. }
  721. EXPORT_SYMBOL_GPL(cs42l51_resume);
  722. const struct of_device_id cs42l51_of_match[] = {
  723. { .compatible = "cirrus,cs42l51", },
  724. { }
  725. };
  726. MODULE_DEVICE_TABLE(of, cs42l51_of_match);
  727. EXPORT_SYMBOL_GPL(cs42l51_of_match);
  728. MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
  729. MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver");
  730. MODULE_LICENSE("GPL");