cs42l42.h 31 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * cs42l42.h -- CS42L42 ALSA SoC audio driver header
  4. *
  5. * Copyright 2016 Cirrus Logic, Inc.
  6. *
  7. * Author: James Schulman <james.schulman@cirrus.com>
  8. * Author: Brian Austin <brian.austin@cirrus.com>
  9. * Author: Michael White <michael.white@cirrus.com>
  10. */
  11. #ifndef __CS42L42_H__
  12. #define __CS42L42_H__
  13. #define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */
  14. #define CS42L42_WIN_START 0x00
  15. #define CS42L42_WIN_LEN 0x100
  16. #define CS42L42_RANGE_MIN 0x00
  17. #define CS42L42_RANGE_MAX 0x7F
  18. #define CS42L42_PAGE_10 0x1000
  19. #define CS42L42_PAGE_11 0x1100
  20. #define CS42L42_PAGE_12 0x1200
  21. #define CS42L42_PAGE_13 0x1300
  22. #define CS42L42_PAGE_15 0x1500
  23. #define CS42L42_PAGE_19 0x1900
  24. #define CS42L42_PAGE_1B 0x1B00
  25. #define CS42L42_PAGE_1C 0x1C00
  26. #define CS42L42_PAGE_1D 0x1D00
  27. #define CS42L42_PAGE_1F 0x1F00
  28. #define CS42L42_PAGE_20 0x2000
  29. #define CS42L42_PAGE_21 0x2100
  30. #define CS42L42_PAGE_23 0x2300
  31. #define CS42L42_PAGE_24 0x2400
  32. #define CS42L42_PAGE_25 0x2500
  33. #define CS42L42_PAGE_26 0x2600
  34. #define CS42L42_PAGE_28 0x2800
  35. #define CS42L42_PAGE_29 0x2900
  36. #define CS42L42_PAGE_2A 0x2A00
  37. #define CS42L42_PAGE_30 0x3000
  38. #define CS42L42_CHIP_ID 0x42A42
  39. /* Page 0x10 Global Registers */
  40. #define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01)
  41. #define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02)
  42. #define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03)
  43. #define CS42L42_FABID (CS42L42_PAGE_10 + 0x04)
  44. #define CS42L42_REVID (CS42L42_PAGE_10 + 0x05)
  45. #define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06)
  46. #define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07)
  47. #define CS42L42_SRC_BYPASS_DAC_SHIFT 1
  48. #define CS42L42_SRC_BYPASS_DAC_MASK (1 << CS42L42_SRC_BYPASS_DAC_SHIFT)
  49. #define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08)
  50. #define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09)
  51. #define CS42L42_INTERNAL_FS_SHIFT 1
  52. #define CS42L42_INTERNAL_FS_MASK (1 << CS42L42_INTERNAL_FS_SHIFT)
  53. #define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A)
  54. #define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E)
  55. #define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F)
  56. #define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10)
  57. /* Page 0x11 Power and Headset Detect Registers */
  58. #define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01)
  59. #define CS42L42_ASP_DAO_PDN_SHIFT 7
  60. #define CS42L42_ASP_DAO_PDN_MASK (1 << CS42L42_ASP_DAO_PDN_SHIFT)
  61. #define CS42L42_ASP_DAI_PDN_SHIFT 6
  62. #define CS42L42_ASP_DAI_PDN_MASK (1 << CS42L42_ASP_DAI_PDN_SHIFT)
  63. #define CS42L42_MIXER_PDN_SHIFT 5
  64. #define CS42L42_MIXER_PDN_MASK (1 << CS42L42_MIXER_PDN_SHIFT)
  65. #define CS42L42_EQ_PDN_SHIFT 4
  66. #define CS42L42_EQ_PDN_MASK (1 << CS42L42_EQ_PDN_SHIFT)
  67. #define CS42L42_HP_PDN_SHIFT 3
  68. #define CS42L42_HP_PDN_MASK (1 << CS42L42_HP_PDN_SHIFT)
  69. #define CS42L42_ADC_PDN_SHIFT 2
  70. #define CS42L42_ADC_PDN_MASK (1 << CS42L42_ADC_PDN_SHIFT)
  71. #define CS42L42_PDN_ALL_SHIFT 0
  72. #define CS42L42_PDN_ALL_MASK (1 << CS42L42_PDN_ALL_SHIFT)
  73. #define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02)
  74. #define CS42L42_ADC_SRC_PDNB_SHIFT 0
  75. #define CS42L42_ADC_SRC_PDNB_MASK (1 << CS42L42_ADC_SRC_PDNB_SHIFT)
  76. #define CS42L42_DAC_SRC_PDNB_SHIFT 1
  77. #define CS42L42_DAC_SRC_PDNB_MASK (1 << CS42L42_DAC_SRC_PDNB_SHIFT)
  78. #define CS42L42_ASP_DAI1_PDN_SHIFT 2
  79. #define CS42L42_ASP_DAI1_PDN_MASK (1 << CS42L42_ASP_DAI1_PDN_SHIFT)
  80. #define CS42L42_SRC_PDN_OVERRIDE_SHIFT 3
  81. #define CS42L42_SRC_PDN_OVERRIDE_MASK (1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT)
  82. #define CS42L42_DISCHARGE_FILT_SHIFT 4
  83. #define CS42L42_DISCHARGE_FILT_MASK (1 << CS42L42_DISCHARGE_FILT_SHIFT)
  84. #define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03)
  85. #define CS42L42_RING_SENSE_PDNB_SHIFT 1
  86. #define CS42L42_RING_SENSE_PDNB_MASK (1 << \
  87. CS42L42_RING_SENSE_PDNB_SHIFT)
  88. #define CS42L42_VPMON_PDNB_SHIFT 2
  89. #define CS42L42_VPMON_PDNB_MASK (1 << \
  90. CS42L42_VPMON_PDNB_SHIFT)
  91. #define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT 5
  92. #define CS42L42_SW_CLK_STP_STAT_SEL_MASK (3 << \
  93. CS42L42_SW_CLK_STP_STAT_SEL_SHIFT)
  94. #define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04)
  95. #define CS42L42_RS_TRIM_R_SHIFT 0
  96. #define CS42L42_RS_TRIM_R_MASK (1 << \
  97. CS42L42_RS_TRIM_R_SHIFT)
  98. #define CS42L42_RS_TRIM_T_SHIFT 1
  99. #define CS42L42_RS_TRIM_T_MASK (1 << \
  100. CS42L42_RS_TRIM_T_SHIFT)
  101. #define CS42L42_HPREF_RS_SHIFT 2
  102. #define CS42L42_HPREF_RS_MASK (1 << \
  103. CS42L42_HPREF_RS_SHIFT)
  104. #define CS42L42_HSBIAS_FILT_REF_RS_SHIFT 3
  105. #define CS42L42_HSBIAS_FILT_REF_RS_MASK (1 << \
  106. CS42L42_HSBIAS_FILT_REF_RS_SHIFT)
  107. #define CS42L42_RING_SENSE_PU_HIZ_SHIFT 6
  108. #define CS42L42_RING_SENSE_PU_HIZ_MASK (1 << \
  109. CS42L42_RING_SENSE_PU_HIZ_SHIFT)
  110. #define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05)
  111. #define CS42L42_TS_RS_GATE_SHIFT 7
  112. #define CS42L42_TS_RS_GATE_MAS (1 << CS42L42_TS_RS_GATE_SHIFT)
  113. #define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07)
  114. #define CS42L42_SCLK_PRESENT_SHIFT 0
  115. #define CS42L42_SCLK_PRESENT_MASK (1 << CS42L42_SCLK_PRESENT_SHIFT)
  116. #define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09)
  117. #define CS42L42_OSC_SW_SEL_STAT_SHIFT 0
  118. #define CS42L42_OSC_SW_SEL_STAT_MASK (3 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
  119. #define CS42L42_OSC_PDNB_STAT_SHIFT 2
  120. #define CS42L42_OSC_PDNB_STAT_MASK (1 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
  121. #define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12)
  122. #define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0
  123. #define CS42L42_RS_RISE_DBNCE_TIME_MASK (7 << \
  124. CS42L42_RS_RISE_DBNCE_TIME_SHIFT)
  125. #define CS42L42_RS_FALL_DBNCE_TIME_SHIFT 3
  126. #define CS42L42_RS_FALL_DBNCE_TIME_MASK (7 << \
  127. CS42L42_RS_FALL_DBNCE_TIME_SHIFT)
  128. #define CS42L42_RS_PU_EN_SHIFT 6
  129. #define CS42L42_RS_PU_EN_MASK (1 << \
  130. CS42L42_RS_PU_EN_SHIFT)
  131. #define CS42L42_RS_INV_SHIFT 7
  132. #define CS42L42_RS_INV_MASK (1 << \
  133. CS42L42_RS_INV_SHIFT)
  134. #define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13)
  135. #define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0
  136. #define CS42L42_TS_RISE_DBNCE_TIME_MASK (7 << \
  137. CS42L42_TS_RISE_DBNCE_TIME_SHIFT)
  138. #define CS42L42_TS_FALL_DBNCE_TIME_SHIFT 3
  139. #define CS42L42_TS_FALL_DBNCE_TIME_MASK (7 << \
  140. CS42L42_TS_FALL_DBNCE_TIME_SHIFT)
  141. #define CS42L42_TS_INV_SHIFT 7
  142. #define CS42L42_TS_INV_MASK (1 << \
  143. CS42L42_TS_INV_SHIFT)
  144. #define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14)
  145. #define CS42L42_D_RS_PLUG_DBNC_SHIFT 0
  146. #define CS42L42_D_RS_PLUG_DBNC_MASK (1 << CS42L42_D_RS_PLUG_DBNC_SHIFT)
  147. #define CS42L42_D_RS_UNPLUG_DBNC_SHIFT 1
  148. #define CS42L42_D_RS_UNPLUG_DBNC_MASK (1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT)
  149. #define CS42L42_D_TS_PLUG_DBNC_SHIFT 2
  150. #define CS42L42_D_TS_PLUG_DBNC_MASK (1 << CS42L42_D_TS_PLUG_DBNC_SHIFT)
  151. #define CS42L42_D_TS_UNPLUG_DBNC_SHIFT 3
  152. #define CS42L42_D_TS_UNPLUG_DBNC_MASK (1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT)
  153. #define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15)
  154. #define CS42L42_RS_PLUG_DBNC_SHIFT 0
  155. #define CS42L42_RS_PLUG_DBNC_MASK (1 << CS42L42_RS_PLUG_DBNC_SHIFT)
  156. #define CS42L42_RS_UNPLUG_DBNC_SHIFT 1
  157. #define CS42L42_RS_UNPLUG_DBNC_MASK (1 << CS42L42_RS_UNPLUG_DBNC_SHIFT)
  158. #define CS42L42_TS_PLUG_DBNC_SHIFT 2
  159. #define CS42L42_TS_PLUG_DBNC_MASK (1 << CS42L42_TS_PLUG_DBNC_SHIFT)
  160. #define CS42L42_TS_UNPLUG_DBNC_SHIFT 3
  161. #define CS42L42_TS_UNPLUG_DBNC_MASK (1 << CS42L42_TS_UNPLUG_DBNC_SHIFT)
  162. #define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F)
  163. #define CS42L42_HSDET_COMP1_LVL_SHIFT 0
  164. #define CS42L42_HSDET_COMP1_LVL_MASK (15 << CS42L42_HSDET_COMP1_LVL_SHIFT)
  165. #define CS42L42_HSDET_COMP2_LVL_SHIFT 4
  166. #define CS42L42_HSDET_COMP2_LVL_MASK (15 << CS42L42_HSDET_COMP2_LVL_SHIFT)
  167. #define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20)
  168. #define CS42L42_HSDET_AUTO_TIME_SHIFT 0
  169. #define CS42L42_HSDET_AUTO_TIME_MASK (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)
  170. #define CS42L42_HSBIAS_REF_SHIFT 3
  171. #define CS42L42_HSBIAS_REF_MASK (1 << CS42L42_HSBIAS_REF_SHIFT)
  172. #define CS42L42_HSDET_SET_SHIFT 4
  173. #define CS42L42_HSDET_SET_MASK (3 << CS42L42_HSDET_SET_SHIFT)
  174. #define CS42L42_HSDET_CTRL_SHIFT 6
  175. #define CS42L42_HSDET_CTRL_MASK (3 << CS42L42_HSDET_CTRL_SHIFT)
  176. #define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21)
  177. #define CS42L42_SW_GNDHS_HS4_SHIFT 0
  178. #define CS42L42_SW_GNDHS_HS4_MASK (1 << CS42L42_SW_GNDHS_HS4_SHIFT)
  179. #define CS42L42_SW_GNDHS_HS3_SHIFT 1
  180. #define CS42L42_SW_GNDHS_HS3_MASK (1 << CS42L42_SW_GNDHS_HS3_SHIFT)
  181. #define CS42L42_SW_HSB_HS4_SHIFT 2
  182. #define CS42L42_SW_HSB_HS4_MASK (1 << CS42L42_SW_HSB_HS4_SHIFT)
  183. #define CS42L42_SW_HSB_HS3_SHIFT 3
  184. #define CS42L42_SW_HSB_HS3_MASK (1 << CS42L42_SW_HSB_HS3_SHIFT)
  185. #define CS42L42_SW_HSB_FILT_HS4_SHIFT 4
  186. #define CS42L42_SW_HSB_FILT_HS4_MASK (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT)
  187. #define CS42L42_SW_HSB_FILT_HS3_SHIFT 5
  188. #define CS42L42_SW_HSB_FILT_HS3_MASK (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT)
  189. #define CS42L42_SW_REF_HS4_SHIFT 6
  190. #define CS42L42_SW_REF_HS4_MASK (1 << CS42L42_SW_REF_HS4_SHIFT)
  191. #define CS42L42_SW_REF_HS3_SHIFT 7
  192. #define CS42L42_SW_REF_HS3_MASK (1 << CS42L42_SW_REF_HS3_SHIFT)
  193. #define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24)
  194. #define CS42L42_HSDET_TYPE_SHIFT 0
  195. #define CS42L42_HSDET_TYPE_MASK (3 << CS42L42_HSDET_TYPE_SHIFT)
  196. #define CS42L42_HSDET_COMP1_OUT_SHIFT 6
  197. #define CS42L42_HSDET_COMP1_OUT_MASK (1 << CS42L42_HSDET_COMP1_OUT_SHIFT)
  198. #define CS42L42_HSDET_COMP2_OUT_SHIFT 7
  199. #define CS42L42_HSDET_COMP2_OUT_MASK (1 << CS42L42_HSDET_COMP2_OUT_SHIFT)
  200. #define CS42L42_PLUG_CTIA 0
  201. #define CS42L42_PLUG_OMTP 1
  202. #define CS42L42_PLUG_HEADPHONE 2
  203. #define CS42L42_PLUG_INVALID 3
  204. #define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29)
  205. #define CS42L42_HS_CLAMP_DISABLE_SHIFT 0
  206. #define CS42L42_HS_CLAMP_DISABLE_MASK (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)
  207. /* Page 0x12 Clocking Registers */
  208. #define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01)
  209. #define CS42L42_MCLKDIV_SHIFT 1
  210. #define CS42L42_MCLKDIV_MASK (1 << CS42L42_MCLKDIV_SHIFT)
  211. #define CS42L42_MCLK_SRC_SEL_SHIFT 0
  212. #define CS42L42_MCLK_SRC_SEL_MASK (1 << CS42L42_MCLK_SRC_SEL_SHIFT)
  213. #define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02)
  214. #define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03)
  215. #define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04)
  216. #define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0
  217. #define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \
  218. CS42L42_FSYNC_PULSE_WIDTH_SHIFT)
  219. #define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05)
  220. #define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06)
  221. #define CS42L42_FSYNC_PERIOD_SHIFT 0
  222. #define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT)
  223. #define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07)
  224. #define CS42L42_ASP_SCLK_EN_SHIFT 5
  225. #define CS42L42_ASP_SCLK_EN_MASK (1 << CS42L42_ASP_SCLK_EN_SHIFT)
  226. #define CS42L42_ASP_MASTER_MODE 0x01
  227. #define CS42L42_ASP_SLAVE_MODE 0x00
  228. #define CS42L42_ASP_MODE_SHIFT 4
  229. #define CS42L42_ASP_MODE_MASK (1 << CS42L42_ASP_MODE_SHIFT)
  230. #define CS42L42_ASP_SCPOL_SHIFT 2
  231. #define CS42L42_ASP_SCPOL_MASK (3 << CS42L42_ASP_SCPOL_SHIFT)
  232. #define CS42L42_ASP_SCPOL_NOR 3
  233. #define CS42L42_ASP_LCPOL_SHIFT 0
  234. #define CS42L42_ASP_LCPOL_MASK (3 << CS42L42_ASP_LCPOL_SHIFT)
  235. #define CS42L42_ASP_LCPOL_INV 3
  236. #define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08)
  237. #define CS42L42_ASP_STP_SHIFT 4
  238. #define CS42L42_ASP_STP_MASK (1 << CS42L42_ASP_STP_SHIFT)
  239. #define CS42L42_ASP_5050_SHIFT 3
  240. #define CS42L42_ASP_5050_MASK (1 << CS42L42_ASP_5050_SHIFT)
  241. #define CS42L42_ASP_FSD_SHIFT 0
  242. #define CS42L42_ASP_FSD_MASK (7 << CS42L42_ASP_FSD_SHIFT)
  243. #define CS42L42_ASP_FSD_0_5 1
  244. #define CS42L42_ASP_FSD_1_0 2
  245. #define CS42L42_ASP_FSD_1_5 3
  246. #define CS42L42_ASP_FSD_2_0 4
  247. #define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09)
  248. #define CS42L42_FS_EN_SHIFT 0
  249. #define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT)
  250. #define CS42L42_FS_EN_IASRC_96K 0x1
  251. #define CS42L42_FS_EN_OASRC_96K 0x2
  252. #define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A)
  253. #define CS42L42_CLK_IASRC_SEL_SHIFT 0
  254. #define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT)
  255. #define CS42L42_CLK_IASRC_SEL_12 1
  256. #define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B)
  257. #define CS42L42_CLK_OASRC_SEL_SHIFT 0
  258. #define CS42L42_CLK_OASRC_SEL_MASK (1 << CS42L42_CLK_OASRC_SEL_SHIFT)
  259. #define CS42L42_CLK_OASRC_SEL_12 1
  260. #define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C)
  261. #define CS42L42_SCLK_PREDIV_SHIFT 0
  262. #define CS42L42_SCLK_PREDIV_MASK (3 << CS42L42_SCLK_PREDIV_SHIFT)
  263. /* Page 0x13 Interrupt Registers */
  264. /* Interrupts */
  265. #define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01)
  266. #define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02)
  267. #define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03)
  268. #define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04)
  269. #define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05)
  270. #define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08)
  271. #define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09)
  272. #define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A)
  273. #define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B)
  274. #define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D)
  275. #define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E)
  276. #define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F)
  277. /* Masks */
  278. #define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16)
  279. #define CS42L42_ADC_OVFL_SHIFT 0
  280. #define CS42L42_ADC_OVFL_MASK (1 << CS42L42_ADC_OVFL_SHIFT)
  281. #define CS42L42_ADC_OVFL_VAL_MASK CS42L42_ADC_OVFL_MASK
  282. #define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17)
  283. #define CS42L42_MIX_CHB_OVFL_SHIFT 0
  284. #define CS42L42_MIX_CHB_OVFL_MASK (1 << CS42L42_MIX_CHB_OVFL_SHIFT)
  285. #define CS42L42_MIX_CHA_OVFL_SHIFT 1
  286. #define CS42L42_MIX_CHA_OVFL_MASK (1 << CS42L42_MIX_CHA_OVFL_SHIFT)
  287. #define CS42L42_EQ_OVFL_SHIFT 2
  288. #define CS42L42_EQ_OVFL_MASK (1 << CS42L42_EQ_OVFL_SHIFT)
  289. #define CS42L42_EQ_BIQUAD_OVFL_SHIFT 3
  290. #define CS42L42_EQ_BIQUAD_OVFL_MASK (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)
  291. #define CS42L42_MIXER_VAL_MASK (CS42L42_MIX_CHB_OVFL_MASK | \
  292. CS42L42_MIX_CHA_OVFL_MASK | \
  293. CS42L42_EQ_OVFL_MASK | \
  294. CS42L42_EQ_BIQUAD_OVFL_MASK)
  295. #define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18)
  296. #define CS42L42_SRC_ILK_SHIFT 0
  297. #define CS42L42_SRC_ILK_MASK (1 << CS42L42_SRC_ILK_SHIFT)
  298. #define CS42L42_SRC_OLK_SHIFT 1
  299. #define CS42L42_SRC_OLK_MASK (1 << CS42L42_SRC_OLK_SHIFT)
  300. #define CS42L42_SRC_IUNLK_SHIFT 2
  301. #define CS42L42_SRC_IUNLK_MASK (1 << CS42L42_SRC_IUNLK_SHIFT)
  302. #define CS42L42_SRC_OUNLK_SHIFT 3
  303. #define CS42L42_SRC_OUNLK_MASK (1 << CS42L42_SRC_OUNLK_SHIFT)
  304. #define CS42L42_SRC_VAL_MASK (CS42L42_SRC_ILK_MASK | \
  305. CS42L42_SRC_OLK_MASK | \
  306. CS42L42_SRC_IUNLK_MASK | \
  307. CS42L42_SRC_OUNLK_MASK)
  308. #define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19)
  309. #define CS42L42_ASPRX_NOLRCK_SHIFT 0
  310. #define CS42L42_ASPRX_NOLRCK_MASK (1 << CS42L42_ASPRX_NOLRCK_SHIFT)
  311. #define CS42L42_ASPRX_EARLY_SHIFT 1
  312. #define CS42L42_ASPRX_EARLY_MASK (1 << CS42L42_ASPRX_EARLY_SHIFT)
  313. #define CS42L42_ASPRX_LATE_SHIFT 2
  314. #define CS42L42_ASPRX_LATE_MASK (1 << CS42L42_ASPRX_LATE_SHIFT)
  315. #define CS42L42_ASPRX_ERROR_SHIFT 3
  316. #define CS42L42_ASPRX_ERROR_MASK (1 << CS42L42_ASPRX_ERROR_SHIFT)
  317. #define CS42L42_ASPRX_OVLD_SHIFT 4
  318. #define CS42L42_ASPRX_OVLD_MASK (1 << CS42L42_ASPRX_OVLD_SHIFT)
  319. #define CS42L42_ASP_RX_VAL_MASK (CS42L42_ASPRX_NOLRCK_MASK | \
  320. CS42L42_ASPRX_EARLY_MASK | \
  321. CS42L42_ASPRX_LATE_MASK | \
  322. CS42L42_ASPRX_ERROR_MASK | \
  323. CS42L42_ASPRX_OVLD_MASK)
  324. #define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A)
  325. #define CS42L42_ASPTX_NOLRCK_SHIFT 0
  326. #define CS42L42_ASPTX_NOLRCK_MASK (1 << CS42L42_ASPTX_NOLRCK_SHIFT)
  327. #define CS42L42_ASPTX_EARLY_SHIFT 1
  328. #define CS42L42_ASPTX_EARLY_MASK (1 << CS42L42_ASPTX_EARLY_SHIFT)
  329. #define CS42L42_ASPTX_LATE_SHIFT 2
  330. #define CS42L42_ASPTX_LATE_MASK (1 << CS42L42_ASPTX_LATE_SHIFT)
  331. #define CS42L42_ASPTX_SMERROR_SHIFT 3
  332. #define CS42L42_ASPTX_SMERROR_MASK (1 << CS42L42_ASPTX_SMERROR_SHIFT)
  333. #define CS42L42_ASP_TX_VAL_MASK (CS42L42_ASPTX_NOLRCK_MASK | \
  334. CS42L42_ASPTX_EARLY_MASK | \
  335. CS42L42_ASPTX_LATE_MASK | \
  336. CS42L42_ASPTX_SMERROR_MASK)
  337. #define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B)
  338. #define CS42L42_PDN_DONE_SHIFT 0
  339. #define CS42L42_PDN_DONE_MASK (1 << CS42L42_PDN_DONE_SHIFT)
  340. #define CS42L42_HSDET_AUTO_DONE_SHIFT 1
  341. #define CS42L42_HSDET_AUTO_DONE_MASK (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)
  342. #define CS42L42_CODEC_VAL_MASK (CS42L42_PDN_DONE_MASK | \
  343. CS42L42_HSDET_AUTO_DONE_MASK)
  344. #define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C)
  345. #define CS42L42_SRCPL_ADC_LK_SHIFT 0
  346. #define CS42L42_SRCPL_ADC_LK_MASK (1 << CS42L42_SRCPL_ADC_LK_SHIFT)
  347. #define CS42L42_SRCPL_DAC_LK_SHIFT 2
  348. #define CS42L42_SRCPL_DAC_LK_MASK (1 << CS42L42_SRCPL_DAC_LK_SHIFT)
  349. #define CS42L42_SRCPL_ADC_UNLK_SHIFT 5
  350. #define CS42L42_SRCPL_ADC_UNLK_MASK (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT)
  351. #define CS42L42_SRCPL_DAC_UNLK_SHIFT 6
  352. #define CS42L42_SRCPL_DAC_UNLK_MASK (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)
  353. #define CS42L42_SRCPL_VAL_MASK (CS42L42_SRCPL_ADC_LK_MASK | \
  354. CS42L42_SRCPL_DAC_LK_MASK | \
  355. CS42L42_SRCPL_ADC_UNLK_MASK | \
  356. CS42L42_SRCPL_DAC_UNLK_MASK)
  357. #define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E)
  358. #define CS42L42_VPMON_SHIFT 0
  359. #define CS42L42_VPMON_MASK (1 << CS42L42_VPMON_SHIFT)
  360. #define CS42L42_VPMON_VAL_MASK CS42L42_VPMON_MASK
  361. #define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F)
  362. #define CS42L42_PLL_LOCK_SHIFT 0
  363. #define CS42L42_PLL_LOCK_MASK (1 << CS42L42_PLL_LOCK_SHIFT)
  364. #define CS42L42_PLL_LOCK_VAL_MASK CS42L42_PLL_LOCK_MASK
  365. #define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20)
  366. #define CS42L42_RS_PLUG_SHIFT 0
  367. #define CS42L42_RS_PLUG_MASK (1 << CS42L42_RS_PLUG_SHIFT)
  368. #define CS42L42_RS_UNPLUG_SHIFT 1
  369. #define CS42L42_RS_UNPLUG_MASK (1 << CS42L42_RS_UNPLUG_SHIFT)
  370. #define CS42L42_TS_PLUG_SHIFT 2
  371. #define CS42L42_TS_PLUG_MASK (1 << CS42L42_TS_PLUG_SHIFT)
  372. #define CS42L42_TS_UNPLUG_SHIFT 3
  373. #define CS42L42_TS_UNPLUG_MASK (1 << CS42L42_TS_UNPLUG_SHIFT)
  374. #define CS42L42_TSRS_PLUG_VAL_MASK (CS42L42_RS_PLUG_MASK | \
  375. CS42L42_RS_UNPLUG_MASK | \
  376. CS42L42_TS_PLUG_MASK | \
  377. CS42L42_TS_UNPLUG_MASK)
  378. #define CS42L42_TS_PLUG 3
  379. #define CS42L42_TS_UNPLUG 0
  380. #define CS42L42_TS_TRANS 1
  381. /* Page 0x15 Fractional-N PLL Registers */
  382. #define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01)
  383. #define CS42L42_PLL_START_SHIFT 0
  384. #define CS42L42_PLL_START_MASK (1 << CS42L42_PLL_START_SHIFT)
  385. #define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02)
  386. #define CS42L42_PLL_DIV_FRAC_SHIFT 0
  387. #define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT)
  388. #define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03)
  389. #define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04)
  390. #define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05)
  391. #define CS42L42_PLL_DIV_INT_SHIFT 0
  392. #define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT)
  393. #define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08)
  394. #define CS42L42_PLL_DIVOUT_SHIFT 0
  395. #define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT)
  396. #define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A)
  397. #define CS42L42_PLL_CAL_RATIO_SHIFT 0
  398. #define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT)
  399. #define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B)
  400. #define CS42L42_PLL_MODE_SHIFT 0
  401. #define CS42L42_PLL_MODE_MASK (3 << CS42L42_PLL_MODE_SHIFT)
  402. /* Page 0x19 HP Load Detect Registers */
  403. #define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25)
  404. #define CS42L42_RLA_STAT_SHIFT 0
  405. #define CS42L42_RLA_STAT_MASK (3 << CS42L42_RLA_STAT_SHIFT)
  406. #define CS42L42_RLA_STAT_15_OHM 0
  407. #define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26)
  408. #define CS42L42_HPLOAD_DET_DONE_SHIFT 0
  409. #define CS42L42_HPLOAD_DET_DONE_MASK (1 << CS42L42_HPLOAD_DET_DONE_SHIFT)
  410. #define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27)
  411. #define CS42L42_HP_LD_EN_SHIFT 0
  412. #define CS42L42_HP_LD_EN_MASK (1 << CS42L42_HP_LD_EN_SHIFT)
  413. /* Page 0x1B Headset Interface Registers */
  414. #define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70)
  415. #define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0
  416. #define CS42L42_HSBIAS_SENSE_TRIP_MASK (7 << \
  417. CS42L42_HSBIAS_SENSE_TRIP_SHIFT)
  418. #define CS42L42_TIP_SENSE_EN_SHIFT 5
  419. #define CS42L42_TIP_SENSE_EN_MASK (1 << \
  420. CS42L42_TIP_SENSE_EN_SHIFT)
  421. #define CS42L42_AUTO_HSBIAS_HIZ_SHIFT 6
  422. #define CS42L42_AUTO_HSBIAS_HIZ_MASK (1 << \
  423. CS42L42_AUTO_HSBIAS_HIZ_SHIFT)
  424. #define CS42L42_HSBIAS_SENSE_EN_SHIFT 7
  425. #define CS42L42_HSBIAS_SENSE_EN_MASK (1 << \
  426. CS42L42_HSBIAS_SENSE_EN_SHIFT)
  427. #define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71)
  428. #define CS42L42_WAKEB_CLEAR_SHIFT 0
  429. #define CS42L42_WAKEB_CLEAR_MASK (1 << CS42L42_WAKEB_CLEAR_SHIFT)
  430. #define CS42L42_WAKEB_MODE_SHIFT 5
  431. #define CS42L42_WAKEB_MODE_MASK (1 << CS42L42_WAKEB_MODE_SHIFT)
  432. #define CS42L42_M_HP_WAKE_SHIFT 6
  433. #define CS42L42_M_HP_WAKE_MASK (1 << CS42L42_M_HP_WAKE_SHIFT)
  434. #define CS42L42_M_MIC_WAKE_SHIFT 7
  435. #define CS42L42_M_MIC_WAKE_MASK (1 << CS42L42_M_MIC_WAKE_SHIFT)
  436. #define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72)
  437. #define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT 7
  438. #define CS42L42_ADC_DISABLE_S0_MUTE_MASK (1 << \
  439. CS42L42_ADC_DISABLE_S0_MUTE_SHIFT)
  440. #define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73)
  441. #define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0
  442. #define CS42L42_TIP_SENSE_DEBOUNCE_MASK (3 << \
  443. CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)
  444. #define CS42L42_TIP_SENSE_INV_SHIFT 5
  445. #define CS42L42_TIP_SENSE_INV_MASK (1 << \
  446. CS42L42_TIP_SENSE_INV_SHIFT)
  447. #define CS42L42_TIP_SENSE_CTRL_SHIFT 6
  448. #define CS42L42_TIP_SENSE_CTRL_MASK (3 << \
  449. CS42L42_TIP_SENSE_CTRL_SHIFT)
  450. #define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74)
  451. #define CS42L42_PDN_MIC_LVL_DET_SHIFT 0
  452. #define CS42L42_PDN_MIC_LVL_DET_MASK (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)
  453. #define CS42L42_HSBIAS_CTL_SHIFT 1
  454. #define CS42L42_HSBIAS_CTL_MASK (3 << CS42L42_HSBIAS_CTL_SHIFT)
  455. #define CS42L42_DETECT_MODE_SHIFT 3
  456. #define CS42L42_DETECT_MODE_MASK (3 << CS42L42_DETECT_MODE_SHIFT)
  457. #define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75)
  458. #define CS42L42_HS_DET_LEVEL_SHIFT 0
  459. #define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT)
  460. #define CS42L42_EVENT_STAT_SEL_SHIFT 6
  461. #define CS42L42_EVENT_STAT_SEL_MASK (1 << CS42L42_EVENT_STAT_SEL_SHIFT)
  462. #define CS42L42_LATCH_TO_VP_SHIFT 7
  463. #define CS42L42_LATCH_TO_VP_MASK (1 << CS42L42_LATCH_TO_VP_SHIFT)
  464. #define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76)
  465. #define CS42L42_DEBOUNCE_TIME_SHIFT 5
  466. #define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT)
  467. #define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77)
  468. #define CS42L42_HSBIAS_HIZ_MODE_SHIFT 6
  469. #define CS42L42_HSBIAS_HIZ_MODE_MASK (1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT)
  470. #define CS42L42_TIP_SENSE_SHIFT 7
  471. #define CS42L42_TIP_SENSE_MASK (1 << CS42L42_TIP_SENSE_SHIFT)
  472. #define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78)
  473. #define CS42L42_SHORT_TRUE_SHIFT 0
  474. #define CS42L42_SHORT_TRUE_MASK (1 << CS42L42_SHORT_TRUE_SHIFT)
  475. #define CS42L42_HS_TRUE_SHIFT 1
  476. #define CS42L42_HS_TRUE_MASK (1 << CS42L42_HS_TRUE_SHIFT)
  477. #define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79)
  478. #define CS42L42_TIP_SENSE_UNPLUG_SHIFT 5
  479. #define CS42L42_TIP_SENSE_UNPLUG_MASK (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT)
  480. #define CS42L42_TIP_SENSE_PLUG_SHIFT 6
  481. #define CS42L42_TIP_SENSE_PLUG_MASK (1 << CS42L42_TIP_SENSE_PLUG_SHIFT)
  482. #define CS42L42_HSBIAS_SENSE_SHIFT 7
  483. #define CS42L42_HSBIAS_SENSE_MASK (1 << CS42L42_HSBIAS_SENSE_SHIFT)
  484. #define CS42L42_DET_INT_VAL1_MASK (CS42L42_TIP_SENSE_UNPLUG_MASK | \
  485. CS42L42_TIP_SENSE_PLUG_MASK | \
  486. CS42L42_HSBIAS_SENSE_MASK)
  487. #define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A)
  488. #define CS42L42_M_SHORT_DET_SHIFT 0
  489. #define CS42L42_M_SHORT_DET_MASK (1 << \
  490. CS42L42_M_SHORT_DET_SHIFT)
  491. #define CS42L42_M_SHORT_RLS_SHIFT 1
  492. #define CS42L42_M_SHORT_RLS_MASK (1 << \
  493. CS42L42_M_SHORT_RLS_SHIFT)
  494. #define CS42L42_M_HSBIAS_HIZ_SHIFT 2
  495. #define CS42L42_M_HSBIAS_HIZ_MASK (1 << \
  496. CS42L42_M_HSBIAS_HIZ_SHIFT)
  497. #define CS42L42_M_DETECT_FT_SHIFT 6
  498. #define CS42L42_M_DETECT_FT_MASK (1 << \
  499. CS42L42_M_DETECT_FT_SHIFT)
  500. #define CS42L42_M_DETECT_TF_SHIFT 7
  501. #define CS42L42_M_DETECT_TF_MASK (1 << \
  502. CS42L42_M_DETECT_TF_SHIFT)
  503. #define CS42L42_DET_INT_VAL2_MASK (CS42L42_M_SHORT_DET_MASK | \
  504. CS42L42_M_SHORT_RLS_MASK | \
  505. CS42L42_M_HSBIAS_HIZ_MASK | \
  506. CS42L42_M_DETECT_FT_MASK | \
  507. CS42L42_M_DETECT_TF_MASK)
  508. /* Page 0x1C Headset Bias Registers */
  509. #define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03)
  510. #define CS42L42_HSBIAS_RAMP_SHIFT 0
  511. #define CS42L42_HSBIAS_RAMP_MASK (3 << CS42L42_HSBIAS_RAMP_SHIFT)
  512. #define CS42L42_HSBIAS_PD_SHIFT 4
  513. #define CS42L42_HSBIAS_PD_MASK (1 << CS42L42_HSBIAS_PD_SHIFT)
  514. #define CS42L42_HSBIAS_CAPLESS_SHIFT 7
  515. #define CS42L42_HSBIAS_CAPLESS_MASK (1 << CS42L42_HSBIAS_CAPLESS_SHIFT)
  516. /* Page 0x1D ADC Registers */
  517. #define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01)
  518. #define CS42L42_ADC_NOTCH_DIS_SHIFT 5
  519. #define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT 4
  520. #define CS42L42_ADC_INV_SHIFT 2
  521. #define CS42L42_ADC_DIG_BOOST_SHIFT 0
  522. #define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03)
  523. #define CS42L42_ADC_VOL_SHIFT 0
  524. #define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04)
  525. #define CS42L42_ADC_WNF_CF_SHIFT 4
  526. #define CS42L42_ADC_WNF_EN_SHIFT 3
  527. #define CS42L42_ADC_HPF_CF_SHIFT 1
  528. #define CS42L42_ADC_HPF_EN_SHIFT 0
  529. /* Page 0x1F DAC Registers */
  530. #define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01)
  531. #define CS42L42_DACB_INV_SHIFT 1
  532. #define CS42L42_DACA_INV_SHIFT 0
  533. #define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06)
  534. #define CS42L42_HPOUT_PULLDOWN_SHIFT 4
  535. #define CS42L42_HPOUT_PULLDOWN_MASK (15 << CS42L42_HPOUT_PULLDOWN_SHIFT)
  536. #define CS42L42_HPOUT_LOAD_SHIFT 3
  537. #define CS42L42_HPOUT_LOAD_MASK (1 << CS42L42_HPOUT_LOAD_SHIFT)
  538. #define CS42L42_HPOUT_CLAMP_SHIFT 2
  539. #define CS42L42_HPOUT_CLAMP_MASK (1 << CS42L42_HPOUT_CLAMP_SHIFT)
  540. #define CS42L42_DAC_HPF_EN_SHIFT 1
  541. #define CS42L42_DAC_HPF_EN_MASK (1 << CS42L42_DAC_HPF_EN_SHIFT)
  542. #define CS42L42_DAC_MON_EN_SHIFT 0
  543. #define CS42L42_DAC_MON_EN_MASK (1 << CS42L42_DAC_MON_EN_SHIFT)
  544. /* Page 0x20 HP CTL Registers */
  545. #define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01)
  546. #define CS42L42_HP_ANA_BMUTE_SHIFT 3
  547. #define CS42L42_HP_ANA_BMUTE_MASK (1 << CS42L42_HP_ANA_BMUTE_SHIFT)
  548. #define CS42L42_HP_ANA_AMUTE_SHIFT 2
  549. #define CS42L42_HP_ANA_AMUTE_MASK (1 << CS42L42_HP_ANA_AMUTE_SHIFT)
  550. #define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1
  551. #define CS42L42_HP_FULL_SCALE_VOL_MASK (1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT)
  552. /* Page 0x21 Class H Registers */
  553. #define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01)
  554. /* Page 0x23 Mixer Volume Registers */
  555. #define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01)
  556. #define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02)
  557. #define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03)
  558. #define CS42L42_MIXER_CH_VOL_SHIFT 0
  559. #define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT)
  560. /* Page 0x24 EQ Registers */
  561. #define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01)
  562. #define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02)
  563. #define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03)
  564. #define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04)
  565. #define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06)
  566. #define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07)
  567. #define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08)
  568. #define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09)
  569. #define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A)
  570. #define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B)
  571. #define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C)
  572. #define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E)
  573. /* Page 0x25 Audio Port Registers */
  574. #define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01)
  575. #define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02)
  576. #define CS42L42_SP_RX_RSYNC_SHIFT 6
  577. #define CS42L42_SP_RX_RSYNC_MASK (1 << CS42L42_SP_RX_RSYNC_SHIFT)
  578. #define CS42L42_SP_RX_NSB_POS_SHIFT 3
  579. #define CS42L42_SP_RX_NSB_POS_MASK (7 << CS42L42_SP_RX_NSB_POS_SHIFT)
  580. #define CS42L42_SP_RX_NFS_NSBB_SHIFT 2
  581. #define CS42L42_SP_RX_NFS_NSBB_MASK (1 << CS42L42_SP_RX_NFS_NSBB_SHIFT)
  582. #define CS42L42_SP_RX_ISOC_MODE_SHIFT 0
  583. #define CS42L42_SP_RX_ISOC_MODE_MASK (3 << CS42L42_SP_RX_ISOC_MODE_SHIFT)
  584. #define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03)
  585. #define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04)
  586. #define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05)
  587. #define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06)
  588. #define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07)
  589. /* Page 0x26 SRC Registers */
  590. #define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01)
  591. #define CS42L42_SRC_SDIN_FS_SHIFT 0
  592. #define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT)
  593. #define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09)
  594. /* Page 0x28 S/PDIF Registers */
  595. #define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01)
  596. #define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02)
  597. #define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03)
  598. #define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04)
  599. /* Page 0x29 Serial Port TX Registers */
  600. #define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01)
  601. #define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02)
  602. #define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03)
  603. #define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04)
  604. #define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05)
  605. #define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06)
  606. #define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A)
  607. #define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B)
  608. /* Page 0x2A Serial Port RX Registers */
  609. #define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01)
  610. #define CS42L42_ASP_RX0_CH_EN_SHIFT 2
  611. #define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT)
  612. #define CS42L42_ASP_RX0_CH1_EN 1
  613. #define CS42L42_ASP_RX0_CH2_EN 2
  614. #define CS42L42_ASP_RX0_CH3_EN 4
  615. #define CS42L42_ASP_RX0_CH4_EN 8
  616. #define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02)
  617. #define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03)
  618. #define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04)
  619. #define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05)
  620. #define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06)
  621. #define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07)
  622. #define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08)
  623. #define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09)
  624. #define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A)
  625. #define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B)
  626. #define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C)
  627. #define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D)
  628. #define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E)
  629. #define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F)
  630. #define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10)
  631. #define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11)
  632. #define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12)
  633. #define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13)
  634. #define CS42L42_ASP_RX_CH_AP_SHIFT 6
  635. #define CS42L42_ASP_RX_CH_AP_MASK (1 << CS42L42_ASP_RX_CH_AP_SHIFT)
  636. #define CS42L42_ASP_RX_CH_AP_LOW 0
  637. #define CS42L42_ASP_RX_CH_AP_HI 1
  638. #define CS42L42_ASP_RX_CH_RES_SHIFT 0
  639. #define CS42L42_ASP_RX_CH_RES_MASK (3 << CS42L42_ASP_RX_CH_RES_SHIFT)
  640. #define CS42L42_ASP_RX_CH_RES_32 3
  641. #define CS42L42_ASP_RX_CH_RES_16 1
  642. #define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0
  643. #define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT)
  644. /* Page 0x30 ID Registers */
  645. #define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14)
  646. #define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14)
  647. /* Defines for fracturing values spread across multiple registers */
  648. #define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff)
  649. #define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8)
  650. #define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16)
  651. #define CS42L42_NUM_SUPPLIES 5
  652. #define CS42L42_BOOT_TIME_US 3000
  653. static const char *const cs42l42_supply_names[CS42L42_NUM_SUPPLIES] = {
  654. "VA",
  655. "VP",
  656. "VCP",
  657. "VD_FILT",
  658. "VL",
  659. };
  660. struct cs42l42_private {
  661. struct regmap *regmap;
  662. struct snd_soc_component *component;
  663. struct regulator_bulk_data supplies[CS42L42_NUM_SUPPLIES];
  664. struct gpio_desc *reset_gpio;
  665. struct completion pdn_done;
  666. u32 sclk;
  667. u32 srate;
  668. u8 plug_state;
  669. u8 hs_type;
  670. u8 ts_inv;
  671. u8 ts_dbnc_rise;
  672. u8 ts_dbnc_fall;
  673. u8 btn_det_init_dbnce;
  674. u8 btn_det_event_dbnce;
  675. u8 bias_thresholds[CS42L42_NUM_BIASES];
  676. u8 hs_bias_ramp_rate;
  677. u8 hs_bias_ramp_time;
  678. };
  679. #endif /* __CS42L42_H__ */