cs42l42.c 57 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cs42l42.c -- CS42L42 ALSA SoC audio driver
  4. *
  5. * Copyright 2016 Cirrus Logic, Inc.
  6. *
  7. * Author: James Schulman <james.schulman@cirrus.com>
  8. * Author: Brian Austin <brian.austin@cirrus.com>
  9. * Author: Michael White <michael.white@cirrus.com>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/version.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/i2c.h>
  18. #include <linux/gpio.h>
  19. #include <linux/regmap.h>
  20. #include <linux/slab.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/property.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/of_device.h>
  26. #include <sound/core.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/soc.h>
  30. #include <sound/soc-dapm.h>
  31. #include <sound/initval.h>
  32. #include <sound/tlv.h>
  33. #include <dt-bindings/sound/cs42l42.h>
  34. #include "cs42l42.h"
  35. static const struct reg_default cs42l42_reg_defaults[] = {
  36. { CS42L42_FRZ_CTL, 0x00 },
  37. { CS42L42_SRC_CTL, 0x10 },
  38. { CS42L42_MCLK_STATUS, 0x02 },
  39. { CS42L42_MCLK_CTL, 0x02 },
  40. { CS42L42_SFTRAMP_RATE, 0xA4 },
  41. { CS42L42_I2C_DEBOUNCE, 0x88 },
  42. { CS42L42_I2C_STRETCH, 0x03 },
  43. { CS42L42_I2C_TIMEOUT, 0xB7 },
  44. { CS42L42_PWR_CTL1, 0xFF },
  45. { CS42L42_PWR_CTL2, 0x84 },
  46. { CS42L42_PWR_CTL3, 0x20 },
  47. { CS42L42_RSENSE_CTL1, 0x40 },
  48. { CS42L42_RSENSE_CTL2, 0x00 },
  49. { CS42L42_OSC_SWITCH, 0x00 },
  50. { CS42L42_OSC_SWITCH_STATUS, 0x05 },
  51. { CS42L42_RSENSE_CTL3, 0x1B },
  52. { CS42L42_TSENSE_CTL, 0x1B },
  53. { CS42L42_TSRS_INT_DISABLE, 0x00 },
  54. { CS42L42_TRSENSE_STATUS, 0x00 },
  55. { CS42L42_HSDET_CTL1, 0x77 },
  56. { CS42L42_HSDET_CTL2, 0x00 },
  57. { CS42L42_HS_SWITCH_CTL, 0xF3 },
  58. { CS42L42_HS_DET_STATUS, 0x00 },
  59. { CS42L42_HS_CLAMP_DISABLE, 0x00 },
  60. { CS42L42_MCLK_SRC_SEL, 0x00 },
  61. { CS42L42_SPDIF_CLK_CFG, 0x00 },
  62. { CS42L42_FSYNC_PW_LOWER, 0x00 },
  63. { CS42L42_FSYNC_PW_UPPER, 0x00 },
  64. { CS42L42_FSYNC_P_LOWER, 0xF9 },
  65. { CS42L42_FSYNC_P_UPPER, 0x00 },
  66. { CS42L42_ASP_CLK_CFG, 0x00 },
  67. { CS42L42_ASP_FRM_CFG, 0x10 },
  68. { CS42L42_FS_RATE_EN, 0x00 },
  69. { CS42L42_IN_ASRC_CLK, 0x00 },
  70. { CS42L42_OUT_ASRC_CLK, 0x00 },
  71. { CS42L42_PLL_DIV_CFG1, 0x00 },
  72. { CS42L42_ADC_OVFL_STATUS, 0x00 },
  73. { CS42L42_MIXER_STATUS, 0x00 },
  74. { CS42L42_SRC_STATUS, 0x00 },
  75. { CS42L42_ASP_RX_STATUS, 0x00 },
  76. { CS42L42_ASP_TX_STATUS, 0x00 },
  77. { CS42L42_CODEC_STATUS, 0x00 },
  78. { CS42L42_DET_INT_STATUS1, 0x00 },
  79. { CS42L42_DET_INT_STATUS2, 0x00 },
  80. { CS42L42_SRCPL_INT_STATUS, 0x00 },
  81. { CS42L42_VPMON_STATUS, 0x00 },
  82. { CS42L42_PLL_LOCK_STATUS, 0x00 },
  83. { CS42L42_TSRS_PLUG_STATUS, 0x00 },
  84. { CS42L42_ADC_OVFL_INT_MASK, 0x01 },
  85. { CS42L42_MIXER_INT_MASK, 0x0F },
  86. { CS42L42_SRC_INT_MASK, 0x0F },
  87. { CS42L42_ASP_RX_INT_MASK, 0x1F },
  88. { CS42L42_ASP_TX_INT_MASK, 0x0F },
  89. { CS42L42_CODEC_INT_MASK, 0x03 },
  90. { CS42L42_SRCPL_INT_MASK, 0x7F },
  91. { CS42L42_VPMON_INT_MASK, 0x01 },
  92. { CS42L42_PLL_LOCK_INT_MASK, 0x01 },
  93. { CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
  94. { CS42L42_PLL_CTL1, 0x00 },
  95. { CS42L42_PLL_DIV_FRAC0, 0x00 },
  96. { CS42L42_PLL_DIV_FRAC1, 0x00 },
  97. { CS42L42_PLL_DIV_FRAC2, 0x00 },
  98. { CS42L42_PLL_DIV_INT, 0x40 },
  99. { CS42L42_PLL_CTL3, 0x10 },
  100. { CS42L42_PLL_CAL_RATIO, 0x80 },
  101. { CS42L42_PLL_CTL4, 0x03 },
  102. { CS42L42_LOAD_DET_RCSTAT, 0x00 },
  103. { CS42L42_LOAD_DET_DONE, 0x00 },
  104. { CS42L42_LOAD_DET_EN, 0x00 },
  105. { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 },
  106. { CS42L42_WAKE_CTL, 0xC0 },
  107. { CS42L42_ADC_DISABLE_MUTE, 0x00 },
  108. { CS42L42_TIPSENSE_CTL, 0x02 },
  109. { CS42L42_MISC_DET_CTL, 0x03 },
  110. { CS42L42_MIC_DET_CTL1, 0x1F },
  111. { CS42L42_MIC_DET_CTL2, 0x2F },
  112. { CS42L42_DET_STATUS1, 0x00 },
  113. { CS42L42_DET_STATUS2, 0x00 },
  114. { CS42L42_DET_INT1_MASK, 0xE0 },
  115. { CS42L42_DET_INT2_MASK, 0xFF },
  116. { CS42L42_HS_BIAS_CTL, 0xC2 },
  117. { CS42L42_ADC_CTL, 0x00 },
  118. { CS42L42_ADC_VOLUME, 0x00 },
  119. { CS42L42_ADC_WNF_HPF_CTL, 0x71 },
  120. { CS42L42_DAC_CTL1, 0x00 },
  121. { CS42L42_DAC_CTL2, 0x02 },
  122. { CS42L42_HP_CTL, 0x0D },
  123. { CS42L42_CLASSH_CTL, 0x07 },
  124. { CS42L42_MIXER_CHA_VOL, 0x3F },
  125. { CS42L42_MIXER_ADC_VOL, 0x3F },
  126. { CS42L42_MIXER_CHB_VOL, 0x3F },
  127. { CS42L42_EQ_COEF_IN0, 0x00 },
  128. { CS42L42_EQ_COEF_IN1, 0x00 },
  129. { CS42L42_EQ_COEF_IN2, 0x00 },
  130. { CS42L42_EQ_COEF_IN3, 0x00 },
  131. { CS42L42_EQ_COEF_RW, 0x00 },
  132. { CS42L42_EQ_COEF_OUT0, 0x00 },
  133. { CS42L42_EQ_COEF_OUT1, 0x00 },
  134. { CS42L42_EQ_COEF_OUT2, 0x00 },
  135. { CS42L42_EQ_COEF_OUT3, 0x00 },
  136. { CS42L42_EQ_INIT_STAT, 0x00 },
  137. { CS42L42_EQ_START_FILT, 0x00 },
  138. { CS42L42_EQ_MUTE_CTL, 0x00 },
  139. { CS42L42_SP_RX_CH_SEL, 0x04 },
  140. { CS42L42_SP_RX_ISOC_CTL, 0x04 },
  141. { CS42L42_SP_RX_FS, 0x8C },
  142. { CS42l42_SPDIF_CH_SEL, 0x0E },
  143. { CS42L42_SP_TX_ISOC_CTL, 0x04 },
  144. { CS42L42_SP_TX_FS, 0xCC },
  145. { CS42L42_SPDIF_SW_CTL1, 0x3F },
  146. { CS42L42_SRC_SDIN_FS, 0x40 },
  147. { CS42L42_SRC_SDOUT_FS, 0x40 },
  148. { CS42L42_SPDIF_CTL1, 0x01 },
  149. { CS42L42_SPDIF_CTL2, 0x00 },
  150. { CS42L42_SPDIF_CTL3, 0x00 },
  151. { CS42L42_SPDIF_CTL4, 0x42 },
  152. { CS42L42_ASP_TX_SZ_EN, 0x00 },
  153. { CS42L42_ASP_TX_CH_EN, 0x00 },
  154. { CS42L42_ASP_TX_CH_AP_RES, 0x0F },
  155. { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
  156. { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
  157. { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 },
  158. { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 },
  159. { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 },
  160. { CS42L42_ASP_RX_DAI0_EN, 0x00 },
  161. { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 },
  162. { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
  163. { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
  164. { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 },
  165. { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
  166. { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 },
  167. { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 },
  168. { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
  169. { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 },
  170. { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 },
  171. { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
  172. { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 },
  173. { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 },
  174. { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 },
  175. { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 },
  176. { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 },
  177. { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 },
  178. { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 },
  179. { CS42L42_SUB_REVID, 0x03 },
  180. };
  181. static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
  182. {
  183. switch (reg) {
  184. case CS42L42_PAGE_REGISTER:
  185. case CS42L42_DEVID_AB:
  186. case CS42L42_DEVID_CD:
  187. case CS42L42_DEVID_E:
  188. case CS42L42_FABID:
  189. case CS42L42_REVID:
  190. case CS42L42_FRZ_CTL:
  191. case CS42L42_SRC_CTL:
  192. case CS42L42_MCLK_STATUS:
  193. case CS42L42_MCLK_CTL:
  194. case CS42L42_SFTRAMP_RATE:
  195. case CS42L42_I2C_DEBOUNCE:
  196. case CS42L42_I2C_STRETCH:
  197. case CS42L42_I2C_TIMEOUT:
  198. case CS42L42_PWR_CTL1:
  199. case CS42L42_PWR_CTL2:
  200. case CS42L42_PWR_CTL3:
  201. case CS42L42_RSENSE_CTL1:
  202. case CS42L42_RSENSE_CTL2:
  203. case CS42L42_OSC_SWITCH:
  204. case CS42L42_OSC_SWITCH_STATUS:
  205. case CS42L42_RSENSE_CTL3:
  206. case CS42L42_TSENSE_CTL:
  207. case CS42L42_TSRS_INT_DISABLE:
  208. case CS42L42_TRSENSE_STATUS:
  209. case CS42L42_HSDET_CTL1:
  210. case CS42L42_HSDET_CTL2:
  211. case CS42L42_HS_SWITCH_CTL:
  212. case CS42L42_HS_DET_STATUS:
  213. case CS42L42_HS_CLAMP_DISABLE:
  214. case CS42L42_MCLK_SRC_SEL:
  215. case CS42L42_SPDIF_CLK_CFG:
  216. case CS42L42_FSYNC_PW_LOWER:
  217. case CS42L42_FSYNC_PW_UPPER:
  218. case CS42L42_FSYNC_P_LOWER:
  219. case CS42L42_FSYNC_P_UPPER:
  220. case CS42L42_ASP_CLK_CFG:
  221. case CS42L42_ASP_FRM_CFG:
  222. case CS42L42_FS_RATE_EN:
  223. case CS42L42_IN_ASRC_CLK:
  224. case CS42L42_OUT_ASRC_CLK:
  225. case CS42L42_PLL_DIV_CFG1:
  226. case CS42L42_ADC_OVFL_STATUS:
  227. case CS42L42_MIXER_STATUS:
  228. case CS42L42_SRC_STATUS:
  229. case CS42L42_ASP_RX_STATUS:
  230. case CS42L42_ASP_TX_STATUS:
  231. case CS42L42_CODEC_STATUS:
  232. case CS42L42_DET_INT_STATUS1:
  233. case CS42L42_DET_INT_STATUS2:
  234. case CS42L42_SRCPL_INT_STATUS:
  235. case CS42L42_VPMON_STATUS:
  236. case CS42L42_PLL_LOCK_STATUS:
  237. case CS42L42_TSRS_PLUG_STATUS:
  238. case CS42L42_ADC_OVFL_INT_MASK:
  239. case CS42L42_MIXER_INT_MASK:
  240. case CS42L42_SRC_INT_MASK:
  241. case CS42L42_ASP_RX_INT_MASK:
  242. case CS42L42_ASP_TX_INT_MASK:
  243. case CS42L42_CODEC_INT_MASK:
  244. case CS42L42_SRCPL_INT_MASK:
  245. case CS42L42_VPMON_INT_MASK:
  246. case CS42L42_PLL_LOCK_INT_MASK:
  247. case CS42L42_TSRS_PLUG_INT_MASK:
  248. case CS42L42_PLL_CTL1:
  249. case CS42L42_PLL_DIV_FRAC0:
  250. case CS42L42_PLL_DIV_FRAC1:
  251. case CS42L42_PLL_DIV_FRAC2:
  252. case CS42L42_PLL_DIV_INT:
  253. case CS42L42_PLL_CTL3:
  254. case CS42L42_PLL_CAL_RATIO:
  255. case CS42L42_PLL_CTL4:
  256. case CS42L42_LOAD_DET_RCSTAT:
  257. case CS42L42_LOAD_DET_DONE:
  258. case CS42L42_LOAD_DET_EN:
  259. case CS42L42_HSBIAS_SC_AUTOCTL:
  260. case CS42L42_WAKE_CTL:
  261. case CS42L42_ADC_DISABLE_MUTE:
  262. case CS42L42_TIPSENSE_CTL:
  263. case CS42L42_MISC_DET_CTL:
  264. case CS42L42_MIC_DET_CTL1:
  265. case CS42L42_MIC_DET_CTL2:
  266. case CS42L42_DET_STATUS1:
  267. case CS42L42_DET_STATUS2:
  268. case CS42L42_DET_INT1_MASK:
  269. case CS42L42_DET_INT2_MASK:
  270. case CS42L42_HS_BIAS_CTL:
  271. case CS42L42_ADC_CTL:
  272. case CS42L42_ADC_VOLUME:
  273. case CS42L42_ADC_WNF_HPF_CTL:
  274. case CS42L42_DAC_CTL1:
  275. case CS42L42_DAC_CTL2:
  276. case CS42L42_HP_CTL:
  277. case CS42L42_CLASSH_CTL:
  278. case CS42L42_MIXER_CHA_VOL:
  279. case CS42L42_MIXER_ADC_VOL:
  280. case CS42L42_MIXER_CHB_VOL:
  281. case CS42L42_EQ_COEF_IN0:
  282. case CS42L42_EQ_COEF_IN1:
  283. case CS42L42_EQ_COEF_IN2:
  284. case CS42L42_EQ_COEF_IN3:
  285. case CS42L42_EQ_COEF_RW:
  286. case CS42L42_EQ_COEF_OUT0:
  287. case CS42L42_EQ_COEF_OUT1:
  288. case CS42L42_EQ_COEF_OUT2:
  289. case CS42L42_EQ_COEF_OUT3:
  290. case CS42L42_EQ_INIT_STAT:
  291. case CS42L42_EQ_START_FILT:
  292. case CS42L42_EQ_MUTE_CTL:
  293. case CS42L42_SP_RX_CH_SEL:
  294. case CS42L42_SP_RX_ISOC_CTL:
  295. case CS42L42_SP_RX_FS:
  296. case CS42l42_SPDIF_CH_SEL:
  297. case CS42L42_SP_TX_ISOC_CTL:
  298. case CS42L42_SP_TX_FS:
  299. case CS42L42_SPDIF_SW_CTL1:
  300. case CS42L42_SRC_SDIN_FS:
  301. case CS42L42_SRC_SDOUT_FS:
  302. case CS42L42_SPDIF_CTL1:
  303. case CS42L42_SPDIF_CTL2:
  304. case CS42L42_SPDIF_CTL3:
  305. case CS42L42_SPDIF_CTL4:
  306. case CS42L42_ASP_TX_SZ_EN:
  307. case CS42L42_ASP_TX_CH_EN:
  308. case CS42L42_ASP_TX_CH_AP_RES:
  309. case CS42L42_ASP_TX_CH1_BIT_MSB:
  310. case CS42L42_ASP_TX_CH1_BIT_LSB:
  311. case CS42L42_ASP_TX_HIZ_DLY_CFG:
  312. case CS42L42_ASP_TX_CH2_BIT_MSB:
  313. case CS42L42_ASP_TX_CH2_BIT_LSB:
  314. case CS42L42_ASP_RX_DAI0_EN:
  315. case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
  316. case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
  317. case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
  318. case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
  319. case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
  320. case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
  321. case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
  322. case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
  323. case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
  324. case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
  325. case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
  326. case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
  327. case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
  328. case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
  329. case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
  330. case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
  331. case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
  332. case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
  333. case CS42L42_SUB_REVID:
  334. return true;
  335. default:
  336. return false;
  337. }
  338. }
  339. static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
  340. {
  341. switch (reg) {
  342. case CS42L42_DEVID_AB:
  343. case CS42L42_DEVID_CD:
  344. case CS42L42_DEVID_E:
  345. case CS42L42_MCLK_STATUS:
  346. case CS42L42_TRSENSE_STATUS:
  347. case CS42L42_HS_DET_STATUS:
  348. case CS42L42_ADC_OVFL_STATUS:
  349. case CS42L42_MIXER_STATUS:
  350. case CS42L42_SRC_STATUS:
  351. case CS42L42_ASP_RX_STATUS:
  352. case CS42L42_ASP_TX_STATUS:
  353. case CS42L42_CODEC_STATUS:
  354. case CS42L42_DET_INT_STATUS1:
  355. case CS42L42_DET_INT_STATUS2:
  356. case CS42L42_SRCPL_INT_STATUS:
  357. case CS42L42_VPMON_STATUS:
  358. case CS42L42_PLL_LOCK_STATUS:
  359. case CS42L42_TSRS_PLUG_STATUS:
  360. case CS42L42_LOAD_DET_RCSTAT:
  361. case CS42L42_LOAD_DET_DONE:
  362. case CS42L42_DET_STATUS1:
  363. case CS42L42_DET_STATUS2:
  364. return true;
  365. default:
  366. return false;
  367. }
  368. }
  369. static const struct regmap_range_cfg cs42l42_page_range = {
  370. .name = "Pages",
  371. .range_min = 0,
  372. .range_max = CS42L42_MAX_REGISTER,
  373. .selector_reg = CS42L42_PAGE_REGISTER,
  374. .selector_mask = 0xff,
  375. .selector_shift = 0,
  376. .window_start = 0,
  377. .window_len = 256,
  378. };
  379. static const struct regmap_config cs42l42_regmap = {
  380. .reg_bits = 8,
  381. .val_bits = 8,
  382. .readable_reg = cs42l42_readable_register,
  383. .volatile_reg = cs42l42_volatile_register,
  384. .ranges = &cs42l42_page_range,
  385. .num_ranges = 1,
  386. .max_register = CS42L42_MAX_REGISTER,
  387. .reg_defaults = cs42l42_reg_defaults,
  388. .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
  389. .cache_type = REGCACHE_RBTREE,
  390. .use_single_read = true,
  391. .use_single_write = true,
  392. };
  393. static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
  394. static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
  395. static const char * const cs42l42_hpf_freq_text[] = {
  396. "1.86Hz", "120Hz", "235Hz", "466Hz"
  397. };
  398. static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
  399. CS42L42_ADC_HPF_CF_SHIFT,
  400. cs42l42_hpf_freq_text);
  401. static const char * const cs42l42_wnf3_freq_text[] = {
  402. "160Hz", "180Hz", "200Hz", "220Hz",
  403. "240Hz", "260Hz", "280Hz", "300Hz"
  404. };
  405. static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
  406. CS42L42_ADC_WNF_CF_SHIFT,
  407. cs42l42_wnf3_freq_text);
  408. static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
  409. /* ADC Volume and Filter Controls */
  410. SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
  411. CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
  412. SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
  413. CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
  414. SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
  415. CS42L42_ADC_INV_SHIFT, true, false),
  416. SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
  417. CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
  418. SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
  419. SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
  420. CS42L42_ADC_WNF_EN_SHIFT, true, false),
  421. SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
  422. CS42L42_ADC_HPF_EN_SHIFT, true, false),
  423. SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
  424. SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
  425. /* DAC Volume and Filter Controls */
  426. SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
  427. CS42L42_DACA_INV_SHIFT, true, false),
  428. SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
  429. CS42L42_DACB_INV_SHIFT, true, false),
  430. SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
  431. CS42L42_DAC_HPF_EN_SHIFT, true, false),
  432. SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
  433. CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
  434. 0x3f, 1, mixer_tlv)
  435. };
  436. static int cs42l42_hpdrv_evt(struct snd_soc_dapm_widget *w,
  437. struct snd_kcontrol *kcontrol, int event)
  438. {
  439. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  440. if (event & SND_SOC_DAPM_POST_PMU) {
  441. /* Enable the channels */
  442. snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
  443. CS42L42_ASP_RX0_CH_EN_MASK,
  444. (CS42L42_ASP_RX0_CH1_EN |
  445. CS42L42_ASP_RX0_CH2_EN) <<
  446. CS42L42_ASP_RX0_CH_EN_SHIFT);
  447. /* Power up */
  448. snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
  449. CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
  450. CS42L42_HP_PDN_MASK, 0);
  451. } else if (event & SND_SOC_DAPM_PRE_PMD) {
  452. /* Disable the channels */
  453. snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
  454. CS42L42_ASP_RX0_CH_EN_MASK, 0);
  455. /* Power down */
  456. snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
  457. CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
  458. CS42L42_HP_PDN_MASK,
  459. CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
  460. CS42L42_HP_PDN_MASK);
  461. } else {
  462. dev_err(component->dev, "Invalid event 0x%x\n", event);
  463. }
  464. return 0;
  465. }
  466. static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
  467. SND_SOC_DAPM_OUTPUT("HP"),
  468. SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS42L42_ASP_CLK_CFG,
  469. CS42L42_ASP_SCLK_EN_SHIFT, false),
  470. SND_SOC_DAPM_OUT_DRV_E("HPDRV", SND_SOC_NOPM, 0,
  471. 0, NULL, 0, cs42l42_hpdrv_evt,
  472. SND_SOC_DAPM_POST_PMU |
  473. SND_SOC_DAPM_PRE_PMD)
  474. };
  475. static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
  476. {"SDIN", NULL, "Playback"},
  477. {"HPDRV", NULL, "SDIN"},
  478. {"HP", NULL, "HPDRV"}
  479. };
  480. static int cs42l42_set_bias_level(struct snd_soc_component *component,
  481. enum snd_soc_bias_level level)
  482. {
  483. struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
  484. int ret;
  485. switch (level) {
  486. case SND_SOC_BIAS_ON:
  487. break;
  488. case SND_SOC_BIAS_PREPARE:
  489. break;
  490. case SND_SOC_BIAS_STANDBY:
  491. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  492. regcache_cache_only(cs42l42->regmap, false);
  493. regcache_sync(cs42l42->regmap);
  494. ret = regulator_bulk_enable(
  495. ARRAY_SIZE(cs42l42->supplies),
  496. cs42l42->supplies);
  497. if (ret != 0) {
  498. dev_err(component->dev,
  499. "Failed to enable regulators: %d\n",
  500. ret);
  501. return ret;
  502. }
  503. }
  504. break;
  505. case SND_SOC_BIAS_OFF:
  506. regcache_cache_only(cs42l42->regmap, true);
  507. regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
  508. cs42l42->supplies);
  509. break;
  510. }
  511. return 0;
  512. }
  513. static int cs42l42_component_probe(struct snd_soc_component *component)
  514. {
  515. struct cs42l42_private *cs42l42 =
  516. (struct cs42l42_private *)snd_soc_component_get_drvdata(component);
  517. cs42l42->component = component;
  518. return 0;
  519. }
  520. static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
  521. .probe = cs42l42_component_probe,
  522. .set_bias_level = cs42l42_set_bias_level,
  523. .dapm_widgets = cs42l42_dapm_widgets,
  524. .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets),
  525. .dapm_routes = cs42l42_audio_map,
  526. .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
  527. .controls = cs42l42_snd_controls,
  528. .num_controls = ARRAY_SIZE(cs42l42_snd_controls),
  529. .idle_bias_on = 1,
  530. .endianness = 1,
  531. .non_legacy_dai_naming = 1,
  532. };
  533. struct cs42l42_pll_params {
  534. u32 sclk;
  535. u8 mclk_div;
  536. u8 mclk_src_sel;
  537. u8 sclk_prediv;
  538. u8 pll_div_int;
  539. u32 pll_div_frac;
  540. u8 pll_mode;
  541. u8 pll_divout;
  542. u32 mclk_int;
  543. u8 pll_cal_ratio;
  544. };
  545. /*
  546. * Common PLL Settings for given SCLK
  547. * Table 4-5 from the Datasheet
  548. */
  549. static const struct cs42l42_pll_params pll_ratio_table[] = {
  550. { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 },
  551. { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
  552. { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
  553. { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
  554. { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 },
  555. { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 },
  556. { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
  557. { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
  558. { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
  559. { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 },
  560. { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 },
  561. { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 },
  562. { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 },
  563. { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 },
  564. { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 }
  565. };
  566. static int cs42l42_pll_config(struct snd_soc_component *component)
  567. {
  568. struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
  569. int i;
  570. u32 fsync;
  571. for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
  572. if (pll_ratio_table[i].sclk == cs42l42->sclk) {
  573. /* Configure the internal sample rate */
  574. snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
  575. CS42L42_INTERNAL_FS_MASK,
  576. ((pll_ratio_table[i].mclk_int !=
  577. 12000000) &&
  578. (pll_ratio_table[i].mclk_int !=
  579. 24000000)) <<
  580. CS42L42_INTERNAL_FS_SHIFT);
  581. /* Set the MCLK src (PLL or SCLK) and the divide
  582. * ratio
  583. */
  584. snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
  585. CS42L42_MCLK_SRC_SEL_MASK |
  586. CS42L42_MCLKDIV_MASK,
  587. (pll_ratio_table[i].mclk_src_sel
  588. << CS42L42_MCLK_SRC_SEL_SHIFT) |
  589. (pll_ratio_table[i].mclk_div <<
  590. CS42L42_MCLKDIV_SHIFT));
  591. /* Set up the LRCLK */
  592. fsync = cs42l42->sclk / cs42l42->srate;
  593. if (((fsync * cs42l42->srate) != cs42l42->sclk)
  594. || ((fsync % 2) != 0)) {
  595. dev_err(component->dev,
  596. "Unsupported sclk %d/sample rate %d\n",
  597. cs42l42->sclk,
  598. cs42l42->srate);
  599. return -EINVAL;
  600. }
  601. /* Set the LRCLK period */
  602. snd_soc_component_update_bits(component,
  603. CS42L42_FSYNC_P_LOWER,
  604. CS42L42_FSYNC_PERIOD_MASK,
  605. CS42L42_FRAC0_VAL(fsync - 1) <<
  606. CS42L42_FSYNC_PERIOD_SHIFT);
  607. snd_soc_component_update_bits(component,
  608. CS42L42_FSYNC_P_UPPER,
  609. CS42L42_FSYNC_PERIOD_MASK,
  610. CS42L42_FRAC1_VAL(fsync - 1) <<
  611. CS42L42_FSYNC_PERIOD_SHIFT);
  612. /* Set the LRCLK to 50% duty cycle */
  613. fsync = fsync / 2;
  614. snd_soc_component_update_bits(component,
  615. CS42L42_FSYNC_PW_LOWER,
  616. CS42L42_FSYNC_PULSE_WIDTH_MASK,
  617. CS42L42_FRAC0_VAL(fsync - 1) <<
  618. CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
  619. snd_soc_component_update_bits(component,
  620. CS42L42_FSYNC_PW_UPPER,
  621. CS42L42_FSYNC_PULSE_WIDTH_MASK,
  622. CS42L42_FRAC1_VAL(fsync - 1) <<
  623. CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
  624. /* Set the sample rates (96k or lower) */
  625. snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
  626. CS42L42_FS_EN_MASK,
  627. (CS42L42_FS_EN_IASRC_96K |
  628. CS42L42_FS_EN_OASRC_96K) <<
  629. CS42L42_FS_EN_SHIFT);
  630. /* Set the input/output internal MCLK clock ~12 MHz */
  631. snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
  632. CS42L42_CLK_IASRC_SEL_MASK,
  633. CS42L42_CLK_IASRC_SEL_12 <<
  634. CS42L42_CLK_IASRC_SEL_SHIFT);
  635. snd_soc_component_update_bits(component,
  636. CS42L42_OUT_ASRC_CLK,
  637. CS42L42_CLK_OASRC_SEL_MASK,
  638. CS42L42_CLK_OASRC_SEL_12 <<
  639. CS42L42_CLK_OASRC_SEL_SHIFT);
  640. if (pll_ratio_table[i].mclk_src_sel == 0) {
  641. /* Pass the clock straight through */
  642. snd_soc_component_update_bits(component,
  643. CS42L42_PLL_CTL1,
  644. CS42L42_PLL_START_MASK, 0);
  645. } else {
  646. /* Configure PLL per table 4-5 */
  647. snd_soc_component_update_bits(component,
  648. CS42L42_PLL_DIV_CFG1,
  649. CS42L42_SCLK_PREDIV_MASK,
  650. pll_ratio_table[i].sclk_prediv
  651. << CS42L42_SCLK_PREDIV_SHIFT);
  652. snd_soc_component_update_bits(component,
  653. CS42L42_PLL_DIV_INT,
  654. CS42L42_PLL_DIV_INT_MASK,
  655. pll_ratio_table[i].pll_div_int
  656. << CS42L42_PLL_DIV_INT_SHIFT);
  657. snd_soc_component_update_bits(component,
  658. CS42L42_PLL_DIV_FRAC0,
  659. CS42L42_PLL_DIV_FRAC_MASK,
  660. CS42L42_FRAC0_VAL(
  661. pll_ratio_table[i].pll_div_frac)
  662. << CS42L42_PLL_DIV_FRAC_SHIFT);
  663. snd_soc_component_update_bits(component,
  664. CS42L42_PLL_DIV_FRAC1,
  665. CS42L42_PLL_DIV_FRAC_MASK,
  666. CS42L42_FRAC1_VAL(
  667. pll_ratio_table[i].pll_div_frac)
  668. << CS42L42_PLL_DIV_FRAC_SHIFT);
  669. snd_soc_component_update_bits(component,
  670. CS42L42_PLL_DIV_FRAC2,
  671. CS42L42_PLL_DIV_FRAC_MASK,
  672. CS42L42_FRAC2_VAL(
  673. pll_ratio_table[i].pll_div_frac)
  674. << CS42L42_PLL_DIV_FRAC_SHIFT);
  675. snd_soc_component_update_bits(component,
  676. CS42L42_PLL_CTL4,
  677. CS42L42_PLL_MODE_MASK,
  678. pll_ratio_table[i].pll_mode
  679. << CS42L42_PLL_MODE_SHIFT);
  680. snd_soc_component_update_bits(component,
  681. CS42L42_PLL_CTL3,
  682. CS42L42_PLL_DIVOUT_MASK,
  683. pll_ratio_table[i].pll_divout
  684. << CS42L42_PLL_DIVOUT_SHIFT);
  685. snd_soc_component_update_bits(component,
  686. CS42L42_PLL_CAL_RATIO,
  687. CS42L42_PLL_CAL_RATIO_MASK,
  688. pll_ratio_table[i].pll_cal_ratio
  689. << CS42L42_PLL_CAL_RATIO_SHIFT);
  690. }
  691. return 0;
  692. }
  693. }
  694. return -EINVAL;
  695. }
  696. static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  697. {
  698. struct snd_soc_component *component = codec_dai->component;
  699. u32 asp_cfg_val = 0;
  700. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  701. case SND_SOC_DAIFMT_CBS_CFM:
  702. asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
  703. CS42L42_ASP_MODE_SHIFT;
  704. break;
  705. case SND_SOC_DAIFMT_CBS_CFS:
  706. asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
  707. CS42L42_ASP_MODE_SHIFT;
  708. break;
  709. default:
  710. return -EINVAL;
  711. }
  712. /* interface format */
  713. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  714. case SND_SOC_DAIFMT_I2S:
  715. /*
  716. * 5050 mode, frame starts on falling edge of LRCLK,
  717. * frame delayed by 1.0 SCLKs
  718. */
  719. snd_soc_component_update_bits(component,
  720. CS42L42_ASP_FRM_CFG,
  721. CS42L42_ASP_STP_MASK |
  722. CS42L42_ASP_5050_MASK |
  723. CS42L42_ASP_FSD_MASK,
  724. CS42L42_ASP_5050_MASK |
  725. (CS42L42_ASP_FSD_1_0 <<
  726. CS42L42_ASP_FSD_SHIFT));
  727. break;
  728. default:
  729. return -EINVAL;
  730. }
  731. /* Bitclock/frame inversion */
  732. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  733. case SND_SOC_DAIFMT_NB_NF:
  734. asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
  735. break;
  736. case SND_SOC_DAIFMT_NB_IF:
  737. asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
  738. asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
  739. break;
  740. case SND_SOC_DAIFMT_IB_NF:
  741. break;
  742. case SND_SOC_DAIFMT_IB_IF:
  743. asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
  744. break;
  745. }
  746. snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
  747. CS42L42_ASP_SCPOL_MASK |
  748. CS42L42_ASP_LCPOL_MASK,
  749. asp_cfg_val);
  750. return 0;
  751. }
  752. static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
  753. struct snd_pcm_hw_params *params,
  754. struct snd_soc_dai *dai)
  755. {
  756. struct snd_soc_component *component = dai->component;
  757. struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
  758. unsigned int width = (params_width(params) / 8) - 1;
  759. unsigned int val = 0;
  760. cs42l42->srate = params_rate(params);
  761. switch(substream->stream) {
  762. case SNDRV_PCM_STREAM_PLAYBACK:
  763. val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
  764. /* channel 1 on low LRCLK */
  765. snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
  766. CS42L42_ASP_RX_CH_AP_MASK |
  767. CS42L42_ASP_RX_CH_RES_MASK, val);
  768. /* Channel 2 on high LRCLK */
  769. val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
  770. snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
  771. CS42L42_ASP_RX_CH_AP_MASK |
  772. CS42L42_ASP_RX_CH_RES_MASK, val);
  773. break;
  774. default:
  775. break;
  776. }
  777. return cs42l42_pll_config(component);
  778. }
  779. static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
  780. int clk_id, unsigned int freq, int dir)
  781. {
  782. struct snd_soc_component *component = dai->component;
  783. struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
  784. cs42l42->sclk = freq;
  785. return 0;
  786. }
  787. static int cs42l42_mute(struct snd_soc_dai *dai, int mute, int direction)
  788. {
  789. struct snd_soc_component *component = dai->component;
  790. unsigned int regval;
  791. u8 fullScaleVol;
  792. if (mute) {
  793. /* Mark SCLK as not present to turn on the internal
  794. * oscillator.
  795. */
  796. snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
  797. CS42L42_SCLK_PRESENT_MASK, 0);
  798. snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
  799. CS42L42_PLL_START_MASK,
  800. 0 << CS42L42_PLL_START_SHIFT);
  801. /* Mute the headphone */
  802. snd_soc_component_update_bits(component, CS42L42_HP_CTL,
  803. CS42L42_HP_ANA_AMUTE_MASK |
  804. CS42L42_HP_ANA_BMUTE_MASK,
  805. CS42L42_HP_ANA_AMUTE_MASK |
  806. CS42L42_HP_ANA_BMUTE_MASK);
  807. } else {
  808. snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
  809. CS42L42_PLL_START_MASK,
  810. 1 << CS42L42_PLL_START_SHIFT);
  811. /* Read the headphone load */
  812. regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT);
  813. if (((regval & CS42L42_RLA_STAT_MASK) >>
  814. CS42L42_RLA_STAT_SHIFT) == CS42L42_RLA_STAT_15_OHM) {
  815. fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
  816. } else {
  817. fullScaleVol = 0;
  818. }
  819. /* Un-mute the headphone, set the full scale volume flag */
  820. snd_soc_component_update_bits(component, CS42L42_HP_CTL,
  821. CS42L42_HP_ANA_AMUTE_MASK |
  822. CS42L42_HP_ANA_BMUTE_MASK |
  823. CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
  824. /* Mark SCLK as present, turn off internal oscillator */
  825. snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
  826. CS42L42_SCLK_PRESENT_MASK,
  827. CS42L42_SCLK_PRESENT_MASK);
  828. }
  829. return 0;
  830. }
  831. #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  832. SNDRV_PCM_FMTBIT_S24_LE |\
  833. SNDRV_PCM_FMTBIT_S32_LE )
  834. static const struct snd_soc_dai_ops cs42l42_ops = {
  835. .hw_params = cs42l42_pcm_hw_params,
  836. .set_fmt = cs42l42_set_dai_fmt,
  837. .set_sysclk = cs42l42_set_sysclk,
  838. .mute_stream = cs42l42_mute,
  839. .no_capture_mute = 1,
  840. };
  841. static struct snd_soc_dai_driver cs42l42_dai = {
  842. .name = "cs42l42",
  843. .playback = {
  844. .stream_name = "Playback",
  845. .channels_min = 1,
  846. .channels_max = 2,
  847. .rates = SNDRV_PCM_RATE_8000_192000,
  848. .formats = CS42L42_FORMATS,
  849. },
  850. .capture = {
  851. .stream_name = "Capture",
  852. .channels_min = 1,
  853. .channels_max = 2,
  854. .rates = SNDRV_PCM_RATE_8000_192000,
  855. .formats = CS42L42_FORMATS,
  856. },
  857. .ops = &cs42l42_ops,
  858. };
  859. static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
  860. {
  861. unsigned int hs_det_status;
  862. unsigned int int_status;
  863. /* Mask the auto detect interrupt */
  864. regmap_update_bits(cs42l42->regmap,
  865. CS42L42_CODEC_INT_MASK,
  866. CS42L42_PDN_DONE_MASK |
  867. CS42L42_HSDET_AUTO_DONE_MASK,
  868. (1 << CS42L42_PDN_DONE_SHIFT) |
  869. (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
  870. /* Set hs detect to automatic, disabled mode */
  871. regmap_update_bits(cs42l42->regmap,
  872. CS42L42_HSDET_CTL2,
  873. CS42L42_HSDET_CTRL_MASK |
  874. CS42L42_HSDET_SET_MASK |
  875. CS42L42_HSBIAS_REF_MASK |
  876. CS42L42_HSDET_AUTO_TIME_MASK,
  877. (2 << CS42L42_HSDET_CTRL_SHIFT) |
  878. (2 << CS42L42_HSDET_SET_SHIFT) |
  879. (0 << CS42L42_HSBIAS_REF_SHIFT) |
  880. (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
  881. /* Read and save the hs detection result */
  882. regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
  883. cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
  884. CS42L42_HSDET_TYPE_SHIFT;
  885. /* Set up button detection */
  886. if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
  887. (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
  888. /* Set auto HS bias settings to default */
  889. regmap_update_bits(cs42l42->regmap,
  890. CS42L42_HSBIAS_SC_AUTOCTL,
  891. CS42L42_HSBIAS_SENSE_EN_MASK |
  892. CS42L42_AUTO_HSBIAS_HIZ_MASK |
  893. CS42L42_TIP_SENSE_EN_MASK |
  894. CS42L42_HSBIAS_SENSE_TRIP_MASK,
  895. (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
  896. (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
  897. (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
  898. (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
  899. /* Set up hs detect level sensitivity */
  900. regmap_update_bits(cs42l42->regmap,
  901. CS42L42_MIC_DET_CTL1,
  902. CS42L42_LATCH_TO_VP_MASK |
  903. CS42L42_EVENT_STAT_SEL_MASK |
  904. CS42L42_HS_DET_LEVEL_MASK,
  905. (1 << CS42L42_LATCH_TO_VP_SHIFT) |
  906. (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
  907. (cs42l42->bias_thresholds[0] <<
  908. CS42L42_HS_DET_LEVEL_SHIFT));
  909. /* Set auto HS bias settings to default */
  910. regmap_update_bits(cs42l42->regmap,
  911. CS42L42_HSBIAS_SC_AUTOCTL,
  912. CS42L42_HSBIAS_SENSE_EN_MASK |
  913. CS42L42_AUTO_HSBIAS_HIZ_MASK |
  914. CS42L42_TIP_SENSE_EN_MASK |
  915. CS42L42_HSBIAS_SENSE_TRIP_MASK,
  916. (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
  917. (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
  918. (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
  919. (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
  920. /* Turn on level detect circuitry */
  921. regmap_update_bits(cs42l42->regmap,
  922. CS42L42_MISC_DET_CTL,
  923. CS42L42_DETECT_MODE_MASK |
  924. CS42L42_HSBIAS_CTL_MASK |
  925. CS42L42_PDN_MIC_LVL_DET_MASK,
  926. (0 << CS42L42_DETECT_MODE_SHIFT) |
  927. (3 << CS42L42_HSBIAS_CTL_SHIFT) |
  928. (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
  929. msleep(cs42l42->btn_det_init_dbnce);
  930. /* Clear any button interrupts before unmasking them */
  931. regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
  932. &int_status);
  933. /* Unmask button detect interrupts */
  934. regmap_update_bits(cs42l42->regmap,
  935. CS42L42_DET_INT2_MASK,
  936. CS42L42_M_DETECT_TF_MASK |
  937. CS42L42_M_DETECT_FT_MASK |
  938. CS42L42_M_HSBIAS_HIZ_MASK |
  939. CS42L42_M_SHORT_RLS_MASK |
  940. CS42L42_M_SHORT_DET_MASK,
  941. (0 << CS42L42_M_DETECT_TF_SHIFT) |
  942. (0 << CS42L42_M_DETECT_FT_SHIFT) |
  943. (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
  944. (1 << CS42L42_M_SHORT_RLS_SHIFT) |
  945. (1 << CS42L42_M_SHORT_DET_SHIFT));
  946. } else {
  947. /* Make sure button detect and HS bias circuits are off */
  948. regmap_update_bits(cs42l42->regmap,
  949. CS42L42_MISC_DET_CTL,
  950. CS42L42_DETECT_MODE_MASK |
  951. CS42L42_HSBIAS_CTL_MASK |
  952. CS42L42_PDN_MIC_LVL_DET_MASK,
  953. (0 << CS42L42_DETECT_MODE_SHIFT) |
  954. (1 << CS42L42_HSBIAS_CTL_SHIFT) |
  955. (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
  956. }
  957. regmap_update_bits(cs42l42->regmap,
  958. CS42L42_DAC_CTL2,
  959. CS42L42_HPOUT_PULLDOWN_MASK |
  960. CS42L42_HPOUT_LOAD_MASK |
  961. CS42L42_HPOUT_CLAMP_MASK |
  962. CS42L42_DAC_HPF_EN_MASK |
  963. CS42L42_DAC_MON_EN_MASK,
  964. (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
  965. (0 << CS42L42_HPOUT_LOAD_SHIFT) |
  966. (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
  967. (1 << CS42L42_DAC_HPF_EN_SHIFT) |
  968. (0 << CS42L42_DAC_MON_EN_SHIFT));
  969. /* Unmask tip sense interrupts */
  970. regmap_update_bits(cs42l42->regmap,
  971. CS42L42_TSRS_PLUG_INT_MASK,
  972. CS42L42_RS_PLUG_MASK |
  973. CS42L42_RS_UNPLUG_MASK |
  974. CS42L42_TS_PLUG_MASK |
  975. CS42L42_TS_UNPLUG_MASK,
  976. (1 << CS42L42_RS_PLUG_SHIFT) |
  977. (1 << CS42L42_RS_UNPLUG_SHIFT) |
  978. (0 << CS42L42_TS_PLUG_SHIFT) |
  979. (0 << CS42L42_TS_UNPLUG_SHIFT));
  980. }
  981. static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
  982. {
  983. /* Mask tip sense interrupts */
  984. regmap_update_bits(cs42l42->regmap,
  985. CS42L42_TSRS_PLUG_INT_MASK,
  986. CS42L42_RS_PLUG_MASK |
  987. CS42L42_RS_UNPLUG_MASK |
  988. CS42L42_TS_PLUG_MASK |
  989. CS42L42_TS_UNPLUG_MASK,
  990. (1 << CS42L42_RS_PLUG_SHIFT) |
  991. (1 << CS42L42_RS_UNPLUG_SHIFT) |
  992. (1 << CS42L42_TS_PLUG_SHIFT) |
  993. (1 << CS42L42_TS_UNPLUG_SHIFT));
  994. /* Make sure button detect and HS bias circuits are off */
  995. regmap_update_bits(cs42l42->regmap,
  996. CS42L42_MISC_DET_CTL,
  997. CS42L42_DETECT_MODE_MASK |
  998. CS42L42_HSBIAS_CTL_MASK |
  999. CS42L42_PDN_MIC_LVL_DET_MASK,
  1000. (0 << CS42L42_DETECT_MODE_SHIFT) |
  1001. (1 << CS42L42_HSBIAS_CTL_SHIFT) |
  1002. (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
  1003. /* Set auto HS bias settings to default */
  1004. regmap_update_bits(cs42l42->regmap,
  1005. CS42L42_HSBIAS_SC_AUTOCTL,
  1006. CS42L42_HSBIAS_SENSE_EN_MASK |
  1007. CS42L42_AUTO_HSBIAS_HIZ_MASK |
  1008. CS42L42_TIP_SENSE_EN_MASK |
  1009. CS42L42_HSBIAS_SENSE_TRIP_MASK,
  1010. (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
  1011. (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
  1012. (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
  1013. (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
  1014. /* Set hs detect to manual, disabled mode */
  1015. regmap_update_bits(cs42l42->regmap,
  1016. CS42L42_HSDET_CTL2,
  1017. CS42L42_HSDET_CTRL_MASK |
  1018. CS42L42_HSDET_SET_MASK |
  1019. CS42L42_HSBIAS_REF_MASK |
  1020. CS42L42_HSDET_AUTO_TIME_MASK,
  1021. (0 << CS42L42_HSDET_CTRL_SHIFT) |
  1022. (2 << CS42L42_HSDET_SET_SHIFT) |
  1023. (0 << CS42L42_HSBIAS_REF_SHIFT) |
  1024. (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
  1025. regmap_update_bits(cs42l42->regmap,
  1026. CS42L42_DAC_CTL2,
  1027. CS42L42_HPOUT_PULLDOWN_MASK |
  1028. CS42L42_HPOUT_LOAD_MASK |
  1029. CS42L42_HPOUT_CLAMP_MASK |
  1030. CS42L42_DAC_HPF_EN_MASK |
  1031. CS42L42_DAC_MON_EN_MASK,
  1032. (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
  1033. (0 << CS42L42_HPOUT_LOAD_SHIFT) |
  1034. (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
  1035. (1 << CS42L42_DAC_HPF_EN_SHIFT) |
  1036. (1 << CS42L42_DAC_MON_EN_SHIFT));
  1037. /* Power up HS bias to 2.7V */
  1038. regmap_update_bits(cs42l42->regmap,
  1039. CS42L42_MISC_DET_CTL,
  1040. CS42L42_DETECT_MODE_MASK |
  1041. CS42L42_HSBIAS_CTL_MASK |
  1042. CS42L42_PDN_MIC_LVL_DET_MASK,
  1043. (0 << CS42L42_DETECT_MODE_SHIFT) |
  1044. (3 << CS42L42_HSBIAS_CTL_SHIFT) |
  1045. (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
  1046. /* Wait for HS bias to ramp up */
  1047. msleep(cs42l42->hs_bias_ramp_time);
  1048. /* Unmask auto detect interrupt */
  1049. regmap_update_bits(cs42l42->regmap,
  1050. CS42L42_CODEC_INT_MASK,
  1051. CS42L42_PDN_DONE_MASK |
  1052. CS42L42_HSDET_AUTO_DONE_MASK,
  1053. (1 << CS42L42_PDN_DONE_SHIFT) |
  1054. (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
  1055. /* Set hs detect to automatic, enabled mode */
  1056. regmap_update_bits(cs42l42->regmap,
  1057. CS42L42_HSDET_CTL2,
  1058. CS42L42_HSDET_CTRL_MASK |
  1059. CS42L42_HSDET_SET_MASK |
  1060. CS42L42_HSBIAS_REF_MASK |
  1061. CS42L42_HSDET_AUTO_TIME_MASK,
  1062. (3 << CS42L42_HSDET_CTRL_SHIFT) |
  1063. (2 << CS42L42_HSDET_SET_SHIFT) |
  1064. (0 << CS42L42_HSBIAS_REF_SHIFT) |
  1065. (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
  1066. }
  1067. static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
  1068. {
  1069. /* Mask button detect interrupts */
  1070. regmap_update_bits(cs42l42->regmap,
  1071. CS42L42_DET_INT2_MASK,
  1072. CS42L42_M_DETECT_TF_MASK |
  1073. CS42L42_M_DETECT_FT_MASK |
  1074. CS42L42_M_HSBIAS_HIZ_MASK |
  1075. CS42L42_M_SHORT_RLS_MASK |
  1076. CS42L42_M_SHORT_DET_MASK,
  1077. (1 << CS42L42_M_DETECT_TF_SHIFT) |
  1078. (1 << CS42L42_M_DETECT_FT_SHIFT) |
  1079. (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
  1080. (1 << CS42L42_M_SHORT_RLS_SHIFT) |
  1081. (1 << CS42L42_M_SHORT_DET_SHIFT));
  1082. /* Ground HS bias */
  1083. regmap_update_bits(cs42l42->regmap,
  1084. CS42L42_MISC_DET_CTL,
  1085. CS42L42_DETECT_MODE_MASK |
  1086. CS42L42_HSBIAS_CTL_MASK |
  1087. CS42L42_PDN_MIC_LVL_DET_MASK,
  1088. (0 << CS42L42_DETECT_MODE_SHIFT) |
  1089. (1 << CS42L42_HSBIAS_CTL_SHIFT) |
  1090. (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
  1091. /* Set auto HS bias settings to default */
  1092. regmap_update_bits(cs42l42->regmap,
  1093. CS42L42_HSBIAS_SC_AUTOCTL,
  1094. CS42L42_HSBIAS_SENSE_EN_MASK |
  1095. CS42L42_AUTO_HSBIAS_HIZ_MASK |
  1096. CS42L42_TIP_SENSE_EN_MASK |
  1097. CS42L42_HSBIAS_SENSE_TRIP_MASK,
  1098. (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
  1099. (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
  1100. (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
  1101. (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
  1102. /* Set hs detect to manual, disabled mode */
  1103. regmap_update_bits(cs42l42->regmap,
  1104. CS42L42_HSDET_CTL2,
  1105. CS42L42_HSDET_CTRL_MASK |
  1106. CS42L42_HSDET_SET_MASK |
  1107. CS42L42_HSBIAS_REF_MASK |
  1108. CS42L42_HSDET_AUTO_TIME_MASK,
  1109. (0 << CS42L42_HSDET_CTRL_SHIFT) |
  1110. (2 << CS42L42_HSDET_SET_SHIFT) |
  1111. (0 << CS42L42_HSBIAS_REF_SHIFT) |
  1112. (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
  1113. }
  1114. static void cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
  1115. {
  1116. int bias_level;
  1117. unsigned int detect_status;
  1118. /* Mask button detect interrupts */
  1119. regmap_update_bits(cs42l42->regmap,
  1120. CS42L42_DET_INT2_MASK,
  1121. CS42L42_M_DETECT_TF_MASK |
  1122. CS42L42_M_DETECT_FT_MASK |
  1123. CS42L42_M_HSBIAS_HIZ_MASK |
  1124. CS42L42_M_SHORT_RLS_MASK |
  1125. CS42L42_M_SHORT_DET_MASK,
  1126. (1 << CS42L42_M_DETECT_TF_SHIFT) |
  1127. (1 << CS42L42_M_DETECT_FT_SHIFT) |
  1128. (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
  1129. (1 << CS42L42_M_SHORT_RLS_SHIFT) |
  1130. (1 << CS42L42_M_SHORT_DET_SHIFT));
  1131. usleep_range(cs42l42->btn_det_event_dbnce * 1000,
  1132. cs42l42->btn_det_event_dbnce * 2000);
  1133. /* Test all 4 level detect biases */
  1134. bias_level = 1;
  1135. do {
  1136. /* Adjust button detect level sensitivity */
  1137. regmap_update_bits(cs42l42->regmap,
  1138. CS42L42_MIC_DET_CTL1,
  1139. CS42L42_LATCH_TO_VP_MASK |
  1140. CS42L42_EVENT_STAT_SEL_MASK |
  1141. CS42L42_HS_DET_LEVEL_MASK,
  1142. (1 << CS42L42_LATCH_TO_VP_SHIFT) |
  1143. (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
  1144. (cs42l42->bias_thresholds[bias_level] <<
  1145. CS42L42_HS_DET_LEVEL_SHIFT));
  1146. regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
  1147. &detect_status);
  1148. } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
  1149. (++bias_level < CS42L42_NUM_BIASES));
  1150. switch (bias_level) {
  1151. case 1: /* Function C button press */
  1152. dev_dbg(cs42l42->component->dev, "Function C button press\n");
  1153. break;
  1154. case 2: /* Function B button press */
  1155. dev_dbg(cs42l42->component->dev, "Function B button press\n");
  1156. break;
  1157. case 3: /* Function D button press */
  1158. dev_dbg(cs42l42->component->dev, "Function D button press\n");
  1159. break;
  1160. case 4: /* Function A button press */
  1161. dev_dbg(cs42l42->component->dev, "Function A button press\n");
  1162. break;
  1163. }
  1164. /* Set button detect level sensitivity back to default */
  1165. regmap_update_bits(cs42l42->regmap,
  1166. CS42L42_MIC_DET_CTL1,
  1167. CS42L42_LATCH_TO_VP_MASK |
  1168. CS42L42_EVENT_STAT_SEL_MASK |
  1169. CS42L42_HS_DET_LEVEL_MASK,
  1170. (1 << CS42L42_LATCH_TO_VP_SHIFT) |
  1171. (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
  1172. (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
  1173. /* Clear any button interrupts before unmasking them */
  1174. regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
  1175. &detect_status);
  1176. /* Unmask button detect interrupts */
  1177. regmap_update_bits(cs42l42->regmap,
  1178. CS42L42_DET_INT2_MASK,
  1179. CS42L42_M_DETECT_TF_MASK |
  1180. CS42L42_M_DETECT_FT_MASK |
  1181. CS42L42_M_HSBIAS_HIZ_MASK |
  1182. CS42L42_M_SHORT_RLS_MASK |
  1183. CS42L42_M_SHORT_DET_MASK,
  1184. (0 << CS42L42_M_DETECT_TF_SHIFT) |
  1185. (0 << CS42L42_M_DETECT_FT_SHIFT) |
  1186. (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
  1187. (1 << CS42L42_M_SHORT_RLS_SHIFT) |
  1188. (1 << CS42L42_M_SHORT_DET_SHIFT));
  1189. }
  1190. struct cs42l42_irq_params {
  1191. u16 status_addr;
  1192. u16 mask_addr;
  1193. u8 mask;
  1194. };
  1195. static const struct cs42l42_irq_params irq_params_table[] = {
  1196. {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
  1197. CS42L42_ADC_OVFL_VAL_MASK},
  1198. {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
  1199. CS42L42_MIXER_VAL_MASK},
  1200. {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
  1201. CS42L42_SRC_VAL_MASK},
  1202. {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
  1203. CS42L42_ASP_RX_VAL_MASK},
  1204. {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
  1205. CS42L42_ASP_TX_VAL_MASK},
  1206. {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
  1207. CS42L42_CODEC_VAL_MASK},
  1208. {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
  1209. CS42L42_DET_INT_VAL1_MASK},
  1210. {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
  1211. CS42L42_DET_INT_VAL2_MASK},
  1212. {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
  1213. CS42L42_SRCPL_VAL_MASK},
  1214. {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
  1215. CS42L42_VPMON_VAL_MASK},
  1216. {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
  1217. CS42L42_PLL_LOCK_VAL_MASK},
  1218. {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
  1219. CS42L42_TSRS_PLUG_VAL_MASK}
  1220. };
  1221. static irqreturn_t cs42l42_irq_thread(int irq, void *data)
  1222. {
  1223. struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
  1224. struct snd_soc_component *component = cs42l42->component;
  1225. unsigned int stickies[12];
  1226. unsigned int masks[12];
  1227. unsigned int current_plug_status;
  1228. unsigned int current_button_status;
  1229. unsigned int i;
  1230. /* Read sticky registers to clear interurpt */
  1231. for (i = 0; i < ARRAY_SIZE(stickies); i++) {
  1232. regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
  1233. &(stickies[i]));
  1234. regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
  1235. &(masks[i]));
  1236. stickies[i] = stickies[i] & (~masks[i]) &
  1237. irq_params_table[i].mask;
  1238. }
  1239. /* Read tip sense status before handling type detect */
  1240. current_plug_status = (stickies[11] &
  1241. (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
  1242. CS42L42_TS_PLUG_SHIFT;
  1243. /* Read button sense status */
  1244. current_button_status = stickies[7] &
  1245. (CS42L42_M_DETECT_TF_MASK |
  1246. CS42L42_M_DETECT_FT_MASK |
  1247. CS42L42_M_HSBIAS_HIZ_MASK);
  1248. /* Check auto-detect status */
  1249. if ((~masks[5]) & irq_params_table[5].mask) {
  1250. if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
  1251. cs42l42_process_hs_type_detect(cs42l42);
  1252. dev_dbg(component->dev,
  1253. "Auto detect done (%d)\n",
  1254. cs42l42->hs_type);
  1255. }
  1256. }
  1257. /* Check tip sense status */
  1258. if ((~masks[11]) & irq_params_table[11].mask) {
  1259. switch (current_plug_status) {
  1260. case CS42L42_TS_PLUG:
  1261. if (cs42l42->plug_state != CS42L42_TS_PLUG) {
  1262. cs42l42->plug_state = CS42L42_TS_PLUG;
  1263. cs42l42_init_hs_type_detect(cs42l42);
  1264. }
  1265. break;
  1266. case CS42L42_TS_UNPLUG:
  1267. if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
  1268. cs42l42->plug_state = CS42L42_TS_UNPLUG;
  1269. cs42l42_cancel_hs_type_detect(cs42l42);
  1270. dev_dbg(component->dev,
  1271. "Unplug event\n");
  1272. }
  1273. break;
  1274. default:
  1275. if (cs42l42->plug_state != CS42L42_TS_TRANS)
  1276. cs42l42->plug_state = CS42L42_TS_TRANS;
  1277. }
  1278. }
  1279. /* Check button detect status */
  1280. if ((~masks[7]) & irq_params_table[7].mask) {
  1281. if (!(current_button_status &
  1282. CS42L42_M_HSBIAS_HIZ_MASK)) {
  1283. if (current_button_status &
  1284. CS42L42_M_DETECT_TF_MASK) {
  1285. dev_dbg(component->dev,
  1286. "Button released\n");
  1287. } else if (current_button_status &
  1288. CS42L42_M_DETECT_FT_MASK) {
  1289. cs42l42_handle_button_press(cs42l42);
  1290. }
  1291. }
  1292. }
  1293. return IRQ_HANDLED;
  1294. }
  1295. static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
  1296. {
  1297. regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
  1298. CS42L42_ADC_OVFL_MASK,
  1299. (1 << CS42L42_ADC_OVFL_SHIFT));
  1300. regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
  1301. CS42L42_MIX_CHB_OVFL_MASK |
  1302. CS42L42_MIX_CHA_OVFL_MASK |
  1303. CS42L42_EQ_OVFL_MASK |
  1304. CS42L42_EQ_BIQUAD_OVFL_MASK,
  1305. (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
  1306. (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
  1307. (1 << CS42L42_EQ_OVFL_SHIFT) |
  1308. (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
  1309. regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
  1310. CS42L42_SRC_ILK_MASK |
  1311. CS42L42_SRC_OLK_MASK |
  1312. CS42L42_SRC_IUNLK_MASK |
  1313. CS42L42_SRC_OUNLK_MASK,
  1314. (1 << CS42L42_SRC_ILK_SHIFT) |
  1315. (1 << CS42L42_SRC_OLK_SHIFT) |
  1316. (1 << CS42L42_SRC_IUNLK_SHIFT) |
  1317. (1 << CS42L42_SRC_OUNLK_SHIFT));
  1318. regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
  1319. CS42L42_ASPRX_NOLRCK_MASK |
  1320. CS42L42_ASPRX_EARLY_MASK |
  1321. CS42L42_ASPRX_LATE_MASK |
  1322. CS42L42_ASPRX_ERROR_MASK |
  1323. CS42L42_ASPRX_OVLD_MASK,
  1324. (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
  1325. (1 << CS42L42_ASPRX_EARLY_SHIFT) |
  1326. (1 << CS42L42_ASPRX_LATE_SHIFT) |
  1327. (1 << CS42L42_ASPRX_ERROR_SHIFT) |
  1328. (1 << CS42L42_ASPRX_OVLD_SHIFT));
  1329. regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
  1330. CS42L42_ASPTX_NOLRCK_MASK |
  1331. CS42L42_ASPTX_EARLY_MASK |
  1332. CS42L42_ASPTX_LATE_MASK |
  1333. CS42L42_ASPTX_SMERROR_MASK,
  1334. (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
  1335. (1 << CS42L42_ASPTX_EARLY_SHIFT) |
  1336. (1 << CS42L42_ASPTX_LATE_SHIFT) |
  1337. (1 << CS42L42_ASPTX_SMERROR_SHIFT));
  1338. regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
  1339. CS42L42_PDN_DONE_MASK |
  1340. CS42L42_HSDET_AUTO_DONE_MASK,
  1341. (1 << CS42L42_PDN_DONE_SHIFT) |
  1342. (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
  1343. regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
  1344. CS42L42_SRCPL_ADC_LK_MASK |
  1345. CS42L42_SRCPL_DAC_LK_MASK |
  1346. CS42L42_SRCPL_ADC_UNLK_MASK |
  1347. CS42L42_SRCPL_DAC_UNLK_MASK,
  1348. (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
  1349. (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
  1350. (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
  1351. (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
  1352. regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
  1353. CS42L42_TIP_SENSE_UNPLUG_MASK |
  1354. CS42L42_TIP_SENSE_PLUG_MASK |
  1355. CS42L42_HSBIAS_SENSE_MASK,
  1356. (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
  1357. (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
  1358. (1 << CS42L42_HSBIAS_SENSE_SHIFT));
  1359. regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
  1360. CS42L42_M_DETECT_TF_MASK |
  1361. CS42L42_M_DETECT_FT_MASK |
  1362. CS42L42_M_HSBIAS_HIZ_MASK |
  1363. CS42L42_M_SHORT_RLS_MASK |
  1364. CS42L42_M_SHORT_DET_MASK,
  1365. (1 << CS42L42_M_DETECT_TF_SHIFT) |
  1366. (1 << CS42L42_M_DETECT_FT_SHIFT) |
  1367. (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
  1368. (1 << CS42L42_M_SHORT_RLS_SHIFT) |
  1369. (1 << CS42L42_M_SHORT_DET_SHIFT));
  1370. regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
  1371. CS42L42_VPMON_MASK,
  1372. (1 << CS42L42_VPMON_SHIFT));
  1373. regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
  1374. CS42L42_PLL_LOCK_MASK,
  1375. (1 << CS42L42_PLL_LOCK_SHIFT));
  1376. regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
  1377. CS42L42_RS_PLUG_MASK |
  1378. CS42L42_RS_UNPLUG_MASK |
  1379. CS42L42_TS_PLUG_MASK |
  1380. CS42L42_TS_UNPLUG_MASK,
  1381. (1 << CS42L42_RS_PLUG_SHIFT) |
  1382. (1 << CS42L42_RS_UNPLUG_SHIFT) |
  1383. (0 << CS42L42_TS_PLUG_SHIFT) |
  1384. (0 << CS42L42_TS_UNPLUG_SHIFT));
  1385. }
  1386. static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
  1387. {
  1388. unsigned int reg;
  1389. cs42l42->hs_type = CS42L42_PLUG_INVALID;
  1390. /* Latch analog controls to VP power domain */
  1391. regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
  1392. CS42L42_LATCH_TO_VP_MASK |
  1393. CS42L42_EVENT_STAT_SEL_MASK |
  1394. CS42L42_HS_DET_LEVEL_MASK,
  1395. (1 << CS42L42_LATCH_TO_VP_SHIFT) |
  1396. (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
  1397. (cs42l42->bias_thresholds[0] <<
  1398. CS42L42_HS_DET_LEVEL_SHIFT));
  1399. /* Remove ground noise-suppression clamps */
  1400. regmap_update_bits(cs42l42->regmap,
  1401. CS42L42_HS_CLAMP_DISABLE,
  1402. CS42L42_HS_CLAMP_DISABLE_MASK,
  1403. (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
  1404. /* Enable the tip sense circuit */
  1405. regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
  1406. CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
  1407. regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
  1408. CS42L42_TIP_SENSE_CTRL_MASK |
  1409. CS42L42_TIP_SENSE_INV_MASK |
  1410. CS42L42_TIP_SENSE_DEBOUNCE_MASK,
  1411. (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
  1412. (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
  1413. (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
  1414. /* Save the initial status of the tip sense */
  1415. regmap_read(cs42l42->regmap,
  1416. CS42L42_TSRS_PLUG_STATUS,
  1417. &reg);
  1418. cs42l42->plug_state = (((char) reg) &
  1419. (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
  1420. CS42L42_TS_PLUG_SHIFT;
  1421. }
  1422. static const unsigned int threshold_defaults[] = {
  1423. CS42L42_HS_DET_LEVEL_15,
  1424. CS42L42_HS_DET_LEVEL_8,
  1425. CS42L42_HS_DET_LEVEL_4,
  1426. CS42L42_HS_DET_LEVEL_1
  1427. };
  1428. static int cs42l42_handle_device_data(struct device *dev,
  1429. struct cs42l42_private *cs42l42)
  1430. {
  1431. unsigned int val;
  1432. u32 thresholds[CS42L42_NUM_BIASES];
  1433. int ret;
  1434. int i;
  1435. ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
  1436. if (!ret) {
  1437. switch (val) {
  1438. case CS42L42_TS_INV_EN:
  1439. case CS42L42_TS_INV_DIS:
  1440. cs42l42->ts_inv = val;
  1441. break;
  1442. default:
  1443. dev_err(dev,
  1444. "Wrong cirrus,ts-inv DT value %d\n",
  1445. val);
  1446. cs42l42->ts_inv = CS42L42_TS_INV_DIS;
  1447. }
  1448. } else {
  1449. cs42l42->ts_inv = CS42L42_TS_INV_DIS;
  1450. }
  1451. ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
  1452. if (!ret) {
  1453. switch (val) {
  1454. case CS42L42_TS_DBNCE_0:
  1455. case CS42L42_TS_DBNCE_125:
  1456. case CS42L42_TS_DBNCE_250:
  1457. case CS42L42_TS_DBNCE_500:
  1458. case CS42L42_TS_DBNCE_750:
  1459. case CS42L42_TS_DBNCE_1000:
  1460. case CS42L42_TS_DBNCE_1250:
  1461. case CS42L42_TS_DBNCE_1500:
  1462. cs42l42->ts_dbnc_rise = val;
  1463. break;
  1464. default:
  1465. dev_err(dev,
  1466. "Wrong cirrus,ts-dbnc-rise DT value %d\n",
  1467. val);
  1468. cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
  1469. }
  1470. } else {
  1471. cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
  1472. }
  1473. regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
  1474. CS42L42_TS_RISE_DBNCE_TIME_MASK,
  1475. (cs42l42->ts_dbnc_rise <<
  1476. CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
  1477. ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
  1478. if (!ret) {
  1479. switch (val) {
  1480. case CS42L42_TS_DBNCE_0:
  1481. case CS42L42_TS_DBNCE_125:
  1482. case CS42L42_TS_DBNCE_250:
  1483. case CS42L42_TS_DBNCE_500:
  1484. case CS42L42_TS_DBNCE_750:
  1485. case CS42L42_TS_DBNCE_1000:
  1486. case CS42L42_TS_DBNCE_1250:
  1487. case CS42L42_TS_DBNCE_1500:
  1488. cs42l42->ts_dbnc_fall = val;
  1489. break;
  1490. default:
  1491. dev_err(dev,
  1492. "Wrong cirrus,ts-dbnc-fall DT value %d\n",
  1493. val);
  1494. cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
  1495. }
  1496. } else {
  1497. cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
  1498. }
  1499. regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
  1500. CS42L42_TS_FALL_DBNCE_TIME_MASK,
  1501. (cs42l42->ts_dbnc_fall <<
  1502. CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
  1503. ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
  1504. if (!ret) {
  1505. if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
  1506. cs42l42->btn_det_init_dbnce = val;
  1507. else {
  1508. dev_err(dev,
  1509. "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
  1510. val);
  1511. cs42l42->btn_det_init_dbnce =
  1512. CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
  1513. }
  1514. } else {
  1515. cs42l42->btn_det_init_dbnce =
  1516. CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
  1517. }
  1518. ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
  1519. if (!ret) {
  1520. if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
  1521. cs42l42->btn_det_event_dbnce = val;
  1522. else {
  1523. dev_err(dev,
  1524. "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
  1525. cs42l42->btn_det_event_dbnce =
  1526. CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
  1527. }
  1528. } else {
  1529. cs42l42->btn_det_event_dbnce =
  1530. CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
  1531. }
  1532. ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
  1533. thresholds, ARRAY_SIZE(thresholds));
  1534. if (!ret) {
  1535. for (i = 0; i < CS42L42_NUM_BIASES; i++) {
  1536. if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
  1537. cs42l42->bias_thresholds[i] = thresholds[i];
  1538. else {
  1539. dev_err(dev,
  1540. "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
  1541. thresholds[i]);
  1542. cs42l42->bias_thresholds[i] = threshold_defaults[i];
  1543. }
  1544. }
  1545. } else {
  1546. for (i = 0; i < CS42L42_NUM_BIASES; i++)
  1547. cs42l42->bias_thresholds[i] = threshold_defaults[i];
  1548. }
  1549. ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
  1550. if (!ret) {
  1551. switch (val) {
  1552. case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
  1553. cs42l42->hs_bias_ramp_rate = val;
  1554. cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
  1555. break;
  1556. case CS42L42_HSBIAS_RAMP_FAST:
  1557. cs42l42->hs_bias_ramp_rate = val;
  1558. cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
  1559. break;
  1560. case CS42L42_HSBIAS_RAMP_SLOW:
  1561. cs42l42->hs_bias_ramp_rate = val;
  1562. cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
  1563. break;
  1564. case CS42L42_HSBIAS_RAMP_SLOWEST:
  1565. cs42l42->hs_bias_ramp_rate = val;
  1566. cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
  1567. break;
  1568. default:
  1569. dev_err(dev,
  1570. "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
  1571. val);
  1572. cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
  1573. cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
  1574. }
  1575. } else {
  1576. cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
  1577. cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
  1578. }
  1579. regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
  1580. CS42L42_HSBIAS_RAMP_MASK,
  1581. (cs42l42->hs_bias_ramp_rate <<
  1582. CS42L42_HSBIAS_RAMP_SHIFT));
  1583. return 0;
  1584. }
  1585. static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
  1586. const struct i2c_device_id *id)
  1587. {
  1588. struct cs42l42_private *cs42l42;
  1589. int ret, i;
  1590. unsigned int devid = 0;
  1591. unsigned int reg;
  1592. cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
  1593. GFP_KERNEL);
  1594. if (!cs42l42)
  1595. return -ENOMEM;
  1596. i2c_set_clientdata(i2c_client, cs42l42);
  1597. cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
  1598. if (IS_ERR(cs42l42->regmap)) {
  1599. ret = PTR_ERR(cs42l42->regmap);
  1600. dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
  1601. return ret;
  1602. }
  1603. for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
  1604. cs42l42->supplies[i].supply = cs42l42_supply_names[i];
  1605. ret = devm_regulator_bulk_get(&i2c_client->dev,
  1606. ARRAY_SIZE(cs42l42->supplies),
  1607. cs42l42->supplies);
  1608. if (ret != 0) {
  1609. dev_err(&i2c_client->dev,
  1610. "Failed to request supplies: %d\n", ret);
  1611. return ret;
  1612. }
  1613. ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
  1614. cs42l42->supplies);
  1615. if (ret != 0) {
  1616. dev_err(&i2c_client->dev,
  1617. "Failed to enable supplies: %d\n", ret);
  1618. return ret;
  1619. }
  1620. /* Reset the Device */
  1621. cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
  1622. "reset", GPIOD_OUT_LOW);
  1623. if (IS_ERR(cs42l42->reset_gpio)) {
  1624. ret = PTR_ERR(cs42l42->reset_gpio);
  1625. goto err_disable;
  1626. }
  1627. if (cs42l42->reset_gpio) {
  1628. dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
  1629. gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
  1630. }
  1631. usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
  1632. /* Request IRQ */
  1633. ret = devm_request_threaded_irq(&i2c_client->dev,
  1634. i2c_client->irq,
  1635. NULL, cs42l42_irq_thread,
  1636. IRQF_ONESHOT | IRQF_TRIGGER_LOW,
  1637. "cs42l42", cs42l42);
  1638. if (ret == -EPROBE_DEFER)
  1639. goto err_disable;
  1640. else if (ret != 0)
  1641. dev_err(&i2c_client->dev,
  1642. "Failed to request IRQ: %d\n", ret);
  1643. /* initialize codec */
  1644. ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, &reg);
  1645. devid = (reg & 0xFF) << 12;
  1646. ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, &reg);
  1647. devid |= (reg & 0xFF) << 4;
  1648. ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, &reg);
  1649. devid |= (reg & 0xF0) >> 4;
  1650. if (devid != CS42L42_CHIP_ID) {
  1651. ret = -ENODEV;
  1652. dev_err(&i2c_client->dev,
  1653. "CS42L42 Device ID (%X). Expected %X\n",
  1654. devid, CS42L42_CHIP_ID);
  1655. goto err_disable;
  1656. }
  1657. ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
  1658. if (ret < 0) {
  1659. dev_err(&i2c_client->dev, "Get Revision ID failed\n");
  1660. goto err_disable;
  1661. }
  1662. dev_info(&i2c_client->dev,
  1663. "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
  1664. /* Power up the codec */
  1665. regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
  1666. CS42L42_ASP_DAO_PDN_MASK |
  1667. CS42L42_ASP_DAI_PDN_MASK |
  1668. CS42L42_MIXER_PDN_MASK |
  1669. CS42L42_EQ_PDN_MASK |
  1670. CS42L42_HP_PDN_MASK |
  1671. CS42L42_ADC_PDN_MASK |
  1672. CS42L42_PDN_ALL_MASK,
  1673. (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
  1674. (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
  1675. (1 << CS42L42_MIXER_PDN_SHIFT) |
  1676. (1 << CS42L42_EQ_PDN_SHIFT) |
  1677. (1 << CS42L42_HP_PDN_SHIFT) |
  1678. (1 << CS42L42_ADC_PDN_SHIFT) |
  1679. (0 << CS42L42_PDN_ALL_SHIFT));
  1680. ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42);
  1681. if (ret != 0)
  1682. goto err_disable;
  1683. /* Setup headset detection */
  1684. cs42l42_setup_hs_type_detect(cs42l42);
  1685. /* Mask/Unmask Interrupts */
  1686. cs42l42_set_interrupt_masks(cs42l42);
  1687. /* Register codec for machine driver */
  1688. ret = devm_snd_soc_register_component(&i2c_client->dev,
  1689. &soc_component_dev_cs42l42, &cs42l42_dai, 1);
  1690. if (ret < 0)
  1691. goto err_disable;
  1692. return 0;
  1693. err_disable:
  1694. regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
  1695. cs42l42->supplies);
  1696. return ret;
  1697. }
  1698. static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
  1699. {
  1700. struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
  1701. /* Hold down reset */
  1702. gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
  1703. return 0;
  1704. }
  1705. #ifdef CONFIG_PM
  1706. static int cs42l42_runtime_suspend(struct device *dev)
  1707. {
  1708. struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
  1709. regcache_cache_only(cs42l42->regmap, true);
  1710. regcache_mark_dirty(cs42l42->regmap);
  1711. /* Hold down reset */
  1712. gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
  1713. /* remove power */
  1714. regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
  1715. cs42l42->supplies);
  1716. return 0;
  1717. }
  1718. static int cs42l42_runtime_resume(struct device *dev)
  1719. {
  1720. struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
  1721. int ret;
  1722. /* Enable power */
  1723. ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
  1724. cs42l42->supplies);
  1725. if (ret != 0) {
  1726. dev_err(dev, "Failed to enable supplies: %d\n",
  1727. ret);
  1728. return ret;
  1729. }
  1730. gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
  1731. usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
  1732. regcache_cache_only(cs42l42->regmap, false);
  1733. regcache_sync(cs42l42->regmap);
  1734. return 0;
  1735. }
  1736. #endif
  1737. static const struct dev_pm_ops cs42l42_runtime_pm = {
  1738. SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
  1739. NULL)
  1740. };
  1741. static const struct of_device_id cs42l42_of_match[] = {
  1742. { .compatible = "cirrus,cs42l42", },
  1743. {},
  1744. };
  1745. MODULE_DEVICE_TABLE(of, cs42l42_of_match);
  1746. static const struct i2c_device_id cs42l42_id[] = {
  1747. {"cs42l42", 0},
  1748. {}
  1749. };
  1750. MODULE_DEVICE_TABLE(i2c, cs42l42_id);
  1751. static struct i2c_driver cs42l42_i2c_driver = {
  1752. .driver = {
  1753. .name = "cs42l42",
  1754. .pm = &cs42l42_runtime_pm,
  1755. .of_match_table = cs42l42_of_match,
  1756. },
  1757. .id_table = cs42l42_id,
  1758. .probe = cs42l42_i2c_probe,
  1759. .remove = cs42l42_i2c_remove,
  1760. };
  1761. module_i2c_driver(cs42l42_i2c_driver);
  1762. MODULE_DESCRIPTION("ASoC CS42L42 driver");
  1763. MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
  1764. MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
  1765. MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
  1766. MODULE_LICENSE("GPL");