cs4271.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * CS4271 ASoC codec driver
  4. *
  5. * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
  6. *
  7. * This driver support CS4271 codec being master or slave, working
  8. * in control port mode, connected either via SPI or I2C.
  9. * The data format accepted is I2S or left-justified.
  10. * DAPM support not implemented.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/slab.h>
  14. #include <linux/delay.h>
  15. #include <linux/gpio.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <sound/pcm.h>
  21. #include <sound/soc.h>
  22. #include <sound/tlv.h>
  23. #include <sound/cs4271.h>
  24. #include "cs4271.h"
  25. #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  26. SNDRV_PCM_FMTBIT_S24_LE | \
  27. SNDRV_PCM_FMTBIT_S32_LE)
  28. #define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000
  29. /*
  30. * CS4271 registers
  31. */
  32. #define CS4271_MODE1 0x01 /* Mode Control 1 */
  33. #define CS4271_DACCTL 0x02 /* DAC Control */
  34. #define CS4271_DACVOL 0x03 /* DAC Volume & Mixing Control */
  35. #define CS4271_VOLA 0x04 /* DAC Channel A Volume Control */
  36. #define CS4271_VOLB 0x05 /* DAC Channel B Volume Control */
  37. #define CS4271_ADCCTL 0x06 /* ADC Control */
  38. #define CS4271_MODE2 0x07 /* Mode Control 2 */
  39. #define CS4271_CHIPID 0x08 /* Chip ID */
  40. #define CS4271_FIRSTREG CS4271_MODE1
  41. #define CS4271_LASTREG CS4271_MODE2
  42. #define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1)
  43. /* Bit masks for the CS4271 registers */
  44. #define CS4271_MODE1_MODE_MASK 0xC0
  45. #define CS4271_MODE1_MODE_1X 0x00
  46. #define CS4271_MODE1_MODE_2X 0x80
  47. #define CS4271_MODE1_MODE_4X 0xC0
  48. #define CS4271_MODE1_DIV_MASK 0x30
  49. #define CS4271_MODE1_DIV_1 0x00
  50. #define CS4271_MODE1_DIV_15 0x10
  51. #define CS4271_MODE1_DIV_2 0x20
  52. #define CS4271_MODE1_DIV_3 0x30
  53. #define CS4271_MODE1_MASTER 0x08
  54. #define CS4271_MODE1_DAC_DIF_MASK 0x07
  55. #define CS4271_MODE1_DAC_DIF_LJ 0x00
  56. #define CS4271_MODE1_DAC_DIF_I2S 0x01
  57. #define CS4271_MODE1_DAC_DIF_RJ16 0x02
  58. #define CS4271_MODE1_DAC_DIF_RJ24 0x03
  59. #define CS4271_MODE1_DAC_DIF_RJ20 0x04
  60. #define CS4271_MODE1_DAC_DIF_RJ18 0x05
  61. #define CS4271_DACCTL_AMUTE 0x80
  62. #define CS4271_DACCTL_IF_SLOW 0x40
  63. #define CS4271_DACCTL_DEM_MASK 0x30
  64. #define CS4271_DACCTL_DEM_DIS 0x00
  65. #define CS4271_DACCTL_DEM_441 0x10
  66. #define CS4271_DACCTL_DEM_48 0x20
  67. #define CS4271_DACCTL_DEM_32 0x30
  68. #define CS4271_DACCTL_SVRU 0x08
  69. #define CS4271_DACCTL_SRD 0x04
  70. #define CS4271_DACCTL_INVA 0x02
  71. #define CS4271_DACCTL_INVB 0x01
  72. #define CS4271_DACVOL_BEQUA 0x40
  73. #define CS4271_DACVOL_SOFT 0x20
  74. #define CS4271_DACVOL_ZEROC 0x10
  75. #define CS4271_DACVOL_ATAPI_MASK 0x0F
  76. #define CS4271_DACVOL_ATAPI_M_M 0x00
  77. #define CS4271_DACVOL_ATAPI_M_BR 0x01
  78. #define CS4271_DACVOL_ATAPI_M_BL 0x02
  79. #define CS4271_DACVOL_ATAPI_M_BLR2 0x03
  80. #define CS4271_DACVOL_ATAPI_AR_M 0x04
  81. #define CS4271_DACVOL_ATAPI_AR_BR 0x05
  82. #define CS4271_DACVOL_ATAPI_AR_BL 0x06
  83. #define CS4271_DACVOL_ATAPI_AR_BLR2 0x07
  84. #define CS4271_DACVOL_ATAPI_AL_M 0x08
  85. #define CS4271_DACVOL_ATAPI_AL_BR 0x09
  86. #define CS4271_DACVOL_ATAPI_AL_BL 0x0A
  87. #define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B
  88. #define CS4271_DACVOL_ATAPI_ALR2_M 0x0C
  89. #define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D
  90. #define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E
  91. #define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F
  92. #define CS4271_VOLA_MUTE 0x80
  93. #define CS4271_VOLA_VOL_MASK 0x7F
  94. #define CS4271_VOLB_MUTE 0x80
  95. #define CS4271_VOLB_VOL_MASK 0x7F
  96. #define CS4271_ADCCTL_DITHER16 0x20
  97. #define CS4271_ADCCTL_ADC_DIF_MASK 0x10
  98. #define CS4271_ADCCTL_ADC_DIF_LJ 0x00
  99. #define CS4271_ADCCTL_ADC_DIF_I2S 0x10
  100. #define CS4271_ADCCTL_MUTEA 0x08
  101. #define CS4271_ADCCTL_MUTEB 0x04
  102. #define CS4271_ADCCTL_HPFDA 0x02
  103. #define CS4271_ADCCTL_HPFDB 0x01
  104. #define CS4271_MODE2_LOOP 0x10
  105. #define CS4271_MODE2_MUTECAEQUB 0x08
  106. #define CS4271_MODE2_FREEZE 0x04
  107. #define CS4271_MODE2_CPEN 0x02
  108. #define CS4271_MODE2_PDN 0x01
  109. #define CS4271_CHIPID_PART_MASK 0xF0
  110. #define CS4271_CHIPID_REV_MASK 0x0F
  111. /*
  112. * Default CS4271 power-up configuration
  113. * Array contains non-existing in hw register at address 0
  114. * Array do not include Chip ID, as codec driver does not use
  115. * registers read operations at all
  116. */
  117. static const struct reg_default cs4271_reg_defaults[] = {
  118. { CS4271_MODE1, 0, },
  119. { CS4271_DACCTL, CS4271_DACCTL_AMUTE, },
  120. { CS4271_DACVOL, CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, },
  121. { CS4271_VOLA, 0, },
  122. { CS4271_VOLB, 0, },
  123. { CS4271_ADCCTL, 0, },
  124. { CS4271_MODE2, 0, },
  125. };
  126. static bool cs4271_volatile_reg(struct device *dev, unsigned int reg)
  127. {
  128. return reg == CS4271_CHIPID;
  129. }
  130. static const char * const supply_names[] = {
  131. "vd", "vl", "va"
  132. };
  133. struct cs4271_private {
  134. unsigned int mclk;
  135. bool master;
  136. bool deemph;
  137. struct regmap *regmap;
  138. /* Current sample rate for de-emphasis control */
  139. int rate;
  140. /* GPIO driving Reset pin, if any */
  141. int gpio_nreset;
  142. /* GPIO that disable serial bus, if any */
  143. int gpio_disable;
  144. /* enable soft reset workaround */
  145. bool enable_soft_reset;
  146. struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  147. };
  148. static const struct snd_soc_dapm_widget cs4271_dapm_widgets[] = {
  149. SND_SOC_DAPM_INPUT("AINA"),
  150. SND_SOC_DAPM_INPUT("AINB"),
  151. SND_SOC_DAPM_OUTPUT("AOUTA+"),
  152. SND_SOC_DAPM_OUTPUT("AOUTA-"),
  153. SND_SOC_DAPM_OUTPUT("AOUTB+"),
  154. SND_SOC_DAPM_OUTPUT("AOUTB-"),
  155. };
  156. static const struct snd_soc_dapm_route cs4271_dapm_routes[] = {
  157. { "Capture", NULL, "AINA" },
  158. { "Capture", NULL, "AINB" },
  159. { "AOUTA+", NULL, "Playback" },
  160. { "AOUTA-", NULL, "Playback" },
  161. { "AOUTB+", NULL, "Playback" },
  162. { "AOUTB-", NULL, "Playback" },
  163. };
  164. /*
  165. * @freq is the desired MCLK rate
  166. * MCLK rate should (c) be the sample rate, multiplied by one of the
  167. * ratios listed in cs4271_mclk_fs_ratios table
  168. */
  169. static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  170. int clk_id, unsigned int freq, int dir)
  171. {
  172. struct snd_soc_component *component = codec_dai->component;
  173. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  174. cs4271->mclk = freq;
  175. return 0;
  176. }
  177. static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
  178. unsigned int format)
  179. {
  180. struct snd_soc_component *component = codec_dai->component;
  181. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  182. unsigned int val = 0;
  183. int ret;
  184. switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
  185. case SND_SOC_DAIFMT_CBS_CFS:
  186. cs4271->master = false;
  187. break;
  188. case SND_SOC_DAIFMT_CBM_CFM:
  189. cs4271->master = true;
  190. val |= CS4271_MODE1_MASTER;
  191. break;
  192. default:
  193. dev_err(component->dev, "Invalid DAI format\n");
  194. return -EINVAL;
  195. }
  196. switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
  197. case SND_SOC_DAIFMT_LEFT_J:
  198. val |= CS4271_MODE1_DAC_DIF_LJ;
  199. ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
  200. CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
  201. if (ret < 0)
  202. return ret;
  203. break;
  204. case SND_SOC_DAIFMT_I2S:
  205. val |= CS4271_MODE1_DAC_DIF_I2S;
  206. ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
  207. CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
  208. if (ret < 0)
  209. return ret;
  210. break;
  211. default:
  212. dev_err(component->dev, "Invalid DAI format\n");
  213. return -EINVAL;
  214. }
  215. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
  216. CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val);
  217. if (ret < 0)
  218. return ret;
  219. return 0;
  220. }
  221. static int cs4271_deemph[] = {0, 44100, 48000, 32000};
  222. static int cs4271_set_deemph(struct snd_soc_component *component)
  223. {
  224. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  225. int i, ret;
  226. int val = CS4271_DACCTL_DEM_DIS;
  227. if (cs4271->deemph) {
  228. /* Find closest de-emphasis freq */
  229. val = 1;
  230. for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
  231. if (abs(cs4271_deemph[i] - cs4271->rate) <
  232. abs(cs4271_deemph[val] - cs4271->rate))
  233. val = i;
  234. val <<= 4;
  235. }
  236. ret = regmap_update_bits(cs4271->regmap, CS4271_DACCTL,
  237. CS4271_DACCTL_DEM_MASK, val);
  238. if (ret < 0)
  239. return ret;
  240. return 0;
  241. }
  242. static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
  243. struct snd_ctl_elem_value *ucontrol)
  244. {
  245. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  246. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  247. ucontrol->value.integer.value[0] = cs4271->deemph;
  248. return 0;
  249. }
  250. static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
  251. struct snd_ctl_elem_value *ucontrol)
  252. {
  253. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  254. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  255. cs4271->deemph = ucontrol->value.integer.value[0];
  256. return cs4271_set_deemph(component);
  257. }
  258. struct cs4271_clk_cfg {
  259. bool master; /* codec mode */
  260. u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */
  261. unsigned short ratio; /* MCLK / sample rate */
  262. u8 ratio_mask; /* ratio bit mask for Master mode */
  263. };
  264. static struct cs4271_clk_cfg cs4271_clk_tab[] = {
  265. {1, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1},
  266. {1, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_15},
  267. {1, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_2},
  268. {1, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_3},
  269. {1, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1},
  270. {1, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_15},
  271. {1, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_2},
  272. {1, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_3},
  273. {1, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1},
  274. {1, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_15},
  275. {1, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_2},
  276. {1, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_3},
  277. {0, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1},
  278. {0, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_1},
  279. {0, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_1},
  280. {0, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_2},
  281. {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2},
  282. {0, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1},
  283. {0, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_1},
  284. {0, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_1},
  285. {0, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_2},
  286. {0, CS4271_MODE1_MODE_2X, 512, CS4271_MODE1_DIV_2},
  287. {0, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1},
  288. {0, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_1},
  289. {0, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_1},
  290. {0, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_2},
  291. {0, CS4271_MODE1_MODE_4X, 256, CS4271_MODE1_DIV_2},
  292. };
  293. #define CS4271_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)
  294. static int cs4271_hw_params(struct snd_pcm_substream *substream,
  295. struct snd_pcm_hw_params *params,
  296. struct snd_soc_dai *dai)
  297. {
  298. struct snd_soc_component *component = dai->component;
  299. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  300. int i, ret;
  301. unsigned int ratio, val;
  302. if (cs4271->enable_soft_reset) {
  303. /*
  304. * Put the codec in soft reset and back again in case it's not
  305. * currently streaming data. This way of bringing the codec in
  306. * sync to the current clocks is not explicitly documented in
  307. * the data sheet, but it seems to work fine, and in contrast
  308. * to a read hardware reset, we don't have to sync back all
  309. * registers every time.
  310. */
  311. if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
  312. !snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_CAPTURE)) ||
  313. (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
  314. !snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_PLAYBACK))) {
  315. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  316. CS4271_MODE2_PDN,
  317. CS4271_MODE2_PDN);
  318. if (ret < 0)
  319. return ret;
  320. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  321. CS4271_MODE2_PDN, 0);
  322. if (ret < 0)
  323. return ret;
  324. }
  325. }
  326. cs4271->rate = params_rate(params);
  327. /* Configure DAC */
  328. if (cs4271->rate < 50000)
  329. val = CS4271_MODE1_MODE_1X;
  330. else if (cs4271->rate < 100000)
  331. val = CS4271_MODE1_MODE_2X;
  332. else
  333. val = CS4271_MODE1_MODE_4X;
  334. ratio = cs4271->mclk / cs4271->rate;
  335. for (i = 0; i < CS4271_NR_RATIOS; i++)
  336. if ((cs4271_clk_tab[i].master == cs4271->master) &&
  337. (cs4271_clk_tab[i].speed_mode == val) &&
  338. (cs4271_clk_tab[i].ratio == ratio))
  339. break;
  340. if (i == CS4271_NR_RATIOS) {
  341. dev_err(component->dev, "Invalid sample rate\n");
  342. return -EINVAL;
  343. }
  344. val |= cs4271_clk_tab[i].ratio_mask;
  345. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
  346. CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val);
  347. if (ret < 0)
  348. return ret;
  349. return cs4271_set_deemph(component);
  350. }
  351. static int cs4271_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
  352. {
  353. struct snd_soc_component *component = dai->component;
  354. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  355. int ret;
  356. int val_a = 0;
  357. int val_b = 0;
  358. if (stream != SNDRV_PCM_STREAM_PLAYBACK)
  359. return 0;
  360. if (mute) {
  361. val_a = CS4271_VOLA_MUTE;
  362. val_b = CS4271_VOLB_MUTE;
  363. }
  364. ret = regmap_update_bits(cs4271->regmap, CS4271_VOLA,
  365. CS4271_VOLA_MUTE, val_a);
  366. if (ret < 0)
  367. return ret;
  368. ret = regmap_update_bits(cs4271->regmap, CS4271_VOLB,
  369. CS4271_VOLB_MUTE, val_b);
  370. if (ret < 0)
  371. return ret;
  372. return 0;
  373. }
  374. /* CS4271 controls */
  375. static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0);
  376. static const struct snd_kcontrol_new cs4271_snd_controls[] = {
  377. SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB,
  378. 0, 0x7F, 1, cs4271_dac_tlv),
  379. SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0),
  380. SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0),
  381. SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0),
  382. SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
  383. cs4271_get_deemph, cs4271_put_deemph),
  384. SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0),
  385. SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0),
  386. SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0),
  387. SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0),
  388. SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0),
  389. SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0),
  390. SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1),
  391. SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0),
  392. SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1),
  393. SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB,
  394. 7, 1, 1),
  395. };
  396. static const struct snd_soc_dai_ops cs4271_dai_ops = {
  397. .hw_params = cs4271_hw_params,
  398. .set_sysclk = cs4271_set_dai_sysclk,
  399. .set_fmt = cs4271_set_dai_fmt,
  400. .mute_stream = cs4271_mute_stream,
  401. };
  402. static struct snd_soc_dai_driver cs4271_dai = {
  403. .name = "cs4271-hifi",
  404. .playback = {
  405. .stream_name = "Playback",
  406. .channels_min = 2,
  407. .channels_max = 2,
  408. .rates = CS4271_PCM_RATES,
  409. .formats = CS4271_PCM_FORMATS,
  410. },
  411. .capture = {
  412. .stream_name = "Capture",
  413. .channels_min = 2,
  414. .channels_max = 2,
  415. .rates = CS4271_PCM_RATES,
  416. .formats = CS4271_PCM_FORMATS,
  417. },
  418. .ops = &cs4271_dai_ops,
  419. .symmetric_rates = 1,
  420. };
  421. static int cs4271_reset(struct snd_soc_component *component)
  422. {
  423. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  424. if (gpio_is_valid(cs4271->gpio_nreset)) {
  425. gpio_direction_output(cs4271->gpio_nreset, 0);
  426. mdelay(1);
  427. gpio_set_value(cs4271->gpio_nreset, 1);
  428. mdelay(1);
  429. }
  430. return 0;
  431. }
  432. #ifdef CONFIG_PM
  433. static int cs4271_soc_suspend(struct snd_soc_component *component)
  434. {
  435. int ret;
  436. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  437. /* Set power-down bit */
  438. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  439. CS4271_MODE2_PDN, CS4271_MODE2_PDN);
  440. if (ret < 0)
  441. return ret;
  442. regcache_mark_dirty(cs4271->regmap);
  443. regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies);
  444. return 0;
  445. }
  446. static int cs4271_soc_resume(struct snd_soc_component *component)
  447. {
  448. int ret;
  449. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  450. ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies),
  451. cs4271->supplies);
  452. if (ret < 0) {
  453. dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
  454. return ret;
  455. }
  456. /* Do a proper reset after power up */
  457. cs4271_reset(component);
  458. /* Restore codec state */
  459. ret = regcache_sync(cs4271->regmap);
  460. if (ret < 0)
  461. return ret;
  462. /* then disable the power-down bit */
  463. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  464. CS4271_MODE2_PDN, 0);
  465. if (ret < 0)
  466. return ret;
  467. return 0;
  468. }
  469. #else
  470. #define cs4271_soc_suspend NULL
  471. #define cs4271_soc_resume NULL
  472. #endif /* CONFIG_PM */
  473. #ifdef CONFIG_OF
  474. const struct of_device_id cs4271_dt_ids[] = {
  475. { .compatible = "cirrus,cs4271", },
  476. { }
  477. };
  478. MODULE_DEVICE_TABLE(of, cs4271_dt_ids);
  479. EXPORT_SYMBOL_GPL(cs4271_dt_ids);
  480. #endif
  481. static int cs4271_component_probe(struct snd_soc_component *component)
  482. {
  483. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  484. struct cs4271_platform_data *cs4271plat = component->dev->platform_data;
  485. int ret;
  486. bool amutec_eq_bmutec = false;
  487. #ifdef CONFIG_OF
  488. if (of_match_device(cs4271_dt_ids, component->dev)) {
  489. if (of_get_property(component->dev->of_node,
  490. "cirrus,amutec-eq-bmutec", NULL))
  491. amutec_eq_bmutec = true;
  492. if (of_get_property(component->dev->of_node,
  493. "cirrus,enable-soft-reset", NULL))
  494. cs4271->enable_soft_reset = true;
  495. }
  496. #endif
  497. ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies),
  498. cs4271->supplies);
  499. if (ret < 0) {
  500. dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
  501. return ret;
  502. }
  503. if (cs4271plat) {
  504. amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec;
  505. cs4271->enable_soft_reset = cs4271plat->enable_soft_reset;
  506. }
  507. /* Reset codec */
  508. cs4271_reset(component);
  509. ret = regcache_sync(cs4271->regmap);
  510. if (ret < 0)
  511. return ret;
  512. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  513. CS4271_MODE2_PDN | CS4271_MODE2_CPEN,
  514. CS4271_MODE2_PDN | CS4271_MODE2_CPEN);
  515. if (ret < 0)
  516. return ret;
  517. ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  518. CS4271_MODE2_PDN, 0);
  519. if (ret < 0)
  520. return ret;
  521. /* Power-up sequence requires 85 uS */
  522. udelay(85);
  523. if (amutec_eq_bmutec)
  524. regmap_update_bits(cs4271->regmap, CS4271_MODE2,
  525. CS4271_MODE2_MUTECAEQUB,
  526. CS4271_MODE2_MUTECAEQUB);
  527. return 0;
  528. }
  529. static void cs4271_component_remove(struct snd_soc_component *component)
  530. {
  531. struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
  532. if (gpio_is_valid(cs4271->gpio_nreset))
  533. /* Set codec to the reset state */
  534. gpio_set_value(cs4271->gpio_nreset, 0);
  535. regcache_mark_dirty(cs4271->regmap);
  536. regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies);
  537. };
  538. static const struct snd_soc_component_driver soc_component_dev_cs4271 = {
  539. .probe = cs4271_component_probe,
  540. .remove = cs4271_component_remove,
  541. .suspend = cs4271_soc_suspend,
  542. .resume = cs4271_soc_resume,
  543. .controls = cs4271_snd_controls,
  544. .num_controls = ARRAY_SIZE(cs4271_snd_controls),
  545. .dapm_widgets = cs4271_dapm_widgets,
  546. .num_dapm_widgets = ARRAY_SIZE(cs4271_dapm_widgets),
  547. .dapm_routes = cs4271_dapm_routes,
  548. .num_dapm_routes = ARRAY_SIZE(cs4271_dapm_routes),
  549. .idle_bias_on = 1,
  550. .use_pmdown_time = 1,
  551. .endianness = 1,
  552. .non_legacy_dai_naming = 1,
  553. };
  554. static int cs4271_common_probe(struct device *dev,
  555. struct cs4271_private **c)
  556. {
  557. struct cs4271_platform_data *cs4271plat = dev->platform_data;
  558. struct cs4271_private *cs4271;
  559. int i, ret;
  560. cs4271 = devm_kzalloc(dev, sizeof(*cs4271), GFP_KERNEL);
  561. if (!cs4271)
  562. return -ENOMEM;
  563. if (of_match_device(cs4271_dt_ids, dev))
  564. cs4271->gpio_nreset =
  565. of_get_named_gpio(dev->of_node, "reset-gpio", 0);
  566. if (cs4271plat)
  567. cs4271->gpio_nreset = cs4271plat->gpio_nreset;
  568. if (gpio_is_valid(cs4271->gpio_nreset)) {
  569. ret = devm_gpio_request(dev, cs4271->gpio_nreset,
  570. "CS4271 Reset");
  571. if (ret < 0)
  572. return ret;
  573. }
  574. for (i = 0; i < ARRAY_SIZE(supply_names); i++)
  575. cs4271->supplies[i].supply = supply_names[i];
  576. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs4271->supplies),
  577. cs4271->supplies);
  578. if (ret < 0) {
  579. dev_err(dev, "Failed to get regulators: %d\n", ret);
  580. return ret;
  581. }
  582. *c = cs4271;
  583. return 0;
  584. }
  585. const struct regmap_config cs4271_regmap_config = {
  586. .max_register = CS4271_LASTREG,
  587. .reg_defaults = cs4271_reg_defaults,
  588. .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults),
  589. .cache_type = REGCACHE_RBTREE,
  590. .volatile_reg = cs4271_volatile_reg,
  591. };
  592. EXPORT_SYMBOL_GPL(cs4271_regmap_config);
  593. int cs4271_probe(struct device *dev, struct regmap *regmap)
  594. {
  595. struct cs4271_private *cs4271;
  596. int ret;
  597. if (IS_ERR(regmap))
  598. return PTR_ERR(regmap);
  599. ret = cs4271_common_probe(dev, &cs4271);
  600. if (ret < 0)
  601. return ret;
  602. dev_set_drvdata(dev, cs4271);
  603. cs4271->regmap = regmap;
  604. return devm_snd_soc_register_component(dev, &soc_component_dev_cs4271,
  605. &cs4271_dai, 1);
  606. }
  607. EXPORT_SYMBOL_GPL(cs4271_probe);
  608. MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
  609. MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
  610. MODULE_LICENSE("GPL");