cs4265.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cs4265.c -- CS4265 ALSA SoC audio driver
  4. *
  5. * Copyright 2014 Cirrus Logic, Inc.
  6. *
  7. * Author: Paul Handrigan <paul.handrigan@cirrus.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/kernel.h>
  12. #include <linux/gpio/consumer.h>
  13. #include <linux/init.h>
  14. #include <linux/delay.h>
  15. #include <linux/i2c.h>
  16. #include <linux/input.h>
  17. #include <linux/regmap.h>
  18. #include <linux/slab.h>
  19. #include <linux/platform_device.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <sound/soc-dapm.h>
  25. #include <sound/initval.h>
  26. #include <sound/tlv.h>
  27. #include "cs4265.h"
  28. struct cs4265_private {
  29. struct regmap *regmap;
  30. struct gpio_desc *reset_gpio;
  31. u8 format;
  32. u32 sysclk;
  33. };
  34. static const struct reg_default cs4265_reg_defaults[] = {
  35. { CS4265_PWRCTL, 0x0F },
  36. { CS4265_DAC_CTL, 0x08 },
  37. { CS4265_ADC_CTL, 0x00 },
  38. { CS4265_MCLK_FREQ, 0x00 },
  39. { CS4265_SIG_SEL, 0x40 },
  40. { CS4265_CHB_PGA_CTL, 0x00 },
  41. { CS4265_CHA_PGA_CTL, 0x00 },
  42. { CS4265_ADC_CTL2, 0x19 },
  43. { CS4265_DAC_CHA_VOL, 0x00 },
  44. { CS4265_DAC_CHB_VOL, 0x00 },
  45. { CS4265_DAC_CTL2, 0xC0 },
  46. { CS4265_SPDIF_CTL1, 0x00 },
  47. { CS4265_SPDIF_CTL2, 0x00 },
  48. { CS4265_INT_MASK, 0x00 },
  49. { CS4265_STATUS_MODE_MSB, 0x00 },
  50. { CS4265_STATUS_MODE_LSB, 0x00 },
  51. };
  52. static bool cs4265_readable_register(struct device *dev, unsigned int reg)
  53. {
  54. switch (reg) {
  55. case CS4265_CHIP_ID ... CS4265_MAX_REGISTER:
  56. return true;
  57. default:
  58. return false;
  59. }
  60. }
  61. static bool cs4265_volatile_register(struct device *dev, unsigned int reg)
  62. {
  63. switch (reg) {
  64. case CS4265_INT_STATUS:
  65. return true;
  66. default:
  67. return false;
  68. }
  69. }
  70. static DECLARE_TLV_DB_SCALE(pga_tlv, -1200, 50, 0);
  71. static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 0);
  72. static const char * const digital_input_mux_text[] = {
  73. "SDIN1", "SDIN2"
  74. };
  75. static SOC_ENUM_SINGLE_DECL(digital_input_mux_enum, CS4265_SIG_SEL, 7,
  76. digital_input_mux_text);
  77. static const struct snd_kcontrol_new digital_input_mux =
  78. SOC_DAPM_ENUM("Digital Input Mux", digital_input_mux_enum);
  79. static const char * const mic_linein_text[] = {
  80. "MIC", "LINEIN"
  81. };
  82. static SOC_ENUM_SINGLE_DECL(mic_linein_enum, CS4265_ADC_CTL2, 0,
  83. mic_linein_text);
  84. static const char * const cam_mode_text[] = {
  85. "One Byte", "Two Byte"
  86. };
  87. static SOC_ENUM_SINGLE_DECL(cam_mode_enum, CS4265_SPDIF_CTL1, 5,
  88. cam_mode_text);
  89. static const char * const cam_mono_stereo_text[] = {
  90. "Stereo", "Mono"
  91. };
  92. static SOC_ENUM_SINGLE_DECL(spdif_mono_stereo_enum, CS4265_SPDIF_CTL2, 2,
  93. cam_mono_stereo_text);
  94. static const char * const mono_select_text[] = {
  95. "Channel A", "Channel B"
  96. };
  97. static SOC_ENUM_SINGLE_DECL(spdif_mono_select_enum, CS4265_SPDIF_CTL2, 0,
  98. mono_select_text);
  99. static const struct snd_kcontrol_new mic_linein_mux =
  100. SOC_DAPM_ENUM("ADC Input Capture Mux", mic_linein_enum);
  101. static const struct snd_kcontrol_new loopback_ctl =
  102. SOC_DAPM_SINGLE("Switch", CS4265_SIG_SEL, 1, 1, 0);
  103. static const struct snd_kcontrol_new spdif_switch =
  104. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 0, 0);
  105. static const struct snd_kcontrol_new dac_switch =
  106. SOC_DAPM_SINGLE("Switch", CS4265_PWRCTL, 1, 1, 0);
  107. static const struct snd_kcontrol_new cs4265_snd_controls[] = {
  108. SOC_DOUBLE_R_SX_TLV("PGA Volume", CS4265_CHA_PGA_CTL,
  109. CS4265_CHB_PGA_CTL, 0, 0x28, 0x30, pga_tlv),
  110. SOC_DOUBLE_R_TLV("DAC Volume", CS4265_DAC_CHA_VOL,
  111. CS4265_DAC_CHB_VOL, 0, 0xFF, 1, dac_tlv),
  112. SOC_SINGLE("De-emp 44.1kHz Switch", CS4265_DAC_CTL, 1,
  113. 1, 0),
  114. SOC_SINGLE("DAC INV Switch", CS4265_DAC_CTL2, 5,
  115. 1, 0),
  116. SOC_SINGLE("DAC Zero Cross Switch", CS4265_DAC_CTL2, 6,
  117. 1, 0),
  118. SOC_SINGLE("DAC Soft Ramp Switch", CS4265_DAC_CTL2, 7,
  119. 1, 0),
  120. SOC_SINGLE("ADC HPF Switch", CS4265_ADC_CTL, 1,
  121. 1, 0),
  122. SOC_SINGLE("ADC Zero Cross Switch", CS4265_ADC_CTL2, 3,
  123. 1, 1),
  124. SOC_SINGLE("ADC Soft Ramp Switch", CS4265_ADC_CTL2, 7,
  125. 1, 0),
  126. SOC_SINGLE("E to F Buffer Disable Switch", CS4265_SPDIF_CTL1,
  127. 6, 1, 0),
  128. SOC_ENUM("C Data Access", cam_mode_enum),
  129. SOC_SINGLE("Validity Bit Control Switch", CS4265_SPDIF_CTL2,
  130. 3, 1, 0),
  131. SOC_ENUM("SPDIF Mono/Stereo", spdif_mono_stereo_enum),
  132. SOC_SINGLE("MMTLR Data Switch", CS4265_SPDIF_CTL2, 0, 1, 0),
  133. SOC_ENUM("Mono Channel Select", spdif_mono_select_enum),
  134. SND_SOC_BYTES("C Data Buffer", CS4265_C_DATA_BUFF, 24),
  135. };
  136. static const struct snd_soc_dapm_widget cs4265_dapm_widgets[] = {
  137. SND_SOC_DAPM_INPUT("LINEINL"),
  138. SND_SOC_DAPM_INPUT("LINEINR"),
  139. SND_SOC_DAPM_INPUT("MICL"),
  140. SND_SOC_DAPM_INPUT("MICR"),
  141. SND_SOC_DAPM_AIF_OUT("DOUT", NULL, 0,
  142. SND_SOC_NOPM, 0, 0),
  143. SND_SOC_DAPM_AIF_OUT("SPDIFOUT", NULL, 0,
  144. SND_SOC_NOPM, 0, 0),
  145. SND_SOC_DAPM_MUX("ADC Mux", SND_SOC_NOPM, 0, 0, &mic_linein_mux),
  146. SND_SOC_DAPM_ADC("ADC", NULL, CS4265_PWRCTL, 2, 1),
  147. SND_SOC_DAPM_PGA("Pre-amp MIC", CS4265_PWRCTL, 3,
  148. 1, NULL, 0),
  149. SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM,
  150. 0, 0, &digital_input_mux),
  151. SND_SOC_DAPM_MIXER("SDIN1 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  152. SND_SOC_DAPM_MIXER("SDIN2 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  153. SND_SOC_DAPM_MIXER("SPDIF Transmitter", SND_SOC_NOPM, 0, 0, NULL, 0),
  154. SND_SOC_DAPM_SWITCH("Loopback", SND_SOC_NOPM, 0, 0,
  155. &loopback_ctl),
  156. SND_SOC_DAPM_SWITCH("SPDIF", CS4265_SPDIF_CTL2, 5, 1,
  157. &spdif_switch),
  158. SND_SOC_DAPM_SWITCH("DAC", CS4265_PWRCTL, 1, 1,
  159. &dac_switch),
  160. SND_SOC_DAPM_AIF_IN("DIN1", NULL, 0,
  161. SND_SOC_NOPM, 0, 0),
  162. SND_SOC_DAPM_AIF_IN("DIN2", NULL, 0,
  163. SND_SOC_NOPM, 0, 0),
  164. SND_SOC_DAPM_AIF_IN("TXIN", NULL, 0,
  165. CS4265_SPDIF_CTL2, 5, 1),
  166. SND_SOC_DAPM_OUTPUT("LINEOUTL"),
  167. SND_SOC_DAPM_OUTPUT("LINEOUTR"),
  168. };
  169. static const struct snd_soc_dapm_route cs4265_audio_map[] = {
  170. {"DIN1", NULL, "DAI1 Playback"},
  171. {"DIN2", NULL, "DAI2 Playback"},
  172. {"SDIN1 Input Mixer", NULL, "DIN1"},
  173. {"SDIN2 Input Mixer", NULL, "DIN2"},
  174. {"Input Mux", "SDIN1", "SDIN1 Input Mixer"},
  175. {"Input Mux", "SDIN2", "SDIN2 Input Mixer"},
  176. {"DAC", "Switch", "Input Mux"},
  177. {"SPDIF", "Switch", "Input Mux"},
  178. {"LINEOUTL", NULL, "DAC"},
  179. {"LINEOUTR", NULL, "DAC"},
  180. {"SPDIFOUT", NULL, "SPDIF"},
  181. {"Pre-amp MIC", NULL, "MICL"},
  182. {"Pre-amp MIC", NULL, "MICR"},
  183. {"ADC Mux", "MIC", "Pre-amp MIC"},
  184. {"ADC Mux", "LINEIN", "LINEINL"},
  185. {"ADC Mux", "LINEIN", "LINEINR"},
  186. {"ADC", NULL, "ADC Mux"},
  187. {"DOUT", NULL, "ADC"},
  188. {"DAI1 Capture", NULL, "DOUT"},
  189. {"DAI2 Capture", NULL, "DOUT"},
  190. /* Loopback */
  191. {"Loopback", "Switch", "ADC"},
  192. {"DAC", NULL, "Loopback"},
  193. };
  194. struct cs4265_clk_para {
  195. u32 mclk;
  196. u32 rate;
  197. u8 fm_mode; /* values 1, 2, or 4 */
  198. u8 mclkdiv;
  199. };
  200. static const struct cs4265_clk_para clk_map_table[] = {
  201. /*32k*/
  202. {8192000, 32000, 0, 0},
  203. {12288000, 32000, 0, 1},
  204. {16384000, 32000, 0, 2},
  205. {24576000, 32000, 0, 3},
  206. {32768000, 32000, 0, 4},
  207. /*44.1k*/
  208. {11289600, 44100, 0, 0},
  209. {16934400, 44100, 0, 1},
  210. {22579200, 44100, 0, 2},
  211. {33868000, 44100, 0, 3},
  212. {45158400, 44100, 0, 4},
  213. /*48k*/
  214. {12288000, 48000, 0, 0},
  215. {18432000, 48000, 0, 1},
  216. {24576000, 48000, 0, 2},
  217. {36864000, 48000, 0, 3},
  218. {49152000, 48000, 0, 4},
  219. /*64k*/
  220. {8192000, 64000, 1, 0},
  221. {12288000, 64000, 1, 1},
  222. {16934400, 64000, 1, 2},
  223. {24576000, 64000, 1, 3},
  224. {32768000, 64000, 1, 4},
  225. /* 88.2k */
  226. {11289600, 88200, 1, 0},
  227. {16934400, 88200, 1, 1},
  228. {22579200, 88200, 1, 2},
  229. {33868000, 88200, 1, 3},
  230. {45158400, 88200, 1, 4},
  231. /* 96k */
  232. {12288000, 96000, 1, 0},
  233. {18432000, 96000, 1, 1},
  234. {24576000, 96000, 1, 2},
  235. {36864000, 96000, 1, 3},
  236. {49152000, 96000, 1, 4},
  237. /* 128k */
  238. {8192000, 128000, 2, 0},
  239. {12288000, 128000, 2, 1},
  240. {16934400, 128000, 2, 2},
  241. {24576000, 128000, 2, 3},
  242. {32768000, 128000, 2, 4},
  243. /* 176.4k */
  244. {11289600, 176400, 2, 0},
  245. {16934400, 176400, 2, 1},
  246. {22579200, 176400, 2, 2},
  247. {33868000, 176400, 2, 3},
  248. {49152000, 176400, 2, 4},
  249. /* 192k */
  250. {12288000, 192000, 2, 0},
  251. {18432000, 192000, 2, 1},
  252. {24576000, 192000, 2, 2},
  253. {36864000, 192000, 2, 3},
  254. {49152000, 192000, 2, 4},
  255. };
  256. static int cs4265_get_clk_index(int mclk, int rate)
  257. {
  258. int i;
  259. for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
  260. if (clk_map_table[i].rate == rate &&
  261. clk_map_table[i].mclk == mclk)
  262. return i;
  263. }
  264. return -EINVAL;
  265. }
  266. static int cs4265_set_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
  267. unsigned int freq, int dir)
  268. {
  269. struct snd_soc_component *component = codec_dai->component;
  270. struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
  271. int i;
  272. if (clk_id != 0) {
  273. dev_err(component->dev, "Invalid clk_id %d\n", clk_id);
  274. return -EINVAL;
  275. }
  276. for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
  277. if (clk_map_table[i].mclk == freq) {
  278. cs4265->sysclk = freq;
  279. return 0;
  280. }
  281. }
  282. cs4265->sysclk = 0;
  283. dev_err(component->dev, "Invalid freq parameter %d\n", freq);
  284. return -EINVAL;
  285. }
  286. static int cs4265_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  287. {
  288. struct snd_soc_component *component = codec_dai->component;
  289. struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
  290. u8 iface = 0;
  291. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  292. case SND_SOC_DAIFMT_CBM_CFM:
  293. snd_soc_component_update_bits(component, CS4265_ADC_CTL,
  294. CS4265_ADC_MASTER,
  295. CS4265_ADC_MASTER);
  296. break;
  297. case SND_SOC_DAIFMT_CBS_CFS:
  298. snd_soc_component_update_bits(component, CS4265_ADC_CTL,
  299. CS4265_ADC_MASTER,
  300. 0);
  301. break;
  302. default:
  303. return -EINVAL;
  304. }
  305. /* interface format */
  306. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  307. case SND_SOC_DAIFMT_I2S:
  308. iface |= SND_SOC_DAIFMT_I2S;
  309. break;
  310. case SND_SOC_DAIFMT_RIGHT_J:
  311. iface |= SND_SOC_DAIFMT_RIGHT_J;
  312. break;
  313. case SND_SOC_DAIFMT_LEFT_J:
  314. iface |= SND_SOC_DAIFMT_LEFT_J;
  315. break;
  316. default:
  317. return -EINVAL;
  318. }
  319. cs4265->format = iface;
  320. return 0;
  321. }
  322. static int cs4265_mute(struct snd_soc_dai *dai, int mute, int direction)
  323. {
  324. struct snd_soc_component *component = dai->component;
  325. if (mute) {
  326. snd_soc_component_update_bits(component, CS4265_DAC_CTL,
  327. CS4265_DAC_CTL_MUTE,
  328. CS4265_DAC_CTL_MUTE);
  329. snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
  330. CS4265_SPDIF_CTL2_MUTE,
  331. CS4265_SPDIF_CTL2_MUTE);
  332. } else {
  333. snd_soc_component_update_bits(component, CS4265_DAC_CTL,
  334. CS4265_DAC_CTL_MUTE,
  335. 0);
  336. snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
  337. CS4265_SPDIF_CTL2_MUTE,
  338. 0);
  339. }
  340. return 0;
  341. }
  342. static int cs4265_pcm_hw_params(struct snd_pcm_substream *substream,
  343. struct snd_pcm_hw_params *params,
  344. struct snd_soc_dai *dai)
  345. {
  346. struct snd_soc_component *component = dai->component;
  347. struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
  348. int index;
  349. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
  350. ((cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK)
  351. == SND_SOC_DAIFMT_RIGHT_J))
  352. return -EINVAL;
  353. index = cs4265_get_clk_index(cs4265->sysclk, params_rate(params));
  354. if (index >= 0) {
  355. snd_soc_component_update_bits(component, CS4265_ADC_CTL,
  356. CS4265_ADC_FM, clk_map_table[index].fm_mode << 6);
  357. snd_soc_component_update_bits(component, CS4265_MCLK_FREQ,
  358. CS4265_MCLK_FREQ_MASK,
  359. clk_map_table[index].mclkdiv << 4);
  360. } else {
  361. dev_err(component->dev, "can't get correct mclk\n");
  362. return -EINVAL;
  363. }
  364. switch (cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK) {
  365. case SND_SOC_DAIFMT_I2S:
  366. snd_soc_component_update_bits(component, CS4265_DAC_CTL,
  367. CS4265_DAC_CTL_DIF, (1 << 4));
  368. snd_soc_component_update_bits(component, CS4265_ADC_CTL,
  369. CS4265_ADC_DIF, (1 << 4));
  370. snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
  371. CS4265_SPDIF_CTL2_DIF, (1 << 6));
  372. break;
  373. case SND_SOC_DAIFMT_RIGHT_J:
  374. if (params_width(params) == 16) {
  375. snd_soc_component_update_bits(component, CS4265_DAC_CTL,
  376. CS4265_DAC_CTL_DIF, (2 << 4));
  377. snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
  378. CS4265_SPDIF_CTL2_DIF, (2 << 6));
  379. } else {
  380. snd_soc_component_update_bits(component, CS4265_DAC_CTL,
  381. CS4265_DAC_CTL_DIF, (3 << 4));
  382. snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
  383. CS4265_SPDIF_CTL2_DIF, (3 << 6));
  384. }
  385. break;
  386. case SND_SOC_DAIFMT_LEFT_J:
  387. snd_soc_component_update_bits(component, CS4265_DAC_CTL,
  388. CS4265_DAC_CTL_DIF, 0);
  389. snd_soc_component_update_bits(component, CS4265_ADC_CTL,
  390. CS4265_ADC_DIF, 0);
  391. snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
  392. CS4265_SPDIF_CTL2_DIF, 0);
  393. break;
  394. default:
  395. return -EINVAL;
  396. }
  397. return 0;
  398. }
  399. static int cs4265_set_bias_level(struct snd_soc_component *component,
  400. enum snd_soc_bias_level level)
  401. {
  402. switch (level) {
  403. case SND_SOC_BIAS_ON:
  404. break;
  405. case SND_SOC_BIAS_PREPARE:
  406. snd_soc_component_update_bits(component, CS4265_PWRCTL,
  407. CS4265_PWRCTL_PDN, 0);
  408. break;
  409. case SND_SOC_BIAS_STANDBY:
  410. snd_soc_component_update_bits(component, CS4265_PWRCTL,
  411. CS4265_PWRCTL_PDN,
  412. CS4265_PWRCTL_PDN);
  413. break;
  414. case SND_SOC_BIAS_OFF:
  415. snd_soc_component_update_bits(component, CS4265_PWRCTL,
  416. CS4265_PWRCTL_PDN,
  417. CS4265_PWRCTL_PDN);
  418. break;
  419. }
  420. return 0;
  421. }
  422. #define CS4265_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  423. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
  424. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
  425. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
  426. #define CS4265_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
  427. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE | \
  428. SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
  429. static const struct snd_soc_dai_ops cs4265_ops = {
  430. .hw_params = cs4265_pcm_hw_params,
  431. .mute_stream = cs4265_mute,
  432. .set_fmt = cs4265_set_fmt,
  433. .set_sysclk = cs4265_set_sysclk,
  434. .no_capture_mute = 1,
  435. };
  436. static struct snd_soc_dai_driver cs4265_dai[] = {
  437. {
  438. .name = "cs4265-dai1",
  439. .playback = {
  440. .stream_name = "DAI1 Playback",
  441. .channels_min = 1,
  442. .channels_max = 2,
  443. .rates = CS4265_RATES,
  444. .formats = CS4265_FORMATS,
  445. },
  446. .capture = {
  447. .stream_name = "DAI1 Capture",
  448. .channels_min = 1,
  449. .channels_max = 2,
  450. .rates = CS4265_RATES,
  451. .formats = CS4265_FORMATS,
  452. },
  453. .ops = &cs4265_ops,
  454. },
  455. {
  456. .name = "cs4265-dai2",
  457. .playback = {
  458. .stream_name = "DAI2 Playback",
  459. .channels_min = 1,
  460. .channels_max = 2,
  461. .rates = CS4265_RATES,
  462. .formats = CS4265_FORMATS,
  463. },
  464. .capture = {
  465. .stream_name = "DAI2 Capture",
  466. .channels_min = 1,
  467. .channels_max = 2,
  468. .rates = CS4265_RATES,
  469. .formats = CS4265_FORMATS,
  470. },
  471. .ops = &cs4265_ops,
  472. },
  473. };
  474. static const struct snd_soc_component_driver soc_component_cs4265 = {
  475. .set_bias_level = cs4265_set_bias_level,
  476. .controls = cs4265_snd_controls,
  477. .num_controls = ARRAY_SIZE(cs4265_snd_controls),
  478. .dapm_widgets = cs4265_dapm_widgets,
  479. .num_dapm_widgets = ARRAY_SIZE(cs4265_dapm_widgets),
  480. .dapm_routes = cs4265_audio_map,
  481. .num_dapm_routes = ARRAY_SIZE(cs4265_audio_map),
  482. .idle_bias_on = 1,
  483. .use_pmdown_time = 1,
  484. .endianness = 1,
  485. .non_legacy_dai_naming = 1,
  486. };
  487. static const struct regmap_config cs4265_regmap = {
  488. .reg_bits = 8,
  489. .val_bits = 8,
  490. .max_register = CS4265_MAX_REGISTER,
  491. .reg_defaults = cs4265_reg_defaults,
  492. .num_reg_defaults = ARRAY_SIZE(cs4265_reg_defaults),
  493. .readable_reg = cs4265_readable_register,
  494. .volatile_reg = cs4265_volatile_register,
  495. .cache_type = REGCACHE_RBTREE,
  496. };
  497. static int cs4265_i2c_probe(struct i2c_client *i2c_client,
  498. const struct i2c_device_id *id)
  499. {
  500. struct cs4265_private *cs4265;
  501. int ret = 0;
  502. unsigned int devid = 0;
  503. unsigned int reg;
  504. cs4265 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs4265_private),
  505. GFP_KERNEL);
  506. if (cs4265 == NULL)
  507. return -ENOMEM;
  508. cs4265->regmap = devm_regmap_init_i2c(i2c_client, &cs4265_regmap);
  509. if (IS_ERR(cs4265->regmap)) {
  510. ret = PTR_ERR(cs4265->regmap);
  511. dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
  512. return ret;
  513. }
  514. cs4265->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
  515. "reset", GPIOD_OUT_LOW);
  516. if (IS_ERR(cs4265->reset_gpio))
  517. return PTR_ERR(cs4265->reset_gpio);
  518. if (cs4265->reset_gpio) {
  519. mdelay(1);
  520. gpiod_set_value_cansleep(cs4265->reset_gpio, 1);
  521. }
  522. i2c_set_clientdata(i2c_client, cs4265);
  523. ret = regmap_read(cs4265->regmap, CS4265_CHIP_ID, &reg);
  524. devid = reg & CS4265_CHIP_ID_MASK;
  525. if (devid != CS4265_CHIP_ID_VAL) {
  526. ret = -ENODEV;
  527. dev_err(&i2c_client->dev,
  528. "CS4265 Device ID (%X). Expected %X\n",
  529. devid, CS4265_CHIP_ID);
  530. return ret;
  531. }
  532. dev_info(&i2c_client->dev,
  533. "CS4265 Version %x\n",
  534. reg & CS4265_REV_ID_MASK);
  535. regmap_write(cs4265->regmap, CS4265_PWRCTL, 0x0F);
  536. ret = devm_snd_soc_register_component(&i2c_client->dev,
  537. &soc_component_cs4265, cs4265_dai,
  538. ARRAY_SIZE(cs4265_dai));
  539. return ret;
  540. }
  541. static const struct of_device_id cs4265_of_match[] = {
  542. { .compatible = "cirrus,cs4265", },
  543. { }
  544. };
  545. MODULE_DEVICE_TABLE(of, cs4265_of_match);
  546. static const struct i2c_device_id cs4265_id[] = {
  547. { "cs4265", 0 },
  548. { }
  549. };
  550. MODULE_DEVICE_TABLE(i2c, cs4265_id);
  551. static struct i2c_driver cs4265_i2c_driver = {
  552. .driver = {
  553. .name = "cs4265",
  554. .of_match_table = cs4265_of_match,
  555. },
  556. .id_table = cs4265_id,
  557. .probe = cs4265_i2c_probe,
  558. };
  559. module_i2c_driver(cs4265_i2c_driver);
  560. MODULE_DESCRIPTION("ASoC CS4265 driver");
  561. MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
  562. MODULE_LICENSE("GPL");