cs4234.h 8.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * ALSA SoC Audio driver for CS4234 codec
  4. *
  5. * Copyright (C) 2020 Cirrus Logic, Inc. and
  6. * Cirrus Logic International Semiconductor Ltd.
  7. */
  8. #ifndef CS4234_H
  9. #define CS4234_H
  10. #define CS4234_DEVID_AB 0x01
  11. #define CS4234_DEVID_CD 0x02
  12. #define CS4234_DEVID_EF 0x03
  13. #define CS4234_REVID 0x05
  14. #define CS4234_CLOCK_SP 0x06
  15. #define CS4234_BASE_RATE_MASK 0xC0
  16. #define CS4234_BASE_RATE_SHIFT 6
  17. #define CS4234_SPEED_MODE_MASK 0x30
  18. #define CS4234_SPEED_MODE_SHIFT 4
  19. #define CS4234_MCLK_RATE_MASK 0x0E
  20. #define CS4234_MCLK_RATE_SHIFT 1
  21. #define CS4234_SAMPLE_WIDTH 0x07
  22. #define CS4234_SDOUTX_SW_MASK 0xC0
  23. #define CS4234_SDOUTX_SW_SHIFT 6
  24. #define CS4234_INPUT_SW_MASK 0x30
  25. #define CS4234_INPUT_SW_SHIFT 4
  26. #define CS4234_LOW_LAT_SW_MASK 0x0C
  27. #define CS4234_LOW_LAT_SW_SHIFT 2
  28. #define CS4234_DAC5_SW_MASK 0x03
  29. #define CS4234_DAC5_SW_SHIFT 0
  30. #define CS4234_SP_CTRL 0x08
  31. #define CS4234_INVT_SCLK_MASK 0x80
  32. #define CS4234_INVT_SCLK_SHIFT 7
  33. #define CS4234_DAC5_SRC_MASK 0x70
  34. #define CS4234_DAC5_SRC_SHIFT 4
  35. #define CS4234_SP_FORMAT_MASK 0x0C
  36. #define CS4234_SP_FORMAT_SHIFT 2
  37. #define CS4234_SDO_CHAIN_MASK 0x02
  38. #define CS4234_SDO_CHAIN_SHIFT 1
  39. #define CS4234_MST_SLV_MASK 0x01
  40. #define CS4234_MST_SLV_SHIFT 0
  41. #define CS4234_SP_DATA_SEL 0x09
  42. #define CS4234_DAC14_SRC_MASK 0x38
  43. #define CS4234_DAC14_SRC_SHIFT 3
  44. #define CS4234_LL_SRC_MASK 0x07
  45. #define CS4234_LL_SRC_SHIFT 0
  46. #define CS4234_SDIN1_MASK1 0x0A
  47. #define CS4234_SDIN1_MASK2 0x0B
  48. #define CS4234_SDIN2_MASK1 0x0C
  49. #define CS4234_SDIN2_MASK2 0x0D
  50. #define CS4234_TPS_CTRL 0x0E
  51. #define CS4234_TPS_MODE_MASK 0x80
  52. #define CS4234_TPS_MODE_SHIFT 7
  53. #define CS4234_TPS_OFST_MASK 0x70
  54. #define CS4234_TPS_OFST_SHIFT 4
  55. #define CS4234_GRP_DELAY_MASK 0x0F
  56. #define CS4234_GRP_DELAY_SHIFT 0
  57. #define CS4234_ADC_CTRL1 0x0F
  58. #define CS4234_VA_SEL_MASK 0x20
  59. #define CS4234_VA_SEL_SHIFT 5
  60. #define CS4234_ENA_HPF_MASK 0x10
  61. #define CS4234_ENA_HPF_SHIFT 4
  62. #define CS4234_INV_ADC_MASK 0x0F
  63. #define CS4234_INV_ADC4_MASK 0x08
  64. #define CS4234_INV_ADC4_SHIFT 3
  65. #define CS4234_INV_ADC3_MASK 0x04
  66. #define CS4234_INV_ADC3_SHIFT 2
  67. #define CS4234_INV_ADC2_MASK 0x02
  68. #define CS4234_INV_ADC2_SHIFT 1
  69. #define CS4234_INV_ADC1_MASK 0x01
  70. #define CS4234_INV_ADC1_SHIFT 0
  71. #define CS4234_ADC_CTRL2 0x10
  72. #define CS4234_MUTE_ADC4_MASK 0x80
  73. #define CS4234_MUTE_ADC4_SHIFT 7
  74. #define CS4234_MUTE_ADC3_MASK 0x40
  75. #define CS4234_MUTE_ADC3_SHIFT 6
  76. #define CS4234_MUTE_ADC2_MASK 0x20
  77. #define CS4234_MUTE_ADC2_SHIFT 5
  78. #define CS4234_MUTE_ADC1_MASK 0x10
  79. #define CS4234_MUTE_ADC1_SHIFT 4
  80. #define CS4234_PDN_ADC4_MASK 0x08
  81. #define CS4234_PDN_ADC4_SHIFT 3
  82. #define CS4234_PDN_ADC3_MASK 0x04
  83. #define CS4234_PDN_ADC3_SHIFT 2
  84. #define CS4234_PDN_ADC2_MASK 0x02
  85. #define CS4234_PDN_ADC2_SHIFT 1
  86. #define CS4234_PDN_ADC1_MASK 0x01
  87. #define CS4234_PDN_ADC1_SHIFT 0
  88. #define CS4234_LOW_LAT_CTRL1 0x11
  89. #define CS4234_LL_NG_MASK 0xE0
  90. #define CS4234_LL_NG_SHIFT 5
  91. #define CS4234_INV_LL_MASK 0x0F
  92. #define CS4234_INV_LL4_MASK 0x08
  93. #define CS4234_INV_LL4_SHIFT 3
  94. #define CS4234_INV_LL3_MASK 0x04
  95. #define CS4234_INV_LL3_SHIFT 2
  96. #define CS4234_INV_LL2_MASK 0x02
  97. #define CS4234_INV_LL2_SHIFT 1
  98. #define CS4234_INV_LL1_MASK 0x01
  99. #define CS4234_INV_LL1_SHIFT 0
  100. #define CS4234_DAC_CTRL1 0x12
  101. #define CS4234_DAC14_NG_MASK 0xE0
  102. #define CS4234_DAC14_NG_SHIFT 5
  103. #define CS4234_DAC14_DE_MASK 0x10
  104. #define CS4234_DAC14_DE_SHIFT 4
  105. #define CS4234_DAC5_DE_MASK 0x08
  106. #define CS4234_DAC5_DE_SHIFT 3
  107. #define CS4234_DAC5_MVC_MASK 0x04
  108. #define CS4234_DAC5_MVC_SHIFT 2
  109. #define CS4234_DAC5_CFG_FLTR_MASK 0x03
  110. #define CS4234_DAC5_CFG_FLTR_SHIFT 0
  111. #define CS4234_DAC_CTRL2 0x13
  112. #define CS4234_DAC5_NG_MASK 0xE0
  113. #define CS4234_DAC5_NG_SHIFT 5
  114. #define CS4234_INV_DAC_MASK 0x1F
  115. #define CS4234_INV_DAC5_MASK 0x10
  116. #define CS4234_INV_DAC5_SHIFT 4
  117. #define CS4234_INV_DAC4_MASK 0x08
  118. #define CS4234_INV_DAC4_SHIFT 3
  119. #define CS4234_INV_DAC3_MASK 0x04
  120. #define CS4234_INV_DAC3_SHIFT 2
  121. #define CS4234_INV_DAC2_MASK 0x02
  122. #define CS4234_INV_DAC2_SHIFT 1
  123. #define CS4234_INV_DAC1_MASK 0x01
  124. #define CS4234_INV_DAC1_SHIFT 0
  125. #define CS4234_DAC_CTRL3 0x14
  126. #define CS4234_DAC5_ATT_MASK 0x80
  127. #define CS4234_DAC5_ATT_SHIFT 7
  128. #define CS4234_DAC14_ATT_MASK 0x40
  129. #define CS4234_DAC14_ATT_SHIFT 6
  130. #define CS4234_MUTE_LL_MASK 0x20
  131. #define CS4234_MUTE_LL_SHIFT 5
  132. #define CS4234_MUTE_DAC5_MASK 0x10
  133. #define CS4234_MUTE_DAC5_SHIFT 4
  134. #define CS4234_MUTE_DAC4_MASK 0x08
  135. #define CS4234_MUTE_DAC4_SHIFT 3
  136. #define CS4234_MUTE_DAC3_MASK 0x04
  137. #define CS4234_MUTE_DAC3_SHIFT 2
  138. #define CS4234_MUTE_DAC2_MASK 0x02
  139. #define CS4234_MUTE_DAC2_SHIFT 1
  140. #define CS4234_MUTE_DAC1_MASK 0x01
  141. #define CS4234_MUTE_DAC1_SHIFT 0
  142. #define CS4234_DAC_CTRL4 0x15
  143. #define CS4234_VQ_RAMP_MASK 0x80
  144. #define CS4234_VQ_RAMP_SHIFT 7
  145. #define CS4234_TPS_GAIN_MASK 0x40
  146. #define CS4234_TPS_GAIN_SHIFT 6
  147. #define CS4234_PDN_DAC5_MASK 0x10
  148. #define CS4234_PDN_DAC5_SHIFT 4
  149. #define CS4234_PDN_DAC4_MASK 0x08
  150. #define CS4234_PDN_DAC4_SHIFT 3
  151. #define CS4234_PDN_DAC3_MASK 0x04
  152. #define CS4234_PDN_DAC3_SHIFT 2
  153. #define CS4234_PDN_DAC2_MASK 0x02
  154. #define CS4234_PDN_DAC2_SHIFT 1
  155. #define CS4234_PDN_DAC1_MASK 0x01
  156. #define CS4234_PDN_DAC1_SHIFT 0
  157. #define CS4234_VOLUME_MODE 0x16
  158. #define CS4234_MUTE_DELAY_MASK 0xC0
  159. #define CS4234_MUTE_DELAY_SHIFT 6
  160. #define CS4234_MIN_DELAY_MASK 0x38
  161. #define CS4234_MIN_DELAY_SHIFT 3
  162. #define CS4234_MAX_DELAY_MASK 0x07
  163. #define CS4234_MAX_DELAY_SHIFT 0
  164. #define CS4234_MASTER_VOL 0x17
  165. #define CS4234_DAC1_VOL 0x18
  166. #define CS4234_DAC2_VOL 0x19
  167. #define CS4234_DAC3_VOL 0x1A
  168. #define CS4234_DAC4_VOL 0x1B
  169. #define CS4234_DAC5_VOL 0x1C
  170. #define CS4234_INT_CTRL 0x1E
  171. #define CS4234_INT_MODE_MASK 0x80
  172. #define CS4234_INT_MODE_SHIFT 7
  173. #define CS4234_INT_PIN_MASK 0x60
  174. #define CS4234_INT_PIN_SHIFT 5
  175. #define CS4234_INT_MASK1 0x1F
  176. #define CS4234_MSK_TST_MODE_MASK 0x80
  177. #define CS4234_MSK_TST_MODE_ERR_SHIFT 7
  178. #define CS4234_MSK_SP_ERR_MASK 0x40
  179. #define CS4234_MSK_SP_ERR_SHIFT 6
  180. #define CS4234_MSK_CLK_ERR_MASK 0x08
  181. #define CS4234_MSK_CLK_ERR_SHIFT 5
  182. #define CS4234_MSK_ADC4_OVFL_MASK 0x08
  183. #define CS4234_MSK_ADC4_OVFL_SHIFT 3
  184. #define CS4234_MSK_ADC3_OVFL_MASK 0x04
  185. #define CS4234_MSK_ADC3_OVFL_SHIFT 2
  186. #define CS4234_MSK_ADC2_OVFL_MASK 0x02
  187. #define CS4234_MSK_ADC2_OVFL_SHIFT 1
  188. #define CS4234_MSK_ADC1_OVFL_MASK 0x01
  189. #define CS4234_MSK_ADC1_OVFL_SHIFT 0
  190. #define CS4234_INT_MASK2 0x20
  191. #define CS4234_MSK_DAC5_CLIP_MASK 0x10
  192. #define CS4234_MSK_DAC5_CLIP_SHIFT 4
  193. #define CS4234_MSK_DAC4_CLIP_MASK 0x08
  194. #define CS4234_MSK_DAC4_CLIP_SHIFT 3
  195. #define CS4234_MSK_DAC3_CLIP_MASK 0x04
  196. #define CS4234_MSK_DAC3_CLIP_SHIFT 2
  197. #define CS4234_MSK_DAC2_CLIP_MASK 0x02
  198. #define CS4234_MSK_DAC2_CLIP_SHIFT 1
  199. #define CS4234_MSK_DAC1_CLIP_MASK 0x01
  200. #define CS4234_MSK_DAC1_CLIP_SHIFT 0
  201. #define CS4234_INT_NOTIFY1 0x21
  202. #define CS4234_TST_MODE_MASK 0x80
  203. #define CS4234_TST_MODE_SHIFT 7
  204. #define CS4234_SP_ERR_MASK 0x40
  205. #define CS4234_SP_ERR_SHIFT 6
  206. #define CS4234_CLK_MOD_ERR_MASK 0x08
  207. #define CS4234_CLK_MOD_ERR_SHIFT 5
  208. #define CS4234_ADC4_OVFL_MASK 0x08
  209. #define CS4234_ADC4_OVFL_SHIFT 3
  210. #define CS4234_ADC3_OVFL_MASK 0x04
  211. #define CS4234_ADC3_OVFL_SHIFT 2
  212. #define CS4234_ADC2_OVFL_MASK 0x02
  213. #define CS4234_ADC2_OVFL_SHIFT 1
  214. #define CS4234_ADC1_OVFL_MASK 0x01
  215. #define CS4234_ADC1_OVFL_SHIFT 0
  216. #define CS4234_INT_NOTIFY2 0x22
  217. #define CS4234_DAC5_CLIP_MASK 0x10
  218. #define CS4234_DAC5_CLIP_SHIFT 4
  219. #define CS4234_DAC4_CLIP_MASK 0x08
  220. #define CS4234_DAC4_CLIP_SHIFT 3
  221. #define CS4234_DAC3_CLIP_MASK 0x04
  222. #define CS4234_DAC3_CLIP_SHIFT 2
  223. #define CS4234_DAC2_CLIP_MASK 0x02
  224. #define CS4234_DAC2_CLIP_SHIFT 1
  225. #define CS4234_DAC1_CLIP_MASK 0x01
  226. #define CS4234_DAC1_CLIP_SHIFT 0
  227. #define CS4234_MAX_REGISTER CS4234_INT_NOTIFY2
  228. #define CS4234_SUPPORTED_ID 0x423400
  229. #define CS4234_BOOT_TIME_US 3000
  230. #define CS4234_HOLD_RESET_TIME_US 1000
  231. #define CS4234_VQ_CHARGE_MS 1000
  232. #define CS4234_PCM_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  233. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
  234. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  235. #define CS4234_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
  236. SNDRV_PCM_FMTBIT_S20_LE | SNDRV_PCM_FMTBIT_S24_LE | \
  237. SNDRV_PCM_FMTBIT_S24_3LE)
  238. enum cs4234_supplies {
  239. CS4234_SUPPLY_VA = 0,
  240. CS4234_SUPPLY_VL,
  241. };
  242. enum cs4234_va_sel {
  243. CS4234_3V3 = 0,
  244. CS4234_5V,
  245. };
  246. enum cs4234_sp_format {
  247. CS4234_LEFT_J = 0,
  248. CS4234_I2S,
  249. CS4234_TDM,
  250. };
  251. enum cs4234_base_rate_advisory {
  252. CS4234_48K = 0,
  253. CS4234_44K1,
  254. CS4234_32K,
  255. };
  256. #endif