cs4234.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. // cs4234.c -- ALSA SoC CS4234 driver
  3. //
  4. // Copyright (C) 2020 Cirrus Logic, Inc. and
  5. // Cirrus Logic International Semiconductor Ltd.
  6. //
  7. #include <linux/clk.h>
  8. #include <linux/completion.h>
  9. #include <linux/delay.h>
  10. #include <linux/gpio/consumer.h>
  11. #include <linux/i2c.h>
  12. #include <linux/jiffies.h>
  13. #include <linux/mod_devicetable.h>
  14. #include <linux/module.h>
  15. #include <sound/pcm.h>
  16. #include <sound/pcm_params.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/regmap.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/slab.h>
  21. #include <sound/soc.h>
  22. #include <sound/tlv.h>
  23. #include <linux/workqueue.h>
  24. #include "cs4234.h"
  25. struct cs4234 {
  26. struct device *dev;
  27. struct regmap *regmap;
  28. struct gpio_desc *reset_gpio;
  29. struct regulator_bulk_data core_supplies[2];
  30. int num_core_supplies;
  31. struct completion vq_ramp_complete;
  32. struct delayed_work vq_ramp_delay;
  33. struct clk *mclk;
  34. unsigned long mclk_rate;
  35. unsigned long lrclk_rate;
  36. unsigned int format;
  37. struct snd_ratnum rate_dividers[2];
  38. struct snd_pcm_hw_constraint_ratnums rate_constraint;
  39. };
  40. /* -89.92dB to +6.02dB with step of 0.38dB */
  41. static const DECLARE_TLV_DB_SCALE(dac_tlv, -8992, 38, 0);
  42. static const char * const cs4234_dac14_delay_text[] = {
  43. "0us", "100us", "150us", "200us", "225us", "250us", "275us", "300us",
  44. "325us", "350us", "375us", "400us", "425us", "450us", "475us", "500us",
  45. };
  46. static SOC_ENUM_SINGLE_DECL(cs4234_dac14_group_delay, CS4234_TPS_CTRL,
  47. CS4234_GRP_DELAY_SHIFT, cs4234_dac14_delay_text);
  48. static const char * const cs4234_noise_gate_text[] = {
  49. "72dB", "78dB", "84dB", "90dB", "96dB", "102dB", "138dB", "Disabled",
  50. };
  51. static SOC_ENUM_SINGLE_DECL(cs4234_ll_noise_gate, CS4234_LOW_LAT_CTRL1,
  52. CS4234_LL_NG_SHIFT, cs4234_noise_gate_text);
  53. static SOC_ENUM_SINGLE_DECL(cs4234_dac14_noise_gate, CS4234_DAC_CTRL1,
  54. CS4234_DAC14_NG_SHIFT, cs4234_noise_gate_text);
  55. static SOC_ENUM_SINGLE_DECL(cs4234_dac5_noise_gate, CS4234_DAC_CTRL2,
  56. CS4234_DAC5_NG_SHIFT, cs4234_noise_gate_text);
  57. static const char * const cs4234_dac5_config_fltr_sel_text[] = {
  58. "Interpolation Filter", "Sample and Hold"
  59. };
  60. static SOC_ENUM_SINGLE_DECL(cs4234_dac5_config_fltr_sel, CS4234_DAC_CTRL1,
  61. CS4234_DAC5_CFG_FLTR_SHIFT,
  62. cs4234_dac5_config_fltr_sel_text);
  63. static const char * const cs4234_mute_delay_text[] = {
  64. "1x", "4x", "16x", "64x",
  65. };
  66. static SOC_ENUM_SINGLE_DECL(cs4234_mute_delay, CS4234_VOLUME_MODE,
  67. CS4234_MUTE_DELAY_SHIFT, cs4234_mute_delay_text);
  68. static const char * const cs4234_minmax_delay_text[] = {
  69. "1x", "2x", "4x", "8x", "16x", "32x", "64x", "128x",
  70. };
  71. static SOC_ENUM_SINGLE_DECL(cs4234_min_delay, CS4234_VOLUME_MODE,
  72. CS4234_MIN_DELAY_SHIFT, cs4234_minmax_delay_text);
  73. static SOC_ENUM_SINGLE_DECL(cs4234_max_delay, CS4234_VOLUME_MODE,
  74. CS4234_MAX_DELAY_SHIFT, cs4234_minmax_delay_text);
  75. static int cs4234_dac14_grp_delay_put(struct snd_kcontrol *kctrl,
  76. struct snd_ctl_elem_value *uctrl)
  77. {
  78. struct snd_soc_component *component = snd_soc_kcontrol_component(kctrl);
  79. struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
  80. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  81. unsigned int val = 0;
  82. int ret = 0;
  83. snd_soc_dapm_mutex_lock(dapm);
  84. regmap_read(cs4234->regmap, CS4234_ADC_CTRL2, &val);
  85. if ((val & 0x0F) != 0x0F) { // are all the ADCs powerdown
  86. ret = -EBUSY;
  87. dev_err(component->dev, "Can't change group delay while ADC are ON\n");
  88. goto exit;
  89. }
  90. regmap_read(cs4234->regmap, CS4234_DAC_CTRL4, &val);
  91. if ((val & 0x1F) != 0x1F) { // are all the DACs powerdown
  92. ret = -EBUSY;
  93. dev_err(component->dev, "Can't change group delay while DAC are ON\n");
  94. goto exit;
  95. }
  96. ret = snd_soc_put_enum_double(kctrl, uctrl);
  97. exit:
  98. snd_soc_dapm_mutex_unlock(dapm);
  99. return ret;
  100. }
  101. static void cs4234_vq_ramp_done(struct work_struct *work)
  102. {
  103. struct delayed_work *dw = to_delayed_work(work);
  104. struct cs4234 *cs4234 = container_of(dw, struct cs4234, vq_ramp_delay);
  105. complete_all(&cs4234->vq_ramp_complete);
  106. }
  107. static int cs4234_set_bias_level(struct snd_soc_component *component,
  108. enum snd_soc_bias_level level)
  109. {
  110. struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
  111. switch (level) {
  112. case SND_SOC_BIAS_PREPARE:
  113. switch (snd_soc_component_get_bias_level(component)) {
  114. case SND_SOC_BIAS_STANDBY:
  115. wait_for_completion(&cs4234->vq_ramp_complete);
  116. break;
  117. default:
  118. break;
  119. }
  120. break;
  121. default:
  122. break;
  123. }
  124. return 0;
  125. }
  126. static const struct snd_soc_dapm_widget cs4234_dapm_widgets[] = {
  127. SND_SOC_DAPM_AIF_IN("SDRX1", NULL, 0, SND_SOC_NOPM, 0, 0),
  128. SND_SOC_DAPM_AIF_IN("SDRX2", NULL, 1, SND_SOC_NOPM, 0, 0),
  129. SND_SOC_DAPM_AIF_IN("SDRX3", NULL, 2, SND_SOC_NOPM, 0, 0),
  130. SND_SOC_DAPM_AIF_IN("SDRX4", NULL, 3, SND_SOC_NOPM, 0, 0),
  131. SND_SOC_DAPM_AIF_IN("SDRX5", NULL, 4, SND_SOC_NOPM, 0, 0),
  132. SND_SOC_DAPM_DAC("DAC1", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC1_SHIFT, 1),
  133. SND_SOC_DAPM_DAC("DAC2", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC2_SHIFT, 1),
  134. SND_SOC_DAPM_DAC("DAC3", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC3_SHIFT, 1),
  135. SND_SOC_DAPM_DAC("DAC4", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC4_SHIFT, 1),
  136. SND_SOC_DAPM_DAC("DAC5", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC5_SHIFT, 1),
  137. SND_SOC_DAPM_OUTPUT("AOUT1"),
  138. SND_SOC_DAPM_OUTPUT("AOUT2"),
  139. SND_SOC_DAPM_OUTPUT("AOUT3"),
  140. SND_SOC_DAPM_OUTPUT("AOUT4"),
  141. SND_SOC_DAPM_OUTPUT("AOUT5"),
  142. SND_SOC_DAPM_INPUT("AIN1"),
  143. SND_SOC_DAPM_INPUT("AIN2"),
  144. SND_SOC_DAPM_INPUT("AIN3"),
  145. SND_SOC_DAPM_INPUT("AIN4"),
  146. SND_SOC_DAPM_ADC("ADC1", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC1_SHIFT, 1),
  147. SND_SOC_DAPM_ADC("ADC2", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC2_SHIFT, 1),
  148. SND_SOC_DAPM_ADC("ADC3", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC3_SHIFT, 1),
  149. SND_SOC_DAPM_ADC("ADC4", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC4_SHIFT, 1),
  150. SND_SOC_DAPM_AIF_OUT("SDTX1", NULL, 0, SND_SOC_NOPM, 0, 1),
  151. SND_SOC_DAPM_AIF_OUT("SDTX2", NULL, 1, SND_SOC_NOPM, 0, 1),
  152. SND_SOC_DAPM_AIF_OUT("SDTX3", NULL, 2, SND_SOC_NOPM, 0, 1),
  153. SND_SOC_DAPM_AIF_OUT("SDTX4", NULL, 3, SND_SOC_NOPM, 0, 1),
  154. };
  155. static const struct snd_soc_dapm_route cs4234_dapm_routes[] = {
  156. /* Playback */
  157. { "AOUT1", NULL, "DAC1" },
  158. { "AOUT2", NULL, "DAC2" },
  159. { "AOUT3", NULL, "DAC3" },
  160. { "AOUT4", NULL, "DAC4" },
  161. { "AOUT5", NULL, "DAC5" },
  162. { "DAC1", NULL, "SDRX1" },
  163. { "DAC2", NULL, "SDRX2" },
  164. { "DAC3", NULL, "SDRX3" },
  165. { "DAC4", NULL, "SDRX4" },
  166. { "DAC5", NULL, "SDRX5" },
  167. { "SDRX1", NULL, "Playback" },
  168. { "SDRX2", NULL, "Playback" },
  169. { "SDRX3", NULL, "Playback" },
  170. { "SDRX4", NULL, "Playback" },
  171. { "SDRX5", NULL, "Playback" },
  172. /* Capture */
  173. { "ADC1", NULL, "AIN1" },
  174. { "ADC2", NULL, "AIN2" },
  175. { "ADC3", NULL, "AIN3" },
  176. { "ADC4", NULL, "AIN4" },
  177. { "SDTX1", NULL, "ADC1" },
  178. { "SDTX2", NULL, "ADC2" },
  179. { "SDTX3", NULL, "ADC3" },
  180. { "SDTX4", NULL, "ADC4" },
  181. { "Capture", NULL, "SDTX1" },
  182. { "Capture", NULL, "SDTX2" },
  183. { "Capture", NULL, "SDTX3" },
  184. { "Capture", NULL, "SDTX4" },
  185. };
  186. static const struct snd_kcontrol_new cs4234_snd_controls[] = {
  187. SOC_SINGLE_TLV("Master Volume", CS4234_MASTER_VOL, 0, 0xff, 1, dac_tlv),
  188. SOC_SINGLE_TLV("DAC1 Volume", CS4234_DAC1_VOL, 0, 0xff, 1, dac_tlv),
  189. SOC_SINGLE_TLV("DAC2 Volume", CS4234_DAC2_VOL, 0, 0xff, 1, dac_tlv),
  190. SOC_SINGLE_TLV("DAC3 Volume", CS4234_DAC3_VOL, 0, 0xff, 1, dac_tlv),
  191. SOC_SINGLE_TLV("DAC4 Volume", CS4234_DAC4_VOL, 0, 0xff, 1, dac_tlv),
  192. SOC_SINGLE_TLV("DAC5 Volume", CS4234_DAC5_VOL, 0, 0xff, 1, dac_tlv),
  193. SOC_SINGLE("DAC5 Soft Ramp Switch", CS4234_DAC_CTRL3, CS4234_DAC5_ATT_SHIFT, 1, 1),
  194. SOC_SINGLE("DAC1-4 Soft Ramp Switch", CS4234_DAC_CTRL3, CS4234_DAC14_ATT_SHIFT, 1, 1),
  195. SOC_SINGLE("ADC HPF Switch", CS4234_ADC_CTRL1, CS4234_ENA_HPF_SHIFT, 1, 0),
  196. SOC_ENUM_EXT("DAC1-4 Group Delay", cs4234_dac14_group_delay,
  197. snd_soc_get_enum_double, cs4234_dac14_grp_delay_put),
  198. SOC_SINGLE("ADC1 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC1_SHIFT, 1, 0),
  199. SOC_SINGLE("ADC2 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC2_SHIFT, 1, 0),
  200. SOC_SINGLE("ADC3 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC3_SHIFT, 1, 0),
  201. SOC_SINGLE("ADC4 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC4_SHIFT, 1, 0),
  202. SOC_SINGLE("DAC1 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC1_SHIFT, 1, 0),
  203. SOC_SINGLE("DAC2 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC2_SHIFT, 1, 0),
  204. SOC_SINGLE("DAC3 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC3_SHIFT, 1, 0),
  205. SOC_SINGLE("DAC4 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC4_SHIFT, 1, 0),
  206. SOC_SINGLE("DAC5 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC5_SHIFT, 1, 0),
  207. SOC_SINGLE("ADC1 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC1_SHIFT, 1, 1),
  208. SOC_SINGLE("ADC2 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC2_SHIFT, 1, 1),
  209. SOC_SINGLE("ADC3 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC3_SHIFT, 1, 1),
  210. SOC_SINGLE("ADC4 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC4_SHIFT, 1, 1),
  211. SOC_SINGLE("DAC1 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC1_SHIFT, 1, 1),
  212. SOC_SINGLE("DAC2 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC2_SHIFT, 1, 1),
  213. SOC_SINGLE("DAC3 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC3_SHIFT, 1, 1),
  214. SOC_SINGLE("DAC4 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC4_SHIFT, 1, 1),
  215. SOC_SINGLE("DAC5 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC5_SHIFT, 1, 1),
  216. SOC_SINGLE("Low-latency Switch", CS4234_DAC_CTRL3, CS4234_MUTE_LL_SHIFT, 1, 1),
  217. SOC_SINGLE("DAC1 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
  218. CS4234_INV_LL1_SHIFT, 1, 0),
  219. SOC_SINGLE("DAC2 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
  220. CS4234_INV_LL2_SHIFT, 1, 0),
  221. SOC_SINGLE("DAC3 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
  222. CS4234_INV_LL3_SHIFT, 1, 0),
  223. SOC_SINGLE("DAC4 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
  224. CS4234_INV_LL4_SHIFT, 1, 0),
  225. SOC_ENUM("Low-latency Noise Gate", cs4234_ll_noise_gate),
  226. SOC_ENUM("DAC1-4 Noise Gate", cs4234_dac14_noise_gate),
  227. SOC_ENUM("DAC5 Noise Gate", cs4234_dac5_noise_gate),
  228. SOC_SINGLE("DAC1-4 De-emphasis Switch", CS4234_DAC_CTRL1,
  229. CS4234_DAC14_DE_SHIFT, 1, 0),
  230. SOC_SINGLE("DAC5 De-emphasis Switch", CS4234_DAC_CTRL1,
  231. CS4234_DAC5_DE_SHIFT, 1, 0),
  232. SOC_SINGLE("DAC5 Master Controlled Switch", CS4234_DAC_CTRL1,
  233. CS4234_DAC5_MVC_SHIFT, 1, 0),
  234. SOC_ENUM("DAC5 Filter", cs4234_dac5_config_fltr_sel),
  235. SOC_ENUM("Mute Delay", cs4234_mute_delay),
  236. SOC_ENUM("Ramp Minimum Delay", cs4234_min_delay),
  237. SOC_ENUM("Ramp Maximum Delay", cs4234_max_delay),
  238. };
  239. static int cs4234_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int format)
  240. {
  241. struct snd_soc_component *component = codec_dai->component;
  242. struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
  243. unsigned int sp_ctrl = 0;
  244. cs4234->format = format & SND_SOC_DAIFMT_FORMAT_MASK;
  245. switch (cs4234->format) {
  246. case SND_SOC_DAIFMT_LEFT_J:
  247. sp_ctrl |= CS4234_LEFT_J << CS4234_SP_FORMAT_SHIFT;
  248. break;
  249. case SND_SOC_DAIFMT_I2S:
  250. sp_ctrl |= CS4234_I2S << CS4234_SP_FORMAT_SHIFT;
  251. break;
  252. case SND_SOC_DAIFMT_DSP_A: /* TDM mode in datasheet */
  253. sp_ctrl |= CS4234_TDM << CS4234_SP_FORMAT_SHIFT;
  254. break;
  255. default:
  256. dev_err(component->dev, "Unsupported dai format\n");
  257. return -EINVAL;
  258. }
  259. switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
  260. case SND_SOC_DAIFMT_CBS_CFS:
  261. break;
  262. case SND_SOC_DAIFMT_CBM_CFM:
  263. if (cs4234->format == SND_SOC_DAIFMT_DSP_A) {
  264. dev_err(component->dev, "Unsupported DSP A format in master mode\n");
  265. return -EINVAL;
  266. }
  267. sp_ctrl |= CS4234_MST_SLV_MASK;
  268. break;
  269. default:
  270. dev_err(component->dev, "Unsupported master/slave mode\n");
  271. return -EINVAL;
  272. }
  273. switch (format & SND_SOC_DAIFMT_INV_MASK) {
  274. case SND_SOC_DAIFMT_NB_NF:
  275. break;
  276. case SND_SOC_DAIFMT_IB_NF:
  277. sp_ctrl |= CS4234_INVT_SCLK_MASK;
  278. break;
  279. default:
  280. dev_err(component->dev, "Unsupported inverted clock setting\n");
  281. return -EINVAL;
  282. }
  283. regmap_update_bits(cs4234->regmap, CS4234_SP_CTRL,
  284. CS4234_SP_FORMAT_MASK | CS4234_MST_SLV_MASK | CS4234_INVT_SCLK_MASK,
  285. sp_ctrl);
  286. return 0;
  287. }
  288. static int cs4234_dai_hw_params(struct snd_pcm_substream *sub,
  289. struct snd_pcm_hw_params *params,
  290. struct snd_soc_dai *dai)
  291. {
  292. struct snd_soc_component *component = dai->component;
  293. struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
  294. unsigned int mclk_mult, double_speed = 0;
  295. int ret = 0, rate_ad, sample_width;
  296. cs4234->lrclk_rate = params_rate(params);
  297. mclk_mult = cs4234->mclk_rate / cs4234->lrclk_rate;
  298. if (cs4234->lrclk_rate > 48000) {
  299. double_speed = 1;
  300. mclk_mult *= 2;
  301. }
  302. switch (mclk_mult) {
  303. case 256:
  304. case 384:
  305. case 512:
  306. regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP,
  307. CS4234_SPEED_MODE_MASK,
  308. double_speed << CS4234_SPEED_MODE_SHIFT);
  309. regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP,
  310. CS4234_MCLK_RATE_MASK,
  311. ((mclk_mult / 128) - 2) << CS4234_MCLK_RATE_SHIFT);
  312. break;
  313. default:
  314. dev_err(component->dev, "Unsupported mclk/lrclk rate\n");
  315. return -EINVAL;
  316. }
  317. switch (cs4234->lrclk_rate) {
  318. case 48000:
  319. case 96000:
  320. rate_ad = CS4234_48K;
  321. break;
  322. case 44100:
  323. case 88200:
  324. rate_ad = CS4234_44K1;
  325. break;
  326. case 32000:
  327. case 64000:
  328. rate_ad = CS4234_32K;
  329. break;
  330. default:
  331. dev_err(component->dev, "Unsupported LR clock\n");
  332. return -EINVAL;
  333. }
  334. regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP, CS4234_BASE_RATE_MASK,
  335. rate_ad << CS4234_BASE_RATE_SHIFT);
  336. sample_width = params_width(params);
  337. switch (sample_width) {
  338. case 16:
  339. sample_width = 0;
  340. break;
  341. case 18:
  342. sample_width = 1;
  343. break;
  344. case 20:
  345. sample_width = 2;
  346. break;
  347. case 24:
  348. sample_width = 3;
  349. break;
  350. default:
  351. dev_err(component->dev, "Unsupported sample width\n");
  352. return -EINVAL;
  353. }
  354. if (sub->stream == SNDRV_PCM_STREAM_CAPTURE)
  355. regmap_update_bits(cs4234->regmap, CS4234_SAMPLE_WIDTH,
  356. CS4234_SDOUTX_SW_MASK,
  357. sample_width << CS4234_SDOUTX_SW_SHIFT);
  358. else
  359. regmap_update_bits(cs4234->regmap, CS4234_SAMPLE_WIDTH,
  360. CS4234_INPUT_SW_MASK | CS4234_LOW_LAT_SW_MASK | CS4234_DAC5_SW_MASK,
  361. sample_width << CS4234_INPUT_SW_SHIFT |
  362. sample_width << CS4234_LOW_LAT_SW_SHIFT |
  363. sample_width << CS4234_DAC5_SW_SHIFT);
  364. return ret;
  365. }
  366. /* Scale MCLK rate by 64 to avoid overflow in the ratnum calculation */
  367. #define CS4234_MCLK_SCALE 64
  368. static const struct snd_ratnum cs4234_dividers[] = {
  369. {
  370. .num = 0,
  371. .den_min = 256 / CS4234_MCLK_SCALE,
  372. .den_max = 512 / CS4234_MCLK_SCALE,
  373. .den_step = 128 / CS4234_MCLK_SCALE,
  374. },
  375. {
  376. .num = 0,
  377. .den_min = 128 / CS4234_MCLK_SCALE,
  378. .den_max = 192 / CS4234_MCLK_SCALE,
  379. .den_step = 64 / CS4234_MCLK_SCALE,
  380. },
  381. };
  382. static int cs4234_dai_rule_rate(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
  383. {
  384. struct cs4234 *cs4234 = rule->private;
  385. int mclk = cs4234->mclk_rate;
  386. struct snd_interval ranges[] = {
  387. { /* Single Speed Mode */
  388. .min = mclk / clamp(mclk / 30000, 256, 512),
  389. .max = mclk / clamp(mclk / 50000, 256, 512),
  390. },
  391. { /* Double Speed Mode */
  392. .min = mclk / clamp(mclk / 60000, 128, 256),
  393. .max = mclk / clamp(mclk / 100000, 128, 256),
  394. },
  395. };
  396. return snd_interval_ranges(hw_param_interval(params, rule->var),
  397. ARRAY_SIZE(ranges), ranges, 0);
  398. }
  399. static int cs4234_dai_startup(struct snd_pcm_substream *sub, struct snd_soc_dai *dai)
  400. {
  401. struct snd_soc_component *comp = dai->component;
  402. struct cs4234 *cs4234 = snd_soc_component_get_drvdata(comp);
  403. int i, ret;
  404. switch (cs4234->format) {
  405. case SND_SOC_DAIFMT_LEFT_J:
  406. case SND_SOC_DAIFMT_I2S:
  407. cs4234->rate_constraint.nrats = 2;
  408. /*
  409. * Playback only supports 24-bit samples in these modes.
  410. * Note: SNDRV_PCM_HW_PARAM_SAMPLE_BITS constrains the physical
  411. * width, which we don't care about, so constrain the format.
  412. */
  413. if (sub->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  414. ret = snd_pcm_hw_constraint_mask64(
  415. sub->runtime,
  416. SNDRV_PCM_HW_PARAM_FORMAT,
  417. SNDRV_PCM_FMTBIT_S24_LE |
  418. SNDRV_PCM_FMTBIT_S24_3LE);
  419. if (ret < 0)
  420. return ret;
  421. ret = snd_pcm_hw_constraint_minmax(sub->runtime,
  422. SNDRV_PCM_HW_PARAM_CHANNELS,
  423. 1, 4);
  424. if (ret < 0)
  425. return ret;
  426. }
  427. break;
  428. case SND_SOC_DAIFMT_DSP_A:
  429. cs4234->rate_constraint.nrats = 1;
  430. break;
  431. default:
  432. dev_err(comp->dev, "Startup unsupported DAI format\n");
  433. return -EINVAL;
  434. }
  435. for (i = 0; i < cs4234->rate_constraint.nrats; i++)
  436. cs4234->rate_dividers[i].num = cs4234->mclk_rate / CS4234_MCLK_SCALE;
  437. ret = snd_pcm_hw_constraint_ratnums(sub->runtime, 0,
  438. SNDRV_PCM_HW_PARAM_RATE,
  439. &cs4234->rate_constraint);
  440. if (ret < 0)
  441. return ret;
  442. /*
  443. * MCLK/rate may be a valid ratio but out-of-spec (e.g. 24576000/64000)
  444. * so this rule limits the range of sample rate for given MCLK.
  445. */
  446. return snd_pcm_hw_rule_add(sub->runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  447. cs4234_dai_rule_rate, cs4234, -1);
  448. }
  449. static int cs4234_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  450. unsigned int rx_mask, int slots, int slot_width)
  451. {
  452. struct snd_soc_component *component = dai->component;
  453. struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
  454. unsigned int slot_offset, dac5_slot, dac5_mask_group;
  455. uint8_t dac5_masks[4];
  456. if (slot_width != 32) {
  457. dev_err(component->dev, "Unsupported slot width\n");
  458. return -EINVAL;
  459. }
  460. /* Either 4 or 5 consecutive bits, DAC5 is optional */
  461. slot_offset = ffs(tx_mask) - 1;
  462. tx_mask >>= slot_offset;
  463. if ((slot_offset % 4) || ((tx_mask != 0x0F) && (tx_mask != 0x1F))) {
  464. dev_err(component->dev, "Unsupported tx slots allocation\n");
  465. return -EINVAL;
  466. }
  467. regmap_update_bits(cs4234->regmap, CS4234_SP_DATA_SEL, CS4234_DAC14_SRC_MASK,
  468. (slot_offset / 4) << CS4234_DAC14_SRC_SHIFT);
  469. regmap_update_bits(cs4234->regmap, CS4234_SP_DATA_SEL, CS4234_LL_SRC_MASK,
  470. (slot_offset / 4) << CS4234_LL_SRC_SHIFT);
  471. if (tx_mask == 0x1F) {
  472. dac5_slot = slot_offset + 4;
  473. memset(dac5_masks, 0xFF, sizeof(dac5_masks));
  474. dac5_mask_group = dac5_slot / 8;
  475. dac5_slot %= 8;
  476. dac5_masks[dac5_mask_group] ^= BIT(7 - dac5_slot);
  477. regmap_bulk_write(cs4234->regmap,
  478. CS4234_SDIN1_MASK1,
  479. dac5_masks,
  480. ARRAY_SIZE(dac5_masks));
  481. }
  482. return 0;
  483. }
  484. static const struct snd_soc_dai_ops cs4234_dai_ops = {
  485. .set_fmt = cs4234_dai_set_fmt,
  486. .hw_params = cs4234_dai_hw_params,
  487. .startup = cs4234_dai_startup,
  488. .set_tdm_slot = cs4234_dai_set_tdm_slot,
  489. };
  490. static struct snd_soc_dai_driver cs4234_dai[] = {
  491. {
  492. .name = "cs4234-dai",
  493. .playback = {
  494. .stream_name = "Playback",
  495. .channels_min = 1,
  496. .channels_max = 5,
  497. .rates = CS4234_PCM_RATES,
  498. .formats = CS4234_FORMATS,
  499. },
  500. .capture = {
  501. .stream_name = "Capture",
  502. .channels_min = 1,
  503. .channels_max = 4,
  504. .rates = CS4234_PCM_RATES,
  505. .formats = CS4234_FORMATS,
  506. },
  507. .ops = &cs4234_dai_ops,
  508. .symmetric_rates = 1,
  509. },
  510. };
  511. static const struct reg_default cs4234_default_reg[] = {
  512. { CS4234_CLOCK_SP, 0x04},
  513. { CS4234_SAMPLE_WIDTH, 0xFF},
  514. { CS4234_SP_CTRL, 0x48},
  515. { CS4234_SP_DATA_SEL, 0x01},
  516. { CS4234_SDIN1_MASK1, 0xFF},
  517. { CS4234_SDIN1_MASK2, 0xFF},
  518. { CS4234_SDIN2_MASK1, 0xFF},
  519. { CS4234_SDIN2_MASK2, 0xFF},
  520. { CS4234_TPS_CTRL, 0x00},
  521. { CS4234_ADC_CTRL1, 0xC0},
  522. { CS4234_ADC_CTRL2, 0xFF},
  523. { CS4234_LOW_LAT_CTRL1, 0xE0},
  524. { CS4234_DAC_CTRL1, 0xE0},
  525. { CS4234_DAC_CTRL2, 0xE0},
  526. { CS4234_DAC_CTRL3, 0xBF},
  527. { CS4234_DAC_CTRL4, 0x1F},
  528. { CS4234_VOLUME_MODE, 0x87},
  529. { CS4234_MASTER_VOL, 0x10},
  530. { CS4234_DAC1_VOL, 0x10},
  531. { CS4234_DAC2_VOL, 0x10},
  532. { CS4234_DAC3_VOL, 0x10},
  533. { CS4234_DAC4_VOL, 0x10},
  534. { CS4234_DAC5_VOL, 0x10},
  535. { CS4234_INT_CTRL, 0x40},
  536. { CS4234_INT_MASK1, 0x10},
  537. { CS4234_INT_MASK2, 0x20},
  538. };
  539. static bool cs4234_readable_register(struct device *dev, unsigned int reg)
  540. {
  541. switch (reg) {
  542. case CS4234_DEVID_AB ... CS4234_DEVID_EF:
  543. case CS4234_REVID ... CS4234_DAC5_VOL:
  544. case CS4234_INT_CTRL ... CS4234_MAX_REGISTER:
  545. return true;
  546. default:
  547. return false;
  548. }
  549. }
  550. static bool cs4234_volatile_reg(struct device *dev, unsigned int reg)
  551. {
  552. switch (reg) {
  553. case CS4234_INT_NOTIFY1:
  554. case CS4234_INT_NOTIFY2:
  555. return true;
  556. default:
  557. return false;
  558. }
  559. }
  560. static bool cs4234_writeable_register(struct device *dev, unsigned int reg)
  561. {
  562. switch (reg) {
  563. case CS4234_DEVID_AB ... CS4234_REVID:
  564. case CS4234_INT_NOTIFY1 ... CS4234_INT_NOTIFY2:
  565. return false;
  566. default:
  567. return true;
  568. }
  569. }
  570. static const struct snd_soc_component_driver soc_component_cs4234 = {
  571. .dapm_widgets = cs4234_dapm_widgets,
  572. .num_dapm_widgets = ARRAY_SIZE(cs4234_dapm_widgets),
  573. .dapm_routes = cs4234_dapm_routes,
  574. .num_dapm_routes = ARRAY_SIZE(cs4234_dapm_routes),
  575. .controls = cs4234_snd_controls,
  576. .num_controls = ARRAY_SIZE(cs4234_snd_controls),
  577. .set_bias_level = cs4234_set_bias_level,
  578. .non_legacy_dai_naming = 1,
  579. .idle_bias_on = 1,
  580. .suspend_bias_off = 1,
  581. };
  582. static const struct regmap_config cs4234_regmap = {
  583. .reg_bits = 8,
  584. .val_bits = 8,
  585. .max_register = CS4234_MAX_REGISTER,
  586. .readable_reg = cs4234_readable_register,
  587. .volatile_reg = cs4234_volatile_reg,
  588. .writeable_reg = cs4234_writeable_register,
  589. .reg_defaults = cs4234_default_reg,
  590. .num_reg_defaults = ARRAY_SIZE(cs4234_default_reg),
  591. .cache_type = REGCACHE_RBTREE,
  592. .use_single_read = true,
  593. .use_single_write = true,
  594. };
  595. static const char * const cs4234_core_supplies[] = {
  596. "VA",
  597. "VL",
  598. };
  599. static void cs4234_shutdown(struct cs4234 *cs4234)
  600. {
  601. cancel_delayed_work_sync(&cs4234->vq_ramp_delay);
  602. reinit_completion(&cs4234->vq_ramp_complete);
  603. regmap_update_bits(cs4234->regmap, CS4234_DAC_CTRL4, CS4234_VQ_RAMP_MASK,
  604. CS4234_VQ_RAMP_MASK);
  605. msleep(50);
  606. regcache_cache_only(cs4234->regmap, true);
  607. /* Clear VQ Ramp Bit in cache for the next PowerUp */
  608. regmap_update_bits(cs4234->regmap, CS4234_DAC_CTRL4, CS4234_VQ_RAMP_MASK, 0);
  609. gpiod_set_value_cansleep(cs4234->reset_gpio, 0);
  610. regulator_bulk_disable(cs4234->num_core_supplies, cs4234->core_supplies);
  611. clk_disable_unprepare(cs4234->mclk);
  612. }
  613. static int cs4234_powerup(struct cs4234 *cs4234)
  614. {
  615. int ret;
  616. ret = clk_prepare_enable(cs4234->mclk);
  617. if (ret) {
  618. dev_err(cs4234->dev, "Failed to enable mclk: %d\n", ret);
  619. return ret;
  620. }
  621. ret = regulator_bulk_enable(cs4234->num_core_supplies, cs4234->core_supplies);
  622. if (ret) {
  623. dev_err(cs4234->dev, "Failed to enable core supplies: %d\n", ret);
  624. clk_disable_unprepare(cs4234->mclk);
  625. return ret;
  626. }
  627. usleep_range(CS4234_HOLD_RESET_TIME_US, 2 * CS4234_HOLD_RESET_TIME_US);
  628. gpiod_set_value_cansleep(cs4234->reset_gpio, 1);
  629. /* Make sure hardware reset done 2 ms + (3000/MCLK) */
  630. usleep_range(CS4234_BOOT_TIME_US, CS4234_BOOT_TIME_US * 2);
  631. queue_delayed_work(system_power_efficient_wq,
  632. &cs4234->vq_ramp_delay,
  633. msecs_to_jiffies(CS4234_VQ_CHARGE_MS));
  634. return 0;
  635. }
  636. static int cs4234_i2c_probe(struct i2c_client *i2c_client, const struct i2c_device_id *id)
  637. {
  638. struct cs4234 *cs4234;
  639. struct device *dev = &i2c_client->dev;
  640. unsigned int revid;
  641. uint32_t devid;
  642. uint8_t ids[3];
  643. int ret = 0, i;
  644. cs4234 = devm_kzalloc(dev, sizeof(*cs4234), GFP_KERNEL);
  645. if (!cs4234)
  646. return -ENOMEM;
  647. i2c_set_clientdata(i2c_client, cs4234);
  648. cs4234->dev = dev;
  649. init_completion(&cs4234->vq_ramp_complete);
  650. INIT_DELAYED_WORK(&cs4234->vq_ramp_delay, cs4234_vq_ramp_done);
  651. cs4234->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
  652. if (IS_ERR(cs4234->reset_gpio))
  653. return PTR_ERR(cs4234->reset_gpio);
  654. BUILD_BUG_ON(ARRAY_SIZE(cs4234->core_supplies) < ARRAY_SIZE(cs4234_core_supplies));
  655. cs4234->num_core_supplies = ARRAY_SIZE(cs4234_core_supplies);
  656. for (i = 0; i < ARRAY_SIZE(cs4234_core_supplies); i++)
  657. cs4234->core_supplies[i].supply = cs4234_core_supplies[i];
  658. ret = devm_regulator_bulk_get(dev, cs4234->num_core_supplies, cs4234->core_supplies);
  659. if (ret) {
  660. dev_err(dev, "Failed to request core supplies %d\n", ret);
  661. return ret;
  662. }
  663. cs4234->mclk = devm_clk_get(dev, "mclk");
  664. if (IS_ERR(cs4234->mclk)) {
  665. ret = PTR_ERR(cs4234->mclk);
  666. dev_err(dev, "Failed to get the mclk: %d\n", ret);
  667. return ret;
  668. }
  669. cs4234->mclk_rate = clk_get_rate(cs4234->mclk);
  670. if (cs4234->mclk_rate < 7680000 || cs4234->mclk_rate > 25600000) {
  671. dev_err(dev, "Invalid Master Clock rate\n");
  672. return -EINVAL;
  673. }
  674. cs4234->regmap = devm_regmap_init_i2c(i2c_client, &cs4234_regmap);
  675. if (IS_ERR(cs4234->regmap)) {
  676. ret = PTR_ERR(cs4234->regmap);
  677. dev_err(dev, "regmap_init() failed: %d\n", ret);
  678. return ret;
  679. }
  680. ret = cs4234_powerup(cs4234);
  681. if (ret)
  682. return ret;
  683. ret = regmap_bulk_read(cs4234->regmap, CS4234_DEVID_AB, ids, ARRAY_SIZE(ids));
  684. if (ret < 0) {
  685. dev_err(dev, "Failed to read DEVID: %d\n", ret);
  686. goto fail_shutdown;
  687. }
  688. devid = (ids[0] << 16) | (ids[1] << 8) | ids[2];
  689. if (devid != CS4234_SUPPORTED_ID) {
  690. dev_err(dev, "Unknown device ID: %x\n", devid);
  691. ret = -EINVAL;
  692. goto fail_shutdown;
  693. }
  694. ret = regmap_read(cs4234->regmap, CS4234_REVID, &revid);
  695. if (ret < 0) {
  696. dev_err(dev, "Failed to read CS4234_REVID: %d\n", ret);
  697. goto fail_shutdown;
  698. }
  699. dev_info(dev, "Cirrus Logic CS4234, Alpha Rev: %02X, Numeric Rev: %02X\n",
  700. (revid & 0xF0) >> 4, revid & 0x0F);
  701. ret = regulator_get_voltage(cs4234->core_supplies[CS4234_SUPPLY_VA].consumer);
  702. switch (ret) {
  703. case 3135000 ... 3650000:
  704. regmap_update_bits(cs4234->regmap, CS4234_ADC_CTRL1,
  705. CS4234_VA_SEL_MASK,
  706. CS4234_3V3 << CS4234_VA_SEL_SHIFT);
  707. break;
  708. case 4750000 ... 5250000:
  709. regmap_update_bits(cs4234->regmap, CS4234_ADC_CTRL1,
  710. CS4234_VA_SEL_MASK,
  711. CS4234_5V << CS4234_VA_SEL_SHIFT);
  712. break;
  713. default:
  714. dev_err(dev, "Invalid VA voltage\n");
  715. ret = -EINVAL;
  716. goto fail_shutdown;
  717. }
  718. pm_runtime_set_active(&i2c_client->dev);
  719. pm_runtime_enable(&i2c_client->dev);
  720. memcpy(&cs4234->rate_dividers, &cs4234_dividers, sizeof(cs4234_dividers));
  721. cs4234->rate_constraint.rats = cs4234->rate_dividers;
  722. ret = snd_soc_register_component(dev, &soc_component_cs4234, cs4234_dai,
  723. ARRAY_SIZE(cs4234_dai));
  724. if (ret < 0) {
  725. dev_err(dev, "Failed to register component:%d\n", ret);
  726. pm_runtime_disable(&i2c_client->dev);
  727. goto fail_shutdown;
  728. }
  729. return ret;
  730. fail_shutdown:
  731. cs4234_shutdown(cs4234);
  732. return ret;
  733. }
  734. static int cs4234_i2c_remove(struct i2c_client *i2c_client)
  735. {
  736. struct cs4234 *cs4234 = i2c_get_clientdata(i2c_client);
  737. struct device *dev = &i2c_client->dev;
  738. snd_soc_unregister_component(dev);
  739. pm_runtime_disable(dev);
  740. cs4234_shutdown(cs4234);
  741. return 0;
  742. }
  743. static int __maybe_unused cs4234_runtime_resume(struct device *dev)
  744. {
  745. struct cs4234 *cs4234 = dev_get_drvdata(dev);
  746. int ret;
  747. ret = cs4234_powerup(cs4234);
  748. if (ret)
  749. return ret;
  750. regcache_mark_dirty(cs4234->regmap);
  751. regcache_cache_only(cs4234->regmap, false);
  752. ret = regcache_sync(cs4234->regmap);
  753. if (ret) {
  754. dev_err(dev, "Failed to sync regmap: %d\n", ret);
  755. cs4234_shutdown(cs4234);
  756. return ret;
  757. }
  758. return 0;
  759. }
  760. static int __maybe_unused cs4234_runtime_suspend(struct device *dev)
  761. {
  762. struct cs4234 *cs4234 = dev_get_drvdata(dev);
  763. cs4234_shutdown(cs4234);
  764. return 0;
  765. }
  766. static const struct dev_pm_ops cs4234_pm = {
  767. SET_RUNTIME_PM_OPS(cs4234_runtime_suspend, cs4234_runtime_resume, NULL)
  768. };
  769. static const struct of_device_id cs4234_of_match[] = {
  770. { .compatible = "cirrus,cs4234", },
  771. { }
  772. };
  773. MODULE_DEVICE_TABLE(of, cs4234_of_match);
  774. static struct i2c_driver cs4234_i2c_driver = {
  775. .driver = {
  776. .name = "cs4234",
  777. .pm = &cs4234_pm,
  778. .of_match_table = cs4234_of_match,
  779. },
  780. .probe = cs4234_i2c_probe,
  781. .remove = cs4234_i2c_remove,
  782. };
  783. module_i2c_driver(cs4234_i2c_driver);
  784. MODULE_DESCRIPTION("ASoC Cirrus Logic CS4234 driver");
  785. MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
  786. MODULE_LICENSE("GPL v2");