cs35l36.c 56 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957
  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // cs35l36.c -- CS35L36 ALSA SoC audio driver
  4. //
  5. // Copyright 2018 Cirrus Logic, Inc.
  6. //
  7. // Author: James Schulman <james.schulman@cirrus.com>
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/i2c.h>
  14. #include <linux/slab.h>
  15. #include <linux/workqueue.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/gpio/consumer.h>
  19. #include <linux/of_device.h>
  20. #include <linux/of_gpio.h>
  21. #include <linux/regmap.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <linux/gpio.h>
  28. #include <sound/initval.h>
  29. #include <sound/tlv.h>
  30. #include <sound/cs35l36.h>
  31. #include <linux/of_irq.h>
  32. #include <linux/completion.h>
  33. #include "cs35l36.h"
  34. /*
  35. * Some fields take zero as a valid value so use a high bit flag that won't
  36. * get written to the device to mark those.
  37. */
  38. #define CS35L36_VALID_PDATA 0x80000000
  39. static const char * const cs35l36_supplies[] = {
  40. "VA",
  41. "VP",
  42. };
  43. struct cs35l36_private {
  44. struct device *dev;
  45. struct cs35l36_platform_data pdata;
  46. struct regmap *regmap;
  47. struct regulator_bulk_data supplies[2];
  48. int num_supplies;
  49. int clksrc;
  50. int chip_version;
  51. int rev_id;
  52. int ldm_mode_sel;
  53. struct gpio_desc *reset_gpio;
  54. };
  55. struct cs35l36_pll_config {
  56. int freq;
  57. int clk_cfg;
  58. int fll_igain;
  59. };
  60. static const struct cs35l36_pll_config cs35l36_pll_sysclk[] = {
  61. {32768, 0x00, 0x05},
  62. {8000, 0x01, 0x03},
  63. {11025, 0x02, 0x03},
  64. {12000, 0x03, 0x03},
  65. {16000, 0x04, 0x04},
  66. {22050, 0x05, 0x04},
  67. {24000, 0x06, 0x04},
  68. {32000, 0x07, 0x05},
  69. {44100, 0x08, 0x05},
  70. {48000, 0x09, 0x05},
  71. {88200, 0x0A, 0x06},
  72. {96000, 0x0B, 0x06},
  73. {128000, 0x0C, 0x07},
  74. {176400, 0x0D, 0x07},
  75. {192000, 0x0E, 0x07},
  76. {256000, 0x0F, 0x08},
  77. {352800, 0x10, 0x08},
  78. {384000, 0x11, 0x08},
  79. {512000, 0x12, 0x09},
  80. {705600, 0x13, 0x09},
  81. {750000, 0x14, 0x09},
  82. {768000, 0x15, 0x09},
  83. {1000000, 0x16, 0x0A},
  84. {1024000, 0x17, 0x0A},
  85. {1200000, 0x18, 0x0A},
  86. {1411200, 0x19, 0x0A},
  87. {1500000, 0x1A, 0x0A},
  88. {1536000, 0x1B, 0x0A},
  89. {2000000, 0x1C, 0x0A},
  90. {2048000, 0x1D, 0x0A},
  91. {2400000, 0x1E, 0x0A},
  92. {2822400, 0x1F, 0x0A},
  93. {3000000, 0x20, 0x0A},
  94. {3072000, 0x21, 0x0A},
  95. {3200000, 0x22, 0x0A},
  96. {4000000, 0x23, 0x0A},
  97. {4096000, 0x24, 0x0A},
  98. {4800000, 0x25, 0x0A},
  99. {5644800, 0x26, 0x0A},
  100. {6000000, 0x27, 0x0A},
  101. {6144000, 0x28, 0x0A},
  102. {6250000, 0x29, 0x08},
  103. {6400000, 0x2A, 0x0A},
  104. {6500000, 0x2B, 0x08},
  105. {6750000, 0x2C, 0x09},
  106. {7526400, 0x2D, 0x0A},
  107. {8000000, 0x2E, 0x0A},
  108. {8192000, 0x2F, 0x0A},
  109. {9600000, 0x30, 0x0A},
  110. {11289600, 0x31, 0x0A},
  111. {12000000, 0x32, 0x0A},
  112. {12288000, 0x33, 0x0A},
  113. {12500000, 0x34, 0x08},
  114. {12800000, 0x35, 0x0A},
  115. {13000000, 0x36, 0x0A},
  116. {13500000, 0x37, 0x0A},
  117. {19200000, 0x38, 0x0A},
  118. {22579200, 0x39, 0x0A},
  119. {24000000, 0x3A, 0x0A},
  120. {24576000, 0x3B, 0x0A},
  121. {25000000, 0x3C, 0x0A},
  122. {25600000, 0x3D, 0x0A},
  123. {26000000, 0x3E, 0x0A},
  124. {27000000, 0x3F, 0x0A},
  125. };
  126. static struct reg_default cs35l36_reg[] = {
  127. {CS35L36_TESTKEY_CTRL, 0x00000000},
  128. {CS35L36_USERKEY_CTL, 0x00000000},
  129. {CS35L36_OTP_CTRL1, 0x00002460},
  130. {CS35L36_OTP_CTRL2, 0x00000000},
  131. {CS35L36_OTP_CTRL3, 0x00000000},
  132. {CS35L36_OTP_CTRL4, 0x00000000},
  133. {CS35L36_OTP_CTRL5, 0x00000000},
  134. {CS35L36_PAC_CTL1, 0x00000004},
  135. {CS35L36_PAC_CTL2, 0x00000000},
  136. {CS35L36_PAC_CTL3, 0x00000000},
  137. {CS35L36_PWR_CTRL1, 0x00000000},
  138. {CS35L36_PWR_CTRL2, 0x00003321},
  139. {CS35L36_PWR_CTRL3, 0x01000010},
  140. {CS35L36_CTRL_OVRRIDE, 0x00000002},
  141. {CS35L36_AMP_OUT_MUTE, 0x00000000},
  142. {CS35L36_OTP_TRIM_STATUS, 0x00000000},
  143. {CS35L36_DISCH_FILT, 0x00000000},
  144. {CS35L36_PROTECT_REL_ERR, 0x00000000},
  145. {CS35L36_PAD_INTERFACE, 0x00000038},
  146. {CS35L36_PLL_CLK_CTRL, 0x00000010},
  147. {CS35L36_GLOBAL_CLK_CTRL, 0x00000003},
  148. {CS35L36_ADC_CLK_CTRL, 0x00000000},
  149. {CS35L36_SWIRE_CLK_CTRL, 0x00000000},
  150. {CS35L36_SP_SCLK_CLK_CTRL, 0x00000000},
  151. {CS35L36_MDSYNC_EN, 0x00000000},
  152. {CS35L36_MDSYNC_TX_ID, 0x00000000},
  153. {CS35L36_MDSYNC_PWR_CTRL, 0x00000000},
  154. {CS35L36_MDSYNC_DATA_TX, 0x00000000},
  155. {CS35L36_MDSYNC_TX_STATUS, 0x00000002},
  156. {CS35L36_MDSYNC_RX_STATUS, 0x00000000},
  157. {CS35L36_MDSYNC_ERR_STATUS, 0x00000000},
  158. {CS35L36_BSTCVRT_VCTRL1, 0x00000000},
  159. {CS35L36_BSTCVRT_VCTRL2, 0x00000001},
  160. {CS35L36_BSTCVRT_PEAK_CUR, 0x0000004A},
  161. {CS35L36_BSTCVRT_SFT_RAMP, 0x00000003},
  162. {CS35L36_BSTCVRT_COEFF, 0x00002424},
  163. {CS35L36_BSTCVRT_SLOPE_LBST, 0x00005800},
  164. {CS35L36_BSTCVRT_SW_FREQ, 0x00010000},
  165. {CS35L36_BSTCVRT_DCM_CTRL, 0x00002001},
  166. {CS35L36_BSTCVRT_DCM_MODE_FORCE, 0x00000000},
  167. {CS35L36_BSTCVRT_OVERVOLT_CTRL, 0x00000130},
  168. {CS35L36_VPI_LIMIT_MODE, 0x00000000},
  169. {CS35L36_VPI_LIMIT_MINMAX, 0x00003000},
  170. {CS35L36_VPI_VP_THLD, 0x00101010},
  171. {CS35L36_VPI_TRACK_CTRL, 0x00000000},
  172. {CS35L36_VPI_TRIG_MODE_CTRL, 0x00000000},
  173. {CS35L36_VPI_TRIG_STEPS, 0x00000000},
  174. {CS35L36_VI_SPKMON_FILT, 0x00000003},
  175. {CS35L36_VI_SPKMON_GAIN, 0x00000909},
  176. {CS35L36_VI_SPKMON_IP_SEL, 0x00000000},
  177. {CS35L36_DTEMP_WARN_THLD, 0x00000002},
  178. {CS35L36_DTEMP_STATUS, 0x00000000},
  179. {CS35L36_VPVBST_FS_SEL, 0x00000001},
  180. {CS35L36_VPVBST_VP_CTRL, 0x000001C0},
  181. {CS35L36_VPVBST_VBST_CTRL, 0x000001C0},
  182. {CS35L36_ASP_TX_PIN_CTRL, 0x00000028},
  183. {CS35L36_ASP_RATE_CTRL, 0x00090000},
  184. {CS35L36_ASP_FORMAT, 0x00000002},
  185. {CS35L36_ASP_FRAME_CTRL, 0x00180018},
  186. {CS35L36_ASP_TX1_TX2_SLOT, 0x00010000},
  187. {CS35L36_ASP_TX3_TX4_SLOT, 0x00030002},
  188. {CS35L36_ASP_TX5_TX6_SLOT, 0x00050004},
  189. {CS35L36_ASP_TX7_TX8_SLOT, 0x00070006},
  190. {CS35L36_ASP_RX1_SLOT, 0x00000000},
  191. {CS35L36_ASP_RX_TX_EN, 0x00000000},
  192. {CS35L36_ASP_RX1_SEL, 0x00000008},
  193. {CS35L36_ASP_TX1_SEL, 0x00000018},
  194. {CS35L36_ASP_TX2_SEL, 0x00000019},
  195. {CS35L36_ASP_TX3_SEL, 0x00000028},
  196. {CS35L36_ASP_TX4_SEL, 0x00000029},
  197. {CS35L36_ASP_TX5_SEL, 0x00000020},
  198. {CS35L36_ASP_TX6_SEL, 0x00000000},
  199. {CS35L36_SWIRE_P1_TX1_SEL, 0x00000018},
  200. {CS35L36_SWIRE_P1_TX2_SEL, 0x00000019},
  201. {CS35L36_SWIRE_P2_TX1_SEL, 0x00000028},
  202. {CS35L36_SWIRE_P2_TX2_SEL, 0x00000029},
  203. {CS35L36_SWIRE_P2_TX3_SEL, 0x00000020},
  204. {CS35L36_SWIRE_DP1_FIFO_CFG, 0x0000001B},
  205. {CS35L36_SWIRE_DP2_FIFO_CFG, 0x0000001B},
  206. {CS35L36_SWIRE_DP3_FIFO_CFG, 0x0000001B},
  207. {CS35L36_SWIRE_PCM_RX_DATA, 0x00000000},
  208. {CS35L36_SWIRE_FS_SEL, 0x00000001},
  209. {CS35L36_AMP_DIG_VOL_CTRL, 0x00008000},
  210. {CS35L36_VPBR_CFG, 0x02AA1905},
  211. {CS35L36_VBBR_CFG, 0x02AA1905},
  212. {CS35L36_VPBR_STATUS, 0x00000000},
  213. {CS35L36_VBBR_STATUS, 0x00000000},
  214. {CS35L36_OVERTEMP_CFG, 0x00000001},
  215. {CS35L36_AMP_ERR_VOL, 0x00000000},
  216. {CS35L36_CLASSH_CFG, 0x000B0405},
  217. {CS35L36_CLASSH_FET_DRV_CFG, 0x00000111},
  218. {CS35L36_NG_CFG, 0x00000033},
  219. {CS35L36_AMP_GAIN_CTRL, 0x00000273},
  220. {CS35L36_PWM_MOD_IO_CTRL, 0x00000000},
  221. {CS35L36_PWM_MOD_STATUS, 0x00000000},
  222. {CS35L36_DAC_MSM_CFG, 0x00000000},
  223. {CS35L36_AMP_SLOPE_CTRL, 0x00000B00},
  224. {CS35L36_AMP_PDM_VOLUME, 0x00000000},
  225. {CS35L36_AMP_PDM_RATE_CTRL, 0x00000000},
  226. {CS35L36_PDM_CH_SEL, 0x00000000},
  227. {CS35L36_AMP_NG_CTRL, 0x0000212F},
  228. {CS35L36_PDM_HIGHFILT_CTRL, 0x00000000},
  229. {CS35L36_PAC_INT0_CTRL, 0x00000001},
  230. {CS35L36_PAC_INT1_CTRL, 0x00000001},
  231. {CS35L36_PAC_INT2_CTRL, 0x00000001},
  232. {CS35L36_PAC_INT3_CTRL, 0x00000001},
  233. {CS35L36_PAC_INT4_CTRL, 0x00000001},
  234. {CS35L36_PAC_INT5_CTRL, 0x00000001},
  235. {CS35L36_PAC_INT6_CTRL, 0x00000001},
  236. {CS35L36_PAC_INT7_CTRL, 0x00000001},
  237. };
  238. static bool cs35l36_readable_reg(struct device *dev, unsigned int reg)
  239. {
  240. switch (reg) {
  241. case CS35L36_SW_RESET:
  242. case CS35L36_SW_REV:
  243. case CS35L36_HW_REV:
  244. case CS35L36_TESTKEY_CTRL:
  245. case CS35L36_USERKEY_CTL:
  246. case CS35L36_OTP_MEM30:
  247. case CS35L36_OTP_CTRL1:
  248. case CS35L36_OTP_CTRL2:
  249. case CS35L36_OTP_CTRL3:
  250. case CS35L36_OTP_CTRL4:
  251. case CS35L36_OTP_CTRL5:
  252. case CS35L36_PAC_CTL1:
  253. case CS35L36_PAC_CTL2:
  254. case CS35L36_PAC_CTL3:
  255. case CS35L36_DEVICE_ID:
  256. case CS35L36_FAB_ID:
  257. case CS35L36_REV_ID:
  258. case CS35L36_PWR_CTRL1:
  259. case CS35L36_PWR_CTRL2:
  260. case CS35L36_PWR_CTRL3:
  261. case CS35L36_CTRL_OVRRIDE:
  262. case CS35L36_AMP_OUT_MUTE:
  263. case CS35L36_OTP_TRIM_STATUS:
  264. case CS35L36_DISCH_FILT:
  265. case CS35L36_PROTECT_REL_ERR:
  266. case CS35L36_PAD_INTERFACE:
  267. case CS35L36_PLL_CLK_CTRL:
  268. case CS35L36_GLOBAL_CLK_CTRL:
  269. case CS35L36_ADC_CLK_CTRL:
  270. case CS35L36_SWIRE_CLK_CTRL:
  271. case CS35L36_SP_SCLK_CLK_CTRL:
  272. case CS35L36_TST_FS_MON0:
  273. case CS35L36_MDSYNC_EN:
  274. case CS35L36_MDSYNC_TX_ID:
  275. case CS35L36_MDSYNC_PWR_CTRL:
  276. case CS35L36_MDSYNC_DATA_TX:
  277. case CS35L36_MDSYNC_TX_STATUS:
  278. case CS35L36_MDSYNC_RX_STATUS:
  279. case CS35L36_MDSYNC_ERR_STATUS:
  280. case CS35L36_BSTCVRT_VCTRL1:
  281. case CS35L36_BSTCVRT_VCTRL2:
  282. case CS35L36_BSTCVRT_PEAK_CUR:
  283. case CS35L36_BSTCVRT_SFT_RAMP:
  284. case CS35L36_BSTCVRT_COEFF:
  285. case CS35L36_BSTCVRT_SLOPE_LBST:
  286. case CS35L36_BSTCVRT_SW_FREQ:
  287. case CS35L36_BSTCVRT_DCM_CTRL:
  288. case CS35L36_BSTCVRT_DCM_MODE_FORCE:
  289. case CS35L36_BSTCVRT_OVERVOLT_CTRL:
  290. case CS35L36_BST_TST_MANUAL:
  291. case CS35L36_BST_ANA2_TEST:
  292. case CS35L36_VPI_LIMIT_MODE:
  293. case CS35L36_VPI_LIMIT_MINMAX:
  294. case CS35L36_VPI_VP_THLD:
  295. case CS35L36_VPI_TRACK_CTRL:
  296. case CS35L36_VPI_TRIG_MODE_CTRL:
  297. case CS35L36_VPI_TRIG_STEPS:
  298. case CS35L36_VI_SPKMON_FILT:
  299. case CS35L36_VI_SPKMON_GAIN:
  300. case CS35L36_VI_SPKMON_IP_SEL:
  301. case CS35L36_DTEMP_WARN_THLD:
  302. case CS35L36_DTEMP_STATUS:
  303. case CS35L36_VPVBST_FS_SEL:
  304. case CS35L36_VPVBST_VP_CTRL:
  305. case CS35L36_VPVBST_VBST_CTRL:
  306. case CS35L36_ASP_TX_PIN_CTRL:
  307. case CS35L36_ASP_RATE_CTRL:
  308. case CS35L36_ASP_FORMAT:
  309. case CS35L36_ASP_FRAME_CTRL:
  310. case CS35L36_ASP_TX1_TX2_SLOT:
  311. case CS35L36_ASP_TX3_TX4_SLOT:
  312. case CS35L36_ASP_TX5_TX6_SLOT:
  313. case CS35L36_ASP_TX7_TX8_SLOT:
  314. case CS35L36_ASP_RX1_SLOT:
  315. case CS35L36_ASP_RX_TX_EN:
  316. case CS35L36_ASP_RX1_SEL:
  317. case CS35L36_ASP_TX1_SEL:
  318. case CS35L36_ASP_TX2_SEL:
  319. case CS35L36_ASP_TX3_SEL:
  320. case CS35L36_ASP_TX4_SEL:
  321. case CS35L36_ASP_TX5_SEL:
  322. case CS35L36_ASP_TX6_SEL:
  323. case CS35L36_SWIRE_P1_TX1_SEL:
  324. case CS35L36_SWIRE_P1_TX2_SEL:
  325. case CS35L36_SWIRE_P2_TX1_SEL:
  326. case CS35L36_SWIRE_P2_TX2_SEL:
  327. case CS35L36_SWIRE_P2_TX3_SEL:
  328. case CS35L36_SWIRE_DP1_FIFO_CFG:
  329. case CS35L36_SWIRE_DP2_FIFO_CFG:
  330. case CS35L36_SWIRE_DP3_FIFO_CFG:
  331. case CS35L36_SWIRE_PCM_RX_DATA:
  332. case CS35L36_SWIRE_FS_SEL:
  333. case CS35L36_AMP_DIG_VOL_CTRL:
  334. case CS35L36_VPBR_CFG:
  335. case CS35L36_VBBR_CFG:
  336. case CS35L36_VPBR_STATUS:
  337. case CS35L36_VBBR_STATUS:
  338. case CS35L36_OVERTEMP_CFG:
  339. case CS35L36_AMP_ERR_VOL:
  340. case CS35L36_CLASSH_CFG:
  341. case CS35L36_CLASSH_FET_DRV_CFG:
  342. case CS35L36_NG_CFG:
  343. case CS35L36_AMP_GAIN_CTRL:
  344. case CS35L36_PWM_MOD_IO_CTRL:
  345. case CS35L36_PWM_MOD_STATUS:
  346. case CS35L36_DAC_MSM_CFG:
  347. case CS35L36_AMP_SLOPE_CTRL:
  348. case CS35L36_AMP_PDM_VOLUME:
  349. case CS35L36_AMP_PDM_RATE_CTRL:
  350. case CS35L36_PDM_CH_SEL:
  351. case CS35L36_AMP_NG_CTRL:
  352. case CS35L36_PDM_HIGHFILT_CTRL:
  353. case CS35L36_INT1_STATUS:
  354. case CS35L36_INT2_STATUS:
  355. case CS35L36_INT3_STATUS:
  356. case CS35L36_INT4_STATUS:
  357. case CS35L36_INT1_RAW_STATUS:
  358. case CS35L36_INT2_RAW_STATUS:
  359. case CS35L36_INT3_RAW_STATUS:
  360. case CS35L36_INT4_RAW_STATUS:
  361. case CS35L36_INT1_MASK:
  362. case CS35L36_INT2_MASK:
  363. case CS35L36_INT3_MASK:
  364. case CS35L36_INT4_MASK:
  365. case CS35L36_INT1_EDGE_LVL_CTRL:
  366. case CS35L36_INT3_EDGE_LVL_CTRL:
  367. case CS35L36_PAC_INT_STATUS:
  368. case CS35L36_PAC_INT_RAW_STATUS:
  369. case CS35L36_PAC_INT_FLUSH_CTRL:
  370. case CS35L36_PAC_INT0_CTRL:
  371. case CS35L36_PAC_INT1_CTRL:
  372. case CS35L36_PAC_INT2_CTRL:
  373. case CS35L36_PAC_INT3_CTRL:
  374. case CS35L36_PAC_INT4_CTRL:
  375. case CS35L36_PAC_INT5_CTRL:
  376. case CS35L36_PAC_INT6_CTRL:
  377. case CS35L36_PAC_INT7_CTRL:
  378. return true;
  379. default:
  380. if (reg >= CS35L36_PAC_PMEM_WORD0 &&
  381. reg <= CS35L36_PAC_PMEM_WORD1023)
  382. return true;
  383. else
  384. return false;
  385. }
  386. }
  387. static bool cs35l36_precious_reg(struct device *dev, unsigned int reg)
  388. {
  389. switch (reg) {
  390. case CS35L36_TESTKEY_CTRL:
  391. case CS35L36_USERKEY_CTL:
  392. case CS35L36_TST_FS_MON0:
  393. return true;
  394. default:
  395. return false;
  396. }
  397. }
  398. static bool cs35l36_volatile_reg(struct device *dev, unsigned int reg)
  399. {
  400. switch (reg) {
  401. case CS35L36_SW_RESET:
  402. case CS35L36_SW_REV:
  403. case CS35L36_HW_REV:
  404. case CS35L36_TESTKEY_CTRL:
  405. case CS35L36_USERKEY_CTL:
  406. case CS35L36_DEVICE_ID:
  407. case CS35L36_FAB_ID:
  408. case CS35L36_REV_ID:
  409. case CS35L36_INT1_STATUS:
  410. case CS35L36_INT2_STATUS:
  411. case CS35L36_INT3_STATUS:
  412. case CS35L36_INT4_STATUS:
  413. case CS35L36_INT1_RAW_STATUS:
  414. case CS35L36_INT2_RAW_STATUS:
  415. case CS35L36_INT3_RAW_STATUS:
  416. case CS35L36_INT4_RAW_STATUS:
  417. case CS35L36_INT1_MASK:
  418. case CS35L36_INT2_MASK:
  419. case CS35L36_INT3_MASK:
  420. case CS35L36_INT4_MASK:
  421. case CS35L36_INT1_EDGE_LVL_CTRL:
  422. case CS35L36_INT3_EDGE_LVL_CTRL:
  423. case CS35L36_PAC_INT_STATUS:
  424. case CS35L36_PAC_INT_RAW_STATUS:
  425. case CS35L36_PAC_INT_FLUSH_CTRL:
  426. return true;
  427. default:
  428. if (reg >= CS35L36_PAC_PMEM_WORD0 &&
  429. reg <= CS35L36_PAC_PMEM_WORD1023)
  430. return true;
  431. else
  432. return false;
  433. }
  434. }
  435. static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 25, 0);
  436. static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
  437. static const char * const cs35l36_pcm_sftramp_text[] = {
  438. "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"};
  439. static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, CS35L36_AMP_DIG_VOL_CTRL, 0,
  440. cs35l36_pcm_sftramp_text);
  441. static int cs35l36_ldm_sel_get(struct snd_kcontrol *kcontrol,
  442. struct snd_ctl_elem_value *ucontrol)
  443. {
  444. struct snd_soc_component *component =
  445. snd_soc_kcontrol_component(kcontrol);
  446. struct cs35l36_private *cs35l36 =
  447. snd_soc_component_get_drvdata(component);
  448. ucontrol->value.integer.value[0] = cs35l36->ldm_mode_sel;
  449. return 0;
  450. }
  451. static int cs35l36_ldm_sel_put(struct snd_kcontrol *kcontrol,
  452. struct snd_ctl_elem_value *ucontrol)
  453. {
  454. struct snd_soc_component *component =
  455. snd_soc_kcontrol_component(kcontrol);
  456. struct cs35l36_private *cs35l36 =
  457. snd_soc_component_get_drvdata(component);
  458. int val = (ucontrol->value.integer.value[0]) ? CS35L36_NG_AMP_EN_MASK :
  459. 0;
  460. cs35l36->ldm_mode_sel = val;
  461. regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
  462. CS35L36_NG_AMP_EN_MASK, val);
  463. return 0;
  464. }
  465. static const struct snd_kcontrol_new cs35l36_aud_controls[] = {
  466. SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L36_AMP_DIG_VOL_CTRL,
  467. 3, 0x4D0, 0x390, dig_vol_tlv),
  468. SOC_SINGLE_TLV("Analog PCM Volume", CS35L36_AMP_GAIN_CTRL, 5, 0x13, 0,
  469. amp_gain_tlv),
  470. SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
  471. SOC_SINGLE("Amp Gain Zero-Cross Switch", CS35L36_AMP_GAIN_CTRL,
  472. CS35L36_AMP_ZC_SHIFT, 1, 0),
  473. SOC_SINGLE("PDM LDM Enter Ramp Switch", CS35L36_DAC_MSM_CFG,
  474. CS35L36_PDM_LDM_ENTER_SHIFT, 1, 0),
  475. SOC_SINGLE("PDM LDM Exit Ramp Switch", CS35L36_DAC_MSM_CFG,
  476. CS35L36_PDM_LDM_EXIT_SHIFT, 1, 0),
  477. SOC_SINGLE_BOOL_EXT("LDM Select Switch", 0, cs35l36_ldm_sel_get,
  478. cs35l36_ldm_sel_put),
  479. };
  480. static int cs35l36_main_amp_event(struct snd_soc_dapm_widget *w,
  481. struct snd_kcontrol *kcontrol, int event)
  482. {
  483. struct snd_soc_component *component =
  484. snd_soc_dapm_to_component(w->dapm);
  485. struct cs35l36_private *cs35l36 =
  486. snd_soc_component_get_drvdata(component);
  487. u32 reg;
  488. switch (event) {
  489. case SND_SOC_DAPM_POST_PMU:
  490. regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
  491. CS35L36_GLOBAL_EN_MASK,
  492. 1 << CS35L36_GLOBAL_EN_SHIFT);
  493. usleep_range(2000, 2100);
  494. regmap_read(cs35l36->regmap, CS35L36_INT4_RAW_STATUS, &reg);
  495. if (WARN_ON_ONCE(reg & CS35L36_PLL_UNLOCK_MASK))
  496. dev_crit(cs35l36->dev, "PLL Unlocked\n");
  497. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
  498. CS35L36_PCM_RX_SEL_MASK,
  499. CS35L36_PCM_RX_SEL_PCM);
  500. regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
  501. CS35L36_AMP_MUTE_MASK,
  502. 0 << CS35L36_AMP_MUTE_SHIFT);
  503. break;
  504. case SND_SOC_DAPM_PRE_PMD:
  505. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
  506. CS35L36_PCM_RX_SEL_MASK,
  507. CS35L36_PCM_RX_SEL_ZERO);
  508. regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
  509. CS35L36_AMP_MUTE_MASK,
  510. 1 << CS35L36_AMP_MUTE_SHIFT);
  511. break;
  512. case SND_SOC_DAPM_POST_PMD:
  513. regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
  514. CS35L36_GLOBAL_EN_MASK,
  515. 0 << CS35L36_GLOBAL_EN_SHIFT);
  516. usleep_range(2000, 2100);
  517. break;
  518. default:
  519. dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
  520. return -EINVAL;
  521. }
  522. return 0;
  523. }
  524. static int cs35l36_boost_event(struct snd_soc_dapm_widget *w,
  525. struct snd_kcontrol *kcontrol, int event)
  526. {
  527. struct snd_soc_component *component =
  528. snd_soc_dapm_to_component(w->dapm);
  529. struct cs35l36_private *cs35l36 =
  530. snd_soc_component_get_drvdata(component);
  531. switch (event) {
  532. case SND_SOC_DAPM_POST_PMU:
  533. if (!cs35l36->pdata.extern_boost)
  534. regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
  535. CS35L36_BST_EN_MASK,
  536. CS35L36_BST_EN <<
  537. CS35L36_BST_EN_SHIFT);
  538. break;
  539. case SND_SOC_DAPM_POST_PMD:
  540. if (!cs35l36->pdata.extern_boost)
  541. regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
  542. CS35L36_BST_EN_MASK,
  543. CS35L36_BST_DIS_VP <<
  544. CS35L36_BST_EN_SHIFT);
  545. break;
  546. default:
  547. dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
  548. return -EINVAL;
  549. }
  550. return 0;
  551. }
  552. static const char * const cs35l36_chan_text[] = {
  553. "RX1",
  554. "RX2",
  555. };
  556. static SOC_ENUM_SINGLE_DECL(chansel_enum, CS35L36_ASP_RX1_SLOT, 0,
  557. cs35l36_chan_text);
  558. static const struct snd_kcontrol_new cs35l36_chan_mux =
  559. SOC_DAPM_ENUM("Input Mux", chansel_enum);
  560. static const struct snd_kcontrol_new amp_enable_ctrl =
  561. SOC_DAPM_SINGLE_AUTODISABLE("Switch", CS35L36_AMP_OUT_MUTE,
  562. CS35L36_AMP_MUTE_SHIFT, 1, 1);
  563. static const struct snd_kcontrol_new boost_ctrl =
  564. SOC_DAPM_SINGLE_VIRT("Switch", 1);
  565. static const char * const asp_tx_src_text[] = {
  566. "Zero Fill", "ASPRX1", "VMON", "IMON", "ERRVOL", "VPMON", "VBSTMON"
  567. };
  568. static const unsigned int asp_tx_src_values[] = {
  569. 0x00, 0x08, 0x18, 0x19, 0x20, 0x28, 0x29
  570. };
  571. static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx1_src_enum, CS35L36_ASP_TX1_SEL, 0,
  572. CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
  573. asp_tx_src_values);
  574. static const struct snd_kcontrol_new asp_tx1_src =
  575. SOC_DAPM_ENUM("ASPTX1SRC", asp_tx1_src_enum);
  576. static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx2_src_enum, CS35L36_ASP_TX2_SEL, 0,
  577. CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
  578. asp_tx_src_values);
  579. static const struct snd_kcontrol_new asp_tx2_src =
  580. SOC_DAPM_ENUM("ASPTX2SRC", asp_tx2_src_enum);
  581. static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx3_src_enum, CS35L36_ASP_TX3_SEL, 0,
  582. CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
  583. asp_tx_src_values);
  584. static const struct snd_kcontrol_new asp_tx3_src =
  585. SOC_DAPM_ENUM("ASPTX3SRC", asp_tx3_src_enum);
  586. static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx4_src_enum, CS35L36_ASP_TX4_SEL, 0,
  587. CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
  588. asp_tx_src_values);
  589. static const struct snd_kcontrol_new asp_tx4_src =
  590. SOC_DAPM_ENUM("ASPTX4SRC", asp_tx4_src_enum);
  591. static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx5_src_enum, CS35L36_ASP_TX5_SEL, 0,
  592. CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
  593. asp_tx_src_values);
  594. static const struct snd_kcontrol_new asp_tx5_src =
  595. SOC_DAPM_ENUM("ASPTX5SRC", asp_tx5_src_enum);
  596. static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx6_src_enum, CS35L36_ASP_TX6_SEL, 0,
  597. CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
  598. asp_tx_src_values);
  599. static const struct snd_kcontrol_new asp_tx6_src =
  600. SOC_DAPM_ENUM("ASPTX6SRC", asp_tx6_src_enum);
  601. static const struct snd_soc_dapm_widget cs35l36_dapm_widgets[] = {
  602. SND_SOC_DAPM_MUX("Channel Mux", SND_SOC_NOPM, 0, 0, &cs35l36_chan_mux),
  603. SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS35L36_ASP_RX_TX_EN, 16, 0),
  604. SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L36_PWR_CTRL2, 0, 0, NULL, 0,
  605. cs35l36_main_amp_event, SND_SOC_DAPM_POST_PMD |
  606. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  607. SND_SOC_DAPM_OUTPUT("SPK"),
  608. SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 1, &amp_enable_ctrl),
  609. SND_SOC_DAPM_MIXER("CLASS H", CS35L36_PWR_CTRL3, 4, 0, NULL, 0),
  610. SND_SOC_DAPM_SWITCH_E("BOOST Enable", SND_SOC_NOPM, 0, 0, &boost_ctrl,
  611. cs35l36_boost_event, SND_SOC_DAPM_POST_PMD |
  612. SND_SOC_DAPM_POST_PMU),
  613. SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L36_ASP_RX_TX_EN, 0, 0),
  614. SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1, CS35L36_ASP_RX_TX_EN, 1, 0),
  615. SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2, CS35L36_ASP_RX_TX_EN, 2, 0),
  616. SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3, CS35L36_ASP_RX_TX_EN, 3, 0),
  617. SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4, CS35L36_ASP_RX_TX_EN, 4, 0),
  618. SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5, CS35L36_ASP_RX_TX_EN, 5, 0),
  619. SND_SOC_DAPM_MUX("ASPTX1SRC", SND_SOC_NOPM, 0, 0, &asp_tx1_src),
  620. SND_SOC_DAPM_MUX("ASPTX2SRC", SND_SOC_NOPM, 0, 0, &asp_tx2_src),
  621. SND_SOC_DAPM_MUX("ASPTX3SRC", SND_SOC_NOPM, 0, 0, &asp_tx3_src),
  622. SND_SOC_DAPM_MUX("ASPTX4SRC", SND_SOC_NOPM, 0, 0, &asp_tx4_src),
  623. SND_SOC_DAPM_MUX("ASPTX5SRC", SND_SOC_NOPM, 0, 0, &asp_tx5_src),
  624. SND_SOC_DAPM_MUX("ASPTX6SRC", SND_SOC_NOPM, 0, 0, &asp_tx6_src),
  625. SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L36_PWR_CTRL2, 12, 0),
  626. SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L36_PWR_CTRL2, 13, 0),
  627. SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L36_PWR_CTRL2, 8, 0),
  628. SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L36_PWR_CTRL2, 9, 0),
  629. SND_SOC_DAPM_INPUT("VP"),
  630. SND_SOC_DAPM_INPUT("VBST"),
  631. SND_SOC_DAPM_INPUT("VSENSE"),
  632. };
  633. static const struct snd_soc_dapm_route cs35l36_audio_map[] = {
  634. {"VPMON ADC", NULL, "VP"},
  635. {"VBSTMON ADC", NULL, "VBST"},
  636. {"IMON ADC", NULL, "VSENSE"},
  637. {"VMON ADC", NULL, "VSENSE"},
  638. {"ASPTX1SRC", "IMON", "IMON ADC"},
  639. {"ASPTX1SRC", "VMON", "VMON ADC"},
  640. {"ASPTX1SRC", "VBSTMON", "VBSTMON ADC"},
  641. {"ASPTX1SRC", "VPMON", "VPMON ADC"},
  642. {"ASPTX2SRC", "IMON", "IMON ADC"},
  643. {"ASPTX2SRC", "VMON", "VMON ADC"},
  644. {"ASPTX2SRC", "VBSTMON", "VBSTMON ADC"},
  645. {"ASPTX2SRC", "VPMON", "VPMON ADC"},
  646. {"ASPTX3SRC", "IMON", "IMON ADC"},
  647. {"ASPTX3SRC", "VMON", "VMON ADC"},
  648. {"ASPTX3SRC", "VBSTMON", "VBSTMON ADC"},
  649. {"ASPTX3SRC", "VPMON", "VPMON ADC"},
  650. {"ASPTX4SRC", "IMON", "IMON ADC"},
  651. {"ASPTX4SRC", "VMON", "VMON ADC"},
  652. {"ASPTX4SRC", "VBSTMON", "VBSTMON ADC"},
  653. {"ASPTX4SRC", "VPMON", "VPMON ADC"},
  654. {"ASPTX5SRC", "IMON", "IMON ADC"},
  655. {"ASPTX5SRC", "VMON", "VMON ADC"},
  656. {"ASPTX5SRC", "VBSTMON", "VBSTMON ADC"},
  657. {"ASPTX5SRC", "VPMON", "VPMON ADC"},
  658. {"ASPTX6SRC", "IMON", "IMON ADC"},
  659. {"ASPTX6SRC", "VMON", "VMON ADC"},
  660. {"ASPTX6SRC", "VBSTMON", "VBSTMON ADC"},
  661. {"ASPTX6SRC", "VPMON", "VPMON ADC"},
  662. {"ASPTX1", NULL, "ASPTX1SRC"},
  663. {"ASPTX2", NULL, "ASPTX2SRC"},
  664. {"ASPTX3", NULL, "ASPTX3SRC"},
  665. {"ASPTX4", NULL, "ASPTX4SRC"},
  666. {"ASPTX5", NULL, "ASPTX5SRC"},
  667. {"ASPTX6", NULL, "ASPTX6SRC"},
  668. {"AMP Capture", NULL, "ASPTX1"},
  669. {"AMP Capture", NULL, "ASPTX2"},
  670. {"AMP Capture", NULL, "ASPTX3"},
  671. {"AMP Capture", NULL, "ASPTX4"},
  672. {"AMP Capture", NULL, "ASPTX5"},
  673. {"AMP Capture", NULL, "ASPTX6"},
  674. {"AMP Enable", "Switch", "AMP Playback"},
  675. {"SDIN", NULL, "AMP Enable"},
  676. {"Channel Mux", "RX1", "SDIN"},
  677. {"Channel Mux", "RX2", "SDIN"},
  678. {"BOOST Enable", "Switch", "Channel Mux"},
  679. {"CLASS H", NULL, "BOOST Enable"},
  680. {"Main AMP", NULL, "Channel Mux"},
  681. {"Main AMP", NULL, "CLASS H"},
  682. {"SPK", NULL, "Main AMP"},
  683. };
  684. static int cs35l36_set_dai_fmt(struct snd_soc_dai *component_dai,
  685. unsigned int fmt)
  686. {
  687. struct cs35l36_private *cs35l36 =
  688. snd_soc_component_get_drvdata(component_dai->component);
  689. unsigned int asp_fmt, lrclk_fmt, sclk_fmt, slave_mode, clk_frc;
  690. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  691. case SND_SOC_DAIFMT_CBM_CFM:
  692. slave_mode = 1;
  693. break;
  694. case SND_SOC_DAIFMT_CBS_CFS:
  695. slave_mode = 0;
  696. break;
  697. default:
  698. return -EINVAL;
  699. }
  700. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
  701. CS35L36_SCLK_MSTR_MASK,
  702. slave_mode << CS35L36_SCLK_MSTR_SHIFT);
  703. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
  704. CS35L36_LRCLK_MSTR_MASK,
  705. slave_mode << CS35L36_LRCLK_MSTR_SHIFT);
  706. switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
  707. case SND_SOC_DAIFMT_CONT:
  708. clk_frc = 1;
  709. break;
  710. case SND_SOC_DAIFMT_GATED:
  711. clk_frc = 0;
  712. break;
  713. default:
  714. return -EINVAL;
  715. }
  716. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
  717. CS35L36_SCLK_FRC_MASK, clk_frc <<
  718. CS35L36_SCLK_FRC_SHIFT);
  719. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
  720. CS35L36_LRCLK_FRC_MASK, clk_frc <<
  721. CS35L36_LRCLK_FRC_SHIFT);
  722. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  723. case SND_SOC_DAIFMT_DSP_A:
  724. asp_fmt = 0;
  725. break;
  726. case SND_SOC_DAIFMT_I2S:
  727. asp_fmt = 2;
  728. break;
  729. default:
  730. return -EINVAL;
  731. }
  732. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  733. case SND_SOC_DAIFMT_NB_IF:
  734. lrclk_fmt = 1;
  735. sclk_fmt = 0;
  736. break;
  737. case SND_SOC_DAIFMT_IB_NF:
  738. lrclk_fmt = 0;
  739. sclk_fmt = 1;
  740. break;
  741. case SND_SOC_DAIFMT_IB_IF:
  742. lrclk_fmt = 1;
  743. sclk_fmt = 1;
  744. break;
  745. case SND_SOC_DAIFMT_NB_NF:
  746. lrclk_fmt = 0;
  747. sclk_fmt = 0;
  748. break;
  749. default:
  750. return -EINVAL;
  751. }
  752. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
  753. CS35L36_LRCLK_INV_MASK,
  754. lrclk_fmt << CS35L36_LRCLK_INV_SHIFT);
  755. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
  756. CS35L36_SCLK_INV_MASK,
  757. sclk_fmt << CS35L36_SCLK_INV_SHIFT);
  758. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FORMAT,
  759. CS35L36_ASP_FMT_MASK, asp_fmt);
  760. return 0;
  761. }
  762. struct cs35l36_global_fs_config {
  763. int rate;
  764. int fs_cfg;
  765. };
  766. static const struct cs35l36_global_fs_config cs35l36_fs_rates[] = {
  767. {12000, 0x01},
  768. {24000, 0x02},
  769. {48000, 0x03},
  770. {96000, 0x04},
  771. {192000, 0x05},
  772. {384000, 0x06},
  773. {11025, 0x09},
  774. {22050, 0x0A},
  775. {44100, 0x0B},
  776. {88200, 0x0C},
  777. {176400, 0x0D},
  778. {8000, 0x11},
  779. {16000, 0x12},
  780. {32000, 0x13},
  781. };
  782. static int cs35l36_pcm_hw_params(struct snd_pcm_substream *substream,
  783. struct snd_pcm_hw_params *params,
  784. struct snd_soc_dai *dai)
  785. {
  786. struct cs35l36_private *cs35l36 =
  787. snd_soc_component_get_drvdata(dai->component);
  788. unsigned int asp_width, global_fs = params_rate(params);
  789. int i;
  790. for (i = 0; i < ARRAY_SIZE(cs35l36_fs_rates); i++) {
  791. if (global_fs == cs35l36_fs_rates[i].rate)
  792. regmap_update_bits(cs35l36->regmap,
  793. CS35L36_GLOBAL_CLK_CTRL,
  794. CS35L36_GLOBAL_FS_MASK,
  795. cs35l36_fs_rates[i].fs_cfg <<
  796. CS35L36_GLOBAL_FS_SHIFT);
  797. }
  798. switch (params_width(params)) {
  799. case 16:
  800. asp_width = CS35L36_ASP_WIDTH_16;
  801. break;
  802. case 24:
  803. asp_width = CS35L36_ASP_WIDTH_24;
  804. break;
  805. case 32:
  806. asp_width = CS35L36_ASP_WIDTH_32;
  807. break;
  808. default:
  809. return -EINVAL;
  810. }
  811. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  812. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
  813. CS35L36_ASP_RX_WIDTH_MASK,
  814. asp_width << CS35L36_ASP_RX_WIDTH_SHIFT);
  815. } else {
  816. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
  817. CS35L36_ASP_TX_WIDTH_MASK,
  818. asp_width << CS35L36_ASP_TX_WIDTH_SHIFT);
  819. }
  820. return 0;
  821. }
  822. static int cs35l36_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  823. unsigned int freq, int dir)
  824. {
  825. struct snd_soc_component *component = dai->component;
  826. struct cs35l36_private *cs35l36 =
  827. snd_soc_component_get_drvdata(component);
  828. int fs1, fs2;
  829. if (freq > CS35L36_FS_NOM_6MHZ) {
  830. fs1 = CS35L36_FS1_DEFAULT_VAL;
  831. fs2 = CS35L36_FS2_DEFAULT_VAL;
  832. } else {
  833. fs1 = 3 * ((CS35L36_FS_NOM_6MHZ * 4 + freq - 1) / freq) + 4;
  834. fs2 = 5 * ((CS35L36_FS_NOM_6MHZ * 4 + freq - 1) / freq) + 4;
  835. }
  836. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  837. CS35L36_TEST_UNLOCK1);
  838. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  839. CS35L36_TEST_UNLOCK2);
  840. regmap_update_bits(cs35l36->regmap, CS35L36_TST_FS_MON0,
  841. CS35L36_FS1_WINDOW_MASK | CS35L36_FS2_WINDOW_MASK,
  842. fs1 | (fs2 << CS35L36_FS2_WINDOW_SHIFT));
  843. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  844. CS35L36_TEST_LOCK1);
  845. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  846. CS35L36_TEST_LOCK2);
  847. return 0;
  848. }
  849. static const struct cs35l36_pll_config *cs35l36_get_clk_config(
  850. struct cs35l36_private *cs35l36, int freq)
  851. {
  852. int i;
  853. for (i = 0; i < ARRAY_SIZE(cs35l36_pll_sysclk); i++) {
  854. if (cs35l36_pll_sysclk[i].freq == freq)
  855. return &cs35l36_pll_sysclk[i];
  856. }
  857. return NULL;
  858. }
  859. static const unsigned int cs35l36_src_rates[] = {
  860. 8000, 12000, 11025, 16000, 22050, 24000, 32000,
  861. 44100, 48000, 88200, 96000, 176400, 192000, 384000
  862. };
  863. static const struct snd_pcm_hw_constraint_list cs35l36_constraints = {
  864. .count = ARRAY_SIZE(cs35l36_src_rates),
  865. .list = cs35l36_src_rates,
  866. };
  867. static int cs35l36_pcm_startup(struct snd_pcm_substream *substream,
  868. struct snd_soc_dai *dai)
  869. {
  870. snd_pcm_hw_constraint_list(substream->runtime, 0,
  871. SNDRV_PCM_HW_PARAM_RATE, &cs35l36_constraints);
  872. return 0;
  873. }
  874. static const struct snd_soc_dai_ops cs35l36_ops = {
  875. .startup = cs35l36_pcm_startup,
  876. .set_fmt = cs35l36_set_dai_fmt,
  877. .hw_params = cs35l36_pcm_hw_params,
  878. .set_sysclk = cs35l36_dai_set_sysclk,
  879. };
  880. static struct snd_soc_dai_driver cs35l36_dai[] = {
  881. {
  882. .name = "cs35l36-pcm",
  883. .id = 0,
  884. .playback = {
  885. .stream_name = "AMP Playback",
  886. .channels_min = 1,
  887. .channels_max = 8,
  888. .rates = SNDRV_PCM_RATE_KNOT,
  889. .formats = CS35L36_RX_FORMATS,
  890. },
  891. .capture = {
  892. .stream_name = "AMP Capture",
  893. .channels_min = 1,
  894. .channels_max = 8,
  895. .rates = SNDRV_PCM_RATE_KNOT,
  896. .formats = CS35L36_TX_FORMATS,
  897. },
  898. .ops = &cs35l36_ops,
  899. .symmetric_rates = 1,
  900. },
  901. };
  902. static int cs35l36_component_set_sysclk(struct snd_soc_component *component,
  903. int clk_id, int source, unsigned int freq,
  904. int dir)
  905. {
  906. struct cs35l36_private *cs35l36 =
  907. snd_soc_component_get_drvdata(component);
  908. const struct cs35l36_pll_config *clk_cfg;
  909. int prev_clksrc;
  910. bool pdm_switch;
  911. prev_clksrc = cs35l36->clksrc;
  912. switch (clk_id) {
  913. case 0:
  914. cs35l36->clksrc = CS35L36_PLLSRC_SCLK;
  915. break;
  916. case 1:
  917. cs35l36->clksrc = CS35L36_PLLSRC_LRCLK;
  918. break;
  919. case 2:
  920. cs35l36->clksrc = CS35L36_PLLSRC_PDMCLK;
  921. break;
  922. case 3:
  923. cs35l36->clksrc = CS35L36_PLLSRC_SELF;
  924. break;
  925. case 4:
  926. cs35l36->clksrc = CS35L36_PLLSRC_MCLK;
  927. break;
  928. default:
  929. return -EINVAL;
  930. }
  931. clk_cfg = cs35l36_get_clk_config(cs35l36, freq);
  932. if (clk_cfg == NULL) {
  933. dev_err(component->dev, "Invalid CLK Config Freq: %d\n", freq);
  934. return -EINVAL;
  935. }
  936. regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
  937. CS35L36_PLL_OPENLOOP_MASK,
  938. 1 << CS35L36_PLL_OPENLOOP_SHIFT);
  939. regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
  940. CS35L36_REFCLK_FREQ_MASK,
  941. clk_cfg->clk_cfg << CS35L36_REFCLK_FREQ_SHIFT);
  942. regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
  943. CS35L36_PLL_REFCLK_EN_MASK,
  944. 0 << CS35L36_PLL_REFCLK_EN_SHIFT);
  945. regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
  946. CS35L36_PLL_CLK_SEL_MASK,
  947. cs35l36->clksrc);
  948. regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
  949. CS35L36_PLL_OPENLOOP_MASK,
  950. 0 << CS35L36_PLL_OPENLOOP_SHIFT);
  951. regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
  952. CS35L36_PLL_REFCLK_EN_MASK,
  953. 1 << CS35L36_PLL_REFCLK_EN_SHIFT);
  954. if (cs35l36->rev_id == CS35L36_REV_A0) {
  955. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  956. CS35L36_TEST_UNLOCK1);
  957. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  958. CS35L36_TEST_UNLOCK2);
  959. regmap_write(cs35l36->regmap, CS35L36_DCO_CTRL, 0x00036DA8);
  960. regmap_write(cs35l36->regmap, CS35L36_MISC_CTRL, 0x0100EE0E);
  961. regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
  962. CS35L36_PLL_IGAIN_MASK,
  963. CS35L36_PLL_IGAIN <<
  964. CS35L36_PLL_IGAIN_SHIFT);
  965. regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
  966. CS35L36_PLL_FFL_IGAIN_MASK,
  967. clk_cfg->fll_igain);
  968. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  969. CS35L36_TEST_LOCK1);
  970. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  971. CS35L36_TEST_LOCK2);
  972. }
  973. if (cs35l36->clksrc == CS35L36_PLLSRC_PDMCLK) {
  974. pdm_switch = cs35l36->ldm_mode_sel &&
  975. (prev_clksrc != CS35L36_PLLSRC_PDMCLK);
  976. if (pdm_switch)
  977. regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
  978. CS35L36_NG_DELAY_MASK,
  979. 0 << CS35L36_NG_DELAY_SHIFT);
  980. regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
  981. CS35L36_PDM_MODE_MASK,
  982. 1 << CS35L36_PDM_MODE_SHIFT);
  983. if (pdm_switch)
  984. regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
  985. CS35L36_NG_DELAY_MASK,
  986. 3 << CS35L36_NG_DELAY_SHIFT);
  987. } else {
  988. pdm_switch = cs35l36->ldm_mode_sel &&
  989. (prev_clksrc == CS35L36_PLLSRC_PDMCLK);
  990. if (pdm_switch)
  991. regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
  992. CS35L36_NG_DELAY_MASK,
  993. 0 << CS35L36_NG_DELAY_SHIFT);
  994. regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
  995. CS35L36_PDM_MODE_MASK,
  996. 0 << CS35L36_PDM_MODE_SHIFT);
  997. if (pdm_switch)
  998. regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
  999. CS35L36_NG_DELAY_MASK,
  1000. 3 << CS35L36_NG_DELAY_SHIFT);
  1001. }
  1002. return 0;
  1003. }
  1004. static int cs35l36_boost_inductor(struct cs35l36_private *cs35l36, int inductor)
  1005. {
  1006. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
  1007. CS35L36_BSTCVRT_K1_MASK, 0x3C);
  1008. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
  1009. CS35L36_BSTCVRT_K2_MASK,
  1010. 0x3C << CS35L36_BSTCVRT_K2_SHIFT);
  1011. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SW_FREQ,
  1012. CS35L36_BSTCVRT_CCMFREQ_MASK, 0x00);
  1013. switch (inductor) {
  1014. case 1000: /* 1 uH */
  1015. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
  1016. CS35L36_BSTCVRT_SLOPE_MASK,
  1017. 0x75 << CS35L36_BSTCVRT_SLOPE_SHIFT);
  1018. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
  1019. CS35L36_BSTCVRT_LBSTVAL_MASK, 0x00);
  1020. break;
  1021. case 1200: /* 1.2 uH */
  1022. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
  1023. CS35L36_BSTCVRT_SLOPE_MASK,
  1024. 0x6B << CS35L36_BSTCVRT_SLOPE_SHIFT);
  1025. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
  1026. CS35L36_BSTCVRT_LBSTVAL_MASK, 0x01);
  1027. break;
  1028. default:
  1029. dev_err(cs35l36->dev, "%s Invalid Inductor Value %d uH\n",
  1030. __func__, inductor);
  1031. return -EINVAL;
  1032. }
  1033. return 0;
  1034. }
  1035. static int cs35l36_component_probe(struct snd_soc_component *component)
  1036. {
  1037. struct cs35l36_private *cs35l36 =
  1038. snd_soc_component_get_drvdata(component);
  1039. int ret = 0;
  1040. if ((cs35l36->rev_id == CS35L36_REV_A0) && cs35l36->pdata.dcm_mode) {
  1041. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_DCM_CTRL,
  1042. CS35L36_DCM_AUTO_MASK,
  1043. CS35L36_DCM_AUTO_MASK);
  1044. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1045. CS35L36_TEST_UNLOCK1);
  1046. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1047. CS35L36_TEST_UNLOCK2);
  1048. regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
  1049. CS35L36_BST_MAN_IPKCOMP_MASK,
  1050. 0 << CS35L36_BST_MAN_IPKCOMP_SHIFT);
  1051. regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
  1052. CS35L36_BST_MAN_IPKCOMP_EN_MASK,
  1053. CS35L36_BST_MAN_IPKCOMP_EN_MASK);
  1054. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1055. CS35L36_TEST_LOCK1);
  1056. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1057. CS35L36_TEST_LOCK2);
  1058. }
  1059. if (cs35l36->pdata.amp_pcm_inv)
  1060. regmap_update_bits(cs35l36->regmap, CS35L36_AMP_DIG_VOL_CTRL,
  1061. CS35L36_AMP_PCM_INV_MASK,
  1062. CS35L36_AMP_PCM_INV_MASK);
  1063. if (cs35l36->pdata.multi_amp_mode)
  1064. regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
  1065. CS35L36_ASP_TX_HIZ_MASK,
  1066. CS35L36_ASP_TX_HIZ_MASK);
  1067. if (cs35l36->pdata.imon_pol_inv)
  1068. regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
  1069. CS35L36_IMON_POL_MASK, 0);
  1070. if (cs35l36->pdata.vmon_pol_inv)
  1071. regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
  1072. CS35L36_VMON_POL_MASK, 0);
  1073. if (cs35l36->pdata.bst_vctl)
  1074. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
  1075. CS35L35_BSTCVRT_CTL_MASK,
  1076. cs35l36->pdata.bst_vctl);
  1077. if (cs35l36->pdata.bst_vctl_sel)
  1078. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
  1079. CS35L35_BSTCVRT_CTL_SEL_MASK,
  1080. cs35l36->pdata.bst_vctl_sel);
  1081. if (cs35l36->pdata.bst_ipk)
  1082. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_PEAK_CUR,
  1083. CS35L36_BST_IPK_MASK,
  1084. cs35l36->pdata.bst_ipk);
  1085. if (cs35l36->pdata.boost_ind) {
  1086. ret = cs35l36_boost_inductor(cs35l36, cs35l36->pdata.boost_ind);
  1087. if (ret < 0) {
  1088. dev_err(cs35l36->dev,
  1089. "Boost inductor config failed(%d)\n", ret);
  1090. return ret;
  1091. }
  1092. }
  1093. if (cs35l36->pdata.temp_warn_thld)
  1094. regmap_update_bits(cs35l36->regmap, CS35L36_DTEMP_WARN_THLD,
  1095. CS35L36_TEMP_THLD_MASK,
  1096. cs35l36->pdata.temp_warn_thld);
  1097. if (cs35l36->pdata.irq_drv_sel)
  1098. regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
  1099. CS35L36_INT_DRV_SEL_MASK,
  1100. cs35l36->pdata.irq_drv_sel <<
  1101. CS35L36_INT_DRV_SEL_SHIFT);
  1102. if (cs35l36->pdata.irq_gpio_sel)
  1103. regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
  1104. CS35L36_INT_GPIO_SEL_MASK,
  1105. cs35l36->pdata.irq_gpio_sel <<
  1106. CS35L36_INT_GPIO_SEL_SHIFT);
  1107. /*
  1108. * Rev B0 has 2 versions
  1109. * L36 is 10V
  1110. * L37 is 12V
  1111. * If L36 we need to clamp some values for safety
  1112. * after probe has setup dt values. We want to make
  1113. * sure we dont miss any values set in probe
  1114. */
  1115. if (cs35l36->chip_version == CS35L36_10V_L36) {
  1116. regmap_update_bits(cs35l36->regmap,
  1117. CS35L36_BSTCVRT_OVERVOLT_CTRL,
  1118. CS35L36_BST_OVP_THLD_MASK,
  1119. CS35L36_BST_OVP_THLD_11V);
  1120. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1121. CS35L36_TEST_UNLOCK1);
  1122. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1123. CS35L36_TEST_UNLOCK2);
  1124. regmap_update_bits(cs35l36->regmap, CS35L36_BST_ANA2_TEST,
  1125. CS35L36_BST_OVP_TRIM_MASK,
  1126. CS35L36_BST_OVP_TRIM_11V <<
  1127. CS35L36_BST_OVP_TRIM_SHIFT);
  1128. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
  1129. CS35L36_BST_CTRL_LIM_MASK,
  1130. 1 << CS35L36_BST_CTRL_LIM_SHIFT);
  1131. regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
  1132. CS35L35_BSTCVRT_CTL_MASK,
  1133. CS35L36_BST_CTRL_10V_CLAMP);
  1134. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1135. CS35L36_TEST_LOCK1);
  1136. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1137. CS35L36_TEST_LOCK2);
  1138. }
  1139. /*
  1140. * RevA and B require the disabling of
  1141. * SYNC_GLOBAL_OVR when GLOBAL_EN = 0.
  1142. * Just turn it off from default
  1143. */
  1144. regmap_update_bits(cs35l36->regmap, CS35L36_CTRL_OVRRIDE,
  1145. CS35L36_SYNC_GLOBAL_OVR_MASK,
  1146. 0 << CS35L36_SYNC_GLOBAL_OVR_SHIFT);
  1147. return 0;
  1148. }
  1149. static const struct snd_soc_component_driver soc_component_dev_cs35l36 = {
  1150. .probe = &cs35l36_component_probe,
  1151. .set_sysclk = cs35l36_component_set_sysclk,
  1152. .dapm_widgets = cs35l36_dapm_widgets,
  1153. .num_dapm_widgets = ARRAY_SIZE(cs35l36_dapm_widgets),
  1154. .dapm_routes = cs35l36_audio_map,
  1155. .num_dapm_routes = ARRAY_SIZE(cs35l36_audio_map),
  1156. .controls = cs35l36_aud_controls,
  1157. .num_controls = ARRAY_SIZE(cs35l36_aud_controls),
  1158. .idle_bias_on = 1,
  1159. .use_pmdown_time = 1,
  1160. .endianness = 1,
  1161. .non_legacy_dai_naming = 1,
  1162. };
  1163. static struct regmap_config cs35l36_regmap = {
  1164. .reg_bits = 32,
  1165. .val_bits = 32,
  1166. .reg_stride = 4,
  1167. .max_register = CS35L36_PAC_PMEM_WORD1023,
  1168. .reg_defaults = cs35l36_reg,
  1169. .num_reg_defaults = ARRAY_SIZE(cs35l36_reg),
  1170. .precious_reg = cs35l36_precious_reg,
  1171. .volatile_reg = cs35l36_volatile_reg,
  1172. .readable_reg = cs35l36_readable_reg,
  1173. .cache_type = REGCACHE_RBTREE,
  1174. };
  1175. static irqreturn_t cs35l36_irq(int irq, void *data)
  1176. {
  1177. struct cs35l36_private *cs35l36 = data;
  1178. unsigned int status[4];
  1179. unsigned int masks[4];
  1180. int ret = IRQ_NONE;
  1181. /* ack the irq by reading all status registers */
  1182. regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_STATUS, status,
  1183. ARRAY_SIZE(status));
  1184. regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_MASK, masks,
  1185. ARRAY_SIZE(masks));
  1186. /* Check to see if unmasked bits are active */
  1187. if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
  1188. !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) {
  1189. return IRQ_NONE;
  1190. }
  1191. /*
  1192. * The following interrupts require a
  1193. * protection release cycle to get the
  1194. * speaker out of Safe-Mode.
  1195. */
  1196. if (status[2] & CS35L36_AMP_SHORT_ERR) {
  1197. dev_crit(cs35l36->dev, "Amp short error\n");
  1198. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1199. CS35L36_AMP_SHORT_ERR_RLS, 0);
  1200. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1201. CS35L36_AMP_SHORT_ERR_RLS,
  1202. CS35L36_AMP_SHORT_ERR_RLS);
  1203. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1204. CS35L36_AMP_SHORT_ERR_RLS, 0);
  1205. regmap_update_bits(cs35l36->regmap, CS35L36_INT3_STATUS,
  1206. CS35L36_AMP_SHORT_ERR,
  1207. CS35L36_AMP_SHORT_ERR);
  1208. ret = IRQ_HANDLED;
  1209. }
  1210. if (status[0] & CS35L36_TEMP_WARN) {
  1211. dev_crit(cs35l36->dev, "Over temperature warning\n");
  1212. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1213. CS35L36_TEMP_WARN_ERR_RLS, 0);
  1214. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1215. CS35L36_TEMP_WARN_ERR_RLS,
  1216. CS35L36_TEMP_WARN_ERR_RLS);
  1217. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1218. CS35L36_TEMP_WARN_ERR_RLS, 0);
  1219. regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
  1220. CS35L36_TEMP_WARN, CS35L36_TEMP_WARN);
  1221. ret = IRQ_HANDLED;
  1222. }
  1223. if (status[0] & CS35L36_TEMP_ERR) {
  1224. dev_crit(cs35l36->dev, "Over temperature error\n");
  1225. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1226. CS35L36_TEMP_ERR_RLS, 0);
  1227. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1228. CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
  1229. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1230. CS35L36_TEMP_ERR_RLS, 0);
  1231. regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
  1232. CS35L36_TEMP_ERR, CS35L36_TEMP_ERR);
  1233. ret = IRQ_HANDLED;
  1234. }
  1235. if (status[0] & CS35L36_BST_OVP_ERR) {
  1236. dev_crit(cs35l36->dev, "VBST Over Voltage error\n");
  1237. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1238. CS35L36_TEMP_ERR_RLS, 0);
  1239. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1240. CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
  1241. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1242. CS35L36_TEMP_ERR_RLS, 0);
  1243. regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
  1244. CS35L36_BST_OVP_ERR, CS35L36_BST_OVP_ERR);
  1245. ret = IRQ_HANDLED;
  1246. }
  1247. if (status[0] & CS35L36_BST_DCM_UVP_ERR) {
  1248. dev_crit(cs35l36->dev, "DCM VBST Under Voltage Error\n");
  1249. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1250. CS35L36_BST_UVP_ERR_RLS, 0);
  1251. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1252. CS35L36_BST_UVP_ERR_RLS,
  1253. CS35L36_BST_UVP_ERR_RLS);
  1254. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1255. CS35L36_BST_UVP_ERR_RLS, 0);
  1256. regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
  1257. CS35L36_BST_DCM_UVP_ERR,
  1258. CS35L36_BST_DCM_UVP_ERR);
  1259. ret = IRQ_HANDLED;
  1260. }
  1261. if (status[0] & CS35L36_BST_SHORT_ERR) {
  1262. dev_crit(cs35l36->dev, "LBST SHORT error!\n");
  1263. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1264. CS35L36_BST_SHORT_ERR_RLS, 0);
  1265. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1266. CS35L36_BST_SHORT_ERR_RLS,
  1267. CS35L36_BST_SHORT_ERR_RLS);
  1268. regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
  1269. CS35L36_BST_SHORT_ERR_RLS, 0);
  1270. regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
  1271. CS35L36_BST_SHORT_ERR,
  1272. CS35L36_BST_SHORT_ERR);
  1273. ret = IRQ_HANDLED;
  1274. }
  1275. return ret;
  1276. }
  1277. static int cs35l36_handle_of_data(struct i2c_client *i2c_client,
  1278. struct cs35l36_platform_data *pdata)
  1279. {
  1280. struct device_node *np = i2c_client->dev.of_node;
  1281. struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
  1282. struct device_node *vpbr_node;
  1283. unsigned int val;
  1284. int ret;
  1285. if (!np)
  1286. return 0;
  1287. ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val);
  1288. if (!ret) {
  1289. if (val < 2550 || val > 12000) {
  1290. dev_err(&i2c_client->dev,
  1291. "Invalid Boost Voltage %d mV\n", val);
  1292. return -EINVAL;
  1293. }
  1294. pdata->bst_vctl = (((val - 2550) / 100) + 1) << 1;
  1295. } else {
  1296. dev_err(&i2c_client->dev,
  1297. "Unable to find required parameter 'cirrus,boost-ctl-millivolt'");
  1298. return -EINVAL;
  1299. }
  1300. ret = of_property_read_u32(np, "cirrus,boost-ctl-select", &val);
  1301. if (!ret)
  1302. pdata->bst_vctl_sel = val | CS35L36_VALID_PDATA;
  1303. ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val);
  1304. if (!ret) {
  1305. if (val < 1600 || val > 4500) {
  1306. dev_err(&i2c_client->dev,
  1307. "Invalid Boost Peak Current %u mA\n", val);
  1308. return -EINVAL;
  1309. }
  1310. pdata->bst_ipk = (val - 1600) / 50;
  1311. } else {
  1312. dev_err(&i2c_client->dev,
  1313. "Unable to find required parameter 'cirrus,boost-peak-milliamp'");
  1314. return -EINVAL;
  1315. }
  1316. pdata->multi_amp_mode = of_property_read_bool(np,
  1317. "cirrus,multi-amp-mode");
  1318. pdata->dcm_mode = of_property_read_bool(np,
  1319. "cirrus,dcm-mode-enable");
  1320. pdata->amp_pcm_inv = of_property_read_bool(np,
  1321. "cirrus,amp-pcm-inv");
  1322. pdata->imon_pol_inv = of_property_read_bool(np,
  1323. "cirrus,imon-pol-inv");
  1324. pdata->vmon_pol_inv = of_property_read_bool(np,
  1325. "cirrus,vmon-pol-inv");
  1326. if (of_property_read_u32(np, "cirrus,temp-warn-threshold", &val) >= 0)
  1327. pdata->temp_warn_thld = val | CS35L36_VALID_PDATA;
  1328. if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) {
  1329. pdata->boost_ind = val;
  1330. } else {
  1331. dev_err(&i2c_client->dev, "Inductor not specified.\n");
  1332. return -EINVAL;
  1333. }
  1334. if (of_property_read_u32(np, "cirrus,irq-drive-select", &val) >= 0)
  1335. pdata->irq_drv_sel = val | CS35L36_VALID_PDATA;
  1336. if (of_property_read_u32(np, "cirrus,irq-gpio-select", &val) >= 0)
  1337. pdata->irq_gpio_sel = val | CS35L36_VALID_PDATA;
  1338. /* VPBR Config */
  1339. vpbr_node = of_get_child_by_name(np, "cirrus,vpbr-config");
  1340. vpbr_config->is_present = vpbr_node ? true : false;
  1341. if (vpbr_config->is_present) {
  1342. if (of_property_read_u32(vpbr_node, "cirrus,vpbr-en",
  1343. &val) >= 0)
  1344. vpbr_config->vpbr_en = val;
  1345. if (of_property_read_u32(vpbr_node, "cirrus,vpbr-thld",
  1346. &val) >= 0)
  1347. vpbr_config->vpbr_thld = val;
  1348. if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-rate",
  1349. &val) >= 0)
  1350. vpbr_config->vpbr_atk_rate = val;
  1351. if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-vol",
  1352. &val) >= 0)
  1353. vpbr_config->vpbr_atk_vol = val;
  1354. if (of_property_read_u32(vpbr_node, "cirrus,vpbr-max-attn",
  1355. &val) >= 0)
  1356. vpbr_config->vpbr_max_attn = val;
  1357. if (of_property_read_u32(vpbr_node, "cirrus,vpbr-wait",
  1358. &val) >= 0)
  1359. vpbr_config->vpbr_wait = val;
  1360. if (of_property_read_u32(vpbr_node, "cirrus,vpbr-rel-rate",
  1361. &val) >= 0)
  1362. vpbr_config->vpbr_rel_rate = val;
  1363. if (of_property_read_u32(vpbr_node, "cirrus,vpbr-mute-en",
  1364. &val) >= 0)
  1365. vpbr_config->vpbr_mute_en = val;
  1366. }
  1367. of_node_put(vpbr_node);
  1368. return 0;
  1369. }
  1370. static int cs35l36_pac(struct cs35l36_private *cs35l36)
  1371. {
  1372. int ret, count;
  1373. unsigned int val;
  1374. if (cs35l36->rev_id != CS35L36_REV_B0)
  1375. return 0;
  1376. /*
  1377. * Magic code for internal PAC
  1378. */
  1379. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1380. CS35L36_TEST_UNLOCK1);
  1381. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1382. CS35L36_TEST_UNLOCK2);
  1383. usleep_range(9500, 10500);
  1384. regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
  1385. CS35L36_PAC_RESET);
  1386. regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
  1387. CS35L36_PAC_MEM_ACCESS);
  1388. regmap_write(cs35l36->regmap, CS35L36_PAC_PMEM_WORD0,
  1389. CS35L36_B0_PAC_PATCH);
  1390. regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
  1391. CS35L36_PAC_MEM_ACCESS_CLR);
  1392. regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
  1393. CS35L36_PAC_ENABLE_MASK);
  1394. usleep_range(9500, 10500);
  1395. ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS, &val);
  1396. if (ret < 0) {
  1397. dev_err(cs35l36->dev, "Failed to read int4_status %d\n", ret);
  1398. return ret;
  1399. }
  1400. count = 0;
  1401. while (!(val & CS35L36_MCU_CONFIG_CLR)) {
  1402. usleep_range(100, 200);
  1403. count++;
  1404. ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS,
  1405. &val);
  1406. if (ret < 0) {
  1407. dev_err(cs35l36->dev, "Failed to read int4_status %d\n",
  1408. ret);
  1409. return ret;
  1410. }
  1411. if (count >= 100)
  1412. return -EINVAL;
  1413. }
  1414. regmap_write(cs35l36->regmap, CS35L36_INT4_STATUS,
  1415. CS35L36_MCU_CONFIG_CLR);
  1416. regmap_update_bits(cs35l36->regmap, CS35L36_PAC_CTL1,
  1417. CS35L36_PAC_ENABLE_MASK, 0);
  1418. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1419. CS35L36_TEST_LOCK1);
  1420. regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
  1421. CS35L36_TEST_LOCK2);
  1422. return 0;
  1423. }
  1424. static void cs35l36_apply_vpbr_config(struct cs35l36_private *cs35l36)
  1425. {
  1426. struct cs35l36_platform_data *pdata = &cs35l36->pdata;
  1427. struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
  1428. regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL3,
  1429. CS35L36_VPBR_EN_MASK,
  1430. vpbr_config->vpbr_en <<
  1431. CS35L36_VPBR_EN_SHIFT);
  1432. regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
  1433. CS35L36_VPBR_THLD_MASK,
  1434. vpbr_config->vpbr_thld <<
  1435. CS35L36_VPBR_THLD_SHIFT);
  1436. regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
  1437. CS35L36_VPBR_MAX_ATTN_MASK,
  1438. vpbr_config->vpbr_max_attn <<
  1439. CS35L36_VPBR_MAX_ATTN_SHIFT);
  1440. regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
  1441. CS35L36_VPBR_ATK_VOL_MASK,
  1442. vpbr_config->vpbr_atk_vol <<
  1443. CS35L36_VPBR_ATK_VOL_SHIFT);
  1444. regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
  1445. CS35L36_VPBR_ATK_RATE_MASK,
  1446. vpbr_config->vpbr_atk_rate <<
  1447. CS35L36_VPBR_ATK_RATE_SHIFT);
  1448. regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
  1449. CS35L36_VPBR_WAIT_MASK,
  1450. vpbr_config->vpbr_wait <<
  1451. CS35L36_VPBR_WAIT_SHIFT);
  1452. regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
  1453. CS35L36_VPBR_REL_RATE_MASK,
  1454. vpbr_config->vpbr_rel_rate <<
  1455. CS35L36_VPBR_REL_RATE_SHIFT);
  1456. regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
  1457. CS35L36_VPBR_MUTE_EN_MASK,
  1458. vpbr_config->vpbr_mute_en <<
  1459. CS35L36_VPBR_MUTE_EN_SHIFT);
  1460. }
  1461. static const struct reg_sequence cs35l36_reva0_errata_patch[] = {
  1462. { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK1 },
  1463. { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK2 },
  1464. /* Errata Writes */
  1465. { CS35L36_OTP_CTRL1, 0x00002060 },
  1466. { CS35L36_OTP_CTRL2, 0x00000001 },
  1467. { CS35L36_OTP_CTRL1, 0x00002460 },
  1468. { CS35L36_OTP_CTRL2, 0x00000001 },
  1469. { 0x00002088, 0x012A1838 },
  1470. { 0x00003014, 0x0100EE0E },
  1471. { 0x00003008, 0x0008184A },
  1472. { 0x00007418, 0x509001C8 },
  1473. { 0x00007064, 0x0929A800 },
  1474. { 0x00002D10, 0x0002C01C },
  1475. { 0x0000410C, 0x00000A11 },
  1476. { 0x00006E08, 0x8B19140C },
  1477. { 0x00006454, 0x0300000A },
  1478. { CS35L36_AMP_NG_CTRL, 0x000020EF },
  1479. { 0x00007E34, 0x0000000E },
  1480. { 0x0000410C, 0x00000A11 },
  1481. { 0x00007410, 0x20514B00 },
  1482. /* PAC Config */
  1483. { CS35L36_CTRL_OVRRIDE, 0x00000000 },
  1484. { CS35L36_PAC_INT0_CTRL, 0x00860001 },
  1485. { CS35L36_PAC_INT1_CTRL, 0x00860001 },
  1486. { CS35L36_PAC_INT2_CTRL, 0x00860001 },
  1487. { CS35L36_PAC_INT3_CTRL, 0x00860001 },
  1488. { CS35L36_PAC_INT4_CTRL, 0x00860001 },
  1489. { CS35L36_PAC_INT5_CTRL, 0x00860001 },
  1490. { CS35L36_PAC_INT6_CTRL, 0x00860001 },
  1491. { CS35L36_PAC_INT7_CTRL, 0x00860001 },
  1492. { CS35L36_PAC_INT_FLUSH_CTRL, 0x000000FF },
  1493. { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK1 },
  1494. { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK2 },
  1495. };
  1496. static const struct reg_sequence cs35l36_revb0_errata_patch[] = {
  1497. { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK1 },
  1498. { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK2 },
  1499. { 0x00007064, 0x0929A800 },
  1500. { 0x00007850, 0x00002FA9 },
  1501. { 0x00007854, 0x0003F1D5 },
  1502. { 0x00007858, 0x0003F5E3 },
  1503. { 0x0000785C, 0x00001137 },
  1504. { 0x00007860, 0x0001A7A5 },
  1505. { 0x00007864, 0x0002F16A },
  1506. { 0x00007868, 0x00003E21 },
  1507. { 0x00007848, 0x00000001 },
  1508. { 0x00003854, 0x05180240 },
  1509. { 0x00007418, 0x509001C8 },
  1510. { 0x0000394C, 0x028764BD },
  1511. { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK1 },
  1512. { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK2 },
  1513. };
  1514. static int cs35l36_i2c_probe(struct i2c_client *i2c_client,
  1515. const struct i2c_device_id *id)
  1516. {
  1517. struct cs35l36_private *cs35l36;
  1518. struct device *dev = &i2c_client->dev;
  1519. struct cs35l36_platform_data *pdata = dev_get_platdata(dev);
  1520. struct irq_data *irq_d;
  1521. int ret, irq_pol, chip_irq_pol, i;
  1522. u32 reg_id, reg_revid, l37_id_reg;
  1523. cs35l36 = devm_kzalloc(dev, sizeof(struct cs35l36_private), GFP_KERNEL);
  1524. if (!cs35l36)
  1525. return -ENOMEM;
  1526. cs35l36->dev = dev;
  1527. i2c_set_clientdata(i2c_client, cs35l36);
  1528. cs35l36->regmap = devm_regmap_init_i2c(i2c_client, &cs35l36_regmap);
  1529. if (IS_ERR(cs35l36->regmap)) {
  1530. ret = PTR_ERR(cs35l36->regmap);
  1531. dev_err(dev, "regmap_init() failed: %d\n", ret);
  1532. goto err;
  1533. }
  1534. cs35l36->num_supplies = ARRAY_SIZE(cs35l36_supplies);
  1535. for (i = 0; i < ARRAY_SIZE(cs35l36_supplies); i++)
  1536. cs35l36->supplies[i].supply = cs35l36_supplies[i];
  1537. ret = devm_regulator_bulk_get(dev, cs35l36->num_supplies,
  1538. cs35l36->supplies);
  1539. if (ret != 0) {
  1540. dev_err(dev, "Failed to request core supplies: %d\n", ret);
  1541. return ret;
  1542. }
  1543. if (pdata) {
  1544. cs35l36->pdata = *pdata;
  1545. } else {
  1546. pdata = devm_kzalloc(dev, sizeof(struct cs35l36_platform_data),
  1547. GFP_KERNEL);
  1548. if (!pdata)
  1549. return -ENOMEM;
  1550. if (i2c_client->dev.of_node) {
  1551. ret = cs35l36_handle_of_data(i2c_client, pdata);
  1552. if (ret != 0)
  1553. return ret;
  1554. }
  1555. cs35l36->pdata = *pdata;
  1556. }
  1557. ret = regulator_bulk_enable(cs35l36->num_supplies, cs35l36->supplies);
  1558. if (ret != 0) {
  1559. dev_err(dev, "Failed to enable core supplies: %d\n", ret);
  1560. return ret;
  1561. }
  1562. /* returning NULL can be an option if in stereo mode */
  1563. cs35l36->reset_gpio = devm_gpiod_get_optional(dev, "reset",
  1564. GPIOD_OUT_LOW);
  1565. if (IS_ERR(cs35l36->reset_gpio)) {
  1566. ret = PTR_ERR(cs35l36->reset_gpio);
  1567. cs35l36->reset_gpio = NULL;
  1568. if (ret == -EBUSY) {
  1569. dev_info(dev, "Reset line busy, assuming shared reset\n");
  1570. } else {
  1571. dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
  1572. goto err_disable_regs;
  1573. }
  1574. }
  1575. if (cs35l36->reset_gpio)
  1576. gpiod_set_value_cansleep(cs35l36->reset_gpio, 1);
  1577. usleep_range(2000, 2100);
  1578. /* initialize amplifier */
  1579. ret = regmap_read(cs35l36->regmap, CS35L36_SW_RESET, &reg_id);
  1580. if (ret < 0) {
  1581. dev_err(dev, "Get Device ID failed %d\n", ret);
  1582. goto err;
  1583. }
  1584. if (reg_id != CS35L36_CHIP_ID) {
  1585. dev_err(dev, "Device ID (%X). Expected ID %X\n", reg_id,
  1586. CS35L36_CHIP_ID);
  1587. ret = -ENODEV;
  1588. goto err;
  1589. }
  1590. ret = regmap_read(cs35l36->regmap, CS35L36_REV_ID, &reg_revid);
  1591. if (ret < 0) {
  1592. dev_err(&i2c_client->dev, "Get Revision ID failed %d\n", ret);
  1593. goto err;
  1594. }
  1595. cs35l36->rev_id = reg_revid >> 8;
  1596. ret = regmap_read(cs35l36->regmap, CS35L36_OTP_MEM30, &l37_id_reg);
  1597. if (ret < 0) {
  1598. dev_err(&i2c_client->dev, "Failed to read otp_id Register %d\n",
  1599. ret);
  1600. return ret;
  1601. }
  1602. if ((l37_id_reg & CS35L36_OTP_REV_MASK) == CS35L36_OTP_REV_L37)
  1603. cs35l36->chip_version = CS35L36_12V_L37;
  1604. else
  1605. cs35l36->chip_version = CS35L36_10V_L36;
  1606. switch (cs35l36->rev_id) {
  1607. case CS35L36_REV_A0:
  1608. ret = regmap_register_patch(cs35l36->regmap,
  1609. cs35l36_reva0_errata_patch,
  1610. ARRAY_SIZE(cs35l36_reva0_errata_patch));
  1611. if (ret < 0) {
  1612. dev_err(dev, "Failed to apply A0 errata patch %d\n",
  1613. ret);
  1614. goto err;
  1615. }
  1616. break;
  1617. case CS35L36_REV_B0:
  1618. ret = cs35l36_pac(cs35l36);
  1619. if (ret < 0) {
  1620. dev_err(dev, "Failed to Trim OTP %d\n", ret);
  1621. goto err;
  1622. }
  1623. ret = regmap_register_patch(cs35l36->regmap,
  1624. cs35l36_revb0_errata_patch,
  1625. ARRAY_SIZE(cs35l36_revb0_errata_patch));
  1626. if (ret < 0) {
  1627. dev_err(dev, "Failed to apply B0 errata patch %d\n",
  1628. ret);
  1629. goto err;
  1630. }
  1631. break;
  1632. }
  1633. if (pdata->vpbr_config.is_present)
  1634. cs35l36_apply_vpbr_config(cs35l36);
  1635. irq_d = irq_get_irq_data(i2c_client->irq);
  1636. if (!irq_d) {
  1637. dev_err(&i2c_client->dev, "Invalid IRQ: %d\n", i2c_client->irq);
  1638. ret = -ENODEV;
  1639. goto err;
  1640. }
  1641. irq_pol = irqd_get_trigger_type(irq_d);
  1642. switch (irq_pol) {
  1643. case IRQF_TRIGGER_FALLING:
  1644. case IRQF_TRIGGER_LOW:
  1645. chip_irq_pol = 0;
  1646. break;
  1647. case IRQF_TRIGGER_RISING:
  1648. case IRQF_TRIGGER_HIGH:
  1649. chip_irq_pol = 1;
  1650. break;
  1651. default:
  1652. dev_err(cs35l36->dev, "Invalid IRQ polarity: %d\n", irq_pol);
  1653. ret = -EINVAL;
  1654. goto err;
  1655. }
  1656. regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
  1657. CS35L36_INT_POL_SEL_MASK,
  1658. chip_irq_pol << CS35L36_INT_POL_SEL_SHIFT);
  1659. ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l36_irq,
  1660. IRQF_ONESHOT | irq_pol, "cs35l36",
  1661. cs35l36);
  1662. if (ret != 0) {
  1663. dev_err(dev, "Failed to request IRQ: %d\n", ret);
  1664. goto err;
  1665. }
  1666. regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
  1667. CS35L36_INT_OUTPUT_EN_MASK, 1);
  1668. /* Set interrupt masks for critical errors */
  1669. regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
  1670. CS35L36_INT1_MASK_DEFAULT);
  1671. regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
  1672. CS35L36_INT3_MASK_DEFAULT);
  1673. dev_info(&i2c_client->dev, "Cirrus Logic CS35L%d, Revision: %02X\n",
  1674. cs35l36->chip_version, reg_revid >> 8);
  1675. ret = devm_snd_soc_register_component(dev, &soc_component_dev_cs35l36,
  1676. cs35l36_dai,
  1677. ARRAY_SIZE(cs35l36_dai));
  1678. if (ret < 0) {
  1679. dev_err(dev, "%s: Register component failed %d\n", __func__,
  1680. ret);
  1681. goto err;
  1682. }
  1683. return 0;
  1684. err:
  1685. gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
  1686. err_disable_regs:
  1687. regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
  1688. return ret;
  1689. }
  1690. static int cs35l36_i2c_remove(struct i2c_client *client)
  1691. {
  1692. struct cs35l36_private *cs35l36 = i2c_get_clientdata(client);
  1693. /* Reset interrupt masks for device removal */
  1694. regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
  1695. CS35L36_INT1_MASK_RESET);
  1696. regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
  1697. CS35L36_INT3_MASK_RESET);
  1698. if (cs35l36->reset_gpio)
  1699. gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
  1700. regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
  1701. return 0;
  1702. }
  1703. static const struct of_device_id cs35l36_of_match[] = {
  1704. {.compatible = "cirrus,cs35l36"},
  1705. {},
  1706. };
  1707. MODULE_DEVICE_TABLE(of, cs35l36_of_match);
  1708. static const struct i2c_device_id cs35l36_id[] = {
  1709. {"cs35l36", 0},
  1710. {}
  1711. };
  1712. MODULE_DEVICE_TABLE(i2c, cs35l36_id);
  1713. static struct i2c_driver cs35l36_i2c_driver = {
  1714. .driver = {
  1715. .name = "cs35l36",
  1716. .of_match_table = cs35l36_of_match,
  1717. },
  1718. .id_table = cs35l36_id,
  1719. .probe = cs35l36_i2c_probe,
  1720. .remove = cs35l36_i2c_remove,
  1721. };
  1722. module_i2c_driver(cs35l36_i2c_driver);
  1723. MODULE_DESCRIPTION("ASoC CS35L36 driver");
  1724. MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
  1725. MODULE_LICENSE("GPL");