cs35l34.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cs35l34.c -- CS35l34 ALSA SoC audio driver
  4. *
  5. * Copyright 2016 Cirrus Logic, Inc.
  6. *
  7. * Author: Paul Handrigan <Paul.Handrigan@cirrus.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/i2c.h>
  15. #include <linux/slab.h>
  16. #include <linux/workqueue.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/regulator/machine.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/of_device.h>
  22. #include <linux/of_gpio.h>
  23. #include <linux/of_irq.h>
  24. #include <sound/core.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include <sound/soc.h>
  28. #include <sound/soc-dapm.h>
  29. #include <linux/gpio.h>
  30. #include <linux/gpio/consumer.h>
  31. #include <sound/initval.h>
  32. #include <sound/tlv.h>
  33. #include <sound/cs35l34.h>
  34. #include "cs35l34.h"
  35. #define PDN_DONE_ATTEMPTS 10
  36. #define CS35L34_START_DELAY 50
  37. struct cs35l34_private {
  38. struct snd_soc_component *component;
  39. struct cs35l34_platform_data pdata;
  40. struct regmap *regmap;
  41. struct regulator_bulk_data core_supplies[2];
  42. int num_core_supplies;
  43. int mclk_int;
  44. bool tdm_mode;
  45. struct gpio_desc *reset_gpio; /* Active-low reset GPIO */
  46. };
  47. static const struct reg_default cs35l34_reg[] = {
  48. {CS35L34_PWRCTL1, 0x01},
  49. {CS35L34_PWRCTL2, 0x19},
  50. {CS35L34_PWRCTL3, 0x01},
  51. {CS35L34_ADSP_CLK_CTL, 0x08},
  52. {CS35L34_MCLK_CTL, 0x11},
  53. {CS35L34_AMP_INP_DRV_CTL, 0x01},
  54. {CS35L34_AMP_DIG_VOL_CTL, 0x12},
  55. {CS35L34_AMP_DIG_VOL, 0x00},
  56. {CS35L34_AMP_ANLG_GAIN_CTL, 0x0F},
  57. {CS35L34_PROTECT_CTL, 0x06},
  58. {CS35L34_AMP_KEEP_ALIVE_CTL, 0x04},
  59. {CS35L34_BST_CVTR_V_CTL, 0x00},
  60. {CS35L34_BST_PEAK_I, 0x10},
  61. {CS35L34_BST_RAMP_CTL, 0x87},
  62. {CS35L34_BST_CONV_COEF_1, 0x24},
  63. {CS35L34_BST_CONV_COEF_2, 0x24},
  64. {CS35L34_BST_CONV_SLOPE_COMP, 0x4E},
  65. {CS35L34_BST_CONV_SW_FREQ, 0x08},
  66. {CS35L34_CLASS_H_CTL, 0x0D},
  67. {CS35L34_CLASS_H_HEADRM_CTL, 0x0D},
  68. {CS35L34_CLASS_H_RELEASE_RATE, 0x08},
  69. {CS35L34_CLASS_H_FET_DRIVE_CTL, 0x41},
  70. {CS35L34_CLASS_H_STATUS, 0x05},
  71. {CS35L34_VPBR_CTL, 0x0A},
  72. {CS35L34_VPBR_VOL_CTL, 0x90},
  73. {CS35L34_VPBR_TIMING_CTL, 0x6A},
  74. {CS35L34_PRED_MAX_ATTEN_SPK_LOAD, 0x95},
  75. {CS35L34_PRED_BROWNOUT_THRESH, 0x1C},
  76. {CS35L34_PRED_BROWNOUT_VOL_CTL, 0x00},
  77. {CS35L34_PRED_BROWNOUT_RATE_CTL, 0x10},
  78. {CS35L34_PRED_WAIT_CTL, 0x10},
  79. {CS35L34_PRED_ZVP_INIT_IMP_CTL, 0x08},
  80. {CS35L34_PRED_MAN_SAFE_VPI_CTL, 0x80},
  81. {CS35L34_VPBR_ATTEN_STATUS, 0x00},
  82. {CS35L34_PRED_BRWNOUT_ATT_STATUS, 0x00},
  83. {CS35L34_SPKR_MON_CTL, 0xC6},
  84. {CS35L34_ADSP_I2S_CTL, 0x00},
  85. {CS35L34_ADSP_TDM_CTL, 0x00},
  86. {CS35L34_TDM_TX_CTL_1_VMON, 0x00},
  87. {CS35L34_TDM_TX_CTL_2_IMON, 0x04},
  88. {CS35L34_TDM_TX_CTL_3_VPMON, 0x03},
  89. {CS35L34_TDM_TX_CTL_4_VBSTMON, 0x07},
  90. {CS35L34_TDM_TX_CTL_5_FLAG1, 0x08},
  91. {CS35L34_TDM_TX_CTL_6_FLAG2, 0x09},
  92. {CS35L34_TDM_TX_SLOT_EN_1, 0x00},
  93. {CS35L34_TDM_TX_SLOT_EN_2, 0x00},
  94. {CS35L34_TDM_TX_SLOT_EN_3, 0x00},
  95. {CS35L34_TDM_TX_SLOT_EN_4, 0x00},
  96. {CS35L34_TDM_RX_CTL_1_AUDIN, 0x40},
  97. {CS35L34_TDM_RX_CTL_3_ALIVE, 0x04},
  98. {CS35L34_MULT_DEV_SYNCH1, 0x00},
  99. {CS35L34_MULT_DEV_SYNCH2, 0x80},
  100. {CS35L34_PROT_RELEASE_CTL, 0x00},
  101. {CS35L34_DIAG_MODE_REG_LOCK, 0x00},
  102. {CS35L34_DIAG_MODE_CTL_1, 0x00},
  103. {CS35L34_DIAG_MODE_CTL_2, 0x00},
  104. {CS35L34_INT_MASK_1, 0xFF},
  105. {CS35L34_INT_MASK_2, 0xFF},
  106. {CS35L34_INT_MASK_3, 0xFF},
  107. {CS35L34_INT_MASK_4, 0xFF},
  108. {CS35L34_INT_STATUS_1, 0x30},
  109. {CS35L34_INT_STATUS_2, 0x05},
  110. {CS35L34_INT_STATUS_3, 0x00},
  111. {CS35L34_INT_STATUS_4, 0x00},
  112. {CS35L34_OTP_TRIM_STATUS, 0x00},
  113. };
  114. static bool cs35l34_volatile_register(struct device *dev, unsigned int reg)
  115. {
  116. switch (reg) {
  117. case CS35L34_DEVID_AB:
  118. case CS35L34_DEVID_CD:
  119. case CS35L34_DEVID_E:
  120. case CS35L34_FAB_ID:
  121. case CS35L34_REV_ID:
  122. case CS35L34_INT_STATUS_1:
  123. case CS35L34_INT_STATUS_2:
  124. case CS35L34_INT_STATUS_3:
  125. case CS35L34_INT_STATUS_4:
  126. case CS35L34_CLASS_H_STATUS:
  127. case CS35L34_VPBR_ATTEN_STATUS:
  128. case CS35L34_OTP_TRIM_STATUS:
  129. return true;
  130. default:
  131. return false;
  132. }
  133. }
  134. static bool cs35l34_readable_register(struct device *dev, unsigned int reg)
  135. {
  136. switch (reg) {
  137. case CS35L34_DEVID_AB:
  138. case CS35L34_DEVID_CD:
  139. case CS35L34_DEVID_E:
  140. case CS35L34_FAB_ID:
  141. case CS35L34_REV_ID:
  142. case CS35L34_PWRCTL1:
  143. case CS35L34_PWRCTL2:
  144. case CS35L34_PWRCTL3:
  145. case CS35L34_ADSP_CLK_CTL:
  146. case CS35L34_MCLK_CTL:
  147. case CS35L34_AMP_INP_DRV_CTL:
  148. case CS35L34_AMP_DIG_VOL_CTL:
  149. case CS35L34_AMP_DIG_VOL:
  150. case CS35L34_AMP_ANLG_GAIN_CTL:
  151. case CS35L34_PROTECT_CTL:
  152. case CS35L34_AMP_KEEP_ALIVE_CTL:
  153. case CS35L34_BST_CVTR_V_CTL:
  154. case CS35L34_BST_PEAK_I:
  155. case CS35L34_BST_RAMP_CTL:
  156. case CS35L34_BST_CONV_COEF_1:
  157. case CS35L34_BST_CONV_COEF_2:
  158. case CS35L34_BST_CONV_SLOPE_COMP:
  159. case CS35L34_BST_CONV_SW_FREQ:
  160. case CS35L34_CLASS_H_CTL:
  161. case CS35L34_CLASS_H_HEADRM_CTL:
  162. case CS35L34_CLASS_H_RELEASE_RATE:
  163. case CS35L34_CLASS_H_FET_DRIVE_CTL:
  164. case CS35L34_CLASS_H_STATUS:
  165. case CS35L34_VPBR_CTL:
  166. case CS35L34_VPBR_VOL_CTL:
  167. case CS35L34_VPBR_TIMING_CTL:
  168. case CS35L34_PRED_MAX_ATTEN_SPK_LOAD:
  169. case CS35L34_PRED_BROWNOUT_THRESH:
  170. case CS35L34_PRED_BROWNOUT_VOL_CTL:
  171. case CS35L34_PRED_BROWNOUT_RATE_CTL:
  172. case CS35L34_PRED_WAIT_CTL:
  173. case CS35L34_PRED_ZVP_INIT_IMP_CTL:
  174. case CS35L34_PRED_MAN_SAFE_VPI_CTL:
  175. case CS35L34_VPBR_ATTEN_STATUS:
  176. case CS35L34_PRED_BRWNOUT_ATT_STATUS:
  177. case CS35L34_SPKR_MON_CTL:
  178. case CS35L34_ADSP_I2S_CTL:
  179. case CS35L34_ADSP_TDM_CTL:
  180. case CS35L34_TDM_TX_CTL_1_VMON:
  181. case CS35L34_TDM_TX_CTL_2_IMON:
  182. case CS35L34_TDM_TX_CTL_3_VPMON:
  183. case CS35L34_TDM_TX_CTL_4_VBSTMON:
  184. case CS35L34_TDM_TX_CTL_5_FLAG1:
  185. case CS35L34_TDM_TX_CTL_6_FLAG2:
  186. case CS35L34_TDM_TX_SLOT_EN_1:
  187. case CS35L34_TDM_TX_SLOT_EN_2:
  188. case CS35L34_TDM_TX_SLOT_EN_3:
  189. case CS35L34_TDM_TX_SLOT_EN_4:
  190. case CS35L34_TDM_RX_CTL_1_AUDIN:
  191. case CS35L34_TDM_RX_CTL_3_ALIVE:
  192. case CS35L34_MULT_DEV_SYNCH1:
  193. case CS35L34_MULT_DEV_SYNCH2:
  194. case CS35L34_PROT_RELEASE_CTL:
  195. case CS35L34_DIAG_MODE_REG_LOCK:
  196. case CS35L34_DIAG_MODE_CTL_1:
  197. case CS35L34_DIAG_MODE_CTL_2:
  198. case CS35L34_INT_MASK_1:
  199. case CS35L34_INT_MASK_2:
  200. case CS35L34_INT_MASK_3:
  201. case CS35L34_INT_MASK_4:
  202. case CS35L34_INT_STATUS_1:
  203. case CS35L34_INT_STATUS_2:
  204. case CS35L34_INT_STATUS_3:
  205. case CS35L34_INT_STATUS_4:
  206. case CS35L34_OTP_TRIM_STATUS:
  207. return true;
  208. default:
  209. return false;
  210. }
  211. }
  212. static bool cs35l34_precious_register(struct device *dev, unsigned int reg)
  213. {
  214. switch (reg) {
  215. case CS35L34_INT_STATUS_1:
  216. case CS35L34_INT_STATUS_2:
  217. case CS35L34_INT_STATUS_3:
  218. case CS35L34_INT_STATUS_4:
  219. return true;
  220. default:
  221. return false;
  222. }
  223. }
  224. static int cs35l34_sdin_event(struct snd_soc_dapm_widget *w,
  225. struct snd_kcontrol *kcontrol, int event)
  226. {
  227. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  228. struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
  229. int ret;
  230. switch (event) {
  231. case SND_SOC_DAPM_PRE_PMU:
  232. if (priv->tdm_mode)
  233. regmap_update_bits(priv->regmap, CS35L34_PWRCTL3,
  234. CS35L34_PDN_TDM, 0x00);
  235. ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1,
  236. CS35L34_PDN_ALL, 0);
  237. if (ret < 0) {
  238. dev_err(component->dev, "Cannot set Power bits %d\n", ret);
  239. return ret;
  240. }
  241. usleep_range(5000, 5100);
  242. break;
  243. case SND_SOC_DAPM_POST_PMD:
  244. if (priv->tdm_mode) {
  245. regmap_update_bits(priv->regmap, CS35L34_PWRCTL3,
  246. CS35L34_PDN_TDM, CS35L34_PDN_TDM);
  247. }
  248. ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1,
  249. CS35L34_PDN_ALL, CS35L34_PDN_ALL);
  250. break;
  251. default:
  252. pr_err("Invalid event = 0x%x\n", event);
  253. }
  254. return 0;
  255. }
  256. static int cs35l34_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  257. unsigned int rx_mask, int slots, int slot_width)
  258. {
  259. struct snd_soc_component *component = dai->component;
  260. struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
  261. unsigned int reg, bit_pos;
  262. int slot, slot_num;
  263. if (slot_width != 8)
  264. return -EINVAL;
  265. priv->tdm_mode = true;
  266. /* scan rx_mask for aud slot */
  267. slot = ffs(rx_mask) - 1;
  268. if (slot >= 0)
  269. snd_soc_component_update_bits(component, CS35L34_TDM_RX_CTL_1_AUDIN,
  270. CS35L34_X_LOC, slot);
  271. /* scan tx_mask: vmon(2 slots); imon (2 slots); vpmon (1 slot)
  272. * vbstmon (1 slot)
  273. */
  274. slot = ffs(tx_mask) - 1;
  275. slot_num = 0;
  276. /* disable vpmon/vbstmon: enable later if set in tx_mask */
  277. snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON,
  278. CS35L34_X_STATE | CS35L34_X_LOC,
  279. CS35L34_X_STATE | CS35L34_X_LOC);
  280. snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_4_VBSTMON,
  281. CS35L34_X_STATE | CS35L34_X_LOC,
  282. CS35L34_X_STATE | CS35L34_X_LOC);
  283. /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/
  284. while (slot >= 0) {
  285. /* configure VMON_TX_LOC */
  286. if (slot_num == 0)
  287. snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_1_VMON,
  288. CS35L34_X_STATE | CS35L34_X_LOC, slot);
  289. /* configure IMON_TX_LOC */
  290. if (slot_num == 4) {
  291. snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_2_IMON,
  292. CS35L34_X_STATE | CS35L34_X_LOC, slot);
  293. }
  294. /* configure VPMON_TX_LOC */
  295. if (slot_num == 3) {
  296. snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON,
  297. CS35L34_X_STATE | CS35L34_X_LOC, slot);
  298. }
  299. /* configure VBSTMON_TX_LOC */
  300. if (slot_num == 7) {
  301. snd_soc_component_update_bits(component,
  302. CS35L34_TDM_TX_CTL_4_VBSTMON,
  303. CS35L34_X_STATE | CS35L34_X_LOC, slot);
  304. }
  305. /* Enable the relevant tx slot */
  306. reg = CS35L34_TDM_TX_SLOT_EN_4 - (slot/8);
  307. bit_pos = slot - ((slot / 8) * (8));
  308. snd_soc_component_update_bits(component, reg,
  309. 1 << bit_pos, 1 << bit_pos);
  310. tx_mask &= ~(1 << slot);
  311. slot = ffs(tx_mask) - 1;
  312. slot_num++;
  313. }
  314. return 0;
  315. }
  316. static int cs35l34_main_amp_event(struct snd_soc_dapm_widget *w,
  317. struct snd_kcontrol *kcontrol, int event)
  318. {
  319. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  320. struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
  321. switch (event) {
  322. case SND_SOC_DAPM_POST_PMU:
  323. regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL,
  324. CS35L34_BST_CVTL_MASK, priv->pdata.boost_vtge);
  325. usleep_range(5000, 5100);
  326. regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL,
  327. CS35L34_MUTE, 0);
  328. break;
  329. case SND_SOC_DAPM_POST_PMD:
  330. regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL,
  331. CS35L34_BST_CVTL_MASK, 0);
  332. regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL,
  333. CS35L34_MUTE, CS35L34_MUTE);
  334. usleep_range(5000, 5100);
  335. break;
  336. default:
  337. pr_err("Invalid event = 0x%x\n", event);
  338. }
  339. return 0;
  340. }
  341. static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0);
  342. static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 300, 100, 0);
  343. static const struct snd_kcontrol_new cs35l34_snd_controls[] = {
  344. SOC_SINGLE_SX_TLV("Digital Volume", CS35L34_AMP_DIG_VOL,
  345. 0, 0x34, 0xE4, dig_vol_tlv),
  346. SOC_SINGLE_TLV("Amp Gain Volume", CS35L34_AMP_ANLG_GAIN_CTL,
  347. 0, 0xF, 0, amp_gain_tlv),
  348. };
  349. static int cs35l34_mclk_event(struct snd_soc_dapm_widget *w,
  350. struct snd_kcontrol *kcontrol, int event)
  351. {
  352. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  353. struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
  354. int ret, i;
  355. unsigned int reg;
  356. switch (event) {
  357. case SND_SOC_DAPM_PRE_PMD:
  358. ret = regmap_read(priv->regmap, CS35L34_AMP_DIG_VOL_CTL,
  359. &reg);
  360. if (ret != 0) {
  361. pr_err("%s regmap read failure %d\n", __func__, ret);
  362. return ret;
  363. }
  364. if (reg & CS35L34_AMP_DIGSFT)
  365. msleep(40);
  366. else
  367. usleep_range(2000, 2100);
  368. for (i = 0; i < PDN_DONE_ATTEMPTS; i++) {
  369. ret = regmap_read(priv->regmap, CS35L34_INT_STATUS_2,
  370. &reg);
  371. if (ret != 0) {
  372. pr_err("%s regmap read failure %d\n",
  373. __func__, ret);
  374. return ret;
  375. }
  376. if (reg & CS35L34_PDN_DONE)
  377. break;
  378. usleep_range(5000, 5100);
  379. }
  380. if (i == PDN_DONE_ATTEMPTS)
  381. pr_err("%s Device did not power down properly\n",
  382. __func__);
  383. break;
  384. default:
  385. pr_err("Invalid event = 0x%x\n", event);
  386. break;
  387. }
  388. return 0;
  389. }
  390. static const struct snd_soc_dapm_widget cs35l34_dapm_widgets[] = {
  391. SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L34_PWRCTL3,
  392. 1, 1, cs35l34_sdin_event,
  393. SND_SOC_DAPM_PRE_PMU |
  394. SND_SOC_DAPM_POST_PMD),
  395. SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L34_PWRCTL3, 2, 1),
  396. SND_SOC_DAPM_SUPPLY("EXTCLK", CS35L34_PWRCTL3, 7, 1,
  397. cs35l34_mclk_event, SND_SOC_DAPM_PRE_PMD),
  398. SND_SOC_DAPM_OUTPUT("SPK"),
  399. SND_SOC_DAPM_INPUT("VP"),
  400. SND_SOC_DAPM_INPUT("VPST"),
  401. SND_SOC_DAPM_INPUT("ISENSE"),
  402. SND_SOC_DAPM_INPUT("VSENSE"),
  403. SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L34_PWRCTL2, 7, 1),
  404. SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L34_PWRCTL2, 6, 1),
  405. SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L34_PWRCTL3, 3, 1),
  406. SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L34_PWRCTL3, 4, 1),
  407. SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L34_PWRCTL2, 5, 1),
  408. SND_SOC_DAPM_ADC("BOOST", NULL, CS35L34_PWRCTL2, 2, 1),
  409. SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L34_PWRCTL2, 0, 1, NULL, 0,
  410. cs35l34_main_amp_event, SND_SOC_DAPM_POST_PMU |
  411. SND_SOC_DAPM_POST_PMD),
  412. };
  413. static const struct snd_soc_dapm_route cs35l34_audio_map[] = {
  414. {"SDIN", NULL, "AMP Playback"},
  415. {"BOOST", NULL, "SDIN"},
  416. {"CLASS H", NULL, "BOOST"},
  417. {"Main AMP", NULL, "CLASS H"},
  418. {"SPK", NULL, "Main AMP"},
  419. {"VPMON ADC", NULL, "CLASS H"},
  420. {"VBSTMON ADC", NULL, "CLASS H"},
  421. {"SPK", NULL, "VPMON ADC"},
  422. {"SPK", NULL, "VBSTMON ADC"},
  423. {"IMON ADC", NULL, "ISENSE"},
  424. {"VMON ADC", NULL, "VSENSE"},
  425. {"SDOUT", NULL, "IMON ADC"},
  426. {"SDOUT", NULL, "VMON ADC"},
  427. {"AMP Capture", NULL, "SDOUT"},
  428. {"SDIN", NULL, "EXTCLK"},
  429. {"SDOUT", NULL, "EXTCLK"},
  430. };
  431. struct cs35l34_mclk_div {
  432. int mclk;
  433. int srate;
  434. u8 adsp_rate;
  435. };
  436. static struct cs35l34_mclk_div cs35l34_mclk_coeffs[] = {
  437. /* MCLK, Sample Rate, adsp_rate */
  438. {5644800, 11025, 0x1},
  439. {5644800, 22050, 0x4},
  440. {5644800, 44100, 0x7},
  441. {6000000, 8000, 0x0},
  442. {6000000, 11025, 0x1},
  443. {6000000, 12000, 0x2},
  444. {6000000, 16000, 0x3},
  445. {6000000, 22050, 0x4},
  446. {6000000, 24000, 0x5},
  447. {6000000, 32000, 0x6},
  448. {6000000, 44100, 0x7},
  449. {6000000, 48000, 0x8},
  450. {6144000, 8000, 0x0},
  451. {6144000, 11025, 0x1},
  452. {6144000, 12000, 0x2},
  453. {6144000, 16000, 0x3},
  454. {6144000, 22050, 0x4},
  455. {6144000, 24000, 0x5},
  456. {6144000, 32000, 0x6},
  457. {6144000, 44100, 0x7},
  458. {6144000, 48000, 0x8},
  459. };
  460. static int cs35l34_get_mclk_coeff(int mclk, int srate)
  461. {
  462. int i;
  463. for (i = 0; i < ARRAY_SIZE(cs35l34_mclk_coeffs); i++) {
  464. if (cs35l34_mclk_coeffs[i].mclk == mclk &&
  465. cs35l34_mclk_coeffs[i].srate == srate)
  466. return i;
  467. }
  468. return -EINVAL;
  469. }
  470. static int cs35l34_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  471. {
  472. struct snd_soc_component *component = codec_dai->component;
  473. struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
  474. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  475. case SND_SOC_DAIFMT_CBM_CFM:
  476. regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
  477. 0x80, 0x80);
  478. break;
  479. case SND_SOC_DAIFMT_CBS_CFS:
  480. regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
  481. 0x80, 0x00);
  482. break;
  483. default:
  484. return -EINVAL;
  485. }
  486. return 0;
  487. }
  488. static int cs35l34_pcm_hw_params(struct snd_pcm_substream *substream,
  489. struct snd_pcm_hw_params *params,
  490. struct snd_soc_dai *dai)
  491. {
  492. struct snd_soc_component *component = dai->component;
  493. struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
  494. int srate = params_rate(params);
  495. int ret;
  496. int coeff = cs35l34_get_mclk_coeff(priv->mclk_int, srate);
  497. if (coeff < 0) {
  498. dev_err(component->dev, "ERROR: Invalid mclk %d and/or srate %d\n",
  499. priv->mclk_int, srate);
  500. return coeff;
  501. }
  502. ret = regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
  503. CS35L34_ADSP_RATE, cs35l34_mclk_coeffs[coeff].adsp_rate);
  504. if (ret != 0)
  505. dev_err(component->dev, "Failed to set clock state %d\n", ret);
  506. return ret;
  507. }
  508. static const unsigned int cs35l34_src_rates[] = {
  509. 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
  510. };
  511. static const struct snd_pcm_hw_constraint_list cs35l34_constraints = {
  512. .count = ARRAY_SIZE(cs35l34_src_rates),
  513. .list = cs35l34_src_rates,
  514. };
  515. static int cs35l34_pcm_startup(struct snd_pcm_substream *substream,
  516. struct snd_soc_dai *dai)
  517. {
  518. snd_pcm_hw_constraint_list(substream->runtime, 0,
  519. SNDRV_PCM_HW_PARAM_RATE, &cs35l34_constraints);
  520. return 0;
  521. }
  522. static int cs35l34_set_tristate(struct snd_soc_dai *dai, int tristate)
  523. {
  524. struct snd_soc_component *component = dai->component;
  525. if (tristate)
  526. snd_soc_component_update_bits(component, CS35L34_PWRCTL3,
  527. CS35L34_PDN_SDOUT, CS35L34_PDN_SDOUT);
  528. else
  529. snd_soc_component_update_bits(component, CS35L34_PWRCTL3,
  530. CS35L34_PDN_SDOUT, 0);
  531. return 0;
  532. }
  533. static int cs35l34_dai_set_sysclk(struct snd_soc_dai *dai,
  534. int clk_id, unsigned int freq, int dir)
  535. {
  536. struct snd_soc_component *component = dai->component;
  537. struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component);
  538. unsigned int value;
  539. switch (freq) {
  540. case CS35L34_MCLK_5644:
  541. value = CS35L34_MCLK_RATE_5P6448;
  542. cs35l34->mclk_int = freq;
  543. break;
  544. case CS35L34_MCLK_6:
  545. value = CS35L34_MCLK_RATE_6P0000;
  546. cs35l34->mclk_int = freq;
  547. break;
  548. case CS35L34_MCLK_6144:
  549. value = CS35L34_MCLK_RATE_6P1440;
  550. cs35l34->mclk_int = freq;
  551. break;
  552. case CS35L34_MCLK_11289:
  553. value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_5P6448;
  554. cs35l34->mclk_int = freq / 2;
  555. break;
  556. case CS35L34_MCLK_12:
  557. value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P0000;
  558. cs35l34->mclk_int = freq / 2;
  559. break;
  560. case CS35L34_MCLK_12288:
  561. value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P1440;
  562. cs35l34->mclk_int = freq / 2;
  563. break;
  564. default:
  565. dev_err(component->dev, "ERROR: Invalid Frequency %d\n", freq);
  566. cs35l34->mclk_int = 0;
  567. return -EINVAL;
  568. }
  569. regmap_update_bits(cs35l34->regmap, CS35L34_MCLK_CTL,
  570. CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_MASK, value);
  571. return 0;
  572. }
  573. static const struct snd_soc_dai_ops cs35l34_ops = {
  574. .startup = cs35l34_pcm_startup,
  575. .set_tristate = cs35l34_set_tristate,
  576. .set_fmt = cs35l34_set_dai_fmt,
  577. .hw_params = cs35l34_pcm_hw_params,
  578. .set_sysclk = cs35l34_dai_set_sysclk,
  579. .set_tdm_slot = cs35l34_set_tdm_slot,
  580. };
  581. static struct snd_soc_dai_driver cs35l34_dai = {
  582. .name = "cs35l34",
  583. .id = 0,
  584. .playback = {
  585. .stream_name = "AMP Playback",
  586. .channels_min = 1,
  587. .channels_max = 8,
  588. .rates = CS35L34_RATES,
  589. .formats = CS35L34_FORMATS,
  590. },
  591. .capture = {
  592. .stream_name = "AMP Capture",
  593. .channels_min = 1,
  594. .channels_max = 8,
  595. .rates = CS35L34_RATES,
  596. .formats = CS35L34_FORMATS,
  597. },
  598. .ops = &cs35l34_ops,
  599. .symmetric_rates = 1,
  600. };
  601. static int cs35l34_boost_inductor(struct cs35l34_private *cs35l34,
  602. unsigned int inductor)
  603. {
  604. struct snd_soc_component *component = cs35l34->component;
  605. switch (inductor) {
  606. case 1000: /* 1 uH */
  607. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x24);
  608. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x24);
  609. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
  610. 0x4E);
  611. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 0);
  612. break;
  613. case 1200: /* 1.2 uH */
  614. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20);
  615. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20);
  616. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
  617. 0x47);
  618. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 1);
  619. break;
  620. case 1500: /* 1.5uH */
  621. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20);
  622. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20);
  623. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
  624. 0x3C);
  625. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 2);
  626. break;
  627. case 2200: /* 2.2uH */
  628. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x19);
  629. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x25);
  630. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
  631. 0x23);
  632. regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 3);
  633. break;
  634. default:
  635. dev_err(component->dev, "%s Invalid Inductor Value %d uH\n",
  636. __func__, inductor);
  637. return -EINVAL;
  638. }
  639. return 0;
  640. }
  641. static int cs35l34_probe(struct snd_soc_component *component)
  642. {
  643. int ret = 0;
  644. struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component);
  645. pm_runtime_get_sync(component->dev);
  646. /* Set over temperature warning attenuation to 6 dB */
  647. regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
  648. CS35L34_OTW_ATTN_MASK, 0x8);
  649. /* Set Power control registers 2 and 3 to have everything
  650. * powered down at initialization
  651. */
  652. regmap_write(cs35l34->regmap, CS35L34_PWRCTL2, 0xFD);
  653. regmap_write(cs35l34->regmap, CS35L34_PWRCTL3, 0x1F);
  654. /* Set mute bit at startup */
  655. regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
  656. CS35L34_MUTE, CS35L34_MUTE);
  657. /* Set Platform Data */
  658. if (cs35l34->pdata.boost_peak)
  659. regmap_update_bits(cs35l34->regmap, CS35L34_BST_PEAK_I,
  660. CS35L34_BST_PEAK_MASK,
  661. cs35l34->pdata.boost_peak);
  662. if (cs35l34->pdata.gain_zc_disable)
  663. regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
  664. CS35L34_GAIN_ZC_MASK, 0);
  665. else
  666. regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
  667. CS35L34_GAIN_ZC_MASK, CS35L34_GAIN_ZC_MASK);
  668. if (cs35l34->pdata.aif_half_drv)
  669. regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_CLK_CTL,
  670. CS35L34_ADSP_DRIVE, 0);
  671. if (cs35l34->pdata.digsft_disable)
  672. regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL,
  673. CS35L34_AMP_DIGSFT, 0);
  674. if (cs35l34->pdata.amp_inv)
  675. regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL,
  676. CS35L34_INV, CS35L34_INV);
  677. if (cs35l34->pdata.boost_ind)
  678. ret = cs35l34_boost_inductor(cs35l34, cs35l34->pdata.boost_ind);
  679. if (cs35l34->pdata.i2s_sdinloc)
  680. regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_I2S_CTL,
  681. CS35L34_I2S_LOC_MASK,
  682. cs35l34->pdata.i2s_sdinloc << CS35L34_I2S_LOC_SHIFT);
  683. if (cs35l34->pdata.tdm_rising_edge)
  684. regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_TDM_CTL,
  685. 1, 1);
  686. pm_runtime_put_sync(component->dev);
  687. return ret;
  688. }
  689. static const struct snd_soc_component_driver soc_component_dev_cs35l34 = {
  690. .probe = cs35l34_probe,
  691. .dapm_widgets = cs35l34_dapm_widgets,
  692. .num_dapm_widgets = ARRAY_SIZE(cs35l34_dapm_widgets),
  693. .dapm_routes = cs35l34_audio_map,
  694. .num_dapm_routes = ARRAY_SIZE(cs35l34_audio_map),
  695. .controls = cs35l34_snd_controls,
  696. .num_controls = ARRAY_SIZE(cs35l34_snd_controls),
  697. .idle_bias_on = 1,
  698. .use_pmdown_time = 1,
  699. .endianness = 1,
  700. .non_legacy_dai_naming = 1,
  701. };
  702. static struct regmap_config cs35l34_regmap = {
  703. .reg_bits = 8,
  704. .val_bits = 8,
  705. .max_register = CS35L34_MAX_REGISTER,
  706. .reg_defaults = cs35l34_reg,
  707. .num_reg_defaults = ARRAY_SIZE(cs35l34_reg),
  708. .volatile_reg = cs35l34_volatile_register,
  709. .readable_reg = cs35l34_readable_register,
  710. .precious_reg = cs35l34_precious_register,
  711. .cache_type = REGCACHE_RBTREE,
  712. };
  713. static int cs35l34_handle_of_data(struct i2c_client *i2c_client,
  714. struct cs35l34_platform_data *pdata)
  715. {
  716. struct device_node *np = i2c_client->dev.of_node;
  717. unsigned int val;
  718. if (of_property_read_u32(np, "cirrus,boost-vtge-millivolt",
  719. &val) >= 0) {
  720. /* Boost Voltage has a maximum of 8V */
  721. if (val > 8000 || (val < 3300 && val > 0)) {
  722. dev_err(&i2c_client->dev,
  723. "Invalid Boost Voltage %d mV\n", val);
  724. return -EINVAL;
  725. }
  726. if (val == 0)
  727. pdata->boost_vtge = 0; /* Use VP */
  728. else
  729. pdata->boost_vtge = ((val - 3300)/100) + 1;
  730. } else {
  731. dev_warn(&i2c_client->dev,
  732. "Boost Voltage not specified. Using VP\n");
  733. }
  734. if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) {
  735. pdata->boost_ind = val;
  736. } else {
  737. dev_err(&i2c_client->dev, "Inductor not specified.\n");
  738. return -EINVAL;
  739. }
  740. if (of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val) >= 0) {
  741. if (val > 3840 || val < 1200) {
  742. dev_err(&i2c_client->dev,
  743. "Invalid Boost Peak Current %d mA\n", val);
  744. return -EINVAL;
  745. }
  746. pdata->boost_peak = ((val - 1200)/80) + 1;
  747. }
  748. pdata->aif_half_drv = of_property_read_bool(np,
  749. "cirrus,aif-half-drv");
  750. pdata->digsft_disable = of_property_read_bool(np,
  751. "cirrus,digsft-disable");
  752. pdata->gain_zc_disable = of_property_read_bool(np,
  753. "cirrus,gain-zc-disable");
  754. pdata->amp_inv = of_property_read_bool(np, "cirrus,amp-inv");
  755. if (of_property_read_u32(np, "cirrus,i2s-sdinloc", &val) >= 0)
  756. pdata->i2s_sdinloc = val;
  757. if (of_property_read_u32(np, "cirrus,tdm-rising-edge", &val) >= 0)
  758. pdata->tdm_rising_edge = val;
  759. return 0;
  760. }
  761. static irqreturn_t cs35l34_irq_thread(int irq, void *data)
  762. {
  763. struct cs35l34_private *cs35l34 = data;
  764. struct snd_soc_component *component = cs35l34->component;
  765. unsigned int sticky1, sticky2, sticky3, sticky4;
  766. unsigned int mask1, mask2, mask3, mask4, current1;
  767. /* ack the irq by reading all status registers */
  768. regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_4, &sticky4);
  769. regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_3, &sticky3);
  770. regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_2, &sticky2);
  771. regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, &sticky1);
  772. regmap_read(cs35l34->regmap, CS35L34_INT_MASK_4, &mask4);
  773. regmap_read(cs35l34->regmap, CS35L34_INT_MASK_3, &mask3);
  774. regmap_read(cs35l34->regmap, CS35L34_INT_MASK_2, &mask2);
  775. regmap_read(cs35l34->regmap, CS35L34_INT_MASK_1, &mask1);
  776. if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3)
  777. && !(sticky4 & ~mask4))
  778. return IRQ_NONE;
  779. regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, &current1);
  780. if (sticky1 & CS35L34_CAL_ERR) {
  781. dev_err(component->dev, "Cal error\n");
  782. /* error is no longer asserted; safe to reset */
  783. if (!(current1 & CS35L34_CAL_ERR)) {
  784. dev_dbg(component->dev, "Cal error release\n");
  785. regmap_update_bits(cs35l34->regmap,
  786. CS35L34_PROT_RELEASE_CTL,
  787. CS35L34_CAL_ERR_RLS, 0);
  788. regmap_update_bits(cs35l34->regmap,
  789. CS35L34_PROT_RELEASE_CTL,
  790. CS35L34_CAL_ERR_RLS,
  791. CS35L34_CAL_ERR_RLS);
  792. regmap_update_bits(cs35l34->regmap,
  793. CS35L34_PROT_RELEASE_CTL,
  794. CS35L34_CAL_ERR_RLS, 0);
  795. /* note: amp will re-calibrate on next resume */
  796. }
  797. }
  798. if (sticky1 & CS35L34_ALIVE_ERR)
  799. dev_err(component->dev, "Alive error\n");
  800. if (sticky1 & CS35L34_AMP_SHORT) {
  801. dev_crit(component->dev, "Amp short error\n");
  802. /* error is no longer asserted; safe to reset */
  803. if (!(current1 & CS35L34_AMP_SHORT)) {
  804. dev_dbg(component->dev,
  805. "Amp short error release\n");
  806. regmap_update_bits(cs35l34->regmap,
  807. CS35L34_PROT_RELEASE_CTL,
  808. CS35L34_SHORT_RLS, 0);
  809. regmap_update_bits(cs35l34->regmap,
  810. CS35L34_PROT_RELEASE_CTL,
  811. CS35L34_SHORT_RLS,
  812. CS35L34_SHORT_RLS);
  813. regmap_update_bits(cs35l34->regmap,
  814. CS35L34_PROT_RELEASE_CTL,
  815. CS35L34_SHORT_RLS, 0);
  816. }
  817. }
  818. if (sticky1 & CS35L34_OTW) {
  819. dev_crit(component->dev, "Over temperature warning\n");
  820. /* error is no longer asserted; safe to reset */
  821. if (!(current1 & CS35L34_OTW)) {
  822. dev_dbg(component->dev,
  823. "Over temperature warning release\n");
  824. regmap_update_bits(cs35l34->regmap,
  825. CS35L34_PROT_RELEASE_CTL,
  826. CS35L34_OTW_RLS, 0);
  827. regmap_update_bits(cs35l34->regmap,
  828. CS35L34_PROT_RELEASE_CTL,
  829. CS35L34_OTW_RLS,
  830. CS35L34_OTW_RLS);
  831. regmap_update_bits(cs35l34->regmap,
  832. CS35L34_PROT_RELEASE_CTL,
  833. CS35L34_OTW_RLS, 0);
  834. }
  835. }
  836. if (sticky1 & CS35L34_OTE) {
  837. dev_crit(component->dev, "Over temperature error\n");
  838. /* error is no longer asserted; safe to reset */
  839. if (!(current1 & CS35L34_OTE)) {
  840. dev_dbg(component->dev,
  841. "Over temperature error release\n");
  842. regmap_update_bits(cs35l34->regmap,
  843. CS35L34_PROT_RELEASE_CTL,
  844. CS35L34_OTE_RLS, 0);
  845. regmap_update_bits(cs35l34->regmap,
  846. CS35L34_PROT_RELEASE_CTL,
  847. CS35L34_OTE_RLS,
  848. CS35L34_OTE_RLS);
  849. regmap_update_bits(cs35l34->regmap,
  850. CS35L34_PROT_RELEASE_CTL,
  851. CS35L34_OTE_RLS, 0);
  852. }
  853. }
  854. if (sticky3 & CS35L34_BST_HIGH) {
  855. dev_crit(component->dev, "VBST too high error; powering off!\n");
  856. regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2,
  857. CS35L34_PDN_AMP, CS35L34_PDN_AMP);
  858. regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1,
  859. CS35L34_PDN_ALL, CS35L34_PDN_ALL);
  860. }
  861. if (sticky3 & CS35L34_LBST_SHORT) {
  862. dev_crit(component->dev, "LBST short error; powering off!\n");
  863. regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2,
  864. CS35L34_PDN_AMP, CS35L34_PDN_AMP);
  865. regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1,
  866. CS35L34_PDN_ALL, CS35L34_PDN_ALL);
  867. }
  868. return IRQ_HANDLED;
  869. }
  870. static const char * const cs35l34_core_supplies[] = {
  871. "VA",
  872. "VP",
  873. };
  874. static int cs35l34_i2c_probe(struct i2c_client *i2c_client,
  875. const struct i2c_device_id *id)
  876. {
  877. struct cs35l34_private *cs35l34;
  878. struct cs35l34_platform_data *pdata =
  879. dev_get_platdata(&i2c_client->dev);
  880. int i;
  881. int ret;
  882. unsigned int devid = 0;
  883. unsigned int reg;
  884. cs35l34 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l34), GFP_KERNEL);
  885. if (!cs35l34)
  886. return -ENOMEM;
  887. i2c_set_clientdata(i2c_client, cs35l34);
  888. cs35l34->regmap = devm_regmap_init_i2c(i2c_client, &cs35l34_regmap);
  889. if (IS_ERR(cs35l34->regmap)) {
  890. ret = PTR_ERR(cs35l34->regmap);
  891. dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
  892. return ret;
  893. }
  894. cs35l34->num_core_supplies = ARRAY_SIZE(cs35l34_core_supplies);
  895. for (i = 0; i < ARRAY_SIZE(cs35l34_core_supplies); i++)
  896. cs35l34->core_supplies[i].supply = cs35l34_core_supplies[i];
  897. ret = devm_regulator_bulk_get(&i2c_client->dev,
  898. cs35l34->num_core_supplies,
  899. cs35l34->core_supplies);
  900. if (ret != 0) {
  901. dev_err(&i2c_client->dev,
  902. "Failed to request core supplies %d\n", ret);
  903. return ret;
  904. }
  905. ret = regulator_bulk_enable(cs35l34->num_core_supplies,
  906. cs35l34->core_supplies);
  907. if (ret != 0) {
  908. dev_err(&i2c_client->dev,
  909. "Failed to enable core supplies: %d\n", ret);
  910. return ret;
  911. }
  912. if (pdata) {
  913. cs35l34->pdata = *pdata;
  914. } else {
  915. pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
  916. GFP_KERNEL);
  917. if (!pdata)
  918. return -ENOMEM;
  919. if (i2c_client->dev.of_node) {
  920. ret = cs35l34_handle_of_data(i2c_client, pdata);
  921. if (ret != 0)
  922. return ret;
  923. }
  924. cs35l34->pdata = *pdata;
  925. }
  926. ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
  927. cs35l34_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
  928. "cs35l34", cs35l34);
  929. if (ret != 0)
  930. dev_err(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
  931. cs35l34->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
  932. "reset-gpios", GPIOD_OUT_LOW);
  933. if (IS_ERR(cs35l34->reset_gpio))
  934. return PTR_ERR(cs35l34->reset_gpio);
  935. gpiod_set_value_cansleep(cs35l34->reset_gpio, 1);
  936. msleep(CS35L34_START_DELAY);
  937. ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_AB, &reg);
  938. devid = (reg & 0xFF) << 12;
  939. ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_CD, &reg);
  940. devid |= (reg & 0xFF) << 4;
  941. ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_E, &reg);
  942. devid |= (reg & 0xF0) >> 4;
  943. if (devid != CS35L34_CHIP_ID) {
  944. dev_err(&i2c_client->dev,
  945. "CS35l34 Device ID (%X). Expected ID %X\n",
  946. devid, CS35L34_CHIP_ID);
  947. ret = -ENODEV;
  948. goto err_regulator;
  949. }
  950. ret = regmap_read(cs35l34->regmap, CS35L34_REV_ID, &reg);
  951. if (ret < 0) {
  952. dev_err(&i2c_client->dev, "Get Revision ID failed\n");
  953. goto err_regulator;
  954. }
  955. dev_info(&i2c_client->dev,
  956. "Cirrus Logic CS35l34 (%x), Revision: %02X\n", devid,
  957. reg & 0xFF);
  958. /* Unmask critical interrupts */
  959. regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_1,
  960. CS35L34_M_CAL_ERR | CS35L34_M_ALIVE_ERR |
  961. CS35L34_M_AMP_SHORT | CS35L34_M_OTW |
  962. CS35L34_M_OTE, 0);
  963. regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_3,
  964. CS35L34_M_BST_HIGH | CS35L34_M_LBST_SHORT, 0);
  965. pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
  966. pm_runtime_use_autosuspend(&i2c_client->dev);
  967. pm_runtime_set_active(&i2c_client->dev);
  968. pm_runtime_enable(&i2c_client->dev);
  969. ret = devm_snd_soc_register_component(&i2c_client->dev,
  970. &soc_component_dev_cs35l34, &cs35l34_dai, 1);
  971. if (ret < 0) {
  972. dev_err(&i2c_client->dev,
  973. "%s: Register component failed\n", __func__);
  974. goto err_regulator;
  975. }
  976. return 0;
  977. err_regulator:
  978. regulator_bulk_disable(cs35l34->num_core_supplies,
  979. cs35l34->core_supplies);
  980. return ret;
  981. }
  982. static int cs35l34_i2c_remove(struct i2c_client *client)
  983. {
  984. struct cs35l34_private *cs35l34 = i2c_get_clientdata(client);
  985. gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
  986. pm_runtime_disable(&client->dev);
  987. regulator_bulk_disable(cs35l34->num_core_supplies,
  988. cs35l34->core_supplies);
  989. return 0;
  990. }
  991. static int __maybe_unused cs35l34_runtime_resume(struct device *dev)
  992. {
  993. struct cs35l34_private *cs35l34 = dev_get_drvdata(dev);
  994. int ret;
  995. ret = regulator_bulk_enable(cs35l34->num_core_supplies,
  996. cs35l34->core_supplies);
  997. if (ret != 0) {
  998. dev_err(dev, "Failed to enable core supplies: %d\n",
  999. ret);
  1000. return ret;
  1001. }
  1002. regcache_cache_only(cs35l34->regmap, false);
  1003. gpiod_set_value_cansleep(cs35l34->reset_gpio, 1);
  1004. msleep(CS35L34_START_DELAY);
  1005. ret = regcache_sync(cs35l34->regmap);
  1006. if (ret != 0) {
  1007. dev_err(dev, "Failed to restore register cache\n");
  1008. goto err;
  1009. }
  1010. return 0;
  1011. err:
  1012. regcache_cache_only(cs35l34->regmap, true);
  1013. regulator_bulk_disable(cs35l34->num_core_supplies,
  1014. cs35l34->core_supplies);
  1015. return ret;
  1016. }
  1017. static int __maybe_unused cs35l34_runtime_suspend(struct device *dev)
  1018. {
  1019. struct cs35l34_private *cs35l34 = dev_get_drvdata(dev);
  1020. regcache_cache_only(cs35l34->regmap, true);
  1021. regcache_mark_dirty(cs35l34->regmap);
  1022. gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
  1023. regulator_bulk_disable(cs35l34->num_core_supplies,
  1024. cs35l34->core_supplies);
  1025. return 0;
  1026. }
  1027. static const struct dev_pm_ops cs35l34_pm_ops = {
  1028. SET_RUNTIME_PM_OPS(cs35l34_runtime_suspend,
  1029. cs35l34_runtime_resume,
  1030. NULL)
  1031. };
  1032. static const struct of_device_id cs35l34_of_match[] = {
  1033. {.compatible = "cirrus,cs35l34"},
  1034. {},
  1035. };
  1036. MODULE_DEVICE_TABLE(of, cs35l34_of_match);
  1037. static const struct i2c_device_id cs35l34_id[] = {
  1038. {"cs35l34", 0},
  1039. {}
  1040. };
  1041. MODULE_DEVICE_TABLE(i2c, cs35l34_id);
  1042. static struct i2c_driver cs35l34_i2c_driver = {
  1043. .driver = {
  1044. .name = "cs35l34",
  1045. .pm = &cs35l34_pm_ops,
  1046. .of_match_table = cs35l34_of_match,
  1047. },
  1048. .id_table = cs35l34_id,
  1049. .probe = cs35l34_i2c_probe,
  1050. .remove = cs35l34_i2c_remove,
  1051. };
  1052. static int __init cs35l34_modinit(void)
  1053. {
  1054. int ret;
  1055. ret = i2c_add_driver(&cs35l34_i2c_driver);
  1056. if (ret != 0) {
  1057. pr_err("Failed to register CS35l34 I2C driver: %d\n", ret);
  1058. return ret;
  1059. }
  1060. return 0;
  1061. }
  1062. module_init(cs35l34_modinit);
  1063. static void __exit cs35l34_exit(void)
  1064. {
  1065. i2c_del_driver(&cs35l34_i2c_driver);
  1066. }
  1067. module_exit(cs35l34_exit);
  1068. MODULE_DESCRIPTION("ASoC CS35l34 driver");
  1069. MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <Paul.Handrigan@cirrus.com>");
  1070. MODULE_LICENSE("GPL");