cs35l33.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cs35l33.c -- CS35L33 ALSA SoC audio driver
  4. *
  5. * Copyright 2016 Cirrus Logic, Inc.
  6. *
  7. * Author: Paul Handrigan <paul.handrigan@cirrus.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/i2c.h>
  15. #include <linux/slab.h>
  16. #include <linux/workqueue.h>
  17. #include <linux/platform_device.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/soc-dapm.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include <linux/gpio.h>
  26. #include <linux/gpio/consumer.h>
  27. #include <sound/cs35l33.h>
  28. #include <linux/pm_runtime.h>
  29. #include <linux/regulator/consumer.h>
  30. #include <linux/regulator/machine.h>
  31. #include <linux/of_gpio.h>
  32. #include <linux/of.h>
  33. #include <linux/of_device.h>
  34. #include <linux/of_irq.h>
  35. #include "cs35l33.h"
  36. #define CS35L33_BOOT_DELAY 50
  37. struct cs35l33_private {
  38. struct snd_soc_component *component;
  39. struct cs35l33_pdata pdata;
  40. struct regmap *regmap;
  41. struct gpio_desc *reset_gpio;
  42. bool amp_cal;
  43. int mclk_int;
  44. struct regulator_bulk_data core_supplies[2];
  45. int num_core_supplies;
  46. bool is_tdm_mode;
  47. bool enable_soft_ramp;
  48. };
  49. static const struct reg_default cs35l33_reg[] = {
  50. {CS35L33_PWRCTL1, 0x85},
  51. {CS35L33_PWRCTL2, 0xFE},
  52. {CS35L33_CLK_CTL, 0x0C},
  53. {CS35L33_BST_PEAK_CTL, 0x90},
  54. {CS35L33_PROTECT_CTL, 0x55},
  55. {CS35L33_BST_CTL1, 0x00},
  56. {CS35L33_BST_CTL2, 0x01},
  57. {CS35L33_ADSP_CTL, 0x00},
  58. {CS35L33_ADC_CTL, 0xC8},
  59. {CS35L33_DAC_CTL, 0x14},
  60. {CS35L33_DIG_VOL_CTL, 0x00},
  61. {CS35L33_CLASSD_CTL, 0x04},
  62. {CS35L33_AMP_CTL, 0x90},
  63. {CS35L33_INT_MASK_1, 0xFF},
  64. {CS35L33_INT_MASK_2, 0xFF},
  65. {CS35L33_DIAG_LOCK, 0x00},
  66. {CS35L33_DIAG_CTRL_1, 0x40},
  67. {CS35L33_DIAG_CTRL_2, 0x00},
  68. {CS35L33_HG_MEMLDO_CTL, 0x62},
  69. {CS35L33_HG_REL_RATE, 0x03},
  70. {CS35L33_LDO_DEL, 0x12},
  71. {CS35L33_HG_HEAD, 0x0A},
  72. {CS35L33_HG_EN, 0x05},
  73. {CS35L33_TX_VMON, 0x00},
  74. {CS35L33_TX_IMON, 0x03},
  75. {CS35L33_TX_VPMON, 0x02},
  76. {CS35L33_TX_VBSTMON, 0x05},
  77. {CS35L33_TX_FLAG, 0x06},
  78. {CS35L33_TX_EN1, 0x00},
  79. {CS35L33_TX_EN2, 0x00},
  80. {CS35L33_TX_EN3, 0x00},
  81. {CS35L33_TX_EN4, 0x00},
  82. {CS35L33_RX_AUD, 0x40},
  83. {CS35L33_RX_SPLY, 0x03},
  84. {CS35L33_RX_ALIVE, 0x04},
  85. {CS35L33_BST_CTL4, 0x63},
  86. };
  87. static const struct reg_sequence cs35l33_patch[] = {
  88. { 0x00, 0x99, 0 },
  89. { 0x59, 0x02, 0 },
  90. { 0x52, 0x30, 0 },
  91. { 0x39, 0x45, 0 },
  92. { 0x57, 0x30, 0 },
  93. { 0x2C, 0x68, 0 },
  94. { 0x00, 0x00, 0 },
  95. };
  96. static bool cs35l33_volatile_register(struct device *dev, unsigned int reg)
  97. {
  98. switch (reg) {
  99. case CS35L33_DEVID_AB:
  100. case CS35L33_DEVID_CD:
  101. case CS35L33_DEVID_E:
  102. case CS35L33_REV_ID:
  103. case CS35L33_INT_STATUS_1:
  104. case CS35L33_INT_STATUS_2:
  105. case CS35L33_HG_STATUS:
  106. return true;
  107. default:
  108. return false;
  109. }
  110. }
  111. static bool cs35l33_writeable_register(struct device *dev, unsigned int reg)
  112. {
  113. switch (reg) {
  114. /* these are read only registers */
  115. case CS35L33_DEVID_AB:
  116. case CS35L33_DEVID_CD:
  117. case CS35L33_DEVID_E:
  118. case CS35L33_REV_ID:
  119. case CS35L33_INT_STATUS_1:
  120. case CS35L33_INT_STATUS_2:
  121. case CS35L33_HG_STATUS:
  122. return false;
  123. default:
  124. return true;
  125. }
  126. }
  127. static bool cs35l33_readable_register(struct device *dev, unsigned int reg)
  128. {
  129. switch (reg) {
  130. case CS35L33_DEVID_AB:
  131. case CS35L33_DEVID_CD:
  132. case CS35L33_DEVID_E:
  133. case CS35L33_REV_ID:
  134. case CS35L33_PWRCTL1:
  135. case CS35L33_PWRCTL2:
  136. case CS35L33_CLK_CTL:
  137. case CS35L33_BST_PEAK_CTL:
  138. case CS35L33_PROTECT_CTL:
  139. case CS35L33_BST_CTL1:
  140. case CS35L33_BST_CTL2:
  141. case CS35L33_ADSP_CTL:
  142. case CS35L33_ADC_CTL:
  143. case CS35L33_DAC_CTL:
  144. case CS35L33_DIG_VOL_CTL:
  145. case CS35L33_CLASSD_CTL:
  146. case CS35L33_AMP_CTL:
  147. case CS35L33_INT_MASK_1:
  148. case CS35L33_INT_MASK_2:
  149. case CS35L33_INT_STATUS_1:
  150. case CS35L33_INT_STATUS_2:
  151. case CS35L33_DIAG_LOCK:
  152. case CS35L33_DIAG_CTRL_1:
  153. case CS35L33_DIAG_CTRL_2:
  154. case CS35L33_HG_MEMLDO_CTL:
  155. case CS35L33_HG_REL_RATE:
  156. case CS35L33_LDO_DEL:
  157. case CS35L33_HG_HEAD:
  158. case CS35L33_HG_EN:
  159. case CS35L33_TX_VMON:
  160. case CS35L33_TX_IMON:
  161. case CS35L33_TX_VPMON:
  162. case CS35L33_TX_VBSTMON:
  163. case CS35L33_TX_FLAG:
  164. case CS35L33_TX_EN1:
  165. case CS35L33_TX_EN2:
  166. case CS35L33_TX_EN3:
  167. case CS35L33_TX_EN4:
  168. case CS35L33_RX_AUD:
  169. case CS35L33_RX_SPLY:
  170. case CS35L33_RX_ALIVE:
  171. case CS35L33_BST_CTL4:
  172. return true;
  173. default:
  174. return false;
  175. }
  176. }
  177. static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 100, 0);
  178. static DECLARE_TLV_DB_SCALE(dac_tlv, -10200, 50, 0);
  179. static const struct snd_kcontrol_new cs35l33_snd_controls[] = {
  180. SOC_SINGLE_TLV("SPK Amp Volume", CS35L33_AMP_CTL,
  181. 4, 0x09, 0, classd_ctl_tlv),
  182. SOC_SINGLE_SX_TLV("DAC Volume", CS35L33_DIG_VOL_CTL,
  183. 0, 0x34, 0xE4, dac_tlv),
  184. };
  185. static int cs35l33_spkrdrv_event(struct snd_soc_dapm_widget *w,
  186. struct snd_kcontrol *kcontrol, int event)
  187. {
  188. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  189. struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
  190. switch (event) {
  191. case SND_SOC_DAPM_POST_PMU:
  192. if (!priv->amp_cal) {
  193. usleep_range(8000, 9000);
  194. priv->amp_cal = true;
  195. regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
  196. CS35L33_AMP_CAL, 0);
  197. dev_dbg(component->dev, "Amp calibration done\n");
  198. }
  199. dev_dbg(component->dev, "Amp turned on\n");
  200. break;
  201. case SND_SOC_DAPM_POST_PMD:
  202. dev_dbg(component->dev, "Amp turned off\n");
  203. break;
  204. default:
  205. dev_err(component->dev, "Invalid event = 0x%x\n", event);
  206. break;
  207. }
  208. return 0;
  209. }
  210. static int cs35l33_sdin_event(struct snd_soc_dapm_widget *w,
  211. struct snd_kcontrol *kcontrol, int event)
  212. {
  213. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  214. struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
  215. unsigned int val;
  216. switch (event) {
  217. case SND_SOC_DAPM_PRE_PMU:
  218. regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
  219. CS35L33_PDN_BST, 0);
  220. val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM;
  221. regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
  222. CS35L33_PDN_TDM, val);
  223. dev_dbg(component->dev, "BST turned on\n");
  224. break;
  225. case SND_SOC_DAPM_POST_PMU:
  226. dev_dbg(component->dev, "SDIN turned on\n");
  227. if (!priv->amp_cal) {
  228. regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
  229. CS35L33_AMP_CAL, CS35L33_AMP_CAL);
  230. dev_dbg(component->dev, "Amp calibration started\n");
  231. usleep_range(10000, 11000);
  232. }
  233. break;
  234. case SND_SOC_DAPM_POST_PMD:
  235. regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
  236. CS35L33_PDN_TDM, CS35L33_PDN_TDM);
  237. usleep_range(4000, 4100);
  238. regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
  239. CS35L33_PDN_BST, CS35L33_PDN_BST);
  240. dev_dbg(component->dev, "BST and SDIN turned off\n");
  241. break;
  242. default:
  243. dev_err(component->dev, "Invalid event = 0x%x\n", event);
  244. }
  245. return 0;
  246. }
  247. static int cs35l33_sdout_event(struct snd_soc_dapm_widget *w,
  248. struct snd_kcontrol *kcontrol, int event)
  249. {
  250. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  251. struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
  252. unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
  253. unsigned int mask2 = CS35L33_SDOUT_3ST_TDM;
  254. unsigned int val, val2;
  255. switch (event) {
  256. case SND_SOC_DAPM_PRE_PMU:
  257. if (priv->is_tdm_mode) {
  258. /* set sdout_3st_i2s and reset pdn_tdm */
  259. val = CS35L33_SDOUT_3ST_I2S;
  260. /* reset sdout_3st_tdm */
  261. val2 = 0;
  262. } else {
  263. /* reset sdout_3st_i2s and set pdn_tdm */
  264. val = CS35L33_PDN_TDM;
  265. /* set sdout_3st_tdm */
  266. val2 = CS35L33_SDOUT_3ST_TDM;
  267. }
  268. dev_dbg(component->dev, "SDOUT turned on\n");
  269. break;
  270. case SND_SOC_DAPM_PRE_PMD:
  271. val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
  272. val2 = CS35L33_SDOUT_3ST_TDM;
  273. dev_dbg(component->dev, "SDOUT turned off\n");
  274. break;
  275. default:
  276. dev_err(component->dev, "Invalid event = 0x%x\n", event);
  277. return 0;
  278. }
  279. regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
  280. mask, val);
  281. regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
  282. mask2, val2);
  283. return 0;
  284. }
  285. static const struct snd_soc_dapm_widget cs35l33_dapm_widgets[] = {
  286. SND_SOC_DAPM_OUTPUT("SPK"),
  287. SND_SOC_DAPM_OUT_DRV_E("SPKDRV", CS35L33_PWRCTL1, 7, 1, NULL, 0,
  288. cs35l33_spkrdrv_event,
  289. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  290. SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L33_PWRCTL2,
  291. 2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU |
  292. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  293. SND_SOC_DAPM_INPUT("MON"),
  294. SND_SOC_DAPM_ADC("VMON", NULL,
  295. CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1),
  296. SND_SOC_DAPM_ADC("IMON", NULL,
  297. CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1),
  298. SND_SOC_DAPM_ADC("VPMON", NULL,
  299. CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1),
  300. SND_SOC_DAPM_ADC("VBSTMON", NULL,
  301. CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1),
  302. SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0,
  303. cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU |
  304. SND_SOC_DAPM_PRE_PMD),
  305. };
  306. static const struct snd_soc_dapm_route cs35l33_audio_map[] = {
  307. {"SDIN", NULL, "CS35L33 Playback"},
  308. {"SPKDRV", NULL, "SDIN"},
  309. {"SPK", NULL, "SPKDRV"},
  310. {"VMON", NULL, "MON"},
  311. {"IMON", NULL, "MON"},
  312. {"SDOUT", NULL, "VMON"},
  313. {"SDOUT", NULL, "IMON"},
  314. {"CS35L33 Capture", NULL, "SDOUT"},
  315. };
  316. static const struct snd_soc_dapm_route cs35l33_vphg_auto_route[] = {
  317. {"SPKDRV", NULL, "VPMON"},
  318. {"VPMON", NULL, "CS35L33 Playback"},
  319. };
  320. static const struct snd_soc_dapm_route cs35l33_vp_vbst_mon_route[] = {
  321. {"SDOUT", NULL, "VPMON"},
  322. {"VPMON", NULL, "MON"},
  323. {"SDOUT", NULL, "VBSTMON"},
  324. {"VBSTMON", NULL, "MON"},
  325. };
  326. static int cs35l33_set_bias_level(struct snd_soc_component *component,
  327. enum snd_soc_bias_level level)
  328. {
  329. unsigned int val;
  330. struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
  331. switch (level) {
  332. case SND_SOC_BIAS_ON:
  333. break;
  334. case SND_SOC_BIAS_PREPARE:
  335. regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
  336. CS35L33_PDN_ALL, 0);
  337. regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
  338. CS35L33_MCLKDIS, 0);
  339. break;
  340. case SND_SOC_BIAS_STANDBY:
  341. regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
  342. CS35L33_PDN_ALL, CS35L33_PDN_ALL);
  343. regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val);
  344. usleep_range(1000, 1100);
  345. if (val & CS35L33_PDN_DONE)
  346. regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
  347. CS35L33_MCLKDIS, CS35L33_MCLKDIS);
  348. break;
  349. case SND_SOC_BIAS_OFF:
  350. break;
  351. default:
  352. return -EINVAL;
  353. }
  354. return 0;
  355. }
  356. struct cs35l33_mclk_div {
  357. int mclk;
  358. int srate;
  359. u8 adsp_rate;
  360. u8 int_fs_ratio;
  361. };
  362. static const struct cs35l33_mclk_div cs35l33_mclk_coeffs[] = {
  363. /* MCLK, Sample Rate, adsp_rate, int_fs_ratio */
  364. {5644800, 11025, 0x4, CS35L33_INT_FS_RATE},
  365. {5644800, 22050, 0x8, CS35L33_INT_FS_RATE},
  366. {5644800, 44100, 0xC, CS35L33_INT_FS_RATE},
  367. {6000000, 8000, 0x1, 0},
  368. {6000000, 11025, 0x2, 0},
  369. {6000000, 11029, 0x3, 0},
  370. {6000000, 12000, 0x4, 0},
  371. {6000000, 16000, 0x5, 0},
  372. {6000000, 22050, 0x6, 0},
  373. {6000000, 22059, 0x7, 0},
  374. {6000000, 24000, 0x8, 0},
  375. {6000000, 32000, 0x9, 0},
  376. {6000000, 44100, 0xA, 0},
  377. {6000000, 44118, 0xB, 0},
  378. {6000000, 48000, 0xC, 0},
  379. {6144000, 8000, 0x1, CS35L33_INT_FS_RATE},
  380. {6144000, 12000, 0x4, CS35L33_INT_FS_RATE},
  381. {6144000, 16000, 0x5, CS35L33_INT_FS_RATE},
  382. {6144000, 24000, 0x8, CS35L33_INT_FS_RATE},
  383. {6144000, 32000, 0x9, CS35L33_INT_FS_RATE},
  384. {6144000, 48000, 0xC, CS35L33_INT_FS_RATE},
  385. };
  386. static int cs35l33_get_mclk_coeff(int mclk, int srate)
  387. {
  388. int i;
  389. for (i = 0; i < ARRAY_SIZE(cs35l33_mclk_coeffs); i++) {
  390. if (cs35l33_mclk_coeffs[i].mclk == mclk &&
  391. cs35l33_mclk_coeffs[i].srate == srate)
  392. return i;
  393. }
  394. return -EINVAL;
  395. }
  396. static int cs35l33_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  397. {
  398. struct snd_soc_component *component = codec_dai->component;
  399. struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
  400. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  401. case SND_SOC_DAIFMT_CBM_CFM:
  402. regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
  403. CS35L33_MS_MASK, CS35L33_MS_MASK);
  404. dev_dbg(component->dev, "Audio port in master mode\n");
  405. break;
  406. case SND_SOC_DAIFMT_CBS_CFS:
  407. regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
  408. CS35L33_MS_MASK, 0);
  409. dev_dbg(component->dev, "Audio port in slave mode\n");
  410. break;
  411. default:
  412. return -EINVAL;
  413. }
  414. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  415. case SND_SOC_DAIFMT_DSP_A:
  416. /*
  417. * tdm mode in cs35l33 resembles dsp-a mode very
  418. * closely, it is dsp-a with fsync shifted left by half bclk
  419. */
  420. priv->is_tdm_mode = true;
  421. dev_dbg(component->dev, "Audio port in TDM mode\n");
  422. break;
  423. case SND_SOC_DAIFMT_I2S:
  424. priv->is_tdm_mode = false;
  425. dev_dbg(component->dev, "Audio port in I2S mode\n");
  426. break;
  427. default:
  428. return -EINVAL;
  429. }
  430. return 0;
  431. }
  432. static int cs35l33_pcm_hw_params(struct snd_pcm_substream *substream,
  433. struct snd_pcm_hw_params *params,
  434. struct snd_soc_dai *dai)
  435. {
  436. struct snd_soc_component *component = dai->component;
  437. struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
  438. int sample_size = params_width(params);
  439. int coeff = cs35l33_get_mclk_coeff(priv->mclk_int, params_rate(params));
  440. if (coeff < 0)
  441. return coeff;
  442. regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
  443. CS35L33_ADSP_FS | CS35L33_INT_FS_RATE,
  444. cs35l33_mclk_coeffs[coeff].int_fs_ratio
  445. | cs35l33_mclk_coeffs[coeff].adsp_rate);
  446. if (priv->is_tdm_mode) {
  447. sample_size = (sample_size / 8) - 1;
  448. if (sample_size > 2)
  449. sample_size = 2;
  450. regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
  451. CS35L33_AUDIN_RX_DEPTH,
  452. sample_size << CS35L33_AUDIN_RX_DEPTH_SHIFT);
  453. }
  454. dev_dbg(component->dev, "sample rate=%d, bits per sample=%d\n",
  455. params_rate(params), params_width(params));
  456. return 0;
  457. }
  458. static const unsigned int cs35l33_src_rates[] = {
  459. 8000, 11025, 11029, 12000, 16000, 22050,
  460. 22059, 24000, 32000, 44100, 44118, 48000
  461. };
  462. static const struct snd_pcm_hw_constraint_list cs35l33_constraints = {
  463. .count = ARRAY_SIZE(cs35l33_src_rates),
  464. .list = cs35l33_src_rates,
  465. };
  466. static int cs35l33_pcm_startup(struct snd_pcm_substream *substream,
  467. struct snd_soc_dai *dai)
  468. {
  469. snd_pcm_hw_constraint_list(substream->runtime, 0,
  470. SNDRV_PCM_HW_PARAM_RATE,
  471. &cs35l33_constraints);
  472. return 0;
  473. }
  474. static int cs35l33_set_tristate(struct snd_soc_dai *dai, int tristate)
  475. {
  476. struct snd_soc_component *component = dai->component;
  477. struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
  478. if (tristate) {
  479. regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
  480. CS35L33_SDOUT_3ST_I2S, CS35L33_SDOUT_3ST_I2S);
  481. regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
  482. CS35L33_SDOUT_3ST_TDM, CS35L33_SDOUT_3ST_TDM);
  483. } else {
  484. regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
  485. CS35L33_SDOUT_3ST_I2S, 0);
  486. regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
  487. CS35L33_SDOUT_3ST_TDM, 0);
  488. }
  489. return 0;
  490. }
  491. static int cs35l33_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  492. unsigned int rx_mask, int slots, int slot_width)
  493. {
  494. struct snd_soc_component *component = dai->component;
  495. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  496. struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
  497. unsigned int reg, bit_pos, i;
  498. int slot, slot_num;
  499. if (slot_width != 8)
  500. return -EINVAL;
  501. /* scan rx_mask for aud slot */
  502. slot = ffs(rx_mask) - 1;
  503. if (slot >= 0) {
  504. regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
  505. CS35L33_X_LOC, slot);
  506. dev_dbg(component->dev, "Audio starts from slots %d", slot);
  507. }
  508. /*
  509. * scan tx_mask: vmon(2 slots); imon (2 slots);
  510. * vpmon (1 slot) vbstmon (1 slot)
  511. */
  512. slot = ffs(tx_mask) - 1;
  513. slot_num = 0;
  514. for (i = 0; i < 2 ; i++) {
  515. /* disable vpmon/vbstmon: enable later if set in tx_mask */
  516. regmap_update_bits(priv->regmap, CS35L33_TX_VPMON + i,
  517. CS35L33_X_STATE | CS35L33_X_LOC, CS35L33_X_STATE
  518. | CS35L33_X_LOC);
  519. }
  520. /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/
  521. snd_soc_dapm_del_routes(dapm, cs35l33_vp_vbst_mon_route,
  522. ARRAY_SIZE(cs35l33_vp_vbst_mon_route));
  523. while (slot >= 0) {
  524. /* configure VMON_TX_LOC */
  525. if (slot_num == 0) {
  526. regmap_update_bits(priv->regmap, CS35L33_TX_VMON,
  527. CS35L33_X_STATE | CS35L33_X_LOC, slot);
  528. dev_dbg(component->dev, "VMON enabled in slots %d-%d",
  529. slot, slot + 1);
  530. }
  531. /* configure IMON_TX_LOC */
  532. if (slot_num == 3) {
  533. regmap_update_bits(priv->regmap, CS35L33_TX_IMON,
  534. CS35L33_X_STATE | CS35L33_X_LOC, slot);
  535. dev_dbg(component->dev, "IMON enabled in slots %d-%d",
  536. slot, slot + 1);
  537. }
  538. /* configure VPMON_TX_LOC */
  539. if (slot_num == 4) {
  540. regmap_update_bits(priv->regmap, CS35L33_TX_VPMON,
  541. CS35L33_X_STATE | CS35L33_X_LOC, slot);
  542. snd_soc_dapm_add_routes(dapm,
  543. &cs35l33_vp_vbst_mon_route[0], 2);
  544. dev_dbg(component->dev, "VPMON enabled in slots %d", slot);
  545. }
  546. /* configure VBSTMON_TX_LOC */
  547. if (slot_num == 5) {
  548. regmap_update_bits(priv->regmap, CS35L33_TX_VBSTMON,
  549. CS35L33_X_STATE | CS35L33_X_LOC, slot);
  550. snd_soc_dapm_add_routes(dapm,
  551. &cs35l33_vp_vbst_mon_route[2], 2);
  552. dev_dbg(component->dev,
  553. "VBSTMON enabled in slots %d", slot);
  554. }
  555. /* Enable the relevant tx slot */
  556. reg = CS35L33_TX_EN4 - (slot/8);
  557. bit_pos = slot - ((slot / 8) * (8));
  558. regmap_update_bits(priv->regmap, reg,
  559. 1 << bit_pos, 1 << bit_pos);
  560. tx_mask &= ~(1 << slot);
  561. slot = ffs(tx_mask) - 1;
  562. slot_num++;
  563. }
  564. return 0;
  565. }
  566. static int cs35l33_component_set_sysclk(struct snd_soc_component *component,
  567. int clk_id, int source, unsigned int freq, int dir)
  568. {
  569. struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
  570. switch (freq) {
  571. case CS35L33_MCLK_5644:
  572. case CS35L33_MCLK_6:
  573. case CS35L33_MCLK_6144:
  574. regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
  575. CS35L33_MCLKDIV2, 0);
  576. cs35l33->mclk_int = freq;
  577. break;
  578. case CS35L33_MCLK_11289:
  579. case CS35L33_MCLK_12:
  580. case CS35L33_MCLK_12288:
  581. regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
  582. CS35L33_MCLKDIV2, CS35L33_MCLKDIV2);
  583. cs35l33->mclk_int = freq/2;
  584. break;
  585. default:
  586. cs35l33->mclk_int = 0;
  587. return -EINVAL;
  588. }
  589. dev_dbg(component->dev, "external mclk freq=%d, internal mclk freq=%d\n",
  590. freq, cs35l33->mclk_int);
  591. return 0;
  592. }
  593. static const struct snd_soc_dai_ops cs35l33_ops = {
  594. .startup = cs35l33_pcm_startup,
  595. .set_tristate = cs35l33_set_tristate,
  596. .set_fmt = cs35l33_set_dai_fmt,
  597. .hw_params = cs35l33_pcm_hw_params,
  598. .set_tdm_slot = cs35l33_set_tdm_slot,
  599. };
  600. static struct snd_soc_dai_driver cs35l33_dai = {
  601. .name = "cs35l33-dai",
  602. .id = 0,
  603. .playback = {
  604. .stream_name = "CS35L33 Playback",
  605. .channels_min = 1,
  606. .channels_max = 1,
  607. .rates = CS35L33_RATES,
  608. .formats = CS35L33_FORMATS,
  609. },
  610. .capture = {
  611. .stream_name = "CS35L33 Capture",
  612. .channels_min = 2,
  613. .channels_max = 2,
  614. .rates = CS35L33_RATES,
  615. .formats = CS35L33_FORMATS,
  616. },
  617. .ops = &cs35l33_ops,
  618. .symmetric_rates = 1,
  619. };
  620. static int cs35l33_set_hg_data(struct snd_soc_component *component,
  621. struct cs35l33_pdata *pdata)
  622. {
  623. struct cs35l33_hg *hg_config = &pdata->hg_config;
  624. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  625. struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
  626. if (hg_config->enable_hg_algo) {
  627. regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
  628. CS35L33_MEM_DEPTH_MASK,
  629. hg_config->mem_depth << CS35L33_MEM_DEPTH_SHIFT);
  630. regmap_write(priv->regmap, CS35L33_HG_REL_RATE,
  631. hg_config->release_rate);
  632. regmap_update_bits(priv->regmap, CS35L33_HG_HEAD,
  633. CS35L33_HD_RM_MASK,
  634. hg_config->hd_rm << CS35L33_HD_RM_SHIFT);
  635. regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
  636. CS35L33_LDO_THLD_MASK,
  637. hg_config->ldo_thld << CS35L33_LDO_THLD_SHIFT);
  638. regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
  639. CS35L33_LDO_DISABLE_MASK,
  640. hg_config->ldo_path_disable <<
  641. CS35L33_LDO_DISABLE_SHIFT);
  642. regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
  643. CS35L33_LDO_ENTRY_DELAY_MASK,
  644. hg_config->ldo_entry_delay <<
  645. CS35L33_LDO_ENTRY_DELAY_SHIFT);
  646. if (hg_config->vp_hg_auto) {
  647. regmap_update_bits(priv->regmap, CS35L33_HG_EN,
  648. CS35L33_VP_HG_AUTO_MASK,
  649. CS35L33_VP_HG_AUTO_MASK);
  650. snd_soc_dapm_add_routes(dapm, cs35l33_vphg_auto_route,
  651. ARRAY_SIZE(cs35l33_vphg_auto_route));
  652. }
  653. regmap_update_bits(priv->regmap, CS35L33_HG_EN,
  654. CS35L33_VP_HG_MASK,
  655. hg_config->vp_hg << CS35L33_VP_HG_SHIFT);
  656. regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
  657. CS35L33_VP_HG_RATE_MASK,
  658. hg_config->vp_hg_rate << CS35L33_VP_HG_RATE_SHIFT);
  659. regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
  660. CS35L33_VP_HG_VA_MASK,
  661. hg_config->vp_hg_va << CS35L33_VP_HG_VA_SHIFT);
  662. regmap_update_bits(priv->regmap, CS35L33_HG_EN,
  663. CS35L33_CLASS_HG_EN_MASK, CS35L33_CLASS_HG_EN_MASK);
  664. }
  665. return 0;
  666. }
  667. static int cs35l33_set_bst_ipk(struct snd_soc_component *component, unsigned int bst)
  668. {
  669. struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
  670. int ret = 0, steps = 0;
  671. /* Boost current in uA */
  672. if (bst > 3600000 || bst < 1850000) {
  673. dev_err(component->dev, "Invalid boost current %d\n", bst);
  674. ret = -EINVAL;
  675. goto err;
  676. }
  677. if (bst % 15625) {
  678. dev_err(component->dev, "Current not a multiple of 15625uA (%d)\n",
  679. bst);
  680. ret = -EINVAL;
  681. goto err;
  682. }
  683. while (bst > 1850000) {
  684. bst -= 15625;
  685. steps++;
  686. }
  687. regmap_write(cs35l33->regmap, CS35L33_BST_PEAK_CTL,
  688. steps+0x70);
  689. err:
  690. return ret;
  691. }
  692. static int cs35l33_probe(struct snd_soc_component *component)
  693. {
  694. struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
  695. cs35l33->component = component;
  696. pm_runtime_get_sync(component->dev);
  697. regmap_update_bits(cs35l33->regmap, CS35L33_PROTECT_CTL,
  698. CS35L33_ALIVE_WD_DIS, 0x8);
  699. regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL2,
  700. CS35L33_ALIVE_WD_DIS2,
  701. CS35L33_ALIVE_WD_DIS2);
  702. /* Set Platform Data */
  703. regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL1,
  704. CS35L33_BST_CTL_MASK, cs35l33->pdata.boost_ctl);
  705. regmap_update_bits(cs35l33->regmap, CS35L33_CLASSD_CTL,
  706. CS35L33_AMP_DRV_SEL_MASK,
  707. cs35l33->pdata.amp_drv_sel << CS35L33_AMP_DRV_SEL_SHIFT);
  708. if (cs35l33->pdata.boost_ipk)
  709. cs35l33_set_bst_ipk(component, cs35l33->pdata.boost_ipk);
  710. if (cs35l33->enable_soft_ramp) {
  711. snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
  712. CS35L33_DIGSFT, CS35L33_DIGSFT);
  713. snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
  714. CS35L33_DSR_RATE, cs35l33->pdata.ramp_rate);
  715. } else {
  716. snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
  717. CS35L33_DIGSFT, 0);
  718. }
  719. /* update IMON scaling rate if different from default of 0x8 */
  720. if (cs35l33->pdata.imon_adc_scale != 0x8)
  721. snd_soc_component_update_bits(component, CS35L33_ADC_CTL,
  722. CS35L33_IMON_SCALE, cs35l33->pdata.imon_adc_scale);
  723. cs35l33_set_hg_data(component, &(cs35l33->pdata));
  724. /*
  725. * unmask important interrupts that causes the chip to enter
  726. * speaker safe mode and hence deserves user attention
  727. */
  728. regmap_update_bits(cs35l33->regmap, CS35L33_INT_MASK_1,
  729. CS35L33_M_OTE | CS35L33_M_OTW | CS35L33_M_AMP_SHORT |
  730. CS35L33_M_CAL_ERR, 0);
  731. pm_runtime_put_sync(component->dev);
  732. return 0;
  733. }
  734. static const struct snd_soc_component_driver soc_component_dev_cs35l33 = {
  735. .probe = cs35l33_probe,
  736. .set_bias_level = cs35l33_set_bias_level,
  737. .set_sysclk = cs35l33_component_set_sysclk,
  738. .controls = cs35l33_snd_controls,
  739. .num_controls = ARRAY_SIZE(cs35l33_snd_controls),
  740. .dapm_widgets = cs35l33_dapm_widgets,
  741. .num_dapm_widgets = ARRAY_SIZE(cs35l33_dapm_widgets),
  742. .dapm_routes = cs35l33_audio_map,
  743. .num_dapm_routes = ARRAY_SIZE(cs35l33_audio_map),
  744. .use_pmdown_time = 1,
  745. .endianness = 1,
  746. .non_legacy_dai_naming = 1,
  747. };
  748. static const struct regmap_config cs35l33_regmap = {
  749. .reg_bits = 8,
  750. .val_bits = 8,
  751. .max_register = CS35L33_MAX_REGISTER,
  752. .reg_defaults = cs35l33_reg,
  753. .num_reg_defaults = ARRAY_SIZE(cs35l33_reg),
  754. .volatile_reg = cs35l33_volatile_register,
  755. .readable_reg = cs35l33_readable_register,
  756. .writeable_reg = cs35l33_writeable_register,
  757. .cache_type = REGCACHE_RBTREE,
  758. .use_single_read = true,
  759. .use_single_write = true,
  760. };
  761. static int __maybe_unused cs35l33_runtime_resume(struct device *dev)
  762. {
  763. struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
  764. int ret;
  765. dev_dbg(dev, "%s\n", __func__);
  766. gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
  767. ret = regulator_bulk_enable(cs35l33->num_core_supplies,
  768. cs35l33->core_supplies);
  769. if (ret != 0) {
  770. dev_err(dev, "Failed to enable core supplies: %d\n", ret);
  771. return ret;
  772. }
  773. regcache_cache_only(cs35l33->regmap, false);
  774. gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
  775. msleep(CS35L33_BOOT_DELAY);
  776. ret = regcache_sync(cs35l33->regmap);
  777. if (ret != 0) {
  778. dev_err(dev, "Failed to restore register cache\n");
  779. goto err;
  780. }
  781. return 0;
  782. err:
  783. regcache_cache_only(cs35l33->regmap, true);
  784. regulator_bulk_disable(cs35l33->num_core_supplies,
  785. cs35l33->core_supplies);
  786. return ret;
  787. }
  788. static int __maybe_unused cs35l33_runtime_suspend(struct device *dev)
  789. {
  790. struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
  791. dev_dbg(dev, "%s\n", __func__);
  792. /* redo the calibration in next power up */
  793. cs35l33->amp_cal = false;
  794. regcache_cache_only(cs35l33->regmap, true);
  795. regcache_mark_dirty(cs35l33->regmap);
  796. regulator_bulk_disable(cs35l33->num_core_supplies,
  797. cs35l33->core_supplies);
  798. return 0;
  799. }
  800. static const struct dev_pm_ops cs35l33_pm_ops = {
  801. SET_RUNTIME_PM_OPS(cs35l33_runtime_suspend,
  802. cs35l33_runtime_resume,
  803. NULL)
  804. };
  805. static int cs35l33_get_hg_data(const struct device_node *np,
  806. struct cs35l33_pdata *pdata)
  807. {
  808. struct device_node *hg;
  809. struct cs35l33_hg *hg_config = &pdata->hg_config;
  810. u32 val32;
  811. hg = of_get_child_by_name(np, "cirrus,hg-algo");
  812. hg_config->enable_hg_algo = hg ? true : false;
  813. if (hg_config->enable_hg_algo) {
  814. if (of_property_read_u32(hg, "cirrus,mem-depth", &val32) >= 0)
  815. hg_config->mem_depth = val32;
  816. if (of_property_read_u32(hg, "cirrus,release-rate",
  817. &val32) >= 0)
  818. hg_config->release_rate = val32;
  819. if (of_property_read_u32(hg, "cirrus,ldo-thld", &val32) >= 0)
  820. hg_config->ldo_thld = val32;
  821. if (of_property_read_u32(hg, "cirrus,ldo-path-disable",
  822. &val32) >= 0)
  823. hg_config->ldo_path_disable = val32;
  824. if (of_property_read_u32(hg, "cirrus,ldo-entry-delay",
  825. &val32) >= 0)
  826. hg_config->ldo_entry_delay = val32;
  827. hg_config->vp_hg_auto = of_property_read_bool(hg,
  828. "cirrus,vp-hg-auto");
  829. if (of_property_read_u32(hg, "cirrus,vp-hg", &val32) >= 0)
  830. hg_config->vp_hg = val32;
  831. if (of_property_read_u32(hg, "cirrus,vp-hg-rate", &val32) >= 0)
  832. hg_config->vp_hg_rate = val32;
  833. if (of_property_read_u32(hg, "cirrus,vp-hg-va", &val32) >= 0)
  834. hg_config->vp_hg_va = val32;
  835. }
  836. of_node_put(hg);
  837. return 0;
  838. }
  839. static irqreturn_t cs35l33_irq_thread(int irq, void *data)
  840. {
  841. struct cs35l33_private *cs35l33 = data;
  842. struct snd_soc_component *component = cs35l33->component;
  843. unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2;
  844. regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2,
  845. &sticky_val2);
  846. regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
  847. &sticky_val1);
  848. regmap_read(cs35l33->regmap, CS35L33_INT_MASK_2, &mask2);
  849. regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1);
  850. /* Check to see if the unmasked bits are active,
  851. * if not then exit.
  852. */
  853. if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2))
  854. return IRQ_NONE;
  855. regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
  856. &current_val);
  857. /* handle the interrupts */
  858. if (sticky_val1 & CS35L33_AMP_SHORT) {
  859. dev_crit(component->dev, "Amp short error\n");
  860. if (!(current_val & CS35L33_AMP_SHORT)) {
  861. dev_dbg(component->dev,
  862. "Amp short error release\n");
  863. regmap_update_bits(cs35l33->regmap,
  864. CS35L33_AMP_CTL,
  865. CS35L33_AMP_SHORT_RLS, 0);
  866. regmap_update_bits(cs35l33->regmap,
  867. CS35L33_AMP_CTL,
  868. CS35L33_AMP_SHORT_RLS,
  869. CS35L33_AMP_SHORT_RLS);
  870. regmap_update_bits(cs35l33->regmap,
  871. CS35L33_AMP_CTL, CS35L33_AMP_SHORT_RLS,
  872. 0);
  873. }
  874. }
  875. if (sticky_val1 & CS35L33_CAL_ERR) {
  876. dev_err(component->dev, "Cal error\n");
  877. /* redo the calibration in next power up */
  878. cs35l33->amp_cal = false;
  879. if (!(current_val & CS35L33_CAL_ERR)) {
  880. dev_dbg(component->dev, "Cal error release\n");
  881. regmap_update_bits(cs35l33->regmap,
  882. CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
  883. 0);
  884. regmap_update_bits(cs35l33->regmap,
  885. CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
  886. CS35L33_CAL_ERR_RLS);
  887. regmap_update_bits(cs35l33->regmap,
  888. CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
  889. 0);
  890. }
  891. }
  892. if (sticky_val1 & CS35L33_OTE) {
  893. dev_crit(component->dev, "Over temperature error\n");
  894. if (!(current_val & CS35L33_OTE)) {
  895. dev_dbg(component->dev,
  896. "Over temperature error release\n");
  897. regmap_update_bits(cs35l33->regmap,
  898. CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
  899. regmap_update_bits(cs35l33->regmap,
  900. CS35L33_AMP_CTL, CS35L33_OTE_RLS,
  901. CS35L33_OTE_RLS);
  902. regmap_update_bits(cs35l33->regmap,
  903. CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
  904. }
  905. }
  906. if (sticky_val1 & CS35L33_OTW) {
  907. dev_err(component->dev, "Over temperature warning\n");
  908. if (!(current_val & CS35L33_OTW)) {
  909. dev_dbg(component->dev,
  910. "Over temperature warning release\n");
  911. regmap_update_bits(cs35l33->regmap,
  912. CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
  913. regmap_update_bits(cs35l33->regmap,
  914. CS35L33_AMP_CTL, CS35L33_OTW_RLS,
  915. CS35L33_OTW_RLS);
  916. regmap_update_bits(cs35l33->regmap,
  917. CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
  918. }
  919. }
  920. if (CS35L33_ALIVE_ERR & sticky_val1)
  921. dev_err(component->dev, "ERROR: ADSPCLK Interrupt\n");
  922. if (CS35L33_MCLK_ERR & sticky_val1)
  923. dev_err(component->dev, "ERROR: MCLK Interrupt\n");
  924. if (CS35L33_VMON_OVFL & sticky_val2)
  925. dev_err(component->dev,
  926. "ERROR: VMON Overflow Interrupt\n");
  927. if (CS35L33_IMON_OVFL & sticky_val2)
  928. dev_err(component->dev,
  929. "ERROR: IMON Overflow Interrupt\n");
  930. if (CS35L33_VPMON_OVFL & sticky_val2)
  931. dev_err(component->dev,
  932. "ERROR: VPMON Overflow Interrupt\n");
  933. return IRQ_HANDLED;
  934. }
  935. static const char * const cs35l33_core_supplies[] = {
  936. "VA",
  937. "VP",
  938. };
  939. static int cs35l33_of_get_pdata(struct device *dev,
  940. struct cs35l33_private *cs35l33)
  941. {
  942. struct device_node *np = dev->of_node;
  943. struct cs35l33_pdata *pdata = &cs35l33->pdata;
  944. u32 val32;
  945. if (!np)
  946. return 0;
  947. if (of_property_read_u32(np, "cirrus,boost-ctl", &val32) >= 0) {
  948. pdata->boost_ctl = val32;
  949. pdata->amp_drv_sel = 1;
  950. }
  951. if (of_property_read_u32(np, "cirrus,ramp-rate", &val32) >= 0) {
  952. pdata->ramp_rate = val32;
  953. cs35l33->enable_soft_ramp = true;
  954. }
  955. if (of_property_read_u32(np, "cirrus,boost-ipk", &val32) >= 0)
  956. pdata->boost_ipk = val32;
  957. if (of_property_read_u32(np, "cirrus,imon-adc-scale", &val32) >= 0) {
  958. if ((val32 == 0x0) || (val32 == 0x7) || (val32 == 0x6))
  959. pdata->imon_adc_scale = val32;
  960. else
  961. /* use default value */
  962. pdata->imon_adc_scale = 0x8;
  963. } else {
  964. /* use default value */
  965. pdata->imon_adc_scale = 0x8;
  966. }
  967. cs35l33_get_hg_data(np, pdata);
  968. return 0;
  969. }
  970. static int cs35l33_i2c_probe(struct i2c_client *i2c_client,
  971. const struct i2c_device_id *id)
  972. {
  973. struct cs35l33_private *cs35l33;
  974. struct cs35l33_pdata *pdata = dev_get_platdata(&i2c_client->dev);
  975. int ret, devid, i;
  976. unsigned int reg;
  977. cs35l33 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l33_private),
  978. GFP_KERNEL);
  979. if (!cs35l33)
  980. return -ENOMEM;
  981. i2c_set_clientdata(i2c_client, cs35l33);
  982. cs35l33->regmap = devm_regmap_init_i2c(i2c_client, &cs35l33_regmap);
  983. if (IS_ERR(cs35l33->regmap)) {
  984. ret = PTR_ERR(cs35l33->regmap);
  985. dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
  986. return ret;
  987. }
  988. regcache_cache_only(cs35l33->regmap, true);
  989. for (i = 0; i < ARRAY_SIZE(cs35l33_core_supplies); i++)
  990. cs35l33->core_supplies[i].supply
  991. = cs35l33_core_supplies[i];
  992. cs35l33->num_core_supplies = ARRAY_SIZE(cs35l33_core_supplies);
  993. ret = devm_regulator_bulk_get(&i2c_client->dev,
  994. cs35l33->num_core_supplies,
  995. cs35l33->core_supplies);
  996. if (ret != 0) {
  997. dev_err(&i2c_client->dev,
  998. "Failed to request core supplies: %d\n",
  999. ret);
  1000. return ret;
  1001. }
  1002. if (pdata) {
  1003. cs35l33->pdata = *pdata;
  1004. } else {
  1005. cs35l33_of_get_pdata(&i2c_client->dev, cs35l33);
  1006. pdata = &cs35l33->pdata;
  1007. }
  1008. ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
  1009. cs35l33_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
  1010. "cs35l33", cs35l33);
  1011. if (ret != 0)
  1012. dev_warn(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
  1013. /* We could issue !RST or skip it based on AMP topology */
  1014. cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
  1015. "reset-gpios", GPIOD_OUT_HIGH);
  1016. if (IS_ERR(cs35l33->reset_gpio)) {
  1017. dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n",
  1018. __func__);
  1019. return PTR_ERR(cs35l33->reset_gpio);
  1020. }
  1021. ret = regulator_bulk_enable(cs35l33->num_core_supplies,
  1022. cs35l33->core_supplies);
  1023. if (ret != 0) {
  1024. dev_err(&i2c_client->dev,
  1025. "Failed to enable core supplies: %d\n",
  1026. ret);
  1027. return ret;
  1028. }
  1029. gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
  1030. msleep(CS35L33_BOOT_DELAY);
  1031. regcache_cache_only(cs35l33->regmap, false);
  1032. /* initialize codec */
  1033. ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_AB, &reg);
  1034. devid = (reg & 0xFF) << 12;
  1035. ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_CD, &reg);
  1036. devid |= (reg & 0xFF) << 4;
  1037. ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_E, &reg);
  1038. devid |= (reg & 0xF0) >> 4;
  1039. if (devid != CS35L33_CHIP_ID) {
  1040. dev_err(&i2c_client->dev,
  1041. "CS35L33 Device ID (%X). Expected ID %X\n",
  1042. devid, CS35L33_CHIP_ID);
  1043. ret = -EINVAL;
  1044. goto err_enable;
  1045. }
  1046. ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, &reg);
  1047. if (ret < 0) {
  1048. dev_err(&i2c_client->dev, "Get Revision ID failed\n");
  1049. goto err_enable;
  1050. }
  1051. dev_info(&i2c_client->dev,
  1052. "Cirrus Logic CS35L33, Revision: %02X\n", reg & 0xFF);
  1053. ret = regmap_register_patch(cs35l33->regmap,
  1054. cs35l33_patch, ARRAY_SIZE(cs35l33_patch));
  1055. if (ret < 0) {
  1056. dev_err(&i2c_client->dev,
  1057. "Error in applying regmap patch: %d\n", ret);
  1058. goto err_enable;
  1059. }
  1060. /* disable mclk and tdm */
  1061. regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
  1062. CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM,
  1063. CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM);
  1064. pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
  1065. pm_runtime_use_autosuspend(&i2c_client->dev);
  1066. pm_runtime_set_active(&i2c_client->dev);
  1067. pm_runtime_enable(&i2c_client->dev);
  1068. ret = devm_snd_soc_register_component(&i2c_client->dev,
  1069. &soc_component_dev_cs35l33, &cs35l33_dai, 1);
  1070. if (ret < 0) {
  1071. dev_err(&i2c_client->dev, "%s: Register component failed\n",
  1072. __func__);
  1073. goto err_enable;
  1074. }
  1075. return 0;
  1076. err_enable:
  1077. regulator_bulk_disable(cs35l33->num_core_supplies,
  1078. cs35l33->core_supplies);
  1079. return ret;
  1080. }
  1081. static int cs35l33_i2c_remove(struct i2c_client *client)
  1082. {
  1083. struct cs35l33_private *cs35l33 = i2c_get_clientdata(client);
  1084. gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
  1085. pm_runtime_disable(&client->dev);
  1086. regulator_bulk_disable(cs35l33->num_core_supplies,
  1087. cs35l33->core_supplies);
  1088. return 0;
  1089. }
  1090. static const struct of_device_id cs35l33_of_match[] = {
  1091. { .compatible = "cirrus,cs35l33", },
  1092. {},
  1093. };
  1094. MODULE_DEVICE_TABLE(of, cs35l33_of_match);
  1095. static const struct i2c_device_id cs35l33_id[] = {
  1096. {"cs35l33", 0},
  1097. {}
  1098. };
  1099. MODULE_DEVICE_TABLE(i2c, cs35l33_id);
  1100. static struct i2c_driver cs35l33_i2c_driver = {
  1101. .driver = {
  1102. .name = "cs35l33",
  1103. .pm = &cs35l33_pm_ops,
  1104. .of_match_table = cs35l33_of_match,
  1105. },
  1106. .id_table = cs35l33_id,
  1107. .probe = cs35l33_i2c_probe,
  1108. .remove = cs35l33_i2c_remove,
  1109. };
  1110. module_i2c_driver(cs35l33_i2c_driver);
  1111. MODULE_DESCRIPTION("ASoC CS35L33 driver");
  1112. MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
  1113. MODULE_LICENSE("GPL");