cs35l32.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cs35l32.c -- CS35L32 ALSA SoC audio driver
  4. *
  5. * Copyright 2014 CirrusLogic, Inc.
  6. *
  7. * Author: Brian Austin <brian.austin@cirrus.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/i2c.h>
  15. #include <linux/gpio.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/gpio/consumer.h>
  21. #include <linux/of_device.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include <dt-bindings/sound/cs35l32.h>
  30. #include "cs35l32.h"
  31. #define CS35L32_NUM_SUPPLIES 2
  32. static const char *const cs35l32_supply_names[CS35L32_NUM_SUPPLIES] = {
  33. "VA",
  34. "VP",
  35. };
  36. struct cs35l32_private {
  37. struct regmap *regmap;
  38. struct snd_soc_component *component;
  39. struct regulator_bulk_data supplies[CS35L32_NUM_SUPPLIES];
  40. struct cs35l32_platform_data pdata;
  41. struct gpio_desc *reset_gpio;
  42. };
  43. static const struct reg_default cs35l32_reg_defaults[] = {
  44. { 0x06, 0x04 }, /* Power Ctl 1 */
  45. { 0x07, 0xE8 }, /* Power Ctl 2 */
  46. { 0x08, 0x40 }, /* Clock Ctl */
  47. { 0x09, 0x20 }, /* Low Battery Threshold */
  48. { 0x0A, 0x00 }, /* Voltage Monitor [RO] */
  49. { 0x0B, 0x40 }, /* Conv Peak Curr Protection CTL */
  50. { 0x0C, 0x07 }, /* IMON Scaling */
  51. { 0x0D, 0x03 }, /* Audio/LED Pwr Manager */
  52. { 0x0F, 0x20 }, /* Serial Port Control */
  53. { 0x10, 0x14 }, /* Class D Amp CTL */
  54. { 0x11, 0x00 }, /* Protection Release CTL */
  55. { 0x12, 0xFF }, /* Interrupt Mask 1 */
  56. { 0x13, 0xFF }, /* Interrupt Mask 2 */
  57. { 0x14, 0xFF }, /* Interrupt Mask 3 */
  58. { 0x19, 0x00 }, /* LED Flash Mode Current */
  59. { 0x1A, 0x00 }, /* LED Movie Mode Current */
  60. { 0x1B, 0x20 }, /* LED Flash Timer */
  61. { 0x1C, 0x00 }, /* LED Flash Inhibit Current */
  62. };
  63. static bool cs35l32_readable_register(struct device *dev, unsigned int reg)
  64. {
  65. switch (reg) {
  66. case CS35L32_DEVID_AB ... CS35L32_AUDIO_LED_MNGR:
  67. case CS35L32_ADSP_CTL ... CS35L32_FLASH_INHIBIT:
  68. return true;
  69. default:
  70. return false;
  71. }
  72. }
  73. static bool cs35l32_volatile_register(struct device *dev, unsigned int reg)
  74. {
  75. switch (reg) {
  76. case CS35L32_DEVID_AB ... CS35L32_REV_ID:
  77. case CS35L32_INT_STATUS_1 ... CS35L32_LED_STATUS:
  78. return true;
  79. default:
  80. return false;
  81. }
  82. }
  83. static bool cs35l32_precious_register(struct device *dev, unsigned int reg)
  84. {
  85. switch (reg) {
  86. case CS35L32_INT_STATUS_1 ... CS35L32_LED_STATUS:
  87. return true;
  88. default:
  89. return false;
  90. }
  91. }
  92. static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 300, 0);
  93. static const struct snd_kcontrol_new imon_ctl =
  94. SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 6, 1, 1);
  95. static const struct snd_kcontrol_new vmon_ctl =
  96. SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 7, 1, 1);
  97. static const struct snd_kcontrol_new vpmon_ctl =
  98. SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 5, 1, 1);
  99. static const struct snd_kcontrol_new cs35l32_snd_controls[] = {
  100. SOC_SINGLE_TLV("Speaker Volume", CS35L32_CLASSD_CTL,
  101. 3, 0x04, 1, classd_ctl_tlv),
  102. SOC_SINGLE("Zero Cross Switch", CS35L32_CLASSD_CTL, 2, 1, 0),
  103. SOC_SINGLE("Gain Manager Switch", CS35L32_AUDIO_LED_MNGR, 3, 1, 0),
  104. };
  105. static const struct snd_soc_dapm_widget cs35l32_dapm_widgets[] = {
  106. SND_SOC_DAPM_SUPPLY("BOOST", CS35L32_PWRCTL1, 2, 1, NULL, 0),
  107. SND_SOC_DAPM_OUT_DRV("Speaker", CS35L32_PWRCTL1, 7, 1, NULL, 0),
  108. SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L32_PWRCTL2, 3, 1),
  109. SND_SOC_DAPM_INPUT("VP"),
  110. SND_SOC_DAPM_INPUT("ISENSE"),
  111. SND_SOC_DAPM_INPUT("VSENSE"),
  112. SND_SOC_DAPM_SWITCH("VMON ADC", CS35L32_PWRCTL2, 7, 1, &vmon_ctl),
  113. SND_SOC_DAPM_SWITCH("IMON ADC", CS35L32_PWRCTL2, 6, 1, &imon_ctl),
  114. SND_SOC_DAPM_SWITCH("VPMON ADC", CS35L32_PWRCTL2, 5, 1, &vpmon_ctl),
  115. };
  116. static const struct snd_soc_dapm_route cs35l32_audio_map[] = {
  117. {"Speaker", NULL, "BOOST"},
  118. {"VMON ADC", NULL, "VSENSE"},
  119. {"IMON ADC", NULL, "ISENSE"},
  120. {"VPMON ADC", NULL, "VP"},
  121. {"SDOUT", "Switch", "VMON ADC"},
  122. {"SDOUT", "Switch", "IMON ADC"},
  123. {"SDOUT", "Switch", "VPMON ADC"},
  124. {"Capture", NULL, "SDOUT"},
  125. };
  126. static int cs35l32_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  127. {
  128. struct snd_soc_component *component = codec_dai->component;
  129. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  130. case SND_SOC_DAIFMT_CBM_CFM:
  131. snd_soc_component_update_bits(component, CS35L32_ADSP_CTL,
  132. CS35L32_ADSP_MASTER_MASK,
  133. CS35L32_ADSP_MASTER_MASK);
  134. break;
  135. case SND_SOC_DAIFMT_CBS_CFS:
  136. snd_soc_component_update_bits(component, CS35L32_ADSP_CTL,
  137. CS35L32_ADSP_MASTER_MASK, 0);
  138. break;
  139. default:
  140. return -EINVAL;
  141. }
  142. return 0;
  143. }
  144. static int cs35l32_set_tristate(struct snd_soc_dai *dai, int tristate)
  145. {
  146. struct snd_soc_component *component = dai->component;
  147. return snd_soc_component_update_bits(component, CS35L32_PWRCTL2,
  148. CS35L32_SDOUT_3ST, tristate << 3);
  149. }
  150. static const struct snd_soc_dai_ops cs35l32_ops = {
  151. .set_fmt = cs35l32_set_dai_fmt,
  152. .set_tristate = cs35l32_set_tristate,
  153. };
  154. static struct snd_soc_dai_driver cs35l32_dai[] = {
  155. {
  156. .name = "cs35l32-monitor",
  157. .id = 0,
  158. .capture = {
  159. .stream_name = "Capture",
  160. .channels_min = 2,
  161. .channels_max = 2,
  162. .rates = CS35L32_RATES,
  163. .formats = CS35L32_FORMATS,
  164. },
  165. .ops = &cs35l32_ops,
  166. .symmetric_rates = 1,
  167. }
  168. };
  169. static int cs35l32_component_set_sysclk(struct snd_soc_component *component,
  170. int clk_id, int source, unsigned int freq, int dir)
  171. {
  172. unsigned int val;
  173. switch (freq) {
  174. case 6000000:
  175. val = CS35L32_MCLK_RATIO;
  176. break;
  177. case 12000000:
  178. val = CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO;
  179. break;
  180. case 6144000:
  181. val = 0;
  182. break;
  183. case 12288000:
  184. val = CS35L32_MCLK_DIV2_MASK;
  185. break;
  186. default:
  187. return -EINVAL;
  188. }
  189. return snd_soc_component_update_bits(component, CS35L32_CLK_CTL,
  190. CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO_MASK, val);
  191. }
  192. static const struct snd_soc_component_driver soc_component_dev_cs35l32 = {
  193. .set_sysclk = cs35l32_component_set_sysclk,
  194. .controls = cs35l32_snd_controls,
  195. .num_controls = ARRAY_SIZE(cs35l32_snd_controls),
  196. .dapm_widgets = cs35l32_dapm_widgets,
  197. .num_dapm_widgets = ARRAY_SIZE(cs35l32_dapm_widgets),
  198. .dapm_routes = cs35l32_audio_map,
  199. .num_dapm_routes = ARRAY_SIZE(cs35l32_audio_map),
  200. .idle_bias_on = 1,
  201. .use_pmdown_time = 1,
  202. .endianness = 1,
  203. .non_legacy_dai_naming = 1,
  204. };
  205. /* Current and threshold powerup sequence Pg37 in datasheet */
  206. static const struct reg_sequence cs35l32_monitor_patch[] = {
  207. { 0x00, 0x99 },
  208. { 0x48, 0x17 },
  209. { 0x49, 0x56 },
  210. { 0x43, 0x01 },
  211. { 0x3B, 0x62 },
  212. { 0x3C, 0x80 },
  213. { 0x00, 0x00 },
  214. };
  215. static const struct regmap_config cs35l32_regmap = {
  216. .reg_bits = 8,
  217. .val_bits = 8,
  218. .max_register = CS35L32_MAX_REGISTER,
  219. .reg_defaults = cs35l32_reg_defaults,
  220. .num_reg_defaults = ARRAY_SIZE(cs35l32_reg_defaults),
  221. .volatile_reg = cs35l32_volatile_register,
  222. .readable_reg = cs35l32_readable_register,
  223. .precious_reg = cs35l32_precious_register,
  224. .cache_type = REGCACHE_RBTREE,
  225. };
  226. static int cs35l32_handle_of_data(struct i2c_client *i2c_client,
  227. struct cs35l32_platform_data *pdata)
  228. {
  229. struct device_node *np = i2c_client->dev.of_node;
  230. unsigned int val;
  231. if (of_property_read_u32(np, "cirrus,sdout-share", &val) >= 0)
  232. pdata->sdout_share = val;
  233. if (of_property_read_u32(np, "cirrus,boost-manager", &val))
  234. val = -1u;
  235. switch (val) {
  236. case CS35L32_BOOST_MGR_AUTO:
  237. case CS35L32_BOOST_MGR_AUTO_AUDIO:
  238. case CS35L32_BOOST_MGR_BYPASS:
  239. case CS35L32_BOOST_MGR_FIXED:
  240. pdata->boost_mng = val;
  241. break;
  242. case -1u:
  243. default:
  244. dev_err(&i2c_client->dev,
  245. "Wrong cirrus,boost-manager DT value %d\n", val);
  246. pdata->boost_mng = CS35L32_BOOST_MGR_BYPASS;
  247. }
  248. if (of_property_read_u32(np, "cirrus,sdout-datacfg", &val))
  249. val = -1u;
  250. switch (val) {
  251. case CS35L32_DATA_CFG_LR_VP:
  252. case CS35L32_DATA_CFG_LR_STAT:
  253. case CS35L32_DATA_CFG_LR:
  254. case CS35L32_DATA_CFG_LR_VPSTAT:
  255. pdata->sdout_datacfg = val;
  256. break;
  257. case -1u:
  258. default:
  259. dev_err(&i2c_client->dev,
  260. "Wrong cirrus,sdout-datacfg DT value %d\n", val);
  261. pdata->sdout_datacfg = CS35L32_DATA_CFG_LR;
  262. }
  263. if (of_property_read_u32(np, "cirrus,battery-threshold", &val))
  264. val = -1u;
  265. switch (val) {
  266. case CS35L32_BATT_THRESH_3_1V:
  267. case CS35L32_BATT_THRESH_3_2V:
  268. case CS35L32_BATT_THRESH_3_3V:
  269. case CS35L32_BATT_THRESH_3_4V:
  270. pdata->batt_thresh = val;
  271. break;
  272. case -1u:
  273. default:
  274. dev_err(&i2c_client->dev,
  275. "Wrong cirrus,battery-threshold DT value %d\n", val);
  276. pdata->batt_thresh = CS35L32_BATT_THRESH_3_3V;
  277. }
  278. if (of_property_read_u32(np, "cirrus,battery-recovery", &val))
  279. val = -1u;
  280. switch (val) {
  281. case CS35L32_BATT_RECOV_3_1V:
  282. case CS35L32_BATT_RECOV_3_2V:
  283. case CS35L32_BATT_RECOV_3_3V:
  284. case CS35L32_BATT_RECOV_3_4V:
  285. case CS35L32_BATT_RECOV_3_5V:
  286. case CS35L32_BATT_RECOV_3_6V:
  287. pdata->batt_recov = val;
  288. break;
  289. case -1u:
  290. default:
  291. dev_err(&i2c_client->dev,
  292. "Wrong cirrus,battery-recovery DT value %d\n", val);
  293. pdata->batt_recov = CS35L32_BATT_RECOV_3_4V;
  294. }
  295. return 0;
  296. }
  297. static int cs35l32_i2c_probe(struct i2c_client *i2c_client,
  298. const struct i2c_device_id *id)
  299. {
  300. struct cs35l32_private *cs35l32;
  301. struct cs35l32_platform_data *pdata =
  302. dev_get_platdata(&i2c_client->dev);
  303. int ret, i;
  304. unsigned int devid = 0;
  305. unsigned int reg;
  306. cs35l32 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l32), GFP_KERNEL);
  307. if (!cs35l32)
  308. return -ENOMEM;
  309. i2c_set_clientdata(i2c_client, cs35l32);
  310. cs35l32->regmap = devm_regmap_init_i2c(i2c_client, &cs35l32_regmap);
  311. if (IS_ERR(cs35l32->regmap)) {
  312. ret = PTR_ERR(cs35l32->regmap);
  313. dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
  314. return ret;
  315. }
  316. if (pdata) {
  317. cs35l32->pdata = *pdata;
  318. } else {
  319. pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
  320. GFP_KERNEL);
  321. if (!pdata)
  322. return -ENOMEM;
  323. if (i2c_client->dev.of_node) {
  324. ret = cs35l32_handle_of_data(i2c_client,
  325. &cs35l32->pdata);
  326. if (ret != 0)
  327. return ret;
  328. }
  329. }
  330. for (i = 0; i < ARRAY_SIZE(cs35l32->supplies); i++)
  331. cs35l32->supplies[i].supply = cs35l32_supply_names[i];
  332. ret = devm_regulator_bulk_get(&i2c_client->dev,
  333. ARRAY_SIZE(cs35l32->supplies),
  334. cs35l32->supplies);
  335. if (ret != 0) {
  336. dev_err(&i2c_client->dev,
  337. "Failed to request supplies: %d\n", ret);
  338. return ret;
  339. }
  340. ret = regulator_bulk_enable(ARRAY_SIZE(cs35l32->supplies),
  341. cs35l32->supplies);
  342. if (ret != 0) {
  343. dev_err(&i2c_client->dev,
  344. "Failed to enable supplies: %d\n", ret);
  345. return ret;
  346. }
  347. /* Reset the Device */
  348. cs35l32->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
  349. "reset", GPIOD_OUT_LOW);
  350. if (IS_ERR(cs35l32->reset_gpio))
  351. return PTR_ERR(cs35l32->reset_gpio);
  352. gpiod_set_value_cansleep(cs35l32->reset_gpio, 1);
  353. /* initialize codec */
  354. ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_AB, &reg);
  355. devid = (reg & 0xFF) << 12;
  356. ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_CD, &reg);
  357. devid |= (reg & 0xFF) << 4;
  358. ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_E, &reg);
  359. devid |= (reg & 0xF0) >> 4;
  360. if (devid != CS35L32_CHIP_ID) {
  361. ret = -ENODEV;
  362. dev_err(&i2c_client->dev,
  363. "CS35L32 Device ID (%X). Expected %X\n",
  364. devid, CS35L32_CHIP_ID);
  365. return ret;
  366. }
  367. ret = regmap_read(cs35l32->regmap, CS35L32_REV_ID, &reg);
  368. if (ret < 0) {
  369. dev_err(&i2c_client->dev, "Get Revision ID failed\n");
  370. return ret;
  371. }
  372. ret = regmap_register_patch(cs35l32->regmap, cs35l32_monitor_patch,
  373. ARRAY_SIZE(cs35l32_monitor_patch));
  374. if (ret < 0) {
  375. dev_err(&i2c_client->dev, "Failed to apply errata patch\n");
  376. return ret;
  377. }
  378. dev_info(&i2c_client->dev,
  379. "Cirrus Logic CS35L32, Revision: %02X\n", reg & 0xFF);
  380. /* Setup VBOOST Management */
  381. if (cs35l32->pdata.boost_mng)
  382. regmap_update_bits(cs35l32->regmap, CS35L32_AUDIO_LED_MNGR,
  383. CS35L32_BOOST_MASK,
  384. cs35l32->pdata.boost_mng);
  385. /* Setup ADSP Format Config */
  386. if (cs35l32->pdata.sdout_share)
  387. regmap_update_bits(cs35l32->regmap, CS35L32_ADSP_CTL,
  388. CS35L32_ADSP_SHARE_MASK,
  389. cs35l32->pdata.sdout_share << 3);
  390. /* Setup ADSP Data Configuration */
  391. if (cs35l32->pdata.sdout_datacfg)
  392. regmap_update_bits(cs35l32->regmap, CS35L32_ADSP_CTL,
  393. CS35L32_ADSP_DATACFG_MASK,
  394. cs35l32->pdata.sdout_datacfg << 4);
  395. /* Setup Low Battery Recovery */
  396. if (cs35l32->pdata.batt_recov)
  397. regmap_update_bits(cs35l32->regmap, CS35L32_BATT_THRESHOLD,
  398. CS35L32_BATT_REC_MASK,
  399. cs35l32->pdata.batt_recov << 1);
  400. /* Setup Low Battery Threshold */
  401. if (cs35l32->pdata.batt_thresh)
  402. regmap_update_bits(cs35l32->regmap, CS35L32_BATT_THRESHOLD,
  403. CS35L32_BATT_THRESH_MASK,
  404. cs35l32->pdata.batt_thresh << 4);
  405. /* Power down the AMP */
  406. regmap_update_bits(cs35l32->regmap, CS35L32_PWRCTL1, CS35L32_PDN_AMP,
  407. CS35L32_PDN_AMP);
  408. /* Clear MCLK Error Bit since we don't have the clock yet */
  409. ret = regmap_read(cs35l32->regmap, CS35L32_INT_STATUS_1, &reg);
  410. ret = devm_snd_soc_register_component(&i2c_client->dev,
  411. &soc_component_dev_cs35l32, cs35l32_dai,
  412. ARRAY_SIZE(cs35l32_dai));
  413. if (ret < 0)
  414. goto err_disable;
  415. return 0;
  416. err_disable:
  417. regulator_bulk_disable(ARRAY_SIZE(cs35l32->supplies),
  418. cs35l32->supplies);
  419. return ret;
  420. }
  421. static int cs35l32_i2c_remove(struct i2c_client *i2c_client)
  422. {
  423. struct cs35l32_private *cs35l32 = i2c_get_clientdata(i2c_client);
  424. /* Hold down reset */
  425. gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
  426. return 0;
  427. }
  428. #ifdef CONFIG_PM
  429. static int cs35l32_runtime_suspend(struct device *dev)
  430. {
  431. struct cs35l32_private *cs35l32 = dev_get_drvdata(dev);
  432. regcache_cache_only(cs35l32->regmap, true);
  433. regcache_mark_dirty(cs35l32->regmap);
  434. /* Hold down reset */
  435. gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
  436. /* remove power */
  437. regulator_bulk_disable(ARRAY_SIZE(cs35l32->supplies),
  438. cs35l32->supplies);
  439. return 0;
  440. }
  441. static int cs35l32_runtime_resume(struct device *dev)
  442. {
  443. struct cs35l32_private *cs35l32 = dev_get_drvdata(dev);
  444. int ret;
  445. /* Enable power */
  446. ret = regulator_bulk_enable(ARRAY_SIZE(cs35l32->supplies),
  447. cs35l32->supplies);
  448. if (ret != 0) {
  449. dev_err(dev, "Failed to enable supplies: %d\n",
  450. ret);
  451. return ret;
  452. }
  453. gpiod_set_value_cansleep(cs35l32->reset_gpio, 1);
  454. regcache_cache_only(cs35l32->regmap, false);
  455. regcache_sync(cs35l32->regmap);
  456. return 0;
  457. }
  458. #endif
  459. static const struct dev_pm_ops cs35l32_runtime_pm = {
  460. SET_RUNTIME_PM_OPS(cs35l32_runtime_suspend, cs35l32_runtime_resume,
  461. NULL)
  462. };
  463. static const struct of_device_id cs35l32_of_match[] = {
  464. { .compatible = "cirrus,cs35l32", },
  465. {},
  466. };
  467. MODULE_DEVICE_TABLE(of, cs35l32_of_match);
  468. static const struct i2c_device_id cs35l32_id[] = {
  469. {"cs35l32", 0},
  470. {}
  471. };
  472. MODULE_DEVICE_TABLE(i2c, cs35l32_id);
  473. static struct i2c_driver cs35l32_i2c_driver = {
  474. .driver = {
  475. .name = "cs35l32",
  476. .pm = &cs35l32_runtime_pm,
  477. .of_match_table = cs35l32_of_match,
  478. },
  479. .id_table = cs35l32_id,
  480. .probe = cs35l32_i2c_probe,
  481. .remove = cs35l32_i2c_remove,
  482. };
  483. module_i2c_driver(cs35l32_i2c_driver);
  484. MODULE_DESCRIPTION("ASoC CS35L32 driver");
  485. MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
  486. MODULE_LICENSE("GPL");