cpcap.c 47 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ALSA SoC CPCAP codec driver
  4. *
  5. * Copyright (C) 2017 - 2018 Sebastian Reichel <sre@kernel.org>
  6. *
  7. * Very loosely based on original driver from Motorola:
  8. * Copyright (C) 2007 - 2009 Motorola, Inc.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/regmap.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/mfd/motorola-cpcap.h>
  14. #include <sound/core.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. /* Register 513 CPCAP_REG_CC --- CODEC */
  18. #define CPCAP_BIT_CDC_CLK2 15
  19. #define CPCAP_BIT_CDC_CLK1 14
  20. #define CPCAP_BIT_CDC_CLK0 13
  21. #define CPCAP_BIT_CDC_SR3 12
  22. #define CPCAP_BIT_CDC_SR2 11
  23. #define CPCAP_BIT_CDC_SR1 10
  24. #define CPCAP_BIT_CDC_SR0 9
  25. #define CPCAP_BIT_CDC_CLOCK_TREE_RESET 8
  26. #define CPCAP_BIT_MIC2_CDC_EN 7
  27. #define CPCAP_BIT_CDC_EN_RX 6
  28. #define CPCAP_BIT_DF_RESET 5
  29. #define CPCAP_BIT_MIC1_CDC_EN 4
  30. #define CPCAP_BIT_AUDOHPF_1 3
  31. #define CPCAP_BIT_AUDOHPF_0 2
  32. #define CPCAP_BIT_AUDIHPF_1 1
  33. #define CPCAP_BIT_AUDIHPF_0 0
  34. /* Register 514 CPCAP_REG_CDI --- CODEC Digital Audio Interface */
  35. #define CPCAP_BIT_CDC_PLL_SEL 15
  36. #define CPCAP_BIT_CLK_IN_SEL 13
  37. #define CPCAP_BIT_DIG_AUD_IN 12
  38. #define CPCAP_BIT_CDC_CLK_EN 11
  39. #define CPCAP_BIT_CDC_DIG_AUD_FS1 10
  40. #define CPCAP_BIT_CDC_DIG_AUD_FS0 9
  41. #define CPCAP_BIT_MIC2_TIMESLOT2 8
  42. #define CPCAP_BIT_MIC2_TIMESLOT1 7
  43. #define CPCAP_BIT_MIC2_TIMESLOT0 6
  44. #define CPCAP_BIT_MIC1_RX_TIMESLOT2 5
  45. #define CPCAP_BIT_MIC1_RX_TIMESLOT1 4
  46. #define CPCAP_BIT_MIC1_RX_TIMESLOT0 3
  47. #define CPCAP_BIT_FS_INV 2
  48. #define CPCAP_BIT_CLK_INV 1
  49. #define CPCAP_BIT_SMB_CDC 0
  50. /* Register 515 CPCAP_REG_SDAC --- Stereo DAC */
  51. #define CPCAP_BIT_FSYNC_CLK_IN_COMMON 11
  52. #define CPCAP_BIT_SLAVE_PLL_CLK_INPUT 10
  53. #define CPCAP_BIT_ST_CLOCK_TREE_RESET 9
  54. #define CPCAP_BIT_DF_RESET_ST_DAC 8
  55. #define CPCAP_BIT_ST_SR3 7
  56. #define CPCAP_BIT_ST_SR2 6
  57. #define CPCAP_BIT_ST_SR1 5
  58. #define CPCAP_BIT_ST_SR0 4
  59. #define CPCAP_BIT_ST_DAC_CLK2 3
  60. #define CPCAP_BIT_ST_DAC_CLK1 2
  61. #define CPCAP_BIT_ST_DAC_CLK0 1
  62. #define CPCAP_BIT_ST_DAC_EN 0
  63. /* Register 516 CPCAP_REG_SDACDI --- Stereo DAC Digital Audio Interface */
  64. #define CPCAP_BIT_ST_L_TIMESLOT2 13
  65. #define CPCAP_BIT_ST_L_TIMESLOT1 12
  66. #define CPCAP_BIT_ST_L_TIMESLOT0 11
  67. #define CPCAP_BIT_ST_R_TIMESLOT2 10
  68. #define CPCAP_BIT_ST_R_TIMESLOT1 9
  69. #define CPCAP_BIT_ST_R_TIMESLOT0 8
  70. #define CPCAP_BIT_ST_DAC_CLK_IN_SEL 7
  71. #define CPCAP_BIT_ST_FS_INV 6
  72. #define CPCAP_BIT_ST_CLK_INV 5
  73. #define CPCAP_BIT_ST_DIG_AUD_FS1 4
  74. #define CPCAP_BIT_ST_DIG_AUD_FS0 3
  75. #define CPCAP_BIT_DIG_AUD_IN_ST_DAC 2
  76. #define CPCAP_BIT_ST_CLK_EN 1
  77. #define CPCAP_BIT_SMB_ST_DAC 0
  78. /* Register 517 CPCAP_REG_TXI --- TX Interface */
  79. #define CPCAP_BIT_PTT_TH 15
  80. #define CPCAP_BIT_PTT_CMP_EN 14
  81. #define CPCAP_BIT_HS_ID_TX 13
  82. #define CPCAP_BIT_MB_ON2 12
  83. #define CPCAP_BIT_MB_ON1L 11
  84. #define CPCAP_BIT_MB_ON1R 10
  85. #define CPCAP_BIT_RX_L_ENCODE 9
  86. #define CPCAP_BIT_RX_R_ENCODE 8
  87. #define CPCAP_BIT_MIC2_MUX 7
  88. #define CPCAP_BIT_MIC2_PGA_EN 6
  89. #define CPCAP_BIT_CDET_DIS 5
  90. #define CPCAP_BIT_EMU_MIC_MUX 4
  91. #define CPCAP_BIT_HS_MIC_MUX 3
  92. #define CPCAP_BIT_MIC1_MUX 2
  93. #define CPCAP_BIT_MIC1_PGA_EN 1
  94. #define CPCAP_BIT_DLM 0
  95. /* Register 518 CPCAP_REG_TXMP --- Mic Gain */
  96. #define CPCAP_BIT_MB_BIAS_R1 11
  97. #define CPCAP_BIT_MB_BIAS_R0 10
  98. #define CPCAP_BIT_MIC2_GAIN_4 9
  99. #define CPCAP_BIT_MIC2_GAIN_3 8
  100. #define CPCAP_BIT_MIC2_GAIN_2 7
  101. #define CPCAP_BIT_MIC2_GAIN_1 6
  102. #define CPCAP_BIT_MIC2_GAIN_0 5
  103. #define CPCAP_BIT_MIC1_GAIN_4 4
  104. #define CPCAP_BIT_MIC1_GAIN_3 3
  105. #define CPCAP_BIT_MIC1_GAIN_2 2
  106. #define CPCAP_BIT_MIC1_GAIN_1 1
  107. #define CPCAP_BIT_MIC1_GAIN_0 0
  108. /* Register 519 CPCAP_REG_RXOA --- RX Output Amplifier */
  109. #define CPCAP_BIT_UNUSED_519_15 15
  110. #define CPCAP_BIT_UNUSED_519_14 14
  111. #define CPCAP_BIT_UNUSED_519_13 13
  112. #define CPCAP_BIT_STDAC_LOW_PWR_DISABLE 12
  113. #define CPCAP_BIT_HS_LOW_PWR 11
  114. #define CPCAP_BIT_HS_ID_RX 10
  115. #define CPCAP_BIT_ST_HS_CP_EN 9
  116. #define CPCAP_BIT_EMU_SPKR_R_EN 8
  117. #define CPCAP_BIT_EMU_SPKR_L_EN 7
  118. #define CPCAP_BIT_HS_L_EN 6
  119. #define CPCAP_BIT_HS_R_EN 5
  120. #define CPCAP_BIT_A4_LINEOUT_L_EN 4
  121. #define CPCAP_BIT_A4_LINEOUT_R_EN 3
  122. #define CPCAP_BIT_A2_LDSP_L_EN 2
  123. #define CPCAP_BIT_A2_LDSP_R_EN 1
  124. #define CPCAP_BIT_A1_EAR_EN 0
  125. /* Register 520 CPCAP_REG_RXVC --- RX Volume Control */
  126. #define CPCAP_BIT_VOL_EXT3 15
  127. #define CPCAP_BIT_VOL_EXT2 14
  128. #define CPCAP_BIT_VOL_EXT1 13
  129. #define CPCAP_BIT_VOL_EXT0 12
  130. #define CPCAP_BIT_VOL_DAC3 11
  131. #define CPCAP_BIT_VOL_DAC2 10
  132. #define CPCAP_BIT_VOL_DAC1 9
  133. #define CPCAP_BIT_VOL_DAC0 8
  134. #define CPCAP_BIT_VOL_DAC_LSB_1dB1 7
  135. #define CPCAP_BIT_VOL_DAC_LSB_1dB0 6
  136. #define CPCAP_BIT_VOL_CDC3 5
  137. #define CPCAP_BIT_VOL_CDC2 4
  138. #define CPCAP_BIT_VOL_CDC1 3
  139. #define CPCAP_BIT_VOL_CDC0 2
  140. #define CPCAP_BIT_VOL_CDC_LSB_1dB1 1
  141. #define CPCAP_BIT_VOL_CDC_LSB_1dB0 0
  142. /* Register 521 CPCAP_REG_RXCOA --- Codec to Output Amp Switches */
  143. #define CPCAP_BIT_PGA_CDC_EN 10
  144. #define CPCAP_BIT_CDC_SW 9
  145. #define CPCAP_BIT_PGA_OUTR_USBDP_CDC_SW 8
  146. #define CPCAP_BIT_PGA_OUTL_USBDN_CDC_SW 7
  147. #define CPCAP_BIT_ALEFT_HS_CDC_SW 6
  148. #define CPCAP_BIT_ARIGHT_HS_CDC_SW 5
  149. #define CPCAP_BIT_A4_LINEOUT_L_CDC_SW 4
  150. #define CPCAP_BIT_A4_LINEOUT_R_CDC_SW 3
  151. #define CPCAP_BIT_A2_LDSP_L_CDC_SW 2
  152. #define CPCAP_BIT_A2_LDSP_R_CDC_SW 1
  153. #define CPCAP_BIT_A1_EAR_CDC_SW 0
  154. /* Register 522 CPCAP_REG_RXSDOA --- RX Stereo DAC to Output Amp Switches */
  155. #define CPCAP_BIT_PGA_DAC_EN 12
  156. #define CPCAP_BIT_ST_DAC_SW 11
  157. #define CPCAP_BIT_MONO_DAC1 10
  158. #define CPCAP_BIT_MONO_DAC0 9
  159. #define CPCAP_BIT_PGA_OUTR_USBDP_DAC_SW 8
  160. #define CPCAP_BIT_PGA_OUTL_USBDN_DAC_SW 7
  161. #define CPCAP_BIT_ALEFT_HS_DAC_SW 6
  162. #define CPCAP_BIT_ARIGHT_HS_DAC_SW 5
  163. #define CPCAP_BIT_A4_LINEOUT_L_DAC_SW 4
  164. #define CPCAP_BIT_A4_LINEOUT_R_DAC_SW 3
  165. #define CPCAP_BIT_A2_LDSP_L_DAC_SW 2
  166. #define CPCAP_BIT_A2_LDSP_R_DAC_SW 1
  167. #define CPCAP_BIT_A1_EAR_DAC_SW 0
  168. /* Register 523 CPCAP_REG_RXEPOA --- RX External PGA to Output Amp Switches */
  169. #define CPCAP_BIT_PGA_EXT_L_EN 14
  170. #define CPCAP_BIT_PGA_EXT_R_EN 13
  171. #define CPCAP_BIT_PGA_IN_L_SW 12
  172. #define CPCAP_BIT_PGA_IN_R_SW 11
  173. #define CPCAP_BIT_MONO_EXT1 10
  174. #define CPCAP_BIT_MONO_EXT0 9
  175. #define CPCAP_BIT_PGA_OUTR_USBDP_EXT_SW 8
  176. #define CPCAP_BIT_PGA_OUTL_USBDN_EXT_SW 7
  177. #define CPCAP_BIT_ALEFT_HS_EXT_SW 6
  178. #define CPCAP_BIT_ARIGHT_HS_EXT_SW 5
  179. #define CPCAP_BIT_A4_LINEOUT_L_EXT_SW 4
  180. #define CPCAP_BIT_A4_LINEOUT_R_EXT_SW 3
  181. #define CPCAP_BIT_A2_LDSP_L_EXT_SW 2
  182. #define CPCAP_BIT_A2_LDSP_R_EXT_SW 1
  183. #define CPCAP_BIT_A1_EAR_EXT_SW 0
  184. /* Register 525 CPCAP_REG_A2LA --- SPK Amplifier and Clock Config for Headset */
  185. #define CPCAP_BIT_NCP_CLK_SYNC 7
  186. #define CPCAP_BIT_A2_CLK_SYNC 6
  187. #define CPCAP_BIT_A2_FREE_RUN 5
  188. #define CPCAP_BIT_A2_CLK2 4
  189. #define CPCAP_BIT_A2_CLK1 3
  190. #define CPCAP_BIT_A2_CLK0 2
  191. #define CPCAP_BIT_A2_CLK_IN 1
  192. #define CPCAP_BIT_A2_CONFIG 0
  193. #define SLEEP_ACTIVATE_POWER 2
  194. #define CLOCK_TREE_RESET_TIME 1
  195. /* constants for ST delay workaround */
  196. #define STM_STDAC_ACTIVATE_RAMP_TIME 1
  197. #define STM_STDAC_EN_TEST_PRE 0x090C
  198. #define STM_STDAC_EN_TEST_POST 0x0000
  199. #define STM_STDAC_EN_ST_TEST1_PRE 0x2400
  200. #define STM_STDAC_EN_ST_TEST1_POST 0x0400
  201. struct cpcap_reg_info {
  202. u16 reg;
  203. u16 mask;
  204. u16 val;
  205. };
  206. static const struct cpcap_reg_info cpcap_default_regs[] = {
  207. { CPCAP_REG_CC, 0xFFFF, 0x0000 },
  208. { CPCAP_REG_CC, 0xFFFF, 0x0000 },
  209. { CPCAP_REG_CDI, 0xBFFF, 0x0000 },
  210. { CPCAP_REG_SDAC, 0x0FFF, 0x0000 },
  211. { CPCAP_REG_SDACDI, 0x3FFF, 0x0000 },
  212. { CPCAP_REG_TXI, 0x0FDF, 0x0000 },
  213. { CPCAP_REG_TXMP, 0x0FFF, 0x0400 },
  214. { CPCAP_REG_RXOA, 0x01FF, 0x0000 },
  215. { CPCAP_REG_RXVC, 0xFF3C, 0x0000 },
  216. { CPCAP_REG_RXCOA, 0x07FF, 0x0000 },
  217. { CPCAP_REG_RXSDOA, 0x1FFF, 0x0000 },
  218. { CPCAP_REG_RXEPOA, 0x7FFF, 0x0000 },
  219. { CPCAP_REG_A2LA, BIT(CPCAP_BIT_A2_FREE_RUN),
  220. BIT(CPCAP_BIT_A2_FREE_RUN) },
  221. };
  222. enum cpcap_dai {
  223. CPCAP_DAI_HIFI,
  224. CPCAP_DAI_VOICE,
  225. };
  226. struct cpcap_audio {
  227. struct snd_soc_component *component;
  228. struct regmap *regmap;
  229. u16 vendor;
  230. int codec_clk_id;
  231. int codec_freq;
  232. int codec_format;
  233. };
  234. static int cpcap_st_workaround(struct snd_soc_dapm_widget *w,
  235. struct snd_kcontrol *kcontrol, int event)
  236. {
  237. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  238. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  239. int err = 0;
  240. /* Only CPCAP from ST requires workaround */
  241. if (cpcap->vendor != CPCAP_VENDOR_ST)
  242. return 0;
  243. switch (event) {
  244. case SND_SOC_DAPM_PRE_PMU:
  245. err = regmap_write(cpcap->regmap, CPCAP_REG_TEST,
  246. STM_STDAC_EN_TEST_PRE);
  247. if (err)
  248. return err;
  249. err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1,
  250. STM_STDAC_EN_ST_TEST1_PRE);
  251. break;
  252. case SND_SOC_DAPM_POST_PMU:
  253. msleep(STM_STDAC_ACTIVATE_RAMP_TIME);
  254. err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1,
  255. STM_STDAC_EN_ST_TEST1_POST);
  256. if (err)
  257. return err;
  258. err = regmap_write(cpcap->regmap, CPCAP_REG_TEST,
  259. STM_STDAC_EN_TEST_POST);
  260. break;
  261. default:
  262. break;
  263. }
  264. return err;
  265. }
  266. /* Capture Gain Control: 0dB to 31dB in 1dB steps */
  267. static const DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
  268. /* Playback Gain Control: -33dB to 12dB in 3dB steps */
  269. static const DECLARE_TLV_DB_SCALE(vol_tlv, -3300, 300, 0);
  270. static const struct snd_kcontrol_new cpcap_snd_controls[] = {
  271. /* Playback Gain */
  272. SOC_SINGLE_TLV("HiFi Playback Volume",
  273. CPCAP_REG_RXVC, CPCAP_BIT_VOL_DAC0, 0xF, 0, vol_tlv),
  274. SOC_SINGLE_TLV("Voice Playback Volume",
  275. CPCAP_REG_RXVC, CPCAP_BIT_VOL_CDC0, 0xF, 0, vol_tlv),
  276. SOC_SINGLE_TLV("Ext Playback Volume",
  277. CPCAP_REG_RXVC, CPCAP_BIT_VOL_EXT0, 0xF, 0, vol_tlv),
  278. /* Capture Gain */
  279. SOC_SINGLE_TLV("Mic1 Capture Volume",
  280. CPCAP_REG_TXMP, CPCAP_BIT_MIC1_GAIN_0, 0x1F, 0, mic_gain_tlv),
  281. SOC_SINGLE_TLV("Mic2 Capture Volume",
  282. CPCAP_REG_TXMP, CPCAP_BIT_MIC2_GAIN_0, 0x1F, 0, mic_gain_tlv),
  283. /* Phase Invert */
  284. SOC_SINGLE("Hifi Left Phase Invert Switch",
  285. CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC0, 1, 0),
  286. SOC_SINGLE("Ext Left Phase Invert Switch",
  287. CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0),
  288. };
  289. static const char * const cpcap_out_mux_texts[] = {
  290. "Off", "Voice", "HiFi", "Ext"
  291. };
  292. static const char * const cpcap_in_right_mux_texts[] = {
  293. "Off", "Mic 1", "Headset Mic", "EMU Mic", "Ext Right"
  294. };
  295. static const char * const cpcap_in_left_mux_texts[] = {
  296. "Off", "Mic 2", "Ext Left"
  297. };
  298. /*
  299. * input muxes use unusual register layout, so that we need to use custom
  300. * getter/setter methods
  301. */
  302. static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_left_mux_enum,
  303. cpcap_in_left_mux_texts);
  304. static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_right_mux_enum,
  305. cpcap_in_right_mux_texts);
  306. /*
  307. * mux uses same bit in CPCAP_REG_RXCOA, CPCAP_REG_RXSDOA & CPCAP_REG_RXEPOA;
  308. * even though the register layout makes it look like a mixer, this is a mux.
  309. * Enabling multiple inputs will result in no audio being forwarded.
  310. */
  311. static SOC_ENUM_SINGLE_DECL(cpcap_earpiece_mux_enum, 0, 0, cpcap_out_mux_texts);
  312. static SOC_ENUM_SINGLE_DECL(cpcap_spkr_r_mux_enum, 0, 1, cpcap_out_mux_texts);
  313. static SOC_ENUM_SINGLE_DECL(cpcap_spkr_l_mux_enum, 0, 2, cpcap_out_mux_texts);
  314. static SOC_ENUM_SINGLE_DECL(cpcap_line_r_mux_enum, 0, 3, cpcap_out_mux_texts);
  315. static SOC_ENUM_SINGLE_DECL(cpcap_line_l_mux_enum, 0, 4, cpcap_out_mux_texts);
  316. static SOC_ENUM_SINGLE_DECL(cpcap_hs_r_mux_enum, 0, 5, cpcap_out_mux_texts);
  317. static SOC_ENUM_SINGLE_DECL(cpcap_hs_l_mux_enum, 0, 6, cpcap_out_mux_texts);
  318. static SOC_ENUM_SINGLE_DECL(cpcap_emu_l_mux_enum, 0, 7, cpcap_out_mux_texts);
  319. static SOC_ENUM_SINGLE_DECL(cpcap_emu_r_mux_enum, 0, 8, cpcap_out_mux_texts);
  320. static int cpcap_output_mux_get_enum(struct snd_kcontrol *kcontrol,
  321. struct snd_ctl_elem_value *ucontrol)
  322. {
  323. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  324. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  325. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  326. unsigned int shift = e->shift_l;
  327. int reg_voice, reg_hifi, reg_ext, status;
  328. int err;
  329. err = regmap_read(cpcap->regmap, CPCAP_REG_RXCOA, &reg_voice);
  330. if (err)
  331. return err;
  332. err = regmap_read(cpcap->regmap, CPCAP_REG_RXSDOA, &reg_hifi);
  333. if (err)
  334. return err;
  335. err = regmap_read(cpcap->regmap, CPCAP_REG_RXEPOA, &reg_ext);
  336. if (err)
  337. return err;
  338. reg_voice = (reg_voice >> shift) & 1;
  339. reg_hifi = (reg_hifi >> shift) & 1;
  340. reg_ext = (reg_ext >> shift) & 1;
  341. status = reg_ext << 2 | reg_hifi << 1 | reg_voice;
  342. switch (status) {
  343. case 0x04:
  344. ucontrol->value.enumerated.item[0] = 3;
  345. break;
  346. case 0x02:
  347. ucontrol->value.enumerated.item[0] = 2;
  348. break;
  349. case 0x01:
  350. ucontrol->value.enumerated.item[0] = 1;
  351. break;
  352. default:
  353. ucontrol->value.enumerated.item[0] = 0;
  354. break;
  355. }
  356. return 0;
  357. }
  358. static int cpcap_output_mux_put_enum(struct snd_kcontrol *kcontrol,
  359. struct snd_ctl_elem_value *ucontrol)
  360. {
  361. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  362. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  363. struct snd_soc_dapm_context *dapm =
  364. snd_soc_dapm_kcontrol_dapm(kcontrol);
  365. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  366. unsigned int muxval = ucontrol->value.enumerated.item[0];
  367. unsigned int mask = BIT(e->shift_l);
  368. u16 reg_voice = 0x00, reg_hifi = 0x00, reg_ext = 0x00;
  369. int err;
  370. switch (muxval) {
  371. case 1:
  372. reg_voice = mask;
  373. break;
  374. case 2:
  375. reg_hifi = mask;
  376. break;
  377. case 3:
  378. reg_ext = mask;
  379. break;
  380. default:
  381. break;
  382. }
  383. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXCOA,
  384. mask, reg_voice);
  385. if (err)
  386. return err;
  387. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXSDOA,
  388. mask, reg_hifi);
  389. if (err)
  390. return err;
  391. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXEPOA,
  392. mask, reg_ext);
  393. if (err)
  394. return err;
  395. snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
  396. return 0;
  397. }
  398. static int cpcap_input_right_mux_get_enum(struct snd_kcontrol *kcontrol,
  399. struct snd_ctl_elem_value *ucontrol)
  400. {
  401. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  402. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  403. int regval, mask;
  404. int err;
  405. err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, &regval);
  406. if (err)
  407. return err;
  408. mask = 0;
  409. mask |= BIT(CPCAP_BIT_MIC1_MUX);
  410. mask |= BIT(CPCAP_BIT_HS_MIC_MUX);
  411. mask |= BIT(CPCAP_BIT_EMU_MIC_MUX);
  412. mask |= BIT(CPCAP_BIT_RX_R_ENCODE);
  413. switch (regval & mask) {
  414. case BIT(CPCAP_BIT_RX_R_ENCODE):
  415. ucontrol->value.enumerated.item[0] = 4;
  416. break;
  417. case BIT(CPCAP_BIT_EMU_MIC_MUX):
  418. ucontrol->value.enumerated.item[0] = 3;
  419. break;
  420. case BIT(CPCAP_BIT_HS_MIC_MUX):
  421. ucontrol->value.enumerated.item[0] = 2;
  422. break;
  423. case BIT(CPCAP_BIT_MIC1_MUX):
  424. ucontrol->value.enumerated.item[0] = 1;
  425. break;
  426. default:
  427. ucontrol->value.enumerated.item[0] = 0;
  428. break;
  429. }
  430. return 0;
  431. }
  432. static int cpcap_input_right_mux_put_enum(struct snd_kcontrol *kcontrol,
  433. struct snd_ctl_elem_value *ucontrol)
  434. {
  435. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  436. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  437. struct snd_soc_dapm_context *dapm =
  438. snd_soc_dapm_kcontrol_dapm(kcontrol);
  439. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  440. unsigned int muxval = ucontrol->value.enumerated.item[0];
  441. int regval = 0, mask;
  442. int err;
  443. mask = 0;
  444. mask |= BIT(CPCAP_BIT_MIC1_MUX);
  445. mask |= BIT(CPCAP_BIT_HS_MIC_MUX);
  446. mask |= BIT(CPCAP_BIT_EMU_MIC_MUX);
  447. mask |= BIT(CPCAP_BIT_RX_R_ENCODE);
  448. switch (muxval) {
  449. case 1:
  450. regval = BIT(CPCAP_BIT_MIC1_MUX);
  451. break;
  452. case 2:
  453. regval = BIT(CPCAP_BIT_HS_MIC_MUX);
  454. break;
  455. case 3:
  456. regval = BIT(CPCAP_BIT_EMU_MIC_MUX);
  457. break;
  458. case 4:
  459. regval = BIT(CPCAP_BIT_RX_R_ENCODE);
  460. break;
  461. default:
  462. break;
  463. }
  464. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
  465. mask, regval);
  466. if (err)
  467. return err;
  468. snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
  469. return 0;
  470. }
  471. static int cpcap_input_left_mux_get_enum(struct snd_kcontrol *kcontrol,
  472. struct snd_ctl_elem_value *ucontrol)
  473. {
  474. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  475. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  476. int regval, mask;
  477. int err;
  478. err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, &regval);
  479. if (err)
  480. return err;
  481. mask = 0;
  482. mask |= BIT(CPCAP_BIT_MIC2_MUX);
  483. mask |= BIT(CPCAP_BIT_RX_L_ENCODE);
  484. switch (regval & mask) {
  485. case BIT(CPCAP_BIT_RX_L_ENCODE):
  486. ucontrol->value.enumerated.item[0] = 2;
  487. break;
  488. case BIT(CPCAP_BIT_MIC2_MUX):
  489. ucontrol->value.enumerated.item[0] = 1;
  490. break;
  491. default:
  492. ucontrol->value.enumerated.item[0] = 0;
  493. break;
  494. }
  495. return 0;
  496. }
  497. static int cpcap_input_left_mux_put_enum(struct snd_kcontrol *kcontrol,
  498. struct snd_ctl_elem_value *ucontrol)
  499. {
  500. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  501. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  502. struct snd_soc_dapm_context *dapm =
  503. snd_soc_dapm_kcontrol_dapm(kcontrol);
  504. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  505. unsigned int muxval = ucontrol->value.enumerated.item[0];
  506. int regval = 0, mask;
  507. int err;
  508. mask = 0;
  509. mask |= BIT(CPCAP_BIT_MIC2_MUX);
  510. mask |= BIT(CPCAP_BIT_RX_L_ENCODE);
  511. switch (muxval) {
  512. case 1:
  513. regval = BIT(CPCAP_BIT_MIC2_MUX);
  514. break;
  515. case 2:
  516. regval = BIT(CPCAP_BIT_RX_L_ENCODE);
  517. break;
  518. default:
  519. break;
  520. }
  521. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
  522. mask, regval);
  523. if (err)
  524. return err;
  525. snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
  526. return 0;
  527. }
  528. static const struct snd_kcontrol_new cpcap_input_left_mux =
  529. SOC_DAPM_ENUM_EXT("Input Left", cpcap_input_left_mux_enum,
  530. cpcap_input_left_mux_get_enum,
  531. cpcap_input_left_mux_put_enum);
  532. static const struct snd_kcontrol_new cpcap_input_right_mux =
  533. SOC_DAPM_ENUM_EXT("Input Right", cpcap_input_right_mux_enum,
  534. cpcap_input_right_mux_get_enum,
  535. cpcap_input_right_mux_put_enum);
  536. static const struct snd_kcontrol_new cpcap_emu_left_mux =
  537. SOC_DAPM_ENUM_EXT("EMU Left", cpcap_emu_l_mux_enum,
  538. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  539. static const struct snd_kcontrol_new cpcap_emu_right_mux =
  540. SOC_DAPM_ENUM_EXT("EMU Right", cpcap_emu_r_mux_enum,
  541. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  542. static const struct snd_kcontrol_new cpcap_hs_left_mux =
  543. SOC_DAPM_ENUM_EXT("Headset Left", cpcap_hs_l_mux_enum,
  544. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  545. static const struct snd_kcontrol_new cpcap_hs_right_mux =
  546. SOC_DAPM_ENUM_EXT("Headset Right", cpcap_hs_r_mux_enum,
  547. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  548. static const struct snd_kcontrol_new cpcap_line_left_mux =
  549. SOC_DAPM_ENUM_EXT("Line Left", cpcap_line_l_mux_enum,
  550. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  551. static const struct snd_kcontrol_new cpcap_line_right_mux =
  552. SOC_DAPM_ENUM_EXT("Line Right", cpcap_line_r_mux_enum,
  553. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  554. static const struct snd_kcontrol_new cpcap_speaker_left_mux =
  555. SOC_DAPM_ENUM_EXT("Speaker Left", cpcap_spkr_l_mux_enum,
  556. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  557. static const struct snd_kcontrol_new cpcap_speaker_right_mux =
  558. SOC_DAPM_ENUM_EXT("Speaker Right", cpcap_spkr_r_mux_enum,
  559. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  560. static const struct snd_kcontrol_new cpcap_earpiece_mux =
  561. SOC_DAPM_ENUM_EXT("Earpiece", cpcap_earpiece_mux_enum,
  562. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  563. static const struct snd_kcontrol_new cpcap_hifi_mono_mixer_controls[] = {
  564. SOC_DAPM_SINGLE("HiFi Mono Playback Switch",
  565. CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC1, 1, 0),
  566. };
  567. static const struct snd_kcontrol_new cpcap_ext_mono_mixer_controls[] = {
  568. SOC_DAPM_SINGLE("Ext Mono Playback Switch",
  569. CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0),
  570. };
  571. static const struct snd_kcontrol_new cpcap_extr_mute_control =
  572. SOC_DAPM_SINGLE("Switch",
  573. CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_R_SW, 1, 0);
  574. static const struct snd_kcontrol_new cpcap_extl_mute_control =
  575. SOC_DAPM_SINGLE("Switch",
  576. CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_L_SW, 1, 0);
  577. static const struct snd_kcontrol_new cpcap_voice_loopback =
  578. SOC_DAPM_SINGLE("Switch",
  579. CPCAP_REG_TXI, CPCAP_BIT_DLM, 1, 0);
  580. static const struct snd_soc_dapm_widget cpcap_dapm_widgets[] = {
  581. /* DAIs */
  582. SND_SOC_DAPM_AIF_IN("HiFi RX", NULL, 0, SND_SOC_NOPM, 0, 0),
  583. SND_SOC_DAPM_AIF_IN("Voice RX", NULL, 0, SND_SOC_NOPM, 0, 0),
  584. SND_SOC_DAPM_AIF_OUT("Voice TX", NULL, 0, SND_SOC_NOPM, 0, 0),
  585. /* Power Supply */
  586. SND_SOC_DAPM_REGULATOR_SUPPLY("VAUDIO", SLEEP_ACTIVATE_POWER, 0),
  587. /* Highpass Filters */
  588. SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter RX",
  589. CPCAP_REG_CC, CPCAP_BIT_AUDIHPF_0, 0x3, 0x3, 0x0),
  590. SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter TX",
  591. CPCAP_REG_CC, CPCAP_BIT_AUDOHPF_0, 0x3, 0x3, 0x0),
  592. /* Clocks */
  593. SND_SOC_DAPM_SUPPLY("HiFi DAI Clock",
  594. CPCAP_REG_SDACDI, CPCAP_BIT_ST_CLK_EN, 0, NULL, 0),
  595. SND_SOC_DAPM_SUPPLY("Voice DAI Clock",
  596. CPCAP_REG_CDI, CPCAP_BIT_CDC_CLK_EN, 0, NULL, 0),
  597. /* Microphone Bias */
  598. SND_SOC_DAPM_SUPPLY("MIC1R Bias",
  599. CPCAP_REG_TXI, CPCAP_BIT_MB_ON1R, 0, NULL, 0),
  600. SND_SOC_DAPM_SUPPLY("MIC1L Bias",
  601. CPCAP_REG_TXI, CPCAP_BIT_MB_ON1L, 0, NULL, 0),
  602. SND_SOC_DAPM_SUPPLY("MIC2 Bias",
  603. CPCAP_REG_TXI, CPCAP_BIT_MB_ON2, 0, NULL, 0),
  604. /* Inputs */
  605. SND_SOC_DAPM_INPUT("MICR"),
  606. SND_SOC_DAPM_INPUT("HSMIC"),
  607. SND_SOC_DAPM_INPUT("EMUMIC"),
  608. SND_SOC_DAPM_INPUT("MICL"),
  609. SND_SOC_DAPM_INPUT("EXTR"),
  610. SND_SOC_DAPM_INPUT("EXTL"),
  611. /* Capture Route */
  612. SND_SOC_DAPM_MUX("Right Capture Route",
  613. SND_SOC_NOPM, 0, 0, &cpcap_input_right_mux),
  614. SND_SOC_DAPM_MUX("Left Capture Route",
  615. SND_SOC_NOPM, 0, 0, &cpcap_input_left_mux),
  616. /* Capture PGAs */
  617. SND_SOC_DAPM_PGA("Microphone 1 PGA",
  618. CPCAP_REG_TXI, CPCAP_BIT_MIC1_PGA_EN, 0, NULL, 0),
  619. SND_SOC_DAPM_PGA("Microphone 2 PGA",
  620. CPCAP_REG_TXI, CPCAP_BIT_MIC2_PGA_EN, 0, NULL, 0),
  621. /* ADC */
  622. SND_SOC_DAPM_ADC("ADC Right", NULL,
  623. CPCAP_REG_CC, CPCAP_BIT_MIC1_CDC_EN, 0),
  624. SND_SOC_DAPM_ADC("ADC Left", NULL,
  625. CPCAP_REG_CC, CPCAP_BIT_MIC2_CDC_EN, 0),
  626. /* DAC */
  627. SND_SOC_DAPM_DAC_E("DAC HiFi", NULL,
  628. CPCAP_REG_SDAC, CPCAP_BIT_ST_DAC_EN, 0,
  629. cpcap_st_workaround,
  630. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  631. SND_SOC_DAPM_DAC_E("DAC Voice", NULL,
  632. CPCAP_REG_CC, CPCAP_BIT_CDC_EN_RX, 0,
  633. cpcap_st_workaround,
  634. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  635. /* Playback PGA */
  636. SND_SOC_DAPM_PGA("HiFi PGA",
  637. CPCAP_REG_RXSDOA, CPCAP_BIT_PGA_DAC_EN, 0, NULL, 0),
  638. SND_SOC_DAPM_PGA("Voice PGA",
  639. CPCAP_REG_RXCOA, CPCAP_BIT_PGA_CDC_EN, 0, NULL, 0),
  640. SND_SOC_DAPM_PGA_E("Ext Right PGA",
  641. CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_R_EN, 0,
  642. NULL, 0,
  643. cpcap_st_workaround,
  644. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  645. SND_SOC_DAPM_PGA_E("Ext Left PGA",
  646. CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_L_EN, 0,
  647. NULL, 0,
  648. cpcap_st_workaround,
  649. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  650. /* Playback Switch */
  651. SND_SOC_DAPM_SWITCH("Ext Right Enable", SND_SOC_NOPM, 0, 0,
  652. &cpcap_extr_mute_control),
  653. SND_SOC_DAPM_SWITCH("Ext Left Enable", SND_SOC_NOPM, 0, 0,
  654. &cpcap_extl_mute_control),
  655. /* Loopback Switch */
  656. SND_SOC_DAPM_SWITCH("Voice Loopback", SND_SOC_NOPM, 0, 0,
  657. &cpcap_voice_loopback),
  658. /* Mono Mixer */
  659. SOC_MIXER_ARRAY("HiFi Mono Left Mixer", SND_SOC_NOPM, 0, 0,
  660. cpcap_hifi_mono_mixer_controls),
  661. SOC_MIXER_ARRAY("HiFi Mono Right Mixer", SND_SOC_NOPM, 0, 0,
  662. cpcap_hifi_mono_mixer_controls),
  663. SOC_MIXER_ARRAY("Ext Mono Left Mixer", SND_SOC_NOPM, 0, 0,
  664. cpcap_ext_mono_mixer_controls),
  665. SOC_MIXER_ARRAY("Ext Mono Right Mixer", SND_SOC_NOPM, 0, 0,
  666. cpcap_ext_mono_mixer_controls),
  667. /* Output Routes */
  668. SND_SOC_DAPM_MUX("Earpiece Playback Route", SND_SOC_NOPM, 0, 0,
  669. &cpcap_earpiece_mux),
  670. SND_SOC_DAPM_MUX("Speaker Right Playback Route", SND_SOC_NOPM, 0, 0,
  671. &cpcap_speaker_right_mux),
  672. SND_SOC_DAPM_MUX("Speaker Left Playback Route", SND_SOC_NOPM, 0, 0,
  673. &cpcap_speaker_left_mux),
  674. SND_SOC_DAPM_MUX("Lineout Right Playback Route", SND_SOC_NOPM, 0, 0,
  675. &cpcap_line_right_mux),
  676. SND_SOC_DAPM_MUX("Lineout Left Playback Route", SND_SOC_NOPM, 0, 0,
  677. &cpcap_line_left_mux),
  678. SND_SOC_DAPM_MUX("Headset Right Playback Route", SND_SOC_NOPM, 0, 0,
  679. &cpcap_hs_right_mux),
  680. SND_SOC_DAPM_MUX("Headset Left Playback Route", SND_SOC_NOPM, 0, 0,
  681. &cpcap_hs_left_mux),
  682. SND_SOC_DAPM_MUX("EMU Right Playback Route", SND_SOC_NOPM, 0, 0,
  683. &cpcap_emu_right_mux),
  684. SND_SOC_DAPM_MUX("EMU Left Playback Route", SND_SOC_NOPM, 0, 0,
  685. &cpcap_emu_left_mux),
  686. /* Output Amplifier */
  687. SND_SOC_DAPM_PGA("Earpiece PGA",
  688. CPCAP_REG_RXOA, CPCAP_BIT_A1_EAR_EN, 0, NULL, 0),
  689. SND_SOC_DAPM_PGA("Speaker Right PGA",
  690. CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_R_EN, 0, NULL, 0),
  691. SND_SOC_DAPM_PGA("Speaker Left PGA",
  692. CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_L_EN, 0, NULL, 0),
  693. SND_SOC_DAPM_PGA("Lineout Right PGA",
  694. CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_R_EN, 0, NULL, 0),
  695. SND_SOC_DAPM_PGA("Lineout Left PGA",
  696. CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_L_EN, 0, NULL, 0),
  697. SND_SOC_DAPM_PGA("Headset Right PGA",
  698. CPCAP_REG_RXOA, CPCAP_BIT_HS_R_EN, 0, NULL, 0),
  699. SND_SOC_DAPM_PGA("Headset Left PGA",
  700. CPCAP_REG_RXOA, CPCAP_BIT_HS_L_EN, 0, NULL, 0),
  701. SND_SOC_DAPM_PGA("EMU Right PGA",
  702. CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_R_EN, 0, NULL, 0),
  703. SND_SOC_DAPM_PGA("EMU Left PGA",
  704. CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_L_EN, 0, NULL, 0),
  705. /* Headet Charge Pump */
  706. SND_SOC_DAPM_SUPPLY("Headset Charge Pump",
  707. CPCAP_REG_RXOA, CPCAP_BIT_ST_HS_CP_EN, 0, NULL, 0),
  708. /* Outputs */
  709. SND_SOC_DAPM_OUTPUT("EP"),
  710. SND_SOC_DAPM_OUTPUT("SPKR"),
  711. SND_SOC_DAPM_OUTPUT("SPKL"),
  712. SND_SOC_DAPM_OUTPUT("LINER"),
  713. SND_SOC_DAPM_OUTPUT("LINEL"),
  714. SND_SOC_DAPM_OUTPUT("HSR"),
  715. SND_SOC_DAPM_OUTPUT("HSL"),
  716. SND_SOC_DAPM_OUTPUT("EMUR"),
  717. SND_SOC_DAPM_OUTPUT("EMUL"),
  718. };
  719. static const struct snd_soc_dapm_route intercon[] = {
  720. /* Power Supply */
  721. {"HiFi PGA", NULL, "VAUDIO"},
  722. {"Voice PGA", NULL, "VAUDIO"},
  723. {"Ext Right PGA", NULL, "VAUDIO"},
  724. {"Ext Left PGA", NULL, "VAUDIO"},
  725. {"Microphone 1 PGA", NULL, "VAUDIO"},
  726. {"Microphone 2 PGA", NULL, "VAUDIO"},
  727. /* Stream -> AIF */
  728. {"HiFi RX", NULL, "HiFi Playback"},
  729. {"Voice RX", NULL, "Voice Playback"},
  730. {"Voice Capture", NULL, "Voice TX"},
  731. /* AIF clocks */
  732. {"HiFi RX", NULL, "HiFi DAI Clock"},
  733. {"Voice RX", NULL, "Voice DAI Clock"},
  734. {"Voice TX", NULL, "Voice DAI Clock"},
  735. /* Digital Loopback */
  736. {"Voice Loopback", "Switch", "Voice TX"},
  737. {"Voice RX", NULL, "Voice Loopback"},
  738. /* Highpass Filters */
  739. {"Highpass Filter RX", NULL, "Voice RX"},
  740. {"Voice TX", NULL, "Highpass Filter TX"},
  741. /* AIF -> DAC mapping */
  742. {"DAC HiFi", NULL, "HiFi RX"},
  743. {"DAC Voice", NULL, "Highpass Filter RX"},
  744. /* DAC -> PGA */
  745. {"HiFi PGA", NULL, "DAC HiFi"},
  746. {"Voice PGA", NULL, "DAC Voice"},
  747. /* Ext Input -> PGA */
  748. {"Ext Right PGA", NULL, "EXTR"},
  749. {"Ext Left PGA", NULL, "EXTL"},
  750. /* Ext PGA -> Ext Playback Switch */
  751. {"Ext Right Enable", "Switch", "Ext Right PGA"},
  752. {"Ext Left Enable", "Switch", "Ext Left PGA"},
  753. /* HiFi PGA -> Mono Mixer */
  754. {"HiFi Mono Left Mixer", NULL, "HiFi PGA"},
  755. {"HiFi Mono Left Mixer", "HiFi Mono Playback Switch", "HiFi PGA"},
  756. {"HiFi Mono Right Mixer", NULL, "HiFi PGA"},
  757. {"HiFi Mono Right Mixer", "HiFi Mono Playback Switch", "HiFi PGA"},
  758. /* Ext Playback Switch -> Ext Mono Mixer */
  759. {"Ext Mono Right Mixer", NULL, "Ext Right Enable"},
  760. {"Ext Mono Right Mixer", "Ext Mono Playback Switch", "Ext Left Enable"},
  761. {"Ext Mono Left Mixer", NULL, "Ext Left Enable"},
  762. {"Ext Mono Left Mixer", "Ext Mono Playback Switch", "Ext Right Enable"},
  763. /* HiFi Mono Mixer -> Output Route */
  764. {"Earpiece Playback Route", "HiFi", "HiFi Mono Right Mixer"},
  765. {"Speaker Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
  766. {"Speaker Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
  767. {"Lineout Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
  768. {"Lineout Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
  769. {"Headset Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
  770. {"Headset Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
  771. {"EMU Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
  772. {"EMU Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
  773. /* Voice PGA -> Output Route */
  774. {"Earpiece Playback Route", "Voice", "Voice PGA"},
  775. {"Speaker Right Playback Route", "Voice", "Voice PGA"},
  776. {"Speaker Left Playback Route", "Voice", "Voice PGA"},
  777. {"Lineout Right Playback Route", "Voice", "Voice PGA"},
  778. {"Lineout Left Playback Route", "Voice", "Voice PGA"},
  779. {"Headset Right Playback Route", "Voice", "Voice PGA"},
  780. {"Headset Left Playback Route", "Voice", "Voice PGA"},
  781. {"EMU Right Playback Route", "Voice", "Voice PGA"},
  782. {"EMU Left Playback Route", "Voice", "Voice PGA"},
  783. /* Ext Mono Mixer -> Output Route */
  784. {"Earpiece Playback Route", "Ext", "Ext Mono Right Mixer"},
  785. {"Speaker Right Playback Route", "Ext", "Ext Mono Right Mixer"},
  786. {"Speaker Left Playback Route", "Ext", "Ext Mono Left Mixer"},
  787. {"Lineout Right Playback Route", "Ext", "Ext Mono Right Mixer"},
  788. {"Lineout Left Playback Route", "Ext", "Ext Mono Left Mixer"},
  789. {"Headset Right Playback Route", "Ext", "Ext Mono Right Mixer"},
  790. {"Headset Left Playback Route", "Ext", "Ext Mono Left Mixer"},
  791. {"EMU Right Playback Route", "Ext", "Ext Mono Right Mixer"},
  792. {"EMU Left Playback Route", "Ext", "Ext Mono Left Mixer"},
  793. /* Output Route -> Output Amplifier */
  794. {"Earpiece PGA", NULL, "Earpiece Playback Route"},
  795. {"Speaker Right PGA", NULL, "Speaker Right Playback Route"},
  796. {"Speaker Left PGA", NULL, "Speaker Left Playback Route"},
  797. {"Lineout Right PGA", NULL, "Lineout Right Playback Route"},
  798. {"Lineout Left PGA", NULL, "Lineout Left Playback Route"},
  799. {"Headset Right PGA", NULL, "Headset Right Playback Route"},
  800. {"Headset Left PGA", NULL, "Headset Left Playback Route"},
  801. {"EMU Right PGA", NULL, "EMU Right Playback Route"},
  802. {"EMU Left PGA", NULL, "EMU Left Playback Route"},
  803. /* Output Amplifier -> Output */
  804. {"EP", NULL, "Earpiece PGA"},
  805. {"SPKR", NULL, "Speaker Right PGA"},
  806. {"SPKL", NULL, "Speaker Left PGA"},
  807. {"LINER", NULL, "Lineout Right PGA"},
  808. {"LINEL", NULL, "Lineout Left PGA"},
  809. {"HSR", NULL, "Headset Right PGA"},
  810. {"HSL", NULL, "Headset Left PGA"},
  811. {"EMUR", NULL, "EMU Right PGA"},
  812. {"EMUL", NULL, "EMU Left PGA"},
  813. /* Headset Charge Pump -> Headset */
  814. {"HSR", NULL, "Headset Charge Pump"},
  815. {"HSL", NULL, "Headset Charge Pump"},
  816. /* Mic -> Mic Route */
  817. {"Right Capture Route", "Mic 1", "MICR"},
  818. {"Right Capture Route", "Headset Mic", "HSMIC"},
  819. {"Right Capture Route", "EMU Mic", "EMUMIC"},
  820. {"Right Capture Route", "Ext Right", "EXTR"},
  821. {"Left Capture Route", "Mic 2", "MICL"},
  822. {"Left Capture Route", "Ext Left", "EXTL"},
  823. /* Input Route -> Microphone PGA */
  824. {"Microphone 1 PGA", NULL, "Right Capture Route"},
  825. {"Microphone 2 PGA", NULL, "Left Capture Route"},
  826. /* Microphone PGA -> ADC */
  827. {"ADC Right", NULL, "Microphone 1 PGA"},
  828. {"ADC Left", NULL, "Microphone 2 PGA"},
  829. /* ADC -> Stream */
  830. {"Highpass Filter TX", NULL, "ADC Right"},
  831. {"Highpass Filter TX", NULL, "ADC Left"},
  832. /* Mic Bias */
  833. {"MICL", NULL, "MIC1L Bias"},
  834. {"MICR", NULL, "MIC1R Bias"},
  835. };
  836. static int cpcap_set_sysclk(struct cpcap_audio *cpcap, enum cpcap_dai dai,
  837. int clk_id, int freq)
  838. {
  839. u16 clkfreqreg, clkfreqshift;
  840. u16 clkfreqmask, clkfreqval;
  841. u16 clkidreg, clkidshift;
  842. u16 mask, val;
  843. int err;
  844. switch (dai) {
  845. case CPCAP_DAI_HIFI:
  846. clkfreqreg = CPCAP_REG_SDAC;
  847. clkfreqshift = CPCAP_BIT_ST_DAC_CLK0;
  848. clkidreg = CPCAP_REG_SDACDI;
  849. clkidshift = CPCAP_BIT_ST_DAC_CLK_IN_SEL;
  850. break;
  851. case CPCAP_DAI_VOICE:
  852. clkfreqreg = CPCAP_REG_CC;
  853. clkfreqshift = CPCAP_BIT_CDC_CLK0;
  854. clkidreg = CPCAP_REG_CDI;
  855. clkidshift = CPCAP_BIT_CLK_IN_SEL;
  856. break;
  857. default:
  858. dev_err(cpcap->component->dev, "invalid DAI: %d", dai);
  859. return -EINVAL;
  860. }
  861. /* setup clk id */
  862. if (clk_id < 0 || clk_id > 1) {
  863. dev_err(cpcap->component->dev, "invalid clk id %d", clk_id);
  864. return -EINVAL;
  865. }
  866. err = regmap_update_bits(cpcap->regmap, clkidreg, BIT(clkidshift),
  867. clk_id ? BIT(clkidshift) : 0);
  868. if (err)
  869. return err;
  870. /* enable PLL for Voice DAI */
  871. if (dai == CPCAP_DAI_VOICE) {
  872. mask = BIT(CPCAP_BIT_CDC_PLL_SEL);
  873. val = BIT(CPCAP_BIT_CDC_PLL_SEL);
  874. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
  875. mask, val);
  876. if (err)
  877. return err;
  878. }
  879. /* setup frequency */
  880. clkfreqmask = 0x7 << clkfreqshift;
  881. switch (freq) {
  882. case 15360000:
  883. clkfreqval = 0x01 << clkfreqshift;
  884. break;
  885. case 16800000:
  886. clkfreqval = 0x02 << clkfreqshift;
  887. break;
  888. case 19200000:
  889. clkfreqval = 0x03 << clkfreqshift;
  890. break;
  891. case 26000000:
  892. clkfreqval = 0x04 << clkfreqshift;
  893. break;
  894. case 33600000:
  895. clkfreqval = 0x05 << clkfreqshift;
  896. break;
  897. case 38400000:
  898. clkfreqval = 0x06 << clkfreqshift;
  899. break;
  900. default:
  901. dev_err(cpcap->component->dev, "unsupported freq %u", freq);
  902. return -EINVAL;
  903. }
  904. err = regmap_update_bits(cpcap->regmap, clkfreqreg,
  905. clkfreqmask, clkfreqval);
  906. if (err)
  907. return err;
  908. if (dai == CPCAP_DAI_VOICE) {
  909. cpcap->codec_clk_id = clk_id;
  910. cpcap->codec_freq = freq;
  911. }
  912. return 0;
  913. }
  914. static int cpcap_set_samprate(struct cpcap_audio *cpcap, enum cpcap_dai dai,
  915. int samplerate)
  916. {
  917. struct snd_soc_component *component = cpcap->component;
  918. u16 sampreg, sampmask, sampshift, sampval, sampreset;
  919. int err, sampreadval;
  920. switch (dai) {
  921. case CPCAP_DAI_HIFI:
  922. sampreg = CPCAP_REG_SDAC;
  923. sampshift = CPCAP_BIT_ST_SR0;
  924. sampreset = BIT(CPCAP_BIT_DF_RESET_ST_DAC) |
  925. BIT(CPCAP_BIT_ST_CLOCK_TREE_RESET);
  926. break;
  927. case CPCAP_DAI_VOICE:
  928. sampreg = CPCAP_REG_CC;
  929. sampshift = CPCAP_BIT_CDC_SR0;
  930. sampreset = BIT(CPCAP_BIT_DF_RESET) |
  931. BIT(CPCAP_BIT_CDC_CLOCK_TREE_RESET);
  932. break;
  933. default:
  934. dev_err(component->dev, "invalid DAI: %d", dai);
  935. return -EINVAL;
  936. }
  937. sampmask = 0xF << sampshift | sampreset;
  938. switch (samplerate) {
  939. case 48000:
  940. sampval = 0x8 << sampshift;
  941. break;
  942. case 44100:
  943. sampval = 0x7 << sampshift;
  944. break;
  945. case 32000:
  946. sampval = 0x6 << sampshift;
  947. break;
  948. case 24000:
  949. sampval = 0x5 << sampshift;
  950. break;
  951. case 22050:
  952. sampval = 0x4 << sampshift;
  953. break;
  954. case 16000:
  955. sampval = 0x3 << sampshift;
  956. break;
  957. case 12000:
  958. sampval = 0x2 << sampshift;
  959. break;
  960. case 11025:
  961. sampval = 0x1 << sampshift;
  962. break;
  963. case 8000:
  964. sampval = 0x0 << sampshift;
  965. break;
  966. default:
  967. dev_err(component->dev, "unsupported samplerate %d", samplerate);
  968. return -EINVAL;
  969. }
  970. err = regmap_update_bits(cpcap->regmap, sampreg,
  971. sampmask, sampval | sampreset);
  972. if (err)
  973. return err;
  974. /* Wait for clock tree reset to complete */
  975. mdelay(CLOCK_TREE_RESET_TIME);
  976. err = regmap_read(cpcap->regmap, sampreg, &sampreadval);
  977. if (err)
  978. return err;
  979. if (sampreadval & sampreset) {
  980. dev_err(component->dev, "reset self-clear failed: %04x",
  981. sampreadval);
  982. return -EIO;
  983. }
  984. return 0;
  985. }
  986. static int cpcap_hifi_hw_params(struct snd_pcm_substream *substream,
  987. struct snd_pcm_hw_params *params,
  988. struct snd_soc_dai *dai)
  989. {
  990. struct snd_soc_component *component = dai->component;
  991. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  992. int rate = params_rate(params);
  993. dev_dbg(component->dev, "HiFi setup HW params: rate=%d", rate);
  994. return cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, rate);
  995. }
  996. static int cpcap_hifi_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
  997. unsigned int freq, int dir)
  998. {
  999. struct snd_soc_component *component = codec_dai->component;
  1000. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1001. struct device *dev = component->dev;
  1002. dev_dbg(dev, "HiFi setup sysclk: clk_id=%u, freq=%u", clk_id, freq);
  1003. return cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, clk_id, freq);
  1004. }
  1005. static int cpcap_hifi_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1006. unsigned int fmt)
  1007. {
  1008. struct snd_soc_component *component = codec_dai->component;
  1009. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1010. struct device *dev = component->dev;
  1011. static const u16 reg = CPCAP_REG_SDACDI;
  1012. static const u16 mask =
  1013. BIT(CPCAP_BIT_SMB_ST_DAC) |
  1014. BIT(CPCAP_BIT_ST_CLK_INV) |
  1015. BIT(CPCAP_BIT_ST_FS_INV) |
  1016. BIT(CPCAP_BIT_ST_DIG_AUD_FS0) |
  1017. BIT(CPCAP_BIT_ST_DIG_AUD_FS1) |
  1018. BIT(CPCAP_BIT_ST_L_TIMESLOT0) |
  1019. BIT(CPCAP_BIT_ST_L_TIMESLOT1) |
  1020. BIT(CPCAP_BIT_ST_L_TIMESLOT2) |
  1021. BIT(CPCAP_BIT_ST_R_TIMESLOT0) |
  1022. BIT(CPCAP_BIT_ST_R_TIMESLOT1) |
  1023. BIT(CPCAP_BIT_ST_R_TIMESLOT2);
  1024. u16 val = 0x0000;
  1025. dev_dbg(dev, "HiFi setup dai format (%08x)", fmt);
  1026. /*
  1027. * "HiFi Playback" should always be configured as
  1028. * SND_SOC_DAIFMT_CBM_CFM - codec clk & frm master
  1029. * SND_SOC_DAIFMT_I2S - I2S mode
  1030. */
  1031. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1032. case SND_SOC_DAIFMT_CBM_CFM:
  1033. val &= ~BIT(CPCAP_BIT_SMB_ST_DAC);
  1034. break;
  1035. default:
  1036. dev_err(dev, "HiFi dai fmt failed: CPCAP should be master");
  1037. return -EINVAL;
  1038. }
  1039. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1040. case SND_SOC_DAIFMT_IB_IF:
  1041. val |= BIT(CPCAP_BIT_ST_FS_INV);
  1042. val |= BIT(CPCAP_BIT_ST_CLK_INV);
  1043. break;
  1044. case SND_SOC_DAIFMT_IB_NF:
  1045. val &= ~BIT(CPCAP_BIT_ST_FS_INV);
  1046. val |= BIT(CPCAP_BIT_ST_CLK_INV);
  1047. break;
  1048. case SND_SOC_DAIFMT_NB_IF:
  1049. val |= BIT(CPCAP_BIT_ST_FS_INV);
  1050. val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
  1051. break;
  1052. case SND_SOC_DAIFMT_NB_NF:
  1053. val &= ~BIT(CPCAP_BIT_ST_FS_INV);
  1054. val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
  1055. break;
  1056. default:
  1057. dev_err(dev, "HiFi dai fmt failed: unsupported clock invert mode");
  1058. return -EINVAL;
  1059. }
  1060. if (val & BIT(CPCAP_BIT_ST_CLK_INV))
  1061. val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
  1062. else
  1063. val |= BIT(CPCAP_BIT_ST_CLK_INV);
  1064. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1065. case SND_SOC_DAIFMT_I2S:
  1066. val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0);
  1067. val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS1);
  1068. break;
  1069. default:
  1070. /* 01 - 4 slots network mode */
  1071. val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0);
  1072. val &= ~BIT(CPCAP_BIT_ST_DIG_AUD_FS1);
  1073. /* L on slot 1 */
  1074. val |= BIT(CPCAP_BIT_ST_L_TIMESLOT0);
  1075. break;
  1076. }
  1077. dev_dbg(dev, "HiFi dai format: val=%04x", val);
  1078. return regmap_update_bits(cpcap->regmap, reg, mask, val);
  1079. }
  1080. static int cpcap_hifi_set_mute(struct snd_soc_dai *dai, int mute, int direction)
  1081. {
  1082. struct snd_soc_component *component = dai->component;
  1083. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1084. static const u16 reg = CPCAP_REG_RXSDOA;
  1085. static const u16 mask = BIT(CPCAP_BIT_ST_DAC_SW);
  1086. u16 val;
  1087. if (mute)
  1088. val = 0;
  1089. else
  1090. val = BIT(CPCAP_BIT_ST_DAC_SW);
  1091. dev_dbg(component->dev, "HiFi mute: %d", mute);
  1092. return regmap_update_bits(cpcap->regmap, reg, mask, val);
  1093. }
  1094. static const struct snd_soc_dai_ops cpcap_dai_hifi_ops = {
  1095. .hw_params = cpcap_hifi_hw_params,
  1096. .set_sysclk = cpcap_hifi_set_dai_sysclk,
  1097. .set_fmt = cpcap_hifi_set_dai_fmt,
  1098. .mute_stream = cpcap_hifi_set_mute,
  1099. .no_capture_mute = 1,
  1100. };
  1101. static int cpcap_voice_hw_params(struct snd_pcm_substream *substream,
  1102. struct snd_pcm_hw_params *params,
  1103. struct snd_soc_dai *dai)
  1104. {
  1105. struct snd_soc_component *component = dai->component;
  1106. struct device *dev = component->dev;
  1107. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1108. static const u16 reg_cdi = CPCAP_REG_CDI;
  1109. int rate = params_rate(params);
  1110. int channels = params_channels(params);
  1111. int direction = substream->stream;
  1112. u16 val, mask;
  1113. int err;
  1114. dev_dbg(dev, "Voice setup HW params: rate=%d, direction=%d, chan=%d",
  1115. rate, direction, channels);
  1116. err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, rate);
  1117. if (err)
  1118. return err;
  1119. if (direction == SNDRV_PCM_STREAM_CAPTURE) {
  1120. mask = 0x0000;
  1121. mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0);
  1122. mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT1);
  1123. mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT2);
  1124. mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT0);
  1125. mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT1);
  1126. mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT2);
  1127. val = 0x0000;
  1128. if (channels >= 2)
  1129. val = BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0);
  1130. err = regmap_update_bits(cpcap->regmap, reg_cdi, mask, val);
  1131. if (err)
  1132. return err;
  1133. }
  1134. return 0;
  1135. }
  1136. static int cpcap_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
  1137. unsigned int freq, int dir)
  1138. {
  1139. struct snd_soc_component *component = codec_dai->component;
  1140. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1141. dev_dbg(component->dev, "Voice setup sysclk: clk_id=%u, freq=%u",
  1142. clk_id, freq);
  1143. return cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, clk_id, freq);
  1144. }
  1145. static int cpcap_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1146. unsigned int fmt)
  1147. {
  1148. struct snd_soc_component *component = codec_dai->component;
  1149. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1150. static const u16 mask = BIT(CPCAP_BIT_SMB_CDC) |
  1151. BIT(CPCAP_BIT_CLK_INV) |
  1152. BIT(CPCAP_BIT_FS_INV) |
  1153. BIT(CPCAP_BIT_CDC_DIG_AUD_FS0) |
  1154. BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
  1155. u16 val = 0x0000;
  1156. int err;
  1157. dev_dbg(component->dev, "Voice setup dai format (%08x)", fmt);
  1158. /*
  1159. * "Voice Playback" and "Voice Capture" should always be
  1160. * configured as SND_SOC_DAIFMT_CBM_CFM - codec clk & frm
  1161. * master
  1162. */
  1163. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1164. case SND_SOC_DAIFMT_CBM_CFM:
  1165. val &= ~BIT(CPCAP_BIT_SMB_CDC);
  1166. break;
  1167. default:
  1168. dev_err(component->dev, "Voice dai fmt failed: CPCAP should be the master");
  1169. val &= ~BIT(CPCAP_BIT_SMB_CDC);
  1170. break;
  1171. }
  1172. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1173. case SND_SOC_DAIFMT_IB_IF:
  1174. val |= BIT(CPCAP_BIT_CLK_INV);
  1175. val |= BIT(CPCAP_BIT_FS_INV);
  1176. break;
  1177. case SND_SOC_DAIFMT_IB_NF:
  1178. val |= BIT(CPCAP_BIT_CLK_INV);
  1179. val &= ~BIT(CPCAP_BIT_FS_INV);
  1180. break;
  1181. case SND_SOC_DAIFMT_NB_IF:
  1182. val &= ~BIT(CPCAP_BIT_CLK_INV);
  1183. val |= BIT(CPCAP_BIT_FS_INV);
  1184. break;
  1185. case SND_SOC_DAIFMT_NB_NF:
  1186. val &= ~BIT(CPCAP_BIT_CLK_INV);
  1187. val &= ~BIT(CPCAP_BIT_FS_INV);
  1188. break;
  1189. default:
  1190. dev_err(component->dev, "Voice dai fmt failed: unsupported clock invert mode");
  1191. break;
  1192. }
  1193. if (val & BIT(CPCAP_BIT_CLK_INV))
  1194. val &= ~BIT(CPCAP_BIT_CLK_INV);
  1195. else
  1196. val |= BIT(CPCAP_BIT_CLK_INV);
  1197. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1198. case SND_SOC_DAIFMT_I2S:
  1199. /* 11 - true I2S mode */
  1200. val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0);
  1201. val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
  1202. break;
  1203. default:
  1204. /* 4 timeslots network mode */
  1205. val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0);
  1206. val &= ~BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
  1207. break;
  1208. }
  1209. dev_dbg(component->dev, "Voice dai format: val=%04x", val);
  1210. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, mask, val);
  1211. if (err)
  1212. return err;
  1213. cpcap->codec_format = val;
  1214. return 0;
  1215. }
  1216. static int cpcap_voice_set_mute(struct snd_soc_dai *dai,
  1217. int mute, int direction)
  1218. {
  1219. struct snd_soc_component *component = dai->component;
  1220. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1221. static const u16 reg = CPCAP_REG_RXCOA;
  1222. static const u16 mask = BIT(CPCAP_BIT_CDC_SW);
  1223. u16 val;
  1224. if (mute)
  1225. val = 0;
  1226. else
  1227. val = BIT(CPCAP_BIT_CDC_SW);
  1228. dev_dbg(component->dev, "Voice mute: %d", mute);
  1229. return regmap_update_bits(cpcap->regmap, reg, mask, val);
  1230. };
  1231. static const struct snd_soc_dai_ops cpcap_dai_voice_ops = {
  1232. .hw_params = cpcap_voice_hw_params,
  1233. .set_sysclk = cpcap_voice_set_dai_sysclk,
  1234. .set_fmt = cpcap_voice_set_dai_fmt,
  1235. .mute_stream = cpcap_voice_set_mute,
  1236. .no_capture_mute = 1,
  1237. };
  1238. static struct snd_soc_dai_driver cpcap_dai[] = {
  1239. {
  1240. .id = 0,
  1241. .name = "cpcap-hifi",
  1242. .playback = {
  1243. .stream_name = "HiFi Playback",
  1244. .channels_min = 2,
  1245. .channels_max = 2,
  1246. .rates = SNDRV_PCM_RATE_8000_48000,
  1247. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE,
  1248. },
  1249. .ops = &cpcap_dai_hifi_ops,
  1250. },
  1251. {
  1252. .id = 1,
  1253. .name = "cpcap-voice",
  1254. .playback = {
  1255. .stream_name = "Voice Playback",
  1256. .channels_min = 1,
  1257. .channels_max = 1,
  1258. .rates = SNDRV_PCM_RATE_8000_48000,
  1259. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1260. },
  1261. .capture = {
  1262. .stream_name = "Voice Capture",
  1263. .channels_min = 1,
  1264. .channels_max = 2,
  1265. .rates = SNDRV_PCM_RATE_8000_48000,
  1266. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1267. },
  1268. .ops = &cpcap_dai_voice_ops,
  1269. },
  1270. };
  1271. static int cpcap_dai_mux(struct cpcap_audio *cpcap, bool swap_dai_configuration)
  1272. {
  1273. u16 hifi_val, voice_val;
  1274. u16 hifi_mask = BIT(CPCAP_BIT_DIG_AUD_IN_ST_DAC);
  1275. u16 voice_mask = BIT(CPCAP_BIT_DIG_AUD_IN);
  1276. int err;
  1277. if (!swap_dai_configuration) {
  1278. /* Codec on DAI0, HiFi on DAI1 */
  1279. voice_val = 0;
  1280. hifi_val = hifi_mask;
  1281. } else {
  1282. /* Codec on DAI1, HiFi on DAI0 */
  1283. voice_val = voice_mask;
  1284. hifi_val = 0;
  1285. }
  1286. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
  1287. voice_mask, voice_val);
  1288. if (err)
  1289. return err;
  1290. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_SDACDI,
  1291. hifi_mask, hifi_val);
  1292. if (err)
  1293. return err;
  1294. return 0;
  1295. }
  1296. static int cpcap_audio_reset(struct snd_soc_component *component,
  1297. bool swap_dai_configuration)
  1298. {
  1299. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1300. int i, err = 0;
  1301. dev_dbg(component->dev, "init audio codec");
  1302. for (i = 0; i < ARRAY_SIZE(cpcap_default_regs); i++) {
  1303. err = regmap_update_bits(cpcap->regmap,
  1304. cpcap_default_regs[i].reg,
  1305. cpcap_default_regs[i].mask,
  1306. cpcap_default_regs[i].val);
  1307. if (err)
  1308. return err;
  1309. }
  1310. /* setup default settings */
  1311. err = cpcap_dai_mux(cpcap, swap_dai_configuration);
  1312. if (err)
  1313. return err;
  1314. err = cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, 0, 26000000);
  1315. if (err)
  1316. return err;
  1317. err = cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, 0, 26000000);
  1318. if (err)
  1319. return err;
  1320. err = cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, 48000);
  1321. if (err)
  1322. return err;
  1323. err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, 48000);
  1324. if (err)
  1325. return err;
  1326. return 0;
  1327. }
  1328. static int cpcap_soc_probe(struct snd_soc_component *component)
  1329. {
  1330. struct cpcap_audio *cpcap;
  1331. int err;
  1332. cpcap = devm_kzalloc(component->dev, sizeof(*cpcap), GFP_KERNEL);
  1333. if (!cpcap)
  1334. return -ENOMEM;
  1335. snd_soc_component_set_drvdata(component, cpcap);
  1336. cpcap->component = component;
  1337. cpcap->regmap = dev_get_regmap(component->dev->parent, NULL);
  1338. if (!cpcap->regmap)
  1339. return -ENODEV;
  1340. snd_soc_component_init_regmap(component, cpcap->regmap);
  1341. err = cpcap_get_vendor(component->dev, cpcap->regmap, &cpcap->vendor);
  1342. if (err)
  1343. return err;
  1344. return cpcap_audio_reset(component, false);
  1345. }
  1346. static struct snd_soc_component_driver soc_codec_dev_cpcap = {
  1347. .probe = cpcap_soc_probe,
  1348. .controls = cpcap_snd_controls,
  1349. .num_controls = ARRAY_SIZE(cpcap_snd_controls),
  1350. .dapm_widgets = cpcap_dapm_widgets,
  1351. .num_dapm_widgets = ARRAY_SIZE(cpcap_dapm_widgets),
  1352. .dapm_routes = intercon,
  1353. .num_dapm_routes = ARRAY_SIZE(intercon),
  1354. .idle_bias_on = 1,
  1355. .use_pmdown_time = 1,
  1356. .endianness = 1,
  1357. .non_legacy_dai_naming = 1,
  1358. };
  1359. static int cpcap_codec_probe(struct platform_device *pdev)
  1360. {
  1361. struct device_node *codec_node =
  1362. of_get_child_by_name(pdev->dev.parent->of_node, "audio-codec");
  1363. if (!codec_node)
  1364. return -ENODEV;
  1365. pdev->dev.of_node = codec_node;
  1366. return devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_cpcap,
  1367. cpcap_dai, ARRAY_SIZE(cpcap_dai));
  1368. }
  1369. static struct platform_driver cpcap_codec_driver = {
  1370. .probe = cpcap_codec_probe,
  1371. .driver = {
  1372. .name = "cpcap-codec",
  1373. },
  1374. };
  1375. module_platform_driver(cpcap_codec_driver);
  1376. MODULE_ALIAS("platform:cpcap-codec");
  1377. MODULE_DESCRIPTION("ASoC CPCAP codec driver");
  1378. MODULE_AUTHOR("Sebastian Reichel");
  1379. MODULE_LICENSE("GPL v2");