ak4642.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
  4. //
  5. // Copyright (C) 2009 Renesas Solutions Corp.
  6. // Kuninori Morimoto <morimoto.kuninori@renesas.com>
  7. //
  8. // Based on wm8731.c by Richard Purdie
  9. // Based on ak4535.c by Richard Purdie
  10. // Based on wm8753.c by Liam Girdwood
  11. /* ** CAUTION **
  12. *
  13. * This is very simple driver.
  14. * It can use headphone output / stereo input only
  15. *
  16. * AK4642 is tested.
  17. * AK4643 is tested.
  18. * AK4648 is tested.
  19. */
  20. #include <linux/clk.h>
  21. #include <linux/clk-provider.h>
  22. #include <linux/delay.h>
  23. #include <linux/i2c.h>
  24. #include <linux/slab.h>
  25. #include <linux/of_device.h>
  26. #include <linux/module.h>
  27. #include <linux/regmap.h>
  28. #include <sound/soc.h>
  29. #include <sound/initval.h>
  30. #include <sound/tlv.h>
  31. #define PW_MGMT1 0x00
  32. #define PW_MGMT2 0x01
  33. #define SG_SL1 0x02
  34. #define SG_SL2 0x03
  35. #define MD_CTL1 0x04
  36. #define MD_CTL2 0x05
  37. #define TIMER 0x06
  38. #define ALC_CTL1 0x07
  39. #define ALC_CTL2 0x08
  40. #define L_IVC 0x09
  41. #define L_DVC 0x0a
  42. #define ALC_CTL3 0x0b
  43. #define R_IVC 0x0c
  44. #define R_DVC 0x0d
  45. #define MD_CTL3 0x0e
  46. #define MD_CTL4 0x0f
  47. #define PW_MGMT3 0x10
  48. #define DF_S 0x11
  49. #define FIL3_0 0x12
  50. #define FIL3_1 0x13
  51. #define FIL3_2 0x14
  52. #define FIL3_3 0x15
  53. #define EQ_0 0x16
  54. #define EQ_1 0x17
  55. #define EQ_2 0x18
  56. #define EQ_3 0x19
  57. #define EQ_4 0x1a
  58. #define EQ_5 0x1b
  59. #define FIL1_0 0x1c
  60. #define FIL1_1 0x1d
  61. #define FIL1_2 0x1e
  62. #define FIL1_3 0x1f /* The maximum valid register for ak4642 */
  63. #define PW_MGMT4 0x20
  64. #define MD_CTL5 0x21
  65. #define LO_MS 0x22
  66. #define HP_MS 0x23
  67. #define SPK_MS 0x24 /* The maximum valid register for ak4643 */
  68. #define EQ_FBEQAB 0x25
  69. #define EQ_FBEQCD 0x26
  70. #define EQ_FBEQE 0x27 /* The maximum valid register for ak4648 */
  71. /* PW_MGMT1*/
  72. #define PMVCM (1 << 6) /* VCOM Power Management */
  73. #define PMMIN (1 << 5) /* MIN Input Power Management */
  74. #define PMDAC (1 << 2) /* DAC Power Management */
  75. #define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
  76. /* PW_MGMT2 */
  77. #define HPMTN (1 << 6)
  78. #define PMHPL (1 << 5)
  79. #define PMHPR (1 << 4)
  80. #define MS (1 << 3) /* master/slave select */
  81. #define MCKO (1 << 1)
  82. #define PMPLL (1 << 0)
  83. #define PMHP_MASK (PMHPL | PMHPR)
  84. #define PMHP PMHP_MASK
  85. /* PW_MGMT3 */
  86. #define PMADR (1 << 0) /* MIC L / ADC R Power Management */
  87. /* SG_SL1 */
  88. #define MINS (1 << 6) /* Switch from MIN to Speaker */
  89. #define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
  90. #define PMMP (1 << 2) /* MPWR pin Power Management */
  91. #define MGAIN0 (1 << 0) /* MIC amp gain*/
  92. /* SG_SL2 */
  93. #define LOPS (1 << 6) /* Stero Line-out Power Save Mode */
  94. /* TIMER */
  95. #define ZTM(param) ((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */
  96. #define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2))
  97. /* ALC_CTL1 */
  98. #define ALC (1 << 5) /* ALC Enable */
  99. #define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
  100. /* MD_CTL1 */
  101. #define PLL3 (1 << 7)
  102. #define PLL2 (1 << 6)
  103. #define PLL1 (1 << 5)
  104. #define PLL0 (1 << 4)
  105. #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
  106. #define BCKO_MASK (1 << 3)
  107. #define BCKO_64 BCKO_MASK
  108. #define DIF_MASK (3 << 0)
  109. #define DSP (0 << 0)
  110. #define RIGHT_J (1 << 0)
  111. #define LEFT_J (2 << 0)
  112. #define I2S (3 << 0)
  113. /* MD_CTL2 */
  114. #define FSs(val) (((val & 0x7) << 0) | ((val & 0x8) << 2))
  115. #define PSs(val) ((val & 0x3) << 6)
  116. /* MD_CTL3 */
  117. #define BST1 (1 << 3)
  118. /* MD_CTL4 */
  119. #define DACH (1 << 0)
  120. struct ak4642_drvdata {
  121. const struct regmap_config *regmap_config;
  122. int extended_frequencies;
  123. };
  124. struct ak4642_priv {
  125. const struct ak4642_drvdata *drvdata;
  126. struct clk *mcko;
  127. };
  128. /*
  129. * Playback Volume (table 39)
  130. *
  131. * max : 0x00 : +12.0 dB
  132. * ( 0.5 dB step )
  133. * min : 0xFE : -115.0 dB
  134. * mute: 0xFF
  135. */
  136. static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
  137. static const struct snd_kcontrol_new ak4642_snd_controls[] = {
  138. SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
  139. 0, 0xFF, 1, out_tlv),
  140. SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0),
  141. SOC_SINGLE("ALC Capture ZC Switch", ALC_CTL1, 4, 1, 1),
  142. };
  143. static const struct snd_kcontrol_new ak4642_headphone_control =
  144. SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
  145. static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
  146. SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
  147. };
  148. /* event handlers */
  149. static int ak4642_lout_event(struct snd_soc_dapm_widget *w,
  150. struct snd_kcontrol *kcontrol, int event)
  151. {
  152. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  153. switch (event) {
  154. case SND_SOC_DAPM_PRE_PMD:
  155. case SND_SOC_DAPM_PRE_PMU:
  156. /* Power save mode ON */
  157. snd_soc_component_update_bits(component, SG_SL2, LOPS, LOPS);
  158. break;
  159. case SND_SOC_DAPM_POST_PMU:
  160. case SND_SOC_DAPM_POST_PMD:
  161. /* Power save mode OFF */
  162. msleep(300);
  163. snd_soc_component_update_bits(component, SG_SL2, LOPS, 0);
  164. break;
  165. }
  166. return 0;
  167. }
  168. static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
  169. /* Outputs */
  170. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  171. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  172. SND_SOC_DAPM_OUTPUT("LINEOUT"),
  173. SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
  174. SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
  175. SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
  176. &ak4642_headphone_control),
  177. SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
  178. SND_SOC_DAPM_MIXER_E("LINEOUT Mixer", PW_MGMT1, 3, 0,
  179. &ak4642_lout_mixer_controls[0],
  180. ARRAY_SIZE(ak4642_lout_mixer_controls),
  181. ak4642_lout_event,
  182. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  183. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  184. /* DAC */
  185. SND_SOC_DAPM_DAC("DAC", NULL, PW_MGMT1, 2, 0),
  186. };
  187. static const struct snd_soc_dapm_route ak4642_intercon[] = {
  188. /* Outputs */
  189. {"HPOUTL", NULL, "HPL Out"},
  190. {"HPOUTR", NULL, "HPR Out"},
  191. {"LINEOUT", NULL, "LINEOUT Mixer"},
  192. {"HPL Out", NULL, "Headphone Enable"},
  193. {"HPR Out", NULL, "Headphone Enable"},
  194. {"Headphone Enable", "Switch", "DACH"},
  195. {"DACH", NULL, "DAC"},
  196. {"LINEOUT Mixer", "DACL", "DAC"},
  197. { "DAC", NULL, "Playback" },
  198. };
  199. /*
  200. * ak4642 register cache
  201. */
  202. static const struct reg_default ak4643_reg[] = {
  203. { 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
  204. { 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
  205. { 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
  206. { 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
  207. { 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
  208. { 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
  209. { 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
  210. { 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
  211. { 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
  212. { 36, 0x00 },
  213. };
  214. /* The default settings for 0x0 ~ 0x1f registers are the same for ak4642
  215. and ak4643. So we reuse the ak4643 reg_default for ak4642.
  216. The valid registers for ak4642 are 0x0 ~ 0x1f which is a subset of ak4643,
  217. so define NUM_AK4642_REG_DEFAULTS for ak4642.
  218. */
  219. #define ak4642_reg ak4643_reg
  220. #define NUM_AK4642_REG_DEFAULTS (FIL1_3 + 1)
  221. static const struct reg_default ak4648_reg[] = {
  222. { 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
  223. { 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
  224. { 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
  225. { 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
  226. { 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
  227. { 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
  228. { 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
  229. { 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
  230. { 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
  231. { 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
  232. };
  233. static int ak4642_dai_startup(struct snd_pcm_substream *substream,
  234. struct snd_soc_dai *dai)
  235. {
  236. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  237. struct snd_soc_component *component = dai->component;
  238. if (is_play) {
  239. /*
  240. * start headphone output
  241. *
  242. * PLL, Master Mode
  243. * Audio I/F Format :MSB justified (ADC & DAC)
  244. * Bass Boost Level : Middle
  245. *
  246. * This operation came from example code of
  247. * "ASAHI KASEI AK4642" (japanese) manual p97.
  248. */
  249. snd_soc_component_write(component, L_IVC, 0x91); /* volume */
  250. snd_soc_component_write(component, R_IVC, 0x91); /* volume */
  251. } else {
  252. /*
  253. * start stereo input
  254. *
  255. * PLL Master Mode
  256. * Audio I/F Format:MSB justified (ADC & DAC)
  257. * Pre MIC AMP:+20dB
  258. * MIC Power On
  259. * ALC setting:Refer to Table 35
  260. * ALC bit=“1”
  261. *
  262. * This operation came from example code of
  263. * "ASAHI KASEI AK4642" (japanese) manual p94.
  264. */
  265. snd_soc_component_update_bits(component, SG_SL1, PMMP | MGAIN0, PMMP | MGAIN0);
  266. snd_soc_component_write(component, TIMER, ZTM(0x3) | WTM(0x3));
  267. snd_soc_component_write(component, ALC_CTL1, ALC | LMTH0);
  268. snd_soc_component_update_bits(component, PW_MGMT1, PMADL, PMADL);
  269. snd_soc_component_update_bits(component, PW_MGMT3, PMADR, PMADR);
  270. }
  271. return 0;
  272. }
  273. static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
  274. struct snd_soc_dai *dai)
  275. {
  276. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  277. struct snd_soc_component *component = dai->component;
  278. if (is_play) {
  279. } else {
  280. /* stop stereo input */
  281. snd_soc_component_update_bits(component, PW_MGMT1, PMADL, 0);
  282. snd_soc_component_update_bits(component, PW_MGMT3, PMADR, 0);
  283. snd_soc_component_update_bits(component, ALC_CTL1, ALC, 0);
  284. }
  285. }
  286. static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
  287. int clk_id, unsigned int freq, int dir)
  288. {
  289. struct snd_soc_component *component = codec_dai->component;
  290. struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
  291. u8 pll;
  292. int extended_freq = 0;
  293. switch (freq) {
  294. case 11289600:
  295. pll = PLL2;
  296. break;
  297. case 12288000:
  298. pll = PLL2 | PLL0;
  299. break;
  300. case 12000000:
  301. pll = PLL2 | PLL1;
  302. break;
  303. case 24000000:
  304. pll = PLL2 | PLL1 | PLL0;
  305. break;
  306. case 13500000:
  307. pll = PLL3 | PLL2;
  308. break;
  309. case 27000000:
  310. pll = PLL3 | PLL2 | PLL0;
  311. break;
  312. case 19200000:
  313. pll = PLL3;
  314. extended_freq = 1;
  315. break;
  316. case 13000000:
  317. pll = PLL3 | PLL2 | PLL1;
  318. extended_freq = 1;
  319. break;
  320. case 26000000:
  321. pll = PLL3 | PLL2 | PLL1 | PLL0;
  322. extended_freq = 1;
  323. break;
  324. default:
  325. return -EINVAL;
  326. }
  327. if (extended_freq && !priv->drvdata->extended_frequencies)
  328. return -EINVAL;
  329. snd_soc_component_update_bits(component, MD_CTL1, PLL_MASK, pll);
  330. return 0;
  331. }
  332. static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  333. {
  334. struct snd_soc_component *component = dai->component;
  335. u8 data;
  336. u8 bcko;
  337. data = MCKO | PMPLL; /* use MCKO */
  338. bcko = 0;
  339. /* set master/slave audio interface */
  340. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  341. case SND_SOC_DAIFMT_CBM_CFM:
  342. data |= MS;
  343. bcko = BCKO_64;
  344. break;
  345. case SND_SOC_DAIFMT_CBS_CFS:
  346. break;
  347. default:
  348. return -EINVAL;
  349. }
  350. snd_soc_component_update_bits(component, PW_MGMT2, MS | MCKO | PMPLL, data);
  351. snd_soc_component_update_bits(component, MD_CTL1, BCKO_MASK, bcko);
  352. /* format type */
  353. data = 0;
  354. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  355. case SND_SOC_DAIFMT_LEFT_J:
  356. data = LEFT_J;
  357. break;
  358. case SND_SOC_DAIFMT_I2S:
  359. data = I2S;
  360. break;
  361. /* FIXME
  362. * Please add RIGHT_J / DSP support here
  363. */
  364. default:
  365. return -EINVAL;
  366. }
  367. snd_soc_component_update_bits(component, MD_CTL1, DIF_MASK, data);
  368. return 0;
  369. }
  370. static int ak4642_set_mcko(struct snd_soc_component *component,
  371. u32 frequency)
  372. {
  373. static const u32 fs_list[] = {
  374. [0] = 8000,
  375. [1] = 12000,
  376. [2] = 16000,
  377. [3] = 24000,
  378. [4] = 7350,
  379. [5] = 11025,
  380. [6] = 14700,
  381. [7] = 22050,
  382. [10] = 32000,
  383. [11] = 48000,
  384. [14] = 29400,
  385. [15] = 44100,
  386. };
  387. static const u32 ps_list[] = {
  388. [0] = 256,
  389. [1] = 128,
  390. [2] = 64,
  391. [3] = 32
  392. };
  393. int ps, fs;
  394. for (ps = 0; ps < ARRAY_SIZE(ps_list); ps++) {
  395. for (fs = 0; fs < ARRAY_SIZE(fs_list); fs++) {
  396. if (frequency == ps_list[ps] * fs_list[fs]) {
  397. snd_soc_component_write(component, MD_CTL2,
  398. PSs(ps) | FSs(fs));
  399. return 0;
  400. }
  401. }
  402. }
  403. return 0;
  404. }
  405. static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
  406. struct snd_pcm_hw_params *params,
  407. struct snd_soc_dai *dai)
  408. {
  409. struct snd_soc_component *component = dai->component;
  410. struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
  411. u32 rate = clk_get_rate(priv->mcko);
  412. if (!rate)
  413. rate = params_rate(params) * 256;
  414. return ak4642_set_mcko(component, rate);
  415. }
  416. static int ak4642_set_bias_level(struct snd_soc_component *component,
  417. enum snd_soc_bias_level level)
  418. {
  419. switch (level) {
  420. case SND_SOC_BIAS_OFF:
  421. snd_soc_component_write(component, PW_MGMT1, 0x00);
  422. break;
  423. default:
  424. snd_soc_component_update_bits(component, PW_MGMT1, PMVCM, PMVCM);
  425. break;
  426. }
  427. return 0;
  428. }
  429. static const struct snd_soc_dai_ops ak4642_dai_ops = {
  430. .startup = ak4642_dai_startup,
  431. .shutdown = ak4642_dai_shutdown,
  432. .set_sysclk = ak4642_dai_set_sysclk,
  433. .set_fmt = ak4642_dai_set_fmt,
  434. .hw_params = ak4642_dai_hw_params,
  435. };
  436. static struct snd_soc_dai_driver ak4642_dai = {
  437. .name = "ak4642-hifi",
  438. .playback = {
  439. .stream_name = "Playback",
  440. .channels_min = 2,
  441. .channels_max = 2,
  442. .rates = SNDRV_PCM_RATE_8000_48000,
  443. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  444. .capture = {
  445. .stream_name = "Capture",
  446. .channels_min = 2,
  447. .channels_max = 2,
  448. .rates = SNDRV_PCM_RATE_8000_48000,
  449. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  450. .ops = &ak4642_dai_ops,
  451. .symmetric_rates = 1,
  452. };
  453. static int ak4642_suspend(struct snd_soc_component *component)
  454. {
  455. struct regmap *regmap = dev_get_regmap(component->dev, NULL);
  456. regcache_cache_only(regmap, true);
  457. regcache_mark_dirty(regmap);
  458. return 0;
  459. }
  460. static int ak4642_resume(struct snd_soc_component *component)
  461. {
  462. struct regmap *regmap = dev_get_regmap(component->dev, NULL);
  463. regcache_cache_only(regmap, false);
  464. regcache_sync(regmap);
  465. return 0;
  466. }
  467. static int ak4642_probe(struct snd_soc_component *component)
  468. {
  469. struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
  470. if (priv->mcko)
  471. ak4642_set_mcko(component, clk_get_rate(priv->mcko));
  472. return 0;
  473. }
  474. static const struct snd_soc_component_driver soc_component_dev_ak4642 = {
  475. .probe = ak4642_probe,
  476. .suspend = ak4642_suspend,
  477. .resume = ak4642_resume,
  478. .set_bias_level = ak4642_set_bias_level,
  479. .controls = ak4642_snd_controls,
  480. .num_controls = ARRAY_SIZE(ak4642_snd_controls),
  481. .dapm_widgets = ak4642_dapm_widgets,
  482. .num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
  483. .dapm_routes = ak4642_intercon,
  484. .num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
  485. .idle_bias_on = 1,
  486. .endianness = 1,
  487. .non_legacy_dai_naming = 1,
  488. };
  489. static const struct regmap_config ak4642_regmap = {
  490. .reg_bits = 8,
  491. .val_bits = 8,
  492. .max_register = FIL1_3,
  493. .reg_defaults = ak4642_reg,
  494. .num_reg_defaults = NUM_AK4642_REG_DEFAULTS,
  495. .cache_type = REGCACHE_RBTREE,
  496. };
  497. static const struct regmap_config ak4643_regmap = {
  498. .reg_bits = 8,
  499. .val_bits = 8,
  500. .max_register = SPK_MS,
  501. .reg_defaults = ak4643_reg,
  502. .num_reg_defaults = ARRAY_SIZE(ak4643_reg),
  503. .cache_type = REGCACHE_RBTREE,
  504. };
  505. static const struct regmap_config ak4648_regmap = {
  506. .reg_bits = 8,
  507. .val_bits = 8,
  508. .max_register = EQ_FBEQE,
  509. .reg_defaults = ak4648_reg,
  510. .num_reg_defaults = ARRAY_SIZE(ak4648_reg),
  511. .cache_type = REGCACHE_RBTREE,
  512. };
  513. static const struct ak4642_drvdata ak4642_drvdata = {
  514. .regmap_config = &ak4642_regmap,
  515. };
  516. static const struct ak4642_drvdata ak4643_drvdata = {
  517. .regmap_config = &ak4643_regmap,
  518. };
  519. static const struct ak4642_drvdata ak4648_drvdata = {
  520. .regmap_config = &ak4648_regmap,
  521. .extended_frequencies = 1,
  522. };
  523. #ifdef CONFIG_COMMON_CLK
  524. static struct clk *ak4642_of_parse_mcko(struct device *dev)
  525. {
  526. struct device_node *np = dev->of_node;
  527. struct clk *clk;
  528. const char *clk_name = np->name;
  529. const char *parent_clk_name = NULL;
  530. u32 rate;
  531. if (of_property_read_u32(np, "clock-frequency", &rate))
  532. return NULL;
  533. if (of_property_read_bool(np, "clocks"))
  534. parent_clk_name = of_clk_get_parent_name(np, 0);
  535. of_property_read_string(np, "clock-output-names", &clk_name);
  536. clk = clk_register_fixed_rate(dev, clk_name, parent_clk_name, 0, rate);
  537. if (!IS_ERR(clk))
  538. of_clk_add_provider(np, of_clk_src_simple_get, clk);
  539. return clk;
  540. }
  541. #else
  542. #define ak4642_of_parse_mcko(d) 0
  543. #endif
  544. static const struct of_device_id ak4642_of_match[];
  545. static int ak4642_i2c_probe(struct i2c_client *i2c,
  546. const struct i2c_device_id *id)
  547. {
  548. struct device *dev = &i2c->dev;
  549. struct device_node *np = dev->of_node;
  550. const struct ak4642_drvdata *drvdata = NULL;
  551. struct regmap *regmap;
  552. struct ak4642_priv *priv;
  553. struct clk *mcko = NULL;
  554. if (np) {
  555. const struct of_device_id *of_id;
  556. mcko = ak4642_of_parse_mcko(dev);
  557. if (IS_ERR(mcko))
  558. mcko = NULL;
  559. of_id = of_match_device(ak4642_of_match, dev);
  560. if (of_id)
  561. drvdata = of_id->data;
  562. } else {
  563. drvdata = (const struct ak4642_drvdata *)id->driver_data;
  564. }
  565. if (!drvdata) {
  566. dev_err(dev, "Unknown device type\n");
  567. return -EINVAL;
  568. }
  569. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  570. if (!priv)
  571. return -ENOMEM;
  572. priv->drvdata = drvdata;
  573. priv->mcko = mcko;
  574. i2c_set_clientdata(i2c, priv);
  575. regmap = devm_regmap_init_i2c(i2c, drvdata->regmap_config);
  576. if (IS_ERR(regmap))
  577. return PTR_ERR(regmap);
  578. return devm_snd_soc_register_component(dev,
  579. &soc_component_dev_ak4642, &ak4642_dai, 1);
  580. }
  581. static const struct of_device_id ak4642_of_match[] = {
  582. { .compatible = "asahi-kasei,ak4642", .data = &ak4642_drvdata},
  583. { .compatible = "asahi-kasei,ak4643", .data = &ak4643_drvdata},
  584. { .compatible = "asahi-kasei,ak4648", .data = &ak4648_drvdata},
  585. {},
  586. };
  587. MODULE_DEVICE_TABLE(of, ak4642_of_match);
  588. static const struct i2c_device_id ak4642_i2c_id[] = {
  589. { "ak4642", (kernel_ulong_t)&ak4642_drvdata },
  590. { "ak4643", (kernel_ulong_t)&ak4643_drvdata },
  591. { "ak4648", (kernel_ulong_t)&ak4648_drvdata },
  592. { }
  593. };
  594. MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
  595. static struct i2c_driver ak4642_i2c_driver = {
  596. .driver = {
  597. .name = "ak4642-codec",
  598. .of_match_table = ak4642_of_match,
  599. },
  600. .probe = ak4642_i2c_probe,
  601. .id_table = ak4642_i2c_id,
  602. };
  603. module_i2c_driver(ak4642_i2c_driver);
  604. MODULE_DESCRIPTION("Soc AK4642 driver");
  605. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
  606. MODULE_LICENSE("GPL v2");