adav80x.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ADAV80X Audio Codec driver supporting ADAV801, ADAV803
  4. *
  5. * Copyright 2011 Analog Devices Inc.
  6. * Author: Yi Li <yi.li@analog.com>
  7. * Author: Lars-Peter Clausen <lars@metafoo.de>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/kernel.h>
  11. #include <linux/regmap.h>
  12. #include <linux/slab.h>
  13. #include <sound/pcm.h>
  14. #include <sound/pcm_params.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include "adav80x.h"
  18. #define ADAV80X_PLAYBACK_CTRL 0x04
  19. #define ADAV80X_AUX_IN_CTRL 0x05
  20. #define ADAV80X_REC_CTRL 0x06
  21. #define ADAV80X_AUX_OUT_CTRL 0x07
  22. #define ADAV80X_DPATH_CTRL1 0x62
  23. #define ADAV80X_DPATH_CTRL2 0x63
  24. #define ADAV80X_DAC_CTRL1 0x64
  25. #define ADAV80X_DAC_CTRL2 0x65
  26. #define ADAV80X_DAC_CTRL3 0x66
  27. #define ADAV80X_DAC_L_VOL 0x68
  28. #define ADAV80X_DAC_R_VOL 0x69
  29. #define ADAV80X_PGA_L_VOL 0x6c
  30. #define ADAV80X_PGA_R_VOL 0x6d
  31. #define ADAV80X_ADC_CTRL1 0x6e
  32. #define ADAV80X_ADC_CTRL2 0x6f
  33. #define ADAV80X_ADC_L_VOL 0x70
  34. #define ADAV80X_ADC_R_VOL 0x71
  35. #define ADAV80X_PLL_CTRL1 0x74
  36. #define ADAV80X_PLL_CTRL2 0x75
  37. #define ADAV80X_ICLK_CTRL1 0x76
  38. #define ADAV80X_ICLK_CTRL2 0x77
  39. #define ADAV80X_PLL_CLK_SRC 0x78
  40. #define ADAV80X_PLL_OUTE 0x7a
  41. #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00
  42. #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll))
  43. #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll))
  44. #define ADAV80X_ICLK_CTRL1_DAC_SRC(src) ((src) << 5)
  45. #define ADAV80X_ICLK_CTRL1_ADC_SRC(src) ((src) << 2)
  46. #define ADAV80X_ICLK_CTRL1_ICLK2_SRC(src) (src)
  47. #define ADAV80X_ICLK_CTRL2_ICLK1_SRC(src) ((src) << 3)
  48. #define ADAV80X_PLL_CTRL1_PLLDIV 0x10
  49. #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll))
  50. #define ADAV80X_PLL_CTRL1_XTLPD 0x02
  51. #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4))
  52. #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00)
  53. #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08)
  54. #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c)
  55. #define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02)
  56. #define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01)
  57. #define ADAV80X_PLL_CTRL2_PLL_MASK(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0f)
  58. #define ADAV80X_ADC_CTRL1_MODULATOR_MASK 0x80
  59. #define ADAV80X_ADC_CTRL1_MODULATOR_128FS 0x00
  60. #define ADAV80X_ADC_CTRL1_MODULATOR_64FS 0x80
  61. #define ADAV80X_DAC_CTRL1_PD 0x80
  62. #define ADAV80X_DAC_CTRL2_DIV1 0x00
  63. #define ADAV80X_DAC_CTRL2_DIV1_5 0x10
  64. #define ADAV80X_DAC_CTRL2_DIV2 0x20
  65. #define ADAV80X_DAC_CTRL2_DIV3 0x30
  66. #define ADAV80X_DAC_CTRL2_DIV_MASK 0x30
  67. #define ADAV80X_DAC_CTRL2_INTERPOL_256FS 0x00
  68. #define ADAV80X_DAC_CTRL2_INTERPOL_128FS 0x40
  69. #define ADAV80X_DAC_CTRL2_INTERPOL_64FS 0x80
  70. #define ADAV80X_DAC_CTRL2_INTERPOL_MASK 0xc0
  71. #define ADAV80X_DAC_CTRL2_DEEMPH_NONE 0x00
  72. #define ADAV80X_DAC_CTRL2_DEEMPH_44 0x01
  73. #define ADAV80X_DAC_CTRL2_DEEMPH_32 0x02
  74. #define ADAV80X_DAC_CTRL2_DEEMPH_48 0x03
  75. #define ADAV80X_DAC_CTRL2_DEEMPH_MASK 0x01
  76. #define ADAV80X_CAPTURE_MODE_MASTER 0x20
  77. #define ADAV80X_CAPTURE_WORD_LEN24 0x00
  78. #define ADAV80X_CAPTURE_WORD_LEN20 0x04
  79. #define ADAV80X_CAPTRUE_WORD_LEN18 0x08
  80. #define ADAV80X_CAPTURE_WORD_LEN16 0x0c
  81. #define ADAV80X_CAPTURE_WORD_LEN_MASK 0x0c
  82. #define ADAV80X_CAPTURE_MODE_LEFT_J 0x00
  83. #define ADAV80X_CAPTURE_MODE_I2S 0x01
  84. #define ADAV80X_CAPTURE_MODE_RIGHT_J 0x03
  85. #define ADAV80X_CAPTURE_MODE_MASK 0x03
  86. #define ADAV80X_PLAYBACK_MODE_MASTER 0x10
  87. #define ADAV80X_PLAYBACK_MODE_LEFT_J 0x00
  88. #define ADAV80X_PLAYBACK_MODE_I2S 0x01
  89. #define ADAV80X_PLAYBACK_MODE_RIGHT_J_24 0x04
  90. #define ADAV80X_PLAYBACK_MODE_RIGHT_J_20 0x05
  91. #define ADAV80X_PLAYBACK_MODE_RIGHT_J_18 0x06
  92. #define ADAV80X_PLAYBACK_MODE_RIGHT_J_16 0x07
  93. #define ADAV80X_PLAYBACK_MODE_MASK 0x07
  94. #define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x))
  95. static const struct reg_default adav80x_reg_defaults[] = {
  96. { ADAV80X_PLAYBACK_CTRL, 0x01 },
  97. { ADAV80X_AUX_IN_CTRL, 0x01 },
  98. { ADAV80X_REC_CTRL, 0x02 },
  99. { ADAV80X_AUX_OUT_CTRL, 0x01 },
  100. { ADAV80X_DPATH_CTRL1, 0xc0 },
  101. { ADAV80X_DPATH_CTRL2, 0x11 },
  102. { ADAV80X_DAC_CTRL1, 0x00 },
  103. { ADAV80X_DAC_CTRL2, 0x00 },
  104. { ADAV80X_DAC_CTRL3, 0x00 },
  105. { ADAV80X_DAC_L_VOL, 0xff },
  106. { ADAV80X_DAC_R_VOL, 0xff },
  107. { ADAV80X_PGA_L_VOL, 0x00 },
  108. { ADAV80X_PGA_R_VOL, 0x00 },
  109. { ADAV80X_ADC_CTRL1, 0x00 },
  110. { ADAV80X_ADC_CTRL2, 0x00 },
  111. { ADAV80X_ADC_L_VOL, 0xff },
  112. { ADAV80X_ADC_R_VOL, 0xff },
  113. { ADAV80X_PLL_CTRL1, 0x00 },
  114. { ADAV80X_PLL_CTRL2, 0x00 },
  115. { ADAV80X_ICLK_CTRL1, 0x00 },
  116. { ADAV80X_ICLK_CTRL2, 0x00 },
  117. { ADAV80X_PLL_CLK_SRC, 0x00 },
  118. { ADAV80X_PLL_OUTE, 0x00 },
  119. };
  120. struct adav80x {
  121. struct regmap *regmap;
  122. enum adav80x_clk_src clk_src;
  123. unsigned int sysclk;
  124. enum adav80x_pll_src pll_src;
  125. unsigned int dai_fmt[2];
  126. unsigned int rate;
  127. bool deemph;
  128. bool sysclk_pd[3];
  129. };
  130. static const char *adav80x_mux_text[] = {
  131. "ADC",
  132. "Playback",
  133. "Aux Playback",
  134. };
  135. static const unsigned int adav80x_mux_values[] = {
  136. 0, 2, 3,
  137. };
  138. #define ADAV80X_MUX_ENUM_DECL(name, reg, shift) \
  139. SOC_VALUE_ENUM_DOUBLE_DECL(name, reg, shift, 7, \
  140. ARRAY_SIZE(adav80x_mux_text), adav80x_mux_text, \
  141. adav80x_mux_values)
  142. static ADAV80X_MUX_ENUM_DECL(adav80x_aux_capture_enum, ADAV80X_DPATH_CTRL1, 0);
  143. static ADAV80X_MUX_ENUM_DECL(adav80x_capture_enum, ADAV80X_DPATH_CTRL1, 3);
  144. static ADAV80X_MUX_ENUM_DECL(adav80x_dac_enum, ADAV80X_DPATH_CTRL2, 3);
  145. static const struct snd_kcontrol_new adav80x_aux_capture_mux_ctrl =
  146. SOC_DAPM_ENUM("Route", adav80x_aux_capture_enum);
  147. static const struct snd_kcontrol_new adav80x_capture_mux_ctrl =
  148. SOC_DAPM_ENUM("Route", adav80x_capture_enum);
  149. static const struct snd_kcontrol_new adav80x_dac_mux_ctrl =
  150. SOC_DAPM_ENUM("Route", adav80x_dac_enum);
  151. #define ADAV80X_MUX(name, ctrl) \
  152. SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
  153. static const struct snd_soc_dapm_widget adav80x_dapm_widgets[] = {
  154. SND_SOC_DAPM_DAC("DAC", NULL, ADAV80X_DAC_CTRL1, 7, 1),
  155. SND_SOC_DAPM_ADC("ADC", NULL, ADAV80X_ADC_CTRL1, 5, 1),
  156. SND_SOC_DAPM_PGA("Right PGA", ADAV80X_ADC_CTRL1, 0, 1, NULL, 0),
  157. SND_SOC_DAPM_PGA("Left PGA", ADAV80X_ADC_CTRL1, 1, 1, NULL, 0),
  158. SND_SOC_DAPM_AIF_OUT("AIFOUT", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
  159. SND_SOC_DAPM_AIF_IN("AIFIN", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
  160. SND_SOC_DAPM_AIF_OUT("AIFAUXOUT", "Aux Capture", 0, SND_SOC_NOPM, 0, 0),
  161. SND_SOC_DAPM_AIF_IN("AIFAUXIN", "Aux Playback", 0, SND_SOC_NOPM, 0, 0),
  162. ADAV80X_MUX("Aux Capture Select", &adav80x_aux_capture_mux_ctrl),
  163. ADAV80X_MUX("Capture Select", &adav80x_capture_mux_ctrl),
  164. ADAV80X_MUX("DAC Select", &adav80x_dac_mux_ctrl),
  165. SND_SOC_DAPM_INPUT("VINR"),
  166. SND_SOC_DAPM_INPUT("VINL"),
  167. SND_SOC_DAPM_OUTPUT("VOUTR"),
  168. SND_SOC_DAPM_OUTPUT("VOUTL"),
  169. SND_SOC_DAPM_SUPPLY("SYSCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
  170. SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PLL_CTRL1, 2, 1, NULL, 0),
  171. SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0),
  172. SND_SOC_DAPM_SUPPLY("OSC", ADAV80X_PLL_CTRL1, 1, 1, NULL, 0),
  173. };
  174. static int adav80x_dapm_sysclk_check(struct snd_soc_dapm_widget *source,
  175. struct snd_soc_dapm_widget *sink)
  176. {
  177. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  178. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  179. const char *clk;
  180. switch (adav80x->clk_src) {
  181. case ADAV80X_CLK_PLL1:
  182. clk = "PLL1";
  183. break;
  184. case ADAV80X_CLK_PLL2:
  185. clk = "PLL2";
  186. break;
  187. case ADAV80X_CLK_XTAL:
  188. clk = "OSC";
  189. break;
  190. default:
  191. return 0;
  192. }
  193. return strcmp(source->name, clk) == 0;
  194. }
  195. static int adav80x_dapm_pll_check(struct snd_soc_dapm_widget *source,
  196. struct snd_soc_dapm_widget *sink)
  197. {
  198. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  199. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  200. return adav80x->pll_src == ADAV80X_PLL_SRC_XTAL;
  201. }
  202. static const struct snd_soc_dapm_route adav80x_dapm_routes[] = {
  203. { "DAC Select", "ADC", "ADC" },
  204. { "DAC Select", "Playback", "AIFIN" },
  205. { "DAC Select", "Aux Playback", "AIFAUXIN" },
  206. { "DAC", NULL, "DAC Select" },
  207. { "Capture Select", "ADC", "ADC" },
  208. { "Capture Select", "Playback", "AIFIN" },
  209. { "Capture Select", "Aux Playback", "AIFAUXIN" },
  210. { "AIFOUT", NULL, "Capture Select" },
  211. { "Aux Capture Select", "ADC", "ADC" },
  212. { "Aux Capture Select", "Playback", "AIFIN" },
  213. { "Aux Capture Select", "Aux Playback", "AIFAUXIN" },
  214. { "AIFAUXOUT", NULL, "Aux Capture Select" },
  215. { "VOUTR", NULL, "DAC" },
  216. { "VOUTL", NULL, "DAC" },
  217. { "Left PGA", NULL, "VINL" },
  218. { "Right PGA", NULL, "VINR" },
  219. { "ADC", NULL, "Left PGA" },
  220. { "ADC", NULL, "Right PGA" },
  221. { "SYSCLK", NULL, "PLL1", adav80x_dapm_sysclk_check },
  222. { "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check },
  223. { "SYSCLK", NULL, "OSC", adav80x_dapm_sysclk_check },
  224. { "PLL1", NULL, "OSC", adav80x_dapm_pll_check },
  225. { "PLL2", NULL, "OSC", adav80x_dapm_pll_check },
  226. { "ADC", NULL, "SYSCLK" },
  227. { "DAC", NULL, "SYSCLK" },
  228. { "AIFOUT", NULL, "SYSCLK" },
  229. { "AIFAUXOUT", NULL, "SYSCLK" },
  230. { "AIFIN", NULL, "SYSCLK" },
  231. { "AIFAUXIN", NULL, "SYSCLK" },
  232. };
  233. static int adav80x_set_deemph(struct snd_soc_component *component)
  234. {
  235. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  236. unsigned int val;
  237. if (adav80x->deemph) {
  238. switch (adav80x->rate) {
  239. case 32000:
  240. val = ADAV80X_DAC_CTRL2_DEEMPH_32;
  241. break;
  242. case 44100:
  243. val = ADAV80X_DAC_CTRL2_DEEMPH_44;
  244. break;
  245. case 48000:
  246. case 64000:
  247. case 88200:
  248. case 96000:
  249. val = ADAV80X_DAC_CTRL2_DEEMPH_48;
  250. break;
  251. default:
  252. val = ADAV80X_DAC_CTRL2_DEEMPH_NONE;
  253. break;
  254. }
  255. } else {
  256. val = ADAV80X_DAC_CTRL2_DEEMPH_NONE;
  257. }
  258. return regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
  259. ADAV80X_DAC_CTRL2_DEEMPH_MASK, val);
  260. }
  261. static int adav80x_put_deemph(struct snd_kcontrol *kcontrol,
  262. struct snd_ctl_elem_value *ucontrol)
  263. {
  264. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  265. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  266. unsigned int deemph = ucontrol->value.integer.value[0];
  267. if (deemph > 1)
  268. return -EINVAL;
  269. adav80x->deemph = deemph;
  270. return adav80x_set_deemph(component);
  271. }
  272. static int adav80x_get_deemph(struct snd_kcontrol *kcontrol,
  273. struct snd_ctl_elem_value *ucontrol)
  274. {
  275. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  276. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  277. ucontrol->value.integer.value[0] = adav80x->deemph;
  278. return 0;
  279. };
  280. static const DECLARE_TLV_DB_SCALE(adav80x_inpga_tlv, 0, 50, 0);
  281. static const DECLARE_TLV_DB_MINMAX(adav80x_digital_tlv, -9563, 0);
  282. static const struct snd_kcontrol_new adav80x_controls[] = {
  283. SOC_DOUBLE_R_TLV("Master Playback Volume", ADAV80X_DAC_L_VOL,
  284. ADAV80X_DAC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv),
  285. SOC_DOUBLE_R_TLV("Master Capture Volume", ADAV80X_ADC_L_VOL,
  286. ADAV80X_ADC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv),
  287. SOC_DOUBLE_R_TLV("PGA Capture Volume", ADAV80X_PGA_L_VOL,
  288. ADAV80X_PGA_R_VOL, 0, 0x30, 0, adav80x_inpga_tlv),
  289. SOC_DOUBLE("Master Playback Switch", ADAV80X_DAC_CTRL1, 0, 1, 1, 0),
  290. SOC_DOUBLE("Master Capture Switch", ADAV80X_ADC_CTRL1, 2, 3, 1, 1),
  291. SOC_SINGLE("ADC High Pass Filter Switch", ADAV80X_ADC_CTRL1, 6, 1, 0),
  292. SOC_SINGLE_BOOL_EXT("Playback De-emphasis Switch", 0,
  293. adav80x_get_deemph, adav80x_put_deemph),
  294. };
  295. static unsigned int adav80x_port_ctrl_regs[2][2] = {
  296. { ADAV80X_REC_CTRL, ADAV80X_PLAYBACK_CTRL, },
  297. { ADAV80X_AUX_OUT_CTRL, ADAV80X_AUX_IN_CTRL },
  298. };
  299. static int adav80x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  300. {
  301. struct snd_soc_component *component = dai->component;
  302. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  303. unsigned int capture = 0x00;
  304. unsigned int playback = 0x00;
  305. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  306. case SND_SOC_DAIFMT_CBM_CFM:
  307. capture |= ADAV80X_CAPTURE_MODE_MASTER;
  308. playback |= ADAV80X_PLAYBACK_MODE_MASTER;
  309. case SND_SOC_DAIFMT_CBS_CFS:
  310. break;
  311. default:
  312. return -EINVAL;
  313. }
  314. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  315. case SND_SOC_DAIFMT_I2S:
  316. capture |= ADAV80X_CAPTURE_MODE_I2S;
  317. playback |= ADAV80X_PLAYBACK_MODE_I2S;
  318. break;
  319. case SND_SOC_DAIFMT_LEFT_J:
  320. capture |= ADAV80X_CAPTURE_MODE_LEFT_J;
  321. playback |= ADAV80X_PLAYBACK_MODE_LEFT_J;
  322. break;
  323. case SND_SOC_DAIFMT_RIGHT_J:
  324. capture |= ADAV80X_CAPTURE_MODE_RIGHT_J;
  325. playback |= ADAV80X_PLAYBACK_MODE_RIGHT_J_24;
  326. break;
  327. default:
  328. return -EINVAL;
  329. }
  330. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  331. case SND_SOC_DAIFMT_NB_NF:
  332. break;
  333. default:
  334. return -EINVAL;
  335. }
  336. regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
  337. ADAV80X_CAPTURE_MODE_MASK | ADAV80X_CAPTURE_MODE_MASTER,
  338. capture);
  339. regmap_write(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
  340. playback);
  341. adav80x->dai_fmt[dai->id] = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  342. return 0;
  343. }
  344. static int adav80x_set_adc_clock(struct snd_soc_component *component,
  345. unsigned int sample_rate)
  346. {
  347. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  348. unsigned int val;
  349. if (sample_rate <= 48000)
  350. val = ADAV80X_ADC_CTRL1_MODULATOR_128FS;
  351. else
  352. val = ADAV80X_ADC_CTRL1_MODULATOR_64FS;
  353. regmap_update_bits(adav80x->regmap, ADAV80X_ADC_CTRL1,
  354. ADAV80X_ADC_CTRL1_MODULATOR_MASK, val);
  355. return 0;
  356. }
  357. static int adav80x_set_dac_clock(struct snd_soc_component *component,
  358. unsigned int sample_rate)
  359. {
  360. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  361. unsigned int val;
  362. if (sample_rate <= 48000)
  363. val = ADAV80X_DAC_CTRL2_DIV1 | ADAV80X_DAC_CTRL2_INTERPOL_256FS;
  364. else
  365. val = ADAV80X_DAC_CTRL2_DIV2 | ADAV80X_DAC_CTRL2_INTERPOL_128FS;
  366. regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
  367. ADAV80X_DAC_CTRL2_DIV_MASK | ADAV80X_DAC_CTRL2_INTERPOL_MASK,
  368. val);
  369. return 0;
  370. }
  371. static int adav80x_set_capture_pcm_format(struct snd_soc_component *component,
  372. struct snd_soc_dai *dai, struct snd_pcm_hw_params *params)
  373. {
  374. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  375. unsigned int val;
  376. switch (params_width(params)) {
  377. case 16:
  378. val = ADAV80X_CAPTURE_WORD_LEN16;
  379. break;
  380. case 18:
  381. val = ADAV80X_CAPTRUE_WORD_LEN18;
  382. break;
  383. case 20:
  384. val = ADAV80X_CAPTURE_WORD_LEN20;
  385. break;
  386. case 24:
  387. val = ADAV80X_CAPTURE_WORD_LEN24;
  388. break;
  389. default:
  390. return -EINVAL;
  391. }
  392. regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
  393. ADAV80X_CAPTURE_WORD_LEN_MASK, val);
  394. return 0;
  395. }
  396. static int adav80x_set_playback_pcm_format(struct snd_soc_component *component,
  397. struct snd_soc_dai *dai, struct snd_pcm_hw_params *params)
  398. {
  399. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  400. unsigned int val;
  401. if (adav80x->dai_fmt[dai->id] != SND_SOC_DAIFMT_RIGHT_J)
  402. return 0;
  403. switch (params_width(params)) {
  404. case 16:
  405. val = ADAV80X_PLAYBACK_MODE_RIGHT_J_16;
  406. break;
  407. case 18:
  408. val = ADAV80X_PLAYBACK_MODE_RIGHT_J_18;
  409. break;
  410. case 20:
  411. val = ADAV80X_PLAYBACK_MODE_RIGHT_J_20;
  412. break;
  413. case 24:
  414. val = ADAV80X_PLAYBACK_MODE_RIGHT_J_24;
  415. break;
  416. default:
  417. return -EINVAL;
  418. }
  419. regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
  420. ADAV80X_PLAYBACK_MODE_MASK, val);
  421. return 0;
  422. }
  423. static int adav80x_hw_params(struct snd_pcm_substream *substream,
  424. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  425. {
  426. struct snd_soc_component *component = dai->component;
  427. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  428. unsigned int rate = params_rate(params);
  429. if (rate * 256 != adav80x->sysclk)
  430. return -EINVAL;
  431. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  432. adav80x_set_playback_pcm_format(component, dai, params);
  433. adav80x_set_dac_clock(component, rate);
  434. } else {
  435. adav80x_set_capture_pcm_format(component, dai, params);
  436. adav80x_set_adc_clock(component, rate);
  437. }
  438. adav80x->rate = rate;
  439. adav80x_set_deemph(component);
  440. return 0;
  441. }
  442. static int adav80x_set_sysclk(struct snd_soc_component *component,
  443. int clk_id, int source,
  444. unsigned int freq, int dir)
  445. {
  446. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  447. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  448. if (dir == SND_SOC_CLOCK_IN) {
  449. switch (clk_id) {
  450. case ADAV80X_CLK_XIN:
  451. case ADAV80X_CLK_XTAL:
  452. case ADAV80X_CLK_MCLKI:
  453. case ADAV80X_CLK_PLL1:
  454. case ADAV80X_CLK_PLL2:
  455. break;
  456. default:
  457. return -EINVAL;
  458. }
  459. adav80x->sysclk = freq;
  460. if (adav80x->clk_src != clk_id) {
  461. unsigned int iclk_ctrl1, iclk_ctrl2;
  462. adav80x->clk_src = clk_id;
  463. if (clk_id == ADAV80X_CLK_XTAL)
  464. clk_id = ADAV80X_CLK_XIN;
  465. iclk_ctrl1 = ADAV80X_ICLK_CTRL1_DAC_SRC(clk_id) |
  466. ADAV80X_ICLK_CTRL1_ADC_SRC(clk_id) |
  467. ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id);
  468. iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id);
  469. regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL1,
  470. iclk_ctrl1);
  471. regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL2,
  472. iclk_ctrl2);
  473. snd_soc_dapm_sync(dapm);
  474. }
  475. } else {
  476. unsigned int mask;
  477. switch (clk_id) {
  478. case ADAV80X_CLK_SYSCLK1:
  479. case ADAV80X_CLK_SYSCLK2:
  480. case ADAV80X_CLK_SYSCLK3:
  481. break;
  482. default:
  483. return -EINVAL;
  484. }
  485. clk_id -= ADAV80X_CLK_SYSCLK1;
  486. mask = ADAV80X_PLL_OUTE_SYSCLKPD(clk_id);
  487. if (freq == 0) {
  488. regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
  489. mask, mask);
  490. adav80x->sysclk_pd[clk_id] = true;
  491. } else {
  492. regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
  493. mask, 0);
  494. adav80x->sysclk_pd[clk_id] = false;
  495. }
  496. snd_soc_dapm_mutex_lock(dapm);
  497. if (adav80x->sysclk_pd[0])
  498. snd_soc_dapm_disable_pin_unlocked(dapm, "PLL1");
  499. else
  500. snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL1");
  501. if (adav80x->sysclk_pd[1] || adav80x->sysclk_pd[2])
  502. snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2");
  503. else
  504. snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2");
  505. snd_soc_dapm_sync_unlocked(dapm);
  506. snd_soc_dapm_mutex_unlock(dapm);
  507. }
  508. return 0;
  509. }
  510. static int adav80x_set_pll(struct snd_soc_component *component, int pll_id,
  511. int source, unsigned int freq_in, unsigned int freq_out)
  512. {
  513. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  514. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  515. unsigned int pll_ctrl1 = 0;
  516. unsigned int pll_ctrl2 = 0;
  517. unsigned int pll_src;
  518. switch (source) {
  519. case ADAV80X_PLL_SRC_XTAL:
  520. case ADAV80X_PLL_SRC_XIN:
  521. case ADAV80X_PLL_SRC_MCLKI:
  522. break;
  523. default:
  524. return -EINVAL;
  525. }
  526. if (!freq_out)
  527. return 0;
  528. switch (freq_in) {
  529. case 27000000:
  530. break;
  531. case 54000000:
  532. if (source == ADAV80X_PLL_SRC_XIN) {
  533. pll_ctrl1 |= ADAV80X_PLL_CTRL1_PLLDIV;
  534. break;
  535. }
  536. fallthrough;
  537. default:
  538. return -EINVAL;
  539. }
  540. if (freq_out > 12288000) {
  541. pll_ctrl2 |= ADAV80X_PLL_CTRL2_DOUB(pll_id);
  542. freq_out /= 2;
  543. }
  544. /* freq_out = sample_rate * 256 */
  545. switch (freq_out) {
  546. case 8192000:
  547. pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_32(pll_id);
  548. break;
  549. case 11289600:
  550. pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_44(pll_id);
  551. break;
  552. case 12288000:
  553. pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_48(pll_id);
  554. break;
  555. default:
  556. return -EINVAL;
  557. }
  558. regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL1,
  559. ADAV80X_PLL_CTRL1_PLLDIV, pll_ctrl1);
  560. regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL2,
  561. ADAV80X_PLL_CTRL2_PLL_MASK(pll_id), pll_ctrl2);
  562. if (source != adav80x->pll_src) {
  563. if (source == ADAV80X_PLL_SRC_MCLKI)
  564. pll_src = ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll_id);
  565. else
  566. pll_src = ADAV80X_PLL_CLK_SRC_PLL_XIN(pll_id);
  567. regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CLK_SRC,
  568. ADAV80X_PLL_CLK_SRC_PLL_MASK(pll_id), pll_src);
  569. adav80x->pll_src = source;
  570. snd_soc_dapm_sync(dapm);
  571. }
  572. return 0;
  573. }
  574. static int adav80x_set_bias_level(struct snd_soc_component *component,
  575. enum snd_soc_bias_level level)
  576. {
  577. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  578. unsigned int mask = ADAV80X_DAC_CTRL1_PD;
  579. switch (level) {
  580. case SND_SOC_BIAS_ON:
  581. break;
  582. case SND_SOC_BIAS_PREPARE:
  583. break;
  584. case SND_SOC_BIAS_STANDBY:
  585. regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
  586. 0x00);
  587. break;
  588. case SND_SOC_BIAS_OFF:
  589. regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
  590. mask);
  591. break;
  592. }
  593. return 0;
  594. }
  595. /* Enforce the same sample rate on all audio interfaces */
  596. static int adav80x_dai_startup(struct snd_pcm_substream *substream,
  597. struct snd_soc_dai *dai)
  598. {
  599. struct snd_soc_component *component = dai->component;
  600. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  601. if (!snd_soc_component_active(component) || !adav80x->rate)
  602. return 0;
  603. return snd_pcm_hw_constraint_single(substream->runtime,
  604. SNDRV_PCM_HW_PARAM_RATE, adav80x->rate);
  605. }
  606. static void adav80x_dai_shutdown(struct snd_pcm_substream *substream,
  607. struct snd_soc_dai *dai)
  608. {
  609. struct snd_soc_component *component = dai->component;
  610. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  611. if (!snd_soc_component_active(component))
  612. adav80x->rate = 0;
  613. }
  614. static const struct snd_soc_dai_ops adav80x_dai_ops = {
  615. .set_fmt = adav80x_set_dai_fmt,
  616. .hw_params = adav80x_hw_params,
  617. .startup = adav80x_dai_startup,
  618. .shutdown = adav80x_dai_shutdown,
  619. };
  620. #define ADAV80X_PLAYBACK_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  621. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | \
  622. SNDRV_PCM_RATE_96000)
  623. #define ADAV80X_CAPTURE_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
  624. #define ADAV80X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
  625. SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
  626. static struct snd_soc_dai_driver adav80x_dais[] = {
  627. {
  628. .name = "adav80x-hifi",
  629. .id = 0,
  630. .playback = {
  631. .stream_name = "HiFi Playback",
  632. .channels_min = 2,
  633. .channels_max = 2,
  634. .rates = ADAV80X_PLAYBACK_RATES,
  635. .formats = ADAV80X_FORMATS,
  636. },
  637. .capture = {
  638. .stream_name = "HiFi Capture",
  639. .channels_min = 2,
  640. .channels_max = 2,
  641. .rates = ADAV80X_CAPTURE_RATES,
  642. .formats = ADAV80X_FORMATS,
  643. },
  644. .ops = &adav80x_dai_ops,
  645. },
  646. {
  647. .name = "adav80x-aux",
  648. .id = 1,
  649. .playback = {
  650. .stream_name = "Aux Playback",
  651. .channels_min = 2,
  652. .channels_max = 2,
  653. .rates = ADAV80X_PLAYBACK_RATES,
  654. .formats = ADAV80X_FORMATS,
  655. },
  656. .capture = {
  657. .stream_name = "Aux Capture",
  658. .channels_min = 2,
  659. .channels_max = 2,
  660. .rates = ADAV80X_CAPTURE_RATES,
  661. .formats = ADAV80X_FORMATS,
  662. },
  663. .ops = &adav80x_dai_ops,
  664. },
  665. };
  666. static int adav80x_probe(struct snd_soc_component *component)
  667. {
  668. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  669. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  670. /* Force PLLs on for SYSCLK output */
  671. snd_soc_dapm_force_enable_pin(dapm, "PLL1");
  672. snd_soc_dapm_force_enable_pin(dapm, "PLL2");
  673. /* Power down S/PDIF receiver, since it is currently not supported */
  674. regmap_write(adav80x->regmap, ADAV80X_PLL_OUTE, 0x20);
  675. /* Disable DAC zero flag */
  676. regmap_write(adav80x->regmap, ADAV80X_DAC_CTRL3, 0x6);
  677. return 0;
  678. }
  679. static int adav80x_resume(struct snd_soc_component *component)
  680. {
  681. struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
  682. regcache_sync(adav80x->regmap);
  683. return 0;
  684. }
  685. static const struct snd_soc_component_driver adav80x_component_driver = {
  686. .probe = adav80x_probe,
  687. .resume = adav80x_resume,
  688. .set_bias_level = adav80x_set_bias_level,
  689. .set_pll = adav80x_set_pll,
  690. .set_sysclk = adav80x_set_sysclk,
  691. .controls = adav80x_controls,
  692. .num_controls = ARRAY_SIZE(adav80x_controls),
  693. .dapm_widgets = adav80x_dapm_widgets,
  694. .num_dapm_widgets = ARRAY_SIZE(adav80x_dapm_widgets),
  695. .dapm_routes = adav80x_dapm_routes,
  696. .num_dapm_routes = ARRAY_SIZE(adav80x_dapm_routes),
  697. .suspend_bias_off = 1,
  698. .idle_bias_on = 1,
  699. .use_pmdown_time = 1,
  700. .endianness = 1,
  701. .non_legacy_dai_naming = 1,
  702. };
  703. int adav80x_bus_probe(struct device *dev, struct regmap *regmap)
  704. {
  705. struct adav80x *adav80x;
  706. if (IS_ERR(regmap))
  707. return PTR_ERR(regmap);
  708. adav80x = devm_kzalloc(dev, sizeof(*adav80x), GFP_KERNEL);
  709. if (!adav80x)
  710. return -ENOMEM;
  711. dev_set_drvdata(dev, adav80x);
  712. adav80x->regmap = regmap;
  713. return devm_snd_soc_register_component(dev, &adav80x_component_driver,
  714. adav80x_dais, ARRAY_SIZE(adav80x_dais));
  715. }
  716. EXPORT_SYMBOL_GPL(adav80x_bus_probe);
  717. const struct regmap_config adav80x_regmap_config = {
  718. .val_bits = 8,
  719. .pad_bits = 1,
  720. .reg_bits = 7,
  721. .max_register = ADAV80X_PLL_OUTE,
  722. .cache_type = REGCACHE_RBTREE,
  723. .reg_defaults = adav80x_reg_defaults,
  724. .num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults),
  725. };
  726. EXPORT_SYMBOL_GPL(adav80x_regmap_config);
  727. MODULE_DESCRIPTION("ASoC ADAV80x driver");
  728. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  729. MODULE_AUTHOR("Yi Li <yi.li@analog.com>>");
  730. MODULE_LICENSE("GPL");