adau1977.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ADAU1977/ADAU1978/ADAU1979 driver
  4. *
  5. * Copyright 2014 Analog Devices Inc.
  6. * Author: Lars-Peter Clausen <lars@metafoo.de>
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/device.h>
  10. #include <linux/gpio/consumer.h>
  11. #include <linux/i2c.h>
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_data/adau1977.h>
  15. #include <linux/regmap.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/slab.h>
  18. #include <sound/core.h>
  19. #include <sound/initval.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include <sound/tlv.h>
  24. #include "adau1977.h"
  25. #define ADAU1977_REG_POWER 0x00
  26. #define ADAU1977_REG_PLL 0x01
  27. #define ADAU1977_REG_BOOST 0x02
  28. #define ADAU1977_REG_MICBIAS 0x03
  29. #define ADAU1977_REG_BLOCK_POWER_SAI 0x04
  30. #define ADAU1977_REG_SAI_CTRL0 0x05
  31. #define ADAU1977_REG_SAI_CTRL1 0x06
  32. #define ADAU1977_REG_CMAP12 0x07
  33. #define ADAU1977_REG_CMAP34 0x08
  34. #define ADAU1977_REG_SAI_OVERTEMP 0x09
  35. #define ADAU1977_REG_POST_ADC_GAIN(x) (0x0a + (x))
  36. #define ADAU1977_REG_MISC_CONTROL 0x0e
  37. #define ADAU1977_REG_DIAG_CONTROL 0x10
  38. #define ADAU1977_REG_STATUS(x) (0x11 + (x))
  39. #define ADAU1977_REG_DIAG_IRQ1 0x15
  40. #define ADAU1977_REG_DIAG_IRQ2 0x16
  41. #define ADAU1977_REG_ADJUST1 0x17
  42. #define ADAU1977_REG_ADJUST2 0x18
  43. #define ADAU1977_REG_ADC_CLIP 0x19
  44. #define ADAU1977_REG_DC_HPF_CAL 0x1a
  45. #define ADAU1977_POWER_RESET BIT(7)
  46. #define ADAU1977_POWER_PWUP BIT(0)
  47. #define ADAU1977_PLL_CLK_S BIT(4)
  48. #define ADAU1977_PLL_MCS_MASK 0x7
  49. #define ADAU1977_MICBIAS_MB_VOLTS_MASK 0xf0
  50. #define ADAU1977_MICBIAS_MB_VOLTS_OFFSET 4
  51. #define ADAU1977_BLOCK_POWER_SAI_LR_POL BIT(7)
  52. #define ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE BIT(6)
  53. #define ADAU1977_BLOCK_POWER_SAI_LDO_EN BIT(5)
  54. #define ADAU1977_SAI_CTRL0_FMT_MASK (0x3 << 6)
  55. #define ADAU1977_SAI_CTRL0_FMT_I2S (0x0 << 6)
  56. #define ADAU1977_SAI_CTRL0_FMT_LJ (0x1 << 6)
  57. #define ADAU1977_SAI_CTRL0_FMT_RJ_24BIT (0x2 << 6)
  58. #define ADAU1977_SAI_CTRL0_FMT_RJ_16BIT (0x3 << 6)
  59. #define ADAU1977_SAI_CTRL0_SAI_MASK (0x7 << 3)
  60. #define ADAU1977_SAI_CTRL0_SAI_I2S (0x0 << 3)
  61. #define ADAU1977_SAI_CTRL0_SAI_TDM_2 (0x1 << 3)
  62. #define ADAU1977_SAI_CTRL0_SAI_TDM_4 (0x2 << 3)
  63. #define ADAU1977_SAI_CTRL0_SAI_TDM_8 (0x3 << 3)
  64. #define ADAU1977_SAI_CTRL0_SAI_TDM_16 (0x4 << 3)
  65. #define ADAU1977_SAI_CTRL0_FS_MASK (0x7)
  66. #define ADAU1977_SAI_CTRL0_FS_8000_12000 (0x0)
  67. #define ADAU1977_SAI_CTRL0_FS_16000_24000 (0x1)
  68. #define ADAU1977_SAI_CTRL0_FS_32000_48000 (0x2)
  69. #define ADAU1977_SAI_CTRL0_FS_64000_96000 (0x3)
  70. #define ADAU1977_SAI_CTRL0_FS_128000_192000 (0x4)
  71. #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK (0x3 << 5)
  72. #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_32 (0x0 << 5)
  73. #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_24 (0x1 << 5)
  74. #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_16 (0x2 << 5)
  75. #define ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK (0x1 << 4)
  76. #define ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT (0x1 << 4)
  77. #define ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT (0x0 << 4)
  78. #define ADAU1977_SAI_CTRL1_LRCLK_PULSE BIT(3)
  79. #define ADAU1977_SAI_CTRL1_MSB BIT(2)
  80. #define ADAU1977_SAI_CTRL1_BCLKRATE_16 (0x1 << 1)
  81. #define ADAU1977_SAI_CTRL1_BCLKRATE_32 (0x0 << 1)
  82. #define ADAU1977_SAI_CTRL1_BCLKRATE_MASK (0x1 << 1)
  83. #define ADAU1977_SAI_CTRL1_MASTER BIT(0)
  84. #define ADAU1977_SAI_OVERTEMP_DRV_C(x) BIT(4 + (x))
  85. #define ADAU1977_SAI_OVERTEMP_DRV_HIZ BIT(3)
  86. #define ADAU1977_MISC_CONTROL_SUM_MODE_MASK (0x3 << 6)
  87. #define ADAU1977_MISC_CONTROL_SUM_MODE_1CH (0x2 << 6)
  88. #define ADAU1977_MISC_CONTROL_SUM_MODE_2CH (0x1 << 6)
  89. #define ADAU1977_MISC_CONTROL_SUM_MODE_4CH (0x0 << 6)
  90. #define ADAU1977_MISC_CONTROL_MMUTE BIT(4)
  91. #define ADAU1977_MISC_CONTROL_DC_CAL BIT(0)
  92. #define ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET 4
  93. #define ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET 0
  94. struct adau1977 {
  95. struct regmap *regmap;
  96. bool right_j;
  97. unsigned int sysclk;
  98. enum adau1977_sysclk_src sysclk_src;
  99. struct gpio_desc *reset_gpio;
  100. enum adau1977_type type;
  101. struct regulator *avdd_reg;
  102. struct regulator *dvdd_reg;
  103. struct snd_pcm_hw_constraint_list constraints;
  104. struct device *dev;
  105. void (*switch_mode)(struct device *dev);
  106. unsigned int max_master_fs;
  107. unsigned int slot_width;
  108. bool enabled;
  109. bool master;
  110. };
  111. static const struct reg_default adau1977_reg_defaults[] = {
  112. { 0x00, 0x00 },
  113. { 0x01, 0x41 },
  114. { 0x02, 0x4a },
  115. { 0x03, 0x7d },
  116. { 0x04, 0x3d },
  117. { 0x05, 0x02 },
  118. { 0x06, 0x00 },
  119. { 0x07, 0x10 },
  120. { 0x08, 0x32 },
  121. { 0x09, 0xf0 },
  122. { 0x0a, 0xa0 },
  123. { 0x0b, 0xa0 },
  124. { 0x0c, 0xa0 },
  125. { 0x0d, 0xa0 },
  126. { 0x0e, 0x02 },
  127. { 0x10, 0x0f },
  128. { 0x15, 0x20 },
  129. { 0x16, 0x00 },
  130. { 0x17, 0x00 },
  131. { 0x18, 0x00 },
  132. { 0x1a, 0x00 },
  133. };
  134. static const DECLARE_TLV_DB_MINMAX_MUTE(adau1977_adc_gain, -3562, 6000);
  135. static const struct snd_soc_dapm_widget adau1977_micbias_dapm_widgets[] = {
  136. SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU1977_REG_MICBIAS,
  137. 3, 0, NULL, 0)
  138. };
  139. static const struct snd_soc_dapm_widget adau1977_dapm_widgets[] = {
  140. SND_SOC_DAPM_SUPPLY("Vref", ADAU1977_REG_BLOCK_POWER_SAI,
  141. 4, 0, NULL, 0),
  142. SND_SOC_DAPM_ADC("ADC1", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 0, 0),
  143. SND_SOC_DAPM_ADC("ADC2", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 1, 0),
  144. SND_SOC_DAPM_ADC("ADC3", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 2, 0),
  145. SND_SOC_DAPM_ADC("ADC4", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 3, 0),
  146. SND_SOC_DAPM_INPUT("AIN1"),
  147. SND_SOC_DAPM_INPUT("AIN2"),
  148. SND_SOC_DAPM_INPUT("AIN3"),
  149. SND_SOC_DAPM_INPUT("AIN4"),
  150. SND_SOC_DAPM_OUTPUT("VREF"),
  151. };
  152. static const struct snd_soc_dapm_route adau1977_dapm_routes[] = {
  153. { "ADC1", NULL, "AIN1" },
  154. { "ADC2", NULL, "AIN2" },
  155. { "ADC3", NULL, "AIN3" },
  156. { "ADC4", NULL, "AIN4" },
  157. { "ADC1", NULL, "Vref" },
  158. { "ADC2", NULL, "Vref" },
  159. { "ADC3", NULL, "Vref" },
  160. { "ADC4", NULL, "Vref" },
  161. { "VREF", NULL, "Vref" },
  162. };
  163. #define ADAU1977_VOLUME(x) \
  164. SOC_SINGLE_TLV("ADC" #x " Capture Volume", \
  165. ADAU1977_REG_POST_ADC_GAIN((x) - 1), \
  166. 0, 255, 1, adau1977_adc_gain)
  167. #define ADAU1977_HPF_SWITCH(x) \
  168. SOC_SINGLE("ADC" #x " Highpass-Filter Capture Switch", \
  169. ADAU1977_REG_DC_HPF_CAL, (x) - 1, 1, 0)
  170. #define ADAU1977_DC_SUB_SWITCH(x) \
  171. SOC_SINGLE("ADC" #x " DC Subtraction Capture Switch", \
  172. ADAU1977_REG_DC_HPF_CAL, (x) + 3, 1, 0)
  173. static const struct snd_kcontrol_new adau1977_snd_controls[] = {
  174. ADAU1977_VOLUME(1),
  175. ADAU1977_VOLUME(2),
  176. ADAU1977_VOLUME(3),
  177. ADAU1977_VOLUME(4),
  178. ADAU1977_HPF_SWITCH(1),
  179. ADAU1977_HPF_SWITCH(2),
  180. ADAU1977_HPF_SWITCH(3),
  181. ADAU1977_HPF_SWITCH(4),
  182. ADAU1977_DC_SUB_SWITCH(1),
  183. ADAU1977_DC_SUB_SWITCH(2),
  184. ADAU1977_DC_SUB_SWITCH(3),
  185. ADAU1977_DC_SUB_SWITCH(4),
  186. };
  187. static int adau1977_reset(struct adau1977 *adau1977)
  188. {
  189. int ret;
  190. /*
  191. * The reset bit is obviously volatile, but we need to be able to cache
  192. * the other bits in the register, so we can't just mark the whole
  193. * register as volatile. Since this is the only place where we'll ever
  194. * touch the reset bit just bypass the cache for this operation.
  195. */
  196. regcache_cache_bypass(adau1977->regmap, true);
  197. ret = regmap_write(adau1977->regmap, ADAU1977_REG_POWER,
  198. ADAU1977_POWER_RESET);
  199. regcache_cache_bypass(adau1977->regmap, false);
  200. if (ret)
  201. return ret;
  202. return ret;
  203. }
  204. /*
  205. * Returns the appropriate setting for ths FS field in the CTRL0 register
  206. * depending on the rate.
  207. */
  208. static int adau1977_lookup_fs(unsigned int rate)
  209. {
  210. if (rate >= 8000 && rate <= 12000)
  211. return ADAU1977_SAI_CTRL0_FS_8000_12000;
  212. else if (rate >= 16000 && rate <= 24000)
  213. return ADAU1977_SAI_CTRL0_FS_16000_24000;
  214. else if (rate >= 32000 && rate <= 48000)
  215. return ADAU1977_SAI_CTRL0_FS_32000_48000;
  216. else if (rate >= 64000 && rate <= 96000)
  217. return ADAU1977_SAI_CTRL0_FS_64000_96000;
  218. else if (rate >= 128000 && rate <= 192000)
  219. return ADAU1977_SAI_CTRL0_FS_128000_192000;
  220. else
  221. return -EINVAL;
  222. }
  223. static int adau1977_lookup_mcs(struct adau1977 *adau1977, unsigned int rate,
  224. unsigned int fs)
  225. {
  226. unsigned int mcs;
  227. /*
  228. * rate = sysclk / (512 * mcs_lut[mcs]) * 2**fs
  229. * => mcs_lut[mcs] = sysclk / (512 * rate) * 2**fs
  230. * => mcs_lut[mcs] = sysclk / ((512 / 2**fs) * rate)
  231. */
  232. rate *= 512 >> fs;
  233. if (adau1977->sysclk % rate != 0)
  234. return -EINVAL;
  235. mcs = adau1977->sysclk / rate;
  236. /* The factors configured by MCS are 1, 2, 3, 4, 6 */
  237. if (mcs < 1 || mcs > 6 || mcs == 5)
  238. return -EINVAL;
  239. mcs = mcs - 1;
  240. if (mcs == 5)
  241. mcs = 4;
  242. return mcs;
  243. }
  244. static int adau1977_hw_params(struct snd_pcm_substream *substream,
  245. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  246. {
  247. struct snd_soc_component *component = dai->component;
  248. struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
  249. unsigned int rate = params_rate(params);
  250. unsigned int slot_width;
  251. unsigned int ctrl0, ctrl0_mask;
  252. unsigned int ctrl1;
  253. int mcs, fs;
  254. int ret;
  255. fs = adau1977_lookup_fs(rate);
  256. if (fs < 0)
  257. return fs;
  258. if (adau1977->sysclk_src == ADAU1977_SYSCLK_SRC_MCLK) {
  259. mcs = adau1977_lookup_mcs(adau1977, rate, fs);
  260. if (mcs < 0)
  261. return mcs;
  262. } else {
  263. mcs = 0;
  264. }
  265. ctrl0_mask = ADAU1977_SAI_CTRL0_FS_MASK;
  266. ctrl0 = fs;
  267. if (adau1977->right_j) {
  268. switch (params_width(params)) {
  269. case 16:
  270. ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_16BIT;
  271. break;
  272. case 24:
  273. ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
  274. break;
  275. default:
  276. return -EINVAL;
  277. }
  278. ctrl0_mask |= ADAU1977_SAI_CTRL0_FMT_MASK;
  279. }
  280. if (adau1977->master) {
  281. switch (params_width(params)) {
  282. case 16:
  283. ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT;
  284. slot_width = 16;
  285. break;
  286. case 24:
  287. case 32:
  288. ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT;
  289. slot_width = 32;
  290. break;
  291. default:
  292. return -EINVAL;
  293. }
  294. /* In TDM mode there is a fixed slot width */
  295. if (adau1977->slot_width)
  296. slot_width = adau1977->slot_width;
  297. if (slot_width == 16)
  298. ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_16;
  299. else
  300. ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_32;
  301. ret = regmap_update_bits(adau1977->regmap,
  302. ADAU1977_REG_SAI_CTRL1,
  303. ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK |
  304. ADAU1977_SAI_CTRL1_BCLKRATE_MASK,
  305. ctrl1);
  306. if (ret < 0)
  307. return ret;
  308. }
  309. ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
  310. ctrl0_mask, ctrl0);
  311. if (ret < 0)
  312. return ret;
  313. return regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
  314. ADAU1977_PLL_MCS_MASK, mcs);
  315. }
  316. static int adau1977_power_disable(struct adau1977 *adau1977)
  317. {
  318. int ret = 0;
  319. if (!adau1977->enabled)
  320. return 0;
  321. ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
  322. ADAU1977_POWER_PWUP, 0);
  323. if (ret)
  324. return ret;
  325. regcache_mark_dirty(adau1977->regmap);
  326. gpiod_set_value_cansleep(adau1977->reset_gpio, 0);
  327. regcache_cache_only(adau1977->regmap, true);
  328. regulator_disable(adau1977->avdd_reg);
  329. if (adau1977->dvdd_reg)
  330. regulator_disable(adau1977->dvdd_reg);
  331. adau1977->enabled = false;
  332. return 0;
  333. }
  334. static int adau1977_power_enable(struct adau1977 *adau1977)
  335. {
  336. unsigned int val;
  337. int ret = 0;
  338. if (adau1977->enabled)
  339. return 0;
  340. ret = regulator_enable(adau1977->avdd_reg);
  341. if (ret)
  342. return ret;
  343. if (adau1977->dvdd_reg) {
  344. ret = regulator_enable(adau1977->dvdd_reg);
  345. if (ret)
  346. goto err_disable_avdd;
  347. }
  348. gpiod_set_value_cansleep(adau1977->reset_gpio, 1);
  349. regcache_cache_only(adau1977->regmap, false);
  350. if (adau1977->switch_mode)
  351. adau1977->switch_mode(adau1977->dev);
  352. ret = adau1977_reset(adau1977);
  353. if (ret)
  354. goto err_disable_dvdd;
  355. ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
  356. ADAU1977_POWER_PWUP, ADAU1977_POWER_PWUP);
  357. if (ret)
  358. goto err_disable_dvdd;
  359. ret = regcache_sync(adau1977->regmap);
  360. if (ret)
  361. goto err_disable_dvdd;
  362. /*
  363. * The PLL register is not affected by the software reset. It is
  364. * possible that the value of the register was changed to the
  365. * default value while we were in cache only mode. In this case
  366. * regcache_sync will skip over it and we have to manually sync
  367. * it.
  368. */
  369. ret = regmap_read(adau1977->regmap, ADAU1977_REG_PLL, &val);
  370. if (ret)
  371. goto err_disable_dvdd;
  372. if (val == 0x41) {
  373. regcache_cache_bypass(adau1977->regmap, true);
  374. ret = regmap_write(adau1977->regmap, ADAU1977_REG_PLL,
  375. 0x41);
  376. if (ret)
  377. goto err_disable_dvdd;
  378. regcache_cache_bypass(adau1977->regmap, false);
  379. }
  380. adau1977->enabled = true;
  381. return ret;
  382. err_disable_dvdd:
  383. if (adau1977->dvdd_reg)
  384. regulator_disable(adau1977->dvdd_reg);
  385. err_disable_avdd:
  386. regulator_disable(adau1977->avdd_reg);
  387. return ret;
  388. }
  389. static int adau1977_set_bias_level(struct snd_soc_component *component,
  390. enum snd_soc_bias_level level)
  391. {
  392. struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
  393. int ret = 0;
  394. switch (level) {
  395. case SND_SOC_BIAS_ON:
  396. break;
  397. case SND_SOC_BIAS_PREPARE:
  398. break;
  399. case SND_SOC_BIAS_STANDBY:
  400. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
  401. ret = adau1977_power_enable(adau1977);
  402. break;
  403. case SND_SOC_BIAS_OFF:
  404. ret = adau1977_power_disable(adau1977);
  405. break;
  406. }
  407. return ret;
  408. }
  409. static int adau1977_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  410. unsigned int rx_mask, int slots, int width)
  411. {
  412. struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
  413. unsigned int ctrl0, ctrl1, drv;
  414. unsigned int slot[4];
  415. unsigned int i;
  416. int ret;
  417. if (slots == 0) {
  418. /* 0 = No fixed slot width */
  419. adau1977->slot_width = 0;
  420. adau1977->max_master_fs = 192000;
  421. return regmap_update_bits(adau1977->regmap,
  422. ADAU1977_REG_SAI_CTRL0, ADAU1977_SAI_CTRL0_SAI_MASK,
  423. ADAU1977_SAI_CTRL0_SAI_I2S);
  424. }
  425. if (rx_mask == 0 || tx_mask != 0)
  426. return -EINVAL;
  427. drv = 0;
  428. for (i = 0; i < 4; i++) {
  429. slot[i] = __ffs(rx_mask);
  430. drv |= ADAU1977_SAI_OVERTEMP_DRV_C(i);
  431. rx_mask &= ~(1 << slot[i]);
  432. if (slot[i] >= slots)
  433. return -EINVAL;
  434. if (rx_mask == 0)
  435. break;
  436. }
  437. if (rx_mask != 0)
  438. return -EINVAL;
  439. switch (width) {
  440. case 16:
  441. ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_16;
  442. break;
  443. case 24:
  444. /* We can only generate 16 bit or 32 bit wide slots */
  445. if (adau1977->master)
  446. return -EINVAL;
  447. ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_24;
  448. break;
  449. case 32:
  450. ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_32;
  451. break;
  452. default:
  453. return -EINVAL;
  454. }
  455. switch (slots) {
  456. case 2:
  457. ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2;
  458. break;
  459. case 4:
  460. ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4;
  461. break;
  462. case 8:
  463. ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8;
  464. break;
  465. case 16:
  466. ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_16;
  467. break;
  468. default:
  469. return -EINVAL;
  470. }
  471. ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
  472. ADAU1977_SAI_OVERTEMP_DRV_C(0) |
  473. ADAU1977_SAI_OVERTEMP_DRV_C(1) |
  474. ADAU1977_SAI_OVERTEMP_DRV_C(2) |
  475. ADAU1977_SAI_OVERTEMP_DRV_C(3), drv);
  476. if (ret)
  477. return ret;
  478. ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP12,
  479. (slot[1] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
  480. (slot[0] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
  481. if (ret)
  482. return ret;
  483. ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP34,
  484. (slot[3] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
  485. (slot[2] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
  486. if (ret)
  487. return ret;
  488. ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
  489. ADAU1977_SAI_CTRL0_SAI_MASK, ctrl0);
  490. if (ret)
  491. return ret;
  492. ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
  493. ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK, ctrl1);
  494. if (ret)
  495. return ret;
  496. adau1977->slot_width = width;
  497. /* In master mode the maximum bitclock is 24.576 MHz */
  498. adau1977->max_master_fs = min(192000, 24576000 / width / slots);
  499. return 0;
  500. }
  501. static int adau1977_mute(struct snd_soc_dai *dai, int mute, int stream)
  502. {
  503. struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
  504. unsigned int val;
  505. if (mute)
  506. val = ADAU1977_MISC_CONTROL_MMUTE;
  507. else
  508. val = 0;
  509. return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MISC_CONTROL,
  510. ADAU1977_MISC_CONTROL_MMUTE, val);
  511. }
  512. static int adau1977_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  513. {
  514. struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
  515. unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0;
  516. bool invert_lrclk;
  517. int ret;
  518. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  519. case SND_SOC_DAIFMT_CBS_CFS:
  520. adau1977->master = false;
  521. break;
  522. case SND_SOC_DAIFMT_CBM_CFM:
  523. ctrl1 |= ADAU1977_SAI_CTRL1_MASTER;
  524. adau1977->master = true;
  525. break;
  526. default:
  527. return -EINVAL;
  528. }
  529. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  530. case SND_SOC_DAIFMT_NB_NF:
  531. invert_lrclk = false;
  532. break;
  533. case SND_SOC_DAIFMT_IB_NF:
  534. block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
  535. invert_lrclk = false;
  536. break;
  537. case SND_SOC_DAIFMT_NB_IF:
  538. invert_lrclk = true;
  539. break;
  540. case SND_SOC_DAIFMT_IB_IF:
  541. block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
  542. invert_lrclk = true;
  543. break;
  544. default:
  545. return -EINVAL;
  546. }
  547. adau1977->right_j = false;
  548. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  549. case SND_SOC_DAIFMT_I2S:
  550. ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
  551. break;
  552. case SND_SOC_DAIFMT_LEFT_J:
  553. ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
  554. invert_lrclk = !invert_lrclk;
  555. break;
  556. case SND_SOC_DAIFMT_RIGHT_J:
  557. ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
  558. adau1977->right_j = true;
  559. invert_lrclk = !invert_lrclk;
  560. break;
  561. case SND_SOC_DAIFMT_DSP_A:
  562. ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
  563. ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
  564. invert_lrclk = false;
  565. break;
  566. case SND_SOC_DAIFMT_DSP_B:
  567. ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
  568. ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
  569. invert_lrclk = false;
  570. break;
  571. default:
  572. return -EINVAL;
  573. }
  574. if (invert_lrclk)
  575. block_power |= ADAU1977_BLOCK_POWER_SAI_LR_POL;
  576. ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
  577. ADAU1977_BLOCK_POWER_SAI_LR_POL |
  578. ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE, block_power);
  579. if (ret)
  580. return ret;
  581. ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
  582. ADAU1977_SAI_CTRL0_FMT_MASK,
  583. ctrl0);
  584. if (ret)
  585. return ret;
  586. return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
  587. ADAU1977_SAI_CTRL1_MASTER | ADAU1977_SAI_CTRL1_LRCLK_PULSE,
  588. ctrl1);
  589. }
  590. static int adau1977_startup(struct snd_pcm_substream *substream,
  591. struct snd_soc_dai *dai)
  592. {
  593. struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
  594. u64 formats = 0;
  595. if (adau1977->slot_width == 16)
  596. formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE;
  597. else if (adau1977->right_j || adau1977->slot_width == 24)
  598. formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
  599. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE;
  600. snd_pcm_hw_constraint_list(substream->runtime, 0,
  601. SNDRV_PCM_HW_PARAM_RATE, &adau1977->constraints);
  602. if (adau1977->master)
  603. snd_pcm_hw_constraint_minmax(substream->runtime,
  604. SNDRV_PCM_HW_PARAM_RATE, 8000, adau1977->max_master_fs);
  605. if (formats != 0)
  606. snd_pcm_hw_constraint_mask64(substream->runtime,
  607. SNDRV_PCM_HW_PARAM_FORMAT, formats);
  608. return 0;
  609. }
  610. static int adau1977_set_tristate(struct snd_soc_dai *dai, int tristate)
  611. {
  612. struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
  613. unsigned int val;
  614. if (tristate)
  615. val = ADAU1977_SAI_OVERTEMP_DRV_HIZ;
  616. else
  617. val = 0;
  618. return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
  619. ADAU1977_SAI_OVERTEMP_DRV_HIZ, val);
  620. }
  621. static const struct snd_soc_dai_ops adau1977_dai_ops = {
  622. .startup = adau1977_startup,
  623. .hw_params = adau1977_hw_params,
  624. .mute_stream = adau1977_mute,
  625. .set_fmt = adau1977_set_dai_fmt,
  626. .set_tdm_slot = adau1977_set_tdm_slot,
  627. .set_tristate = adau1977_set_tristate,
  628. };
  629. static struct snd_soc_dai_driver adau1977_dai = {
  630. .name = "adau1977-hifi",
  631. .capture = {
  632. .stream_name = "Capture",
  633. .channels_min = 1,
  634. .channels_max = 4,
  635. .rates = SNDRV_PCM_RATE_KNOT,
  636. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
  637. SNDRV_PCM_FMTBIT_S32_LE,
  638. .sig_bits = 24,
  639. },
  640. .ops = &adau1977_dai_ops,
  641. };
  642. static const unsigned int adau1977_rates[] = {
  643. 8000, 16000, 32000, 64000, 128000,
  644. 11025, 22050, 44100, 88200, 172400,
  645. 12000, 24000, 48000, 96000, 192000,
  646. };
  647. #define ADAU1977_RATE_CONSTRAINT_MASK_32000 0x001f
  648. #define ADAU1977_RATE_CONSTRAINT_MASK_44100 0x03e0
  649. #define ADAU1977_RATE_CONSTRAINT_MASK_48000 0x7c00
  650. /* All rates >= 32000 */
  651. #define ADAU1977_RATE_CONSTRAINT_MASK_LRCLK 0x739c
  652. static bool adau1977_check_sysclk(unsigned int mclk, unsigned int base_freq)
  653. {
  654. unsigned int mcs;
  655. if (mclk % (base_freq * 128) != 0)
  656. return false;
  657. mcs = mclk / (128 * base_freq);
  658. if (mcs < 1 || mcs > 6 || mcs == 5)
  659. return false;
  660. return true;
  661. }
  662. static int adau1977_set_sysclk(struct snd_soc_component *component,
  663. int clk_id, int source, unsigned int freq, int dir)
  664. {
  665. struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
  666. unsigned int mask = 0;
  667. unsigned int clk_src;
  668. unsigned int ret;
  669. if (dir != SND_SOC_CLOCK_IN)
  670. return -EINVAL;
  671. if (clk_id != ADAU1977_SYSCLK)
  672. return -EINVAL;
  673. switch (source) {
  674. case ADAU1977_SYSCLK_SRC_MCLK:
  675. clk_src = 0;
  676. break;
  677. case ADAU1977_SYSCLK_SRC_LRCLK:
  678. clk_src = ADAU1977_PLL_CLK_S;
  679. break;
  680. default:
  681. return -EINVAL;
  682. }
  683. if (freq != 0 && source == ADAU1977_SYSCLK_SRC_MCLK) {
  684. if (freq < 4000000 || freq > 36864000)
  685. return -EINVAL;
  686. if (adau1977_check_sysclk(freq, 32000))
  687. mask |= ADAU1977_RATE_CONSTRAINT_MASK_32000;
  688. if (adau1977_check_sysclk(freq, 44100))
  689. mask |= ADAU1977_RATE_CONSTRAINT_MASK_44100;
  690. if (adau1977_check_sysclk(freq, 48000))
  691. mask |= ADAU1977_RATE_CONSTRAINT_MASK_48000;
  692. if (mask == 0)
  693. return -EINVAL;
  694. } else if (source == ADAU1977_SYSCLK_SRC_LRCLK) {
  695. mask = ADAU1977_RATE_CONSTRAINT_MASK_LRCLK;
  696. }
  697. ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
  698. ADAU1977_PLL_CLK_S, clk_src);
  699. if (ret)
  700. return ret;
  701. adau1977->constraints.mask = mask;
  702. adau1977->sysclk_src = source;
  703. adau1977->sysclk = freq;
  704. return 0;
  705. }
  706. static int adau1977_component_probe(struct snd_soc_component *component)
  707. {
  708. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  709. struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
  710. int ret;
  711. switch (adau1977->type) {
  712. case ADAU1977:
  713. ret = snd_soc_dapm_new_controls(dapm,
  714. adau1977_micbias_dapm_widgets,
  715. ARRAY_SIZE(adau1977_micbias_dapm_widgets));
  716. if (ret < 0)
  717. return ret;
  718. break;
  719. default:
  720. break;
  721. }
  722. return 0;
  723. }
  724. static const struct snd_soc_component_driver adau1977_component_driver = {
  725. .probe = adau1977_component_probe,
  726. .set_bias_level = adau1977_set_bias_level,
  727. .set_sysclk = adau1977_set_sysclk,
  728. .controls = adau1977_snd_controls,
  729. .num_controls = ARRAY_SIZE(adau1977_snd_controls),
  730. .dapm_widgets = adau1977_dapm_widgets,
  731. .num_dapm_widgets = ARRAY_SIZE(adau1977_dapm_widgets),
  732. .dapm_routes = adau1977_dapm_routes,
  733. .num_dapm_routes = ARRAY_SIZE(adau1977_dapm_routes),
  734. .use_pmdown_time = 1,
  735. .endianness = 1,
  736. .non_legacy_dai_naming = 1,
  737. };
  738. static int adau1977_setup_micbias(struct adau1977 *adau1977)
  739. {
  740. struct adau1977_platform_data *pdata = adau1977->dev->platform_data;
  741. unsigned int micbias;
  742. if (pdata)
  743. micbias = pdata->micbias;
  744. else if (device_property_read_u32(adau1977->dev, "adi,micbias",
  745. &micbias))
  746. micbias = ADAU1977_MICBIAS_8V5;
  747. if (micbias > ADAU1977_MICBIAS_9V0) {
  748. dev_err(adau1977->dev, "Invalid value for 'adi,micbias'\n");
  749. return -EINVAL;
  750. }
  751. return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MICBIAS,
  752. ADAU1977_MICBIAS_MB_VOLTS_MASK,
  753. micbias << ADAU1977_MICBIAS_MB_VOLTS_OFFSET);
  754. }
  755. int adau1977_probe(struct device *dev, struct regmap *regmap,
  756. enum adau1977_type type, void (*switch_mode)(struct device *dev))
  757. {
  758. unsigned int power_off_mask;
  759. struct adau1977 *adau1977;
  760. int ret;
  761. if (IS_ERR(regmap))
  762. return PTR_ERR(regmap);
  763. adau1977 = devm_kzalloc(dev, sizeof(*adau1977), GFP_KERNEL);
  764. if (adau1977 == NULL)
  765. return -ENOMEM;
  766. adau1977->dev = dev;
  767. adau1977->type = type;
  768. adau1977->regmap = regmap;
  769. adau1977->switch_mode = switch_mode;
  770. adau1977->max_master_fs = 192000;
  771. adau1977->constraints.list = adau1977_rates;
  772. adau1977->constraints.count = ARRAY_SIZE(adau1977_rates);
  773. adau1977->avdd_reg = devm_regulator_get(dev, "AVDD");
  774. if (IS_ERR(adau1977->avdd_reg))
  775. return PTR_ERR(adau1977->avdd_reg);
  776. adau1977->dvdd_reg = devm_regulator_get_optional(dev, "DVDD");
  777. if (IS_ERR(adau1977->dvdd_reg)) {
  778. if (PTR_ERR(adau1977->dvdd_reg) != -ENODEV)
  779. return PTR_ERR(adau1977->dvdd_reg);
  780. adau1977->dvdd_reg = NULL;
  781. }
  782. adau1977->reset_gpio = devm_gpiod_get_optional(dev, "reset",
  783. GPIOD_OUT_LOW);
  784. if (IS_ERR(adau1977->reset_gpio))
  785. return PTR_ERR(adau1977->reset_gpio);
  786. dev_set_drvdata(dev, adau1977);
  787. if (adau1977->reset_gpio)
  788. ndelay(100);
  789. ret = adau1977_power_enable(adau1977);
  790. if (ret)
  791. return ret;
  792. if (type == ADAU1977) {
  793. ret = adau1977_setup_micbias(adau1977);
  794. if (ret)
  795. goto err_poweroff;
  796. }
  797. if (adau1977->dvdd_reg)
  798. power_off_mask = ~0;
  799. else
  800. power_off_mask = (unsigned int)~ADAU1977_BLOCK_POWER_SAI_LDO_EN;
  801. ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
  802. power_off_mask, 0x00);
  803. if (ret)
  804. goto err_poweroff;
  805. ret = adau1977_power_disable(adau1977);
  806. if (ret)
  807. return ret;
  808. return devm_snd_soc_register_component(dev, &adau1977_component_driver,
  809. &adau1977_dai, 1);
  810. err_poweroff:
  811. adau1977_power_disable(adau1977);
  812. return ret;
  813. }
  814. EXPORT_SYMBOL_GPL(adau1977_probe);
  815. static bool adau1977_register_volatile(struct device *dev, unsigned int reg)
  816. {
  817. switch (reg) {
  818. case ADAU1977_REG_STATUS(0):
  819. case ADAU1977_REG_STATUS(1):
  820. case ADAU1977_REG_STATUS(2):
  821. case ADAU1977_REG_STATUS(3):
  822. case ADAU1977_REG_ADC_CLIP:
  823. return true;
  824. }
  825. return false;
  826. }
  827. const struct regmap_config adau1977_regmap_config = {
  828. .max_register = ADAU1977_REG_DC_HPF_CAL,
  829. .volatile_reg = adau1977_register_volatile,
  830. .cache_type = REGCACHE_RBTREE,
  831. .reg_defaults = adau1977_reg_defaults,
  832. .num_reg_defaults = ARRAY_SIZE(adau1977_reg_defaults),
  833. };
  834. EXPORT_SYMBOL_GPL(adau1977_regmap_config);
  835. MODULE_DESCRIPTION("ASoC ADAU1977/ADAU1978/ADAU1979 driver");
  836. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  837. MODULE_LICENSE("GPL");