adau17x1.h 3.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __ADAU17X1_H__
  3. #define __ADAU17X1_H__
  4. #include <linux/regmap.h>
  5. #include <linux/platform_data/adau17x1.h>
  6. #include "sigmadsp.h"
  7. enum adau17x1_type {
  8. ADAU1361,
  9. ADAU1761,
  10. ADAU1381,
  11. ADAU1781,
  12. };
  13. enum adau17x1_pll {
  14. ADAU17X1_PLL,
  15. };
  16. enum adau17x1_pll_src {
  17. ADAU17X1_PLL_SRC_MCLK,
  18. };
  19. enum adau17x1_clk_src {
  20. /* Automatically configure PLL based on the sample rate */
  21. ADAU17X1_CLK_SRC_PLL_AUTO,
  22. ADAU17X1_CLK_SRC_MCLK,
  23. ADAU17X1_CLK_SRC_PLL,
  24. };
  25. struct clk;
  26. struct adau {
  27. unsigned int sysclk;
  28. unsigned int pll_freq;
  29. struct clk *mclk;
  30. enum adau17x1_clk_src clk_src;
  31. enum adau17x1_type type;
  32. void (*switch_mode)(struct device *dev);
  33. unsigned int dai_fmt;
  34. uint8_t pll_regs[6];
  35. bool master;
  36. unsigned int tdm_slot[2];
  37. bool dsp_bypass[2];
  38. struct regmap *regmap;
  39. struct sigmadsp *sigmadsp;
  40. };
  41. int adau17x1_add_widgets(struct snd_soc_component *component);
  42. int adau17x1_add_routes(struct snd_soc_component *component);
  43. int adau17x1_probe(struct device *dev, struct regmap *regmap,
  44. enum adau17x1_type type, void (*switch_mode)(struct device *dev),
  45. const char *firmware_name);
  46. void adau17x1_remove(struct device *dev);
  47. int adau17x1_set_micbias_voltage(struct snd_soc_component *component,
  48. enum adau17x1_micbias_voltage micbias);
  49. bool adau17x1_readable_register(struct device *dev, unsigned int reg);
  50. bool adau17x1_volatile_register(struct device *dev, unsigned int reg);
  51. bool adau17x1_precious_register(struct device *dev, unsigned int reg);
  52. int adau17x1_resume(struct snd_soc_component *component);
  53. extern const struct snd_soc_dai_ops adau17x1_dai_ops;
  54. #define ADAU17X1_CLOCK_CONTROL 0x4000
  55. #define ADAU17X1_PLL_CONTROL 0x4002
  56. #define ADAU17X1_REC_POWER_MGMT 0x4009
  57. #define ADAU17X1_MICBIAS 0x4010
  58. #define ADAU17X1_SERIAL_PORT0 0x4015
  59. #define ADAU17X1_SERIAL_PORT1 0x4016
  60. #define ADAU17X1_CONVERTER0 0x4017
  61. #define ADAU17X1_CONVERTER1 0x4018
  62. #define ADAU17X1_LEFT_INPUT_DIGITAL_VOL 0x401a
  63. #define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL 0x401b
  64. #define ADAU17X1_ADC_CONTROL 0x4019
  65. #define ADAU17X1_PLAY_POWER_MGMT 0x4029
  66. #define ADAU17X1_DAC_CONTROL0 0x402a
  67. #define ADAU17X1_DAC_CONTROL1 0x402b
  68. #define ADAU17X1_DAC_CONTROL2 0x402c
  69. #define ADAU17X1_SERIAL_PORT_PAD 0x402d
  70. #define ADAU17X1_CONTROL_PORT_PAD0 0x402f
  71. #define ADAU17X1_CONTROL_PORT_PAD1 0x4030
  72. #define ADAU17X1_DSP_SAMPLING_RATE 0x40eb
  73. #define ADAU17X1_SERIAL_INPUT_ROUTE 0x40f2
  74. #define ADAU17X1_SERIAL_OUTPUT_ROUTE 0x40f3
  75. #define ADAU17X1_DSP_ENABLE 0x40f5
  76. #define ADAU17X1_DSP_RUN 0x40f6
  77. #define ADAU17X1_SERIAL_SAMPLING_RATE 0x40f8
  78. #define ADAU17X1_SERIAL_PORT0_BCLK_POL BIT(4)
  79. #define ADAU17X1_SERIAL_PORT0_LRCLK_POL BIT(3)
  80. #define ADAU17X1_SERIAL_PORT0_MASTER BIT(0)
  81. #define ADAU17X1_SERIAL_PORT1_DELAY1 0x00
  82. #define ADAU17X1_SERIAL_PORT1_DELAY0 0x01
  83. #define ADAU17X1_SERIAL_PORT1_DELAY8 0x02
  84. #define ADAU17X1_SERIAL_PORT1_DELAY16 0x03
  85. #define ADAU17X1_SERIAL_PORT1_DELAY_MASK 0x03
  86. #define ADAU17X1_CLOCK_CONTROL_INFREQ_MASK 0x6
  87. #define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL BIT(3)
  88. #define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN BIT(0)
  89. #define ADAU17X1_SERIAL_PORT1_BCLK64 (0x0 << 5)
  90. #define ADAU17X1_SERIAL_PORT1_BCLK32 (0x1 << 5)
  91. #define ADAU17X1_SERIAL_PORT1_BCLK48 (0x2 << 5)
  92. #define ADAU17X1_SERIAL_PORT1_BCLK128 (0x3 << 5)
  93. #define ADAU17X1_SERIAL_PORT1_BCLK256 (0x4 << 5)
  94. #define ADAU17X1_SERIAL_PORT1_BCLK_MASK (0x7 << 5)
  95. #define ADAU17X1_SERIAL_PORT0_STEREO (0x0 << 1)
  96. #define ADAU17X1_SERIAL_PORT0_TDM4 (0x1 << 1)
  97. #define ADAU17X1_SERIAL_PORT0_TDM8 (0x2 << 1)
  98. #define ADAU17X1_SERIAL_PORT0_TDM_MASK (0x3 << 1)
  99. #define ADAU17X1_SERIAL_PORT0_PULSE_MODE BIT(5)
  100. #define ADAU17X1_CONVERTER0_DAC_PAIR(x) (((x) - 1) << 5)
  101. #define ADAU17X1_CONVERTER0_DAC_PAIR_MASK (0x3 << 5)
  102. #define ADAU17X1_CONVERTER1_ADC_PAIR(x) ((x) - 1)
  103. #define ADAU17X1_CONVERTER1_ADC_PAIR_MASK 0x3
  104. #define ADAU17X1_CONVERTER0_CONVSR_MASK 0x7
  105. #define ADAU17X1_CONVERTER0_ADOSR BIT(3)
  106. #endif