adau1701.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for ADAU1701 SigmaDSP processor
  4. *
  5. * Copyright 2011 Analog Devices Inc.
  6. * Author: Lars-Peter Clausen <lars@metafoo.de>
  7. * based on an inital version by Cliff Cai <cliff.cai@analog.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/init.h>
  11. #include <linux/i2c.h>
  12. #include <linux/delay.h>
  13. #include <linux/slab.h>
  14. #include <linux/of.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/of_device.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/regmap.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include <asm/unaligned.h>
  24. #include "sigmadsp.h"
  25. #include "adau1701.h"
  26. #define ADAU1701_SAFELOAD_DATA(i) (0x0810 + (i))
  27. #define ADAU1701_SAFELOAD_ADDR(i) (0x0815 + (i))
  28. #define ADAU1701_DSPCTRL 0x081c
  29. #define ADAU1701_SEROCTL 0x081e
  30. #define ADAU1701_SERICTL 0x081f
  31. #define ADAU1701_AUXNPOW 0x0822
  32. #define ADAU1701_PINCONF_0 0x0820
  33. #define ADAU1701_PINCONF_1 0x0821
  34. #define ADAU1701_AUXNPOW 0x0822
  35. #define ADAU1701_OSCIPOW 0x0826
  36. #define ADAU1701_DACSET 0x0827
  37. #define ADAU1701_MAX_REGISTER 0x0828
  38. #define ADAU1701_DSPCTRL_CR (1 << 2)
  39. #define ADAU1701_DSPCTRL_DAM (1 << 3)
  40. #define ADAU1701_DSPCTRL_ADM (1 << 4)
  41. #define ADAU1701_DSPCTRL_IST (1 << 5)
  42. #define ADAU1701_DSPCTRL_SR_48 0x00
  43. #define ADAU1701_DSPCTRL_SR_96 0x01
  44. #define ADAU1701_DSPCTRL_SR_192 0x02
  45. #define ADAU1701_DSPCTRL_SR_MASK 0x03
  46. #define ADAU1701_SEROCTL_INV_LRCLK 0x2000
  47. #define ADAU1701_SEROCTL_INV_BCLK 0x1000
  48. #define ADAU1701_SEROCTL_MASTER 0x0800
  49. #define ADAU1701_SEROCTL_OBF16 0x0000
  50. #define ADAU1701_SEROCTL_OBF8 0x0200
  51. #define ADAU1701_SEROCTL_OBF4 0x0400
  52. #define ADAU1701_SEROCTL_OBF2 0x0600
  53. #define ADAU1701_SEROCTL_OBF_MASK 0x0600
  54. #define ADAU1701_SEROCTL_OLF1024 0x0000
  55. #define ADAU1701_SEROCTL_OLF512 0x0080
  56. #define ADAU1701_SEROCTL_OLF256 0x0100
  57. #define ADAU1701_SEROCTL_OLF_MASK 0x0180
  58. #define ADAU1701_SEROCTL_MSB_DEALY1 0x0000
  59. #define ADAU1701_SEROCTL_MSB_DEALY0 0x0004
  60. #define ADAU1701_SEROCTL_MSB_DEALY8 0x0008
  61. #define ADAU1701_SEROCTL_MSB_DEALY12 0x000c
  62. #define ADAU1701_SEROCTL_MSB_DEALY16 0x0010
  63. #define ADAU1701_SEROCTL_MSB_DEALY_MASK 0x001c
  64. #define ADAU1701_SEROCTL_WORD_LEN_24 0x0000
  65. #define ADAU1701_SEROCTL_WORD_LEN_20 0x0001
  66. #define ADAU1701_SEROCTL_WORD_LEN_16 0x0002
  67. #define ADAU1701_SEROCTL_WORD_LEN_MASK 0x0003
  68. #define ADAU1701_AUXNPOW_VBPD 0x40
  69. #define ADAU1701_AUXNPOW_VRPD 0x20
  70. #define ADAU1701_SERICTL_I2S 0
  71. #define ADAU1701_SERICTL_LEFTJ 1
  72. #define ADAU1701_SERICTL_TDM 2
  73. #define ADAU1701_SERICTL_RIGHTJ_24 3
  74. #define ADAU1701_SERICTL_RIGHTJ_20 4
  75. #define ADAU1701_SERICTL_RIGHTJ_18 5
  76. #define ADAU1701_SERICTL_RIGHTJ_16 6
  77. #define ADAU1701_SERICTL_MODE_MASK 7
  78. #define ADAU1701_SERICTL_INV_BCLK BIT(3)
  79. #define ADAU1701_SERICTL_INV_LRCLK BIT(4)
  80. #define ADAU1701_OSCIPOW_OPD 0x04
  81. #define ADAU1701_DACSET_DACINIT 1
  82. #define ADAU1707_CLKDIV_UNSET (-1U)
  83. #define ADAU1701_FIRMWARE "adau1701.bin"
  84. static const char * const supply_names[] = {
  85. "dvdd", "avdd"
  86. };
  87. struct adau1701 {
  88. int gpio_nreset;
  89. int gpio_pll_mode[2];
  90. unsigned int dai_fmt;
  91. unsigned int pll_clkdiv;
  92. unsigned int sysclk;
  93. struct regmap *regmap;
  94. struct i2c_client *client;
  95. u8 pin_config[12];
  96. struct sigmadsp *sigmadsp;
  97. struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  98. };
  99. static const struct snd_kcontrol_new adau1701_controls[] = {
  100. SOC_SINGLE("Master Capture Switch", ADAU1701_DSPCTRL, 4, 1, 0),
  101. };
  102. static const struct snd_soc_dapm_widget adau1701_dapm_widgets[] = {
  103. SND_SOC_DAPM_DAC("DAC0", "Playback", ADAU1701_AUXNPOW, 3, 1),
  104. SND_SOC_DAPM_DAC("DAC1", "Playback", ADAU1701_AUXNPOW, 2, 1),
  105. SND_SOC_DAPM_DAC("DAC2", "Playback", ADAU1701_AUXNPOW, 1, 1),
  106. SND_SOC_DAPM_DAC("DAC3", "Playback", ADAU1701_AUXNPOW, 0, 1),
  107. SND_SOC_DAPM_ADC("ADC", "Capture", ADAU1701_AUXNPOW, 7, 1),
  108. SND_SOC_DAPM_OUTPUT("OUT0"),
  109. SND_SOC_DAPM_OUTPUT("OUT1"),
  110. SND_SOC_DAPM_OUTPUT("OUT2"),
  111. SND_SOC_DAPM_OUTPUT("OUT3"),
  112. SND_SOC_DAPM_INPUT("IN0"),
  113. SND_SOC_DAPM_INPUT("IN1"),
  114. };
  115. static const struct snd_soc_dapm_route adau1701_dapm_routes[] = {
  116. { "OUT0", NULL, "DAC0" },
  117. { "OUT1", NULL, "DAC1" },
  118. { "OUT2", NULL, "DAC2" },
  119. { "OUT3", NULL, "DAC3" },
  120. { "ADC", NULL, "IN0" },
  121. { "ADC", NULL, "IN1" },
  122. };
  123. static unsigned int adau1701_register_size(struct device *dev,
  124. unsigned int reg)
  125. {
  126. switch (reg) {
  127. case ADAU1701_PINCONF_0:
  128. case ADAU1701_PINCONF_1:
  129. return 3;
  130. case ADAU1701_DSPCTRL:
  131. case ADAU1701_SEROCTL:
  132. case ADAU1701_AUXNPOW:
  133. case ADAU1701_OSCIPOW:
  134. case ADAU1701_DACSET:
  135. return 2;
  136. case ADAU1701_SERICTL:
  137. return 1;
  138. }
  139. dev_err(dev, "Unsupported register address: %d\n", reg);
  140. return 0;
  141. }
  142. static bool adau1701_volatile_reg(struct device *dev, unsigned int reg)
  143. {
  144. switch (reg) {
  145. case ADAU1701_DACSET:
  146. case ADAU1701_DSPCTRL:
  147. return true;
  148. default:
  149. return false;
  150. }
  151. }
  152. static int adau1701_reg_write(void *context, unsigned int reg,
  153. unsigned int value)
  154. {
  155. struct i2c_client *client = context;
  156. unsigned int i;
  157. unsigned int size;
  158. uint8_t buf[5];
  159. int ret;
  160. size = adau1701_register_size(&client->dev, reg);
  161. if (size == 0)
  162. return -EINVAL;
  163. buf[0] = reg >> 8;
  164. buf[1] = reg & 0xff;
  165. for (i = size + 1; i >= 2; --i) {
  166. buf[i] = value;
  167. value >>= 8;
  168. }
  169. ret = i2c_master_send(client, buf, size + 2);
  170. if (ret == size + 2)
  171. return 0;
  172. else if (ret < 0)
  173. return ret;
  174. else
  175. return -EIO;
  176. }
  177. static int adau1701_reg_read(void *context, unsigned int reg,
  178. unsigned int *value)
  179. {
  180. int ret;
  181. unsigned int i;
  182. unsigned int size;
  183. uint8_t send_buf[2], recv_buf[3];
  184. struct i2c_client *client = context;
  185. struct i2c_msg msgs[2];
  186. size = adau1701_register_size(&client->dev, reg);
  187. if (size == 0)
  188. return -EINVAL;
  189. send_buf[0] = reg >> 8;
  190. send_buf[1] = reg & 0xff;
  191. msgs[0].addr = client->addr;
  192. msgs[0].len = sizeof(send_buf);
  193. msgs[0].buf = send_buf;
  194. msgs[0].flags = 0;
  195. msgs[1].addr = client->addr;
  196. msgs[1].len = size;
  197. msgs[1].buf = recv_buf;
  198. msgs[1].flags = I2C_M_RD;
  199. ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  200. if (ret < 0)
  201. return ret;
  202. else if (ret != ARRAY_SIZE(msgs))
  203. return -EIO;
  204. *value = 0;
  205. for (i = 0; i < size; i++) {
  206. *value <<= 8;
  207. *value |= recv_buf[i];
  208. }
  209. return 0;
  210. }
  211. static int adau1701_safeload(struct sigmadsp *sigmadsp, unsigned int addr,
  212. const uint8_t bytes[], size_t len)
  213. {
  214. struct i2c_client *client = to_i2c_client(sigmadsp->dev);
  215. struct adau1701 *adau1701 = i2c_get_clientdata(client);
  216. unsigned int val;
  217. unsigned int i;
  218. uint8_t buf[10];
  219. int ret;
  220. ret = regmap_read(adau1701->regmap, ADAU1701_DSPCTRL, &val);
  221. if (ret)
  222. return ret;
  223. if (val & ADAU1701_DSPCTRL_IST)
  224. msleep(50);
  225. for (i = 0; i < len / 4; i++) {
  226. put_unaligned_le16(ADAU1701_SAFELOAD_DATA(i), buf);
  227. buf[2] = 0x00;
  228. memcpy(buf + 3, bytes + i * 4, 4);
  229. ret = i2c_master_send(client, buf, 7);
  230. if (ret < 0)
  231. return ret;
  232. else if (ret != 7)
  233. return -EIO;
  234. put_unaligned_le16(ADAU1701_SAFELOAD_ADDR(i), buf);
  235. put_unaligned_le16(addr + i, buf + 2);
  236. ret = i2c_master_send(client, buf, 4);
  237. if (ret < 0)
  238. return ret;
  239. else if (ret != 4)
  240. return -EIO;
  241. }
  242. return regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL,
  243. ADAU1701_DSPCTRL_IST, ADAU1701_DSPCTRL_IST);
  244. }
  245. static const struct sigmadsp_ops adau1701_sigmadsp_ops = {
  246. .safeload = adau1701_safeload,
  247. };
  248. static int adau1701_reset(struct snd_soc_component *component, unsigned int clkdiv,
  249. unsigned int rate)
  250. {
  251. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  252. int ret;
  253. sigmadsp_reset(adau1701->sigmadsp);
  254. if (clkdiv != ADAU1707_CLKDIV_UNSET &&
  255. gpio_is_valid(adau1701->gpio_pll_mode[0]) &&
  256. gpio_is_valid(adau1701->gpio_pll_mode[1])) {
  257. switch (clkdiv) {
  258. case 64:
  259. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0);
  260. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0);
  261. break;
  262. case 256:
  263. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0);
  264. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1);
  265. break;
  266. case 384:
  267. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1);
  268. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0);
  269. break;
  270. case 0: /* fallback */
  271. case 512:
  272. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1);
  273. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1);
  274. break;
  275. }
  276. }
  277. adau1701->pll_clkdiv = clkdiv;
  278. if (gpio_is_valid(adau1701->gpio_nreset)) {
  279. gpio_set_value_cansleep(adau1701->gpio_nreset, 0);
  280. /* minimum reset time is 20ns */
  281. udelay(1);
  282. gpio_set_value_cansleep(adau1701->gpio_nreset, 1);
  283. /* power-up time may be as long as 85ms */
  284. mdelay(85);
  285. }
  286. /*
  287. * Postpone the firmware download to a point in time when we
  288. * know the correct PLL setup
  289. */
  290. if (clkdiv != ADAU1707_CLKDIV_UNSET) {
  291. ret = sigmadsp_setup(adau1701->sigmadsp, rate);
  292. if (ret) {
  293. dev_warn(component->dev, "Failed to load firmware\n");
  294. return ret;
  295. }
  296. }
  297. regmap_write(adau1701->regmap, ADAU1701_DACSET, ADAU1701_DACSET_DACINIT);
  298. regmap_write(adau1701->regmap, ADAU1701_DSPCTRL, ADAU1701_DSPCTRL_CR);
  299. regcache_mark_dirty(adau1701->regmap);
  300. regcache_sync(adau1701->regmap);
  301. return 0;
  302. }
  303. static int adau1701_set_capture_pcm_format(struct snd_soc_component *component,
  304. struct snd_pcm_hw_params *params)
  305. {
  306. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  307. unsigned int mask = ADAU1701_SEROCTL_WORD_LEN_MASK;
  308. unsigned int val;
  309. switch (params_width(params)) {
  310. case 16:
  311. val = ADAU1701_SEROCTL_WORD_LEN_16;
  312. break;
  313. case 20:
  314. val = ADAU1701_SEROCTL_WORD_LEN_20;
  315. break;
  316. case 24:
  317. val = ADAU1701_SEROCTL_WORD_LEN_24;
  318. break;
  319. default:
  320. return -EINVAL;
  321. }
  322. if (adau1701->dai_fmt == SND_SOC_DAIFMT_RIGHT_J) {
  323. switch (params_width(params)) {
  324. case 16:
  325. val |= ADAU1701_SEROCTL_MSB_DEALY16;
  326. break;
  327. case 20:
  328. val |= ADAU1701_SEROCTL_MSB_DEALY12;
  329. break;
  330. case 24:
  331. val |= ADAU1701_SEROCTL_MSB_DEALY8;
  332. break;
  333. }
  334. mask |= ADAU1701_SEROCTL_MSB_DEALY_MASK;
  335. }
  336. regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL, mask, val);
  337. return 0;
  338. }
  339. static int adau1701_set_playback_pcm_format(struct snd_soc_component *component,
  340. struct snd_pcm_hw_params *params)
  341. {
  342. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  343. unsigned int val;
  344. if (adau1701->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
  345. return 0;
  346. switch (params_width(params)) {
  347. case 16:
  348. val = ADAU1701_SERICTL_RIGHTJ_16;
  349. break;
  350. case 20:
  351. val = ADAU1701_SERICTL_RIGHTJ_20;
  352. break;
  353. case 24:
  354. val = ADAU1701_SERICTL_RIGHTJ_24;
  355. break;
  356. default:
  357. return -EINVAL;
  358. }
  359. regmap_update_bits(adau1701->regmap, ADAU1701_SERICTL,
  360. ADAU1701_SERICTL_MODE_MASK, val);
  361. return 0;
  362. }
  363. static int adau1701_hw_params(struct snd_pcm_substream *substream,
  364. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  365. {
  366. struct snd_soc_component *component = dai->component;
  367. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  368. unsigned int clkdiv = adau1701->sysclk / params_rate(params);
  369. unsigned int val;
  370. int ret;
  371. /*
  372. * If the mclk/lrclk ratio changes, the chip needs updated PLL
  373. * mode GPIO settings, and a full reset cycle, including a new
  374. * firmware upload.
  375. */
  376. if (clkdiv != adau1701->pll_clkdiv) {
  377. ret = adau1701_reset(component, clkdiv, params_rate(params));
  378. if (ret < 0)
  379. return ret;
  380. }
  381. switch (params_rate(params)) {
  382. case 192000:
  383. val = ADAU1701_DSPCTRL_SR_192;
  384. break;
  385. case 96000:
  386. val = ADAU1701_DSPCTRL_SR_96;
  387. break;
  388. case 48000:
  389. val = ADAU1701_DSPCTRL_SR_48;
  390. break;
  391. default:
  392. return -EINVAL;
  393. }
  394. regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL,
  395. ADAU1701_DSPCTRL_SR_MASK, val);
  396. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  397. return adau1701_set_playback_pcm_format(component, params);
  398. else
  399. return adau1701_set_capture_pcm_format(component, params);
  400. }
  401. static int adau1701_set_dai_fmt(struct snd_soc_dai *codec_dai,
  402. unsigned int fmt)
  403. {
  404. struct snd_soc_component *component = codec_dai->component;
  405. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  406. unsigned int serictl = 0x00, seroctl = 0x00;
  407. bool invert_lrclk;
  408. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  409. case SND_SOC_DAIFMT_CBM_CFM:
  410. /* master, 64-bits per sample, 1 frame per sample */
  411. seroctl |= ADAU1701_SEROCTL_MASTER | ADAU1701_SEROCTL_OBF16
  412. | ADAU1701_SEROCTL_OLF1024;
  413. break;
  414. case SND_SOC_DAIFMT_CBS_CFS:
  415. break;
  416. default:
  417. return -EINVAL;
  418. }
  419. /* clock inversion */
  420. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  421. case SND_SOC_DAIFMT_NB_NF:
  422. invert_lrclk = false;
  423. break;
  424. case SND_SOC_DAIFMT_NB_IF:
  425. invert_lrclk = true;
  426. break;
  427. case SND_SOC_DAIFMT_IB_NF:
  428. invert_lrclk = false;
  429. serictl |= ADAU1701_SERICTL_INV_BCLK;
  430. seroctl |= ADAU1701_SEROCTL_INV_BCLK;
  431. break;
  432. case SND_SOC_DAIFMT_IB_IF:
  433. invert_lrclk = true;
  434. serictl |= ADAU1701_SERICTL_INV_BCLK;
  435. seroctl |= ADAU1701_SEROCTL_INV_BCLK;
  436. break;
  437. default:
  438. return -EINVAL;
  439. }
  440. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  441. case SND_SOC_DAIFMT_I2S:
  442. break;
  443. case SND_SOC_DAIFMT_LEFT_J:
  444. serictl |= ADAU1701_SERICTL_LEFTJ;
  445. seroctl |= ADAU1701_SEROCTL_MSB_DEALY0;
  446. invert_lrclk = !invert_lrclk;
  447. break;
  448. case SND_SOC_DAIFMT_RIGHT_J:
  449. serictl |= ADAU1701_SERICTL_RIGHTJ_24;
  450. seroctl |= ADAU1701_SEROCTL_MSB_DEALY8;
  451. invert_lrclk = !invert_lrclk;
  452. break;
  453. default:
  454. return -EINVAL;
  455. }
  456. if (invert_lrclk) {
  457. seroctl |= ADAU1701_SEROCTL_INV_LRCLK;
  458. serictl |= ADAU1701_SERICTL_INV_LRCLK;
  459. }
  460. adau1701->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  461. regmap_write(adau1701->regmap, ADAU1701_SERICTL, serictl);
  462. regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL,
  463. ~ADAU1701_SEROCTL_WORD_LEN_MASK, seroctl);
  464. return 0;
  465. }
  466. static int adau1701_set_bias_level(struct snd_soc_component *component,
  467. enum snd_soc_bias_level level)
  468. {
  469. unsigned int mask = ADAU1701_AUXNPOW_VBPD | ADAU1701_AUXNPOW_VRPD;
  470. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  471. switch (level) {
  472. case SND_SOC_BIAS_ON:
  473. break;
  474. case SND_SOC_BIAS_PREPARE:
  475. break;
  476. case SND_SOC_BIAS_STANDBY:
  477. /* Enable VREF and VREF buffer */
  478. regmap_update_bits(adau1701->regmap,
  479. ADAU1701_AUXNPOW, mask, 0x00);
  480. break;
  481. case SND_SOC_BIAS_OFF:
  482. /* Disable VREF and VREF buffer */
  483. regmap_update_bits(adau1701->regmap,
  484. ADAU1701_AUXNPOW, mask, mask);
  485. break;
  486. }
  487. return 0;
  488. }
  489. static int adau1701_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
  490. {
  491. struct snd_soc_component *component = dai->component;
  492. unsigned int mask = ADAU1701_DSPCTRL_DAM;
  493. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  494. unsigned int val;
  495. if (mute)
  496. val = 0;
  497. else
  498. val = mask;
  499. regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL, mask, val);
  500. return 0;
  501. }
  502. static int adau1701_set_sysclk(struct snd_soc_component *component, int clk_id,
  503. int source, unsigned int freq, int dir)
  504. {
  505. unsigned int val;
  506. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  507. switch (clk_id) {
  508. case ADAU1701_CLK_SRC_OSC:
  509. val = 0x0;
  510. break;
  511. case ADAU1701_CLK_SRC_MCLK:
  512. val = ADAU1701_OSCIPOW_OPD;
  513. break;
  514. default:
  515. return -EINVAL;
  516. }
  517. regmap_update_bits(adau1701->regmap, ADAU1701_OSCIPOW,
  518. ADAU1701_OSCIPOW_OPD, val);
  519. adau1701->sysclk = freq;
  520. return 0;
  521. }
  522. static int adau1701_startup(struct snd_pcm_substream *substream,
  523. struct snd_soc_dai *dai)
  524. {
  525. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(dai->component);
  526. return sigmadsp_restrict_params(adau1701->sigmadsp, substream);
  527. }
  528. #define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
  529. SNDRV_PCM_RATE_192000)
  530. #define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  531. SNDRV_PCM_FMTBIT_S24_LE)
  532. static const struct snd_soc_dai_ops adau1701_dai_ops = {
  533. .set_fmt = adau1701_set_dai_fmt,
  534. .hw_params = adau1701_hw_params,
  535. .mute_stream = adau1701_mute_stream,
  536. .startup = adau1701_startup,
  537. .no_capture_mute = 1,
  538. };
  539. static struct snd_soc_dai_driver adau1701_dai = {
  540. .name = "adau1701",
  541. .playback = {
  542. .stream_name = "Playback",
  543. .channels_min = 2,
  544. .channels_max = 8,
  545. .rates = ADAU1701_RATES,
  546. .formats = ADAU1701_FORMATS,
  547. },
  548. .capture = {
  549. .stream_name = "Capture",
  550. .channels_min = 2,
  551. .channels_max = 8,
  552. .rates = ADAU1701_RATES,
  553. .formats = ADAU1701_FORMATS,
  554. },
  555. .ops = &adau1701_dai_ops,
  556. .symmetric_rates = 1,
  557. };
  558. #ifdef CONFIG_OF
  559. static const struct of_device_id adau1701_dt_ids[] = {
  560. { .compatible = "adi,adau1701", },
  561. { }
  562. };
  563. MODULE_DEVICE_TABLE(of, adau1701_dt_ids);
  564. #endif
  565. static int adau1701_probe(struct snd_soc_component *component)
  566. {
  567. int i, ret;
  568. unsigned int val;
  569. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  570. ret = sigmadsp_attach(adau1701->sigmadsp, component);
  571. if (ret)
  572. return ret;
  573. ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
  574. adau1701->supplies);
  575. if (ret < 0) {
  576. dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
  577. return ret;
  578. }
  579. /*
  580. * Let the pll_clkdiv variable default to something that won't happen
  581. * at runtime. That way, we can postpone the firmware download from
  582. * adau1701_reset() to a point in time when we know the correct PLL
  583. * mode parameters.
  584. */
  585. adau1701->pll_clkdiv = ADAU1707_CLKDIV_UNSET;
  586. /* initalize with pre-configured pll mode settings */
  587. ret = adau1701_reset(component, adau1701->pll_clkdiv, 0);
  588. if (ret < 0)
  589. goto exit_regulators_disable;
  590. /* set up pin config */
  591. val = 0;
  592. for (i = 0; i < 6; i++)
  593. val |= adau1701->pin_config[i] << (i * 4);
  594. regmap_write(adau1701->regmap, ADAU1701_PINCONF_0, val);
  595. val = 0;
  596. for (i = 0; i < 6; i++)
  597. val |= adau1701->pin_config[i + 6] << (i * 4);
  598. regmap_write(adau1701->regmap, ADAU1701_PINCONF_1, val);
  599. return 0;
  600. exit_regulators_disable:
  601. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
  602. return ret;
  603. }
  604. static void adau1701_remove(struct snd_soc_component *component)
  605. {
  606. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  607. if (gpio_is_valid(adau1701->gpio_nreset))
  608. gpio_set_value_cansleep(adau1701->gpio_nreset, 0);
  609. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
  610. }
  611. #ifdef CONFIG_PM
  612. static int adau1701_suspend(struct snd_soc_component *component)
  613. {
  614. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  615. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies),
  616. adau1701->supplies);
  617. return 0;
  618. }
  619. static int adau1701_resume(struct snd_soc_component *component)
  620. {
  621. struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
  622. int ret;
  623. ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
  624. adau1701->supplies);
  625. if (ret < 0) {
  626. dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
  627. return ret;
  628. }
  629. return adau1701_reset(component, adau1701->pll_clkdiv, 0);
  630. }
  631. #else
  632. #define adau1701_resume NULL
  633. #define adau1701_suspend NULL
  634. #endif /* CONFIG_PM */
  635. static const struct snd_soc_component_driver adau1701_component_drv = {
  636. .probe = adau1701_probe,
  637. .remove = adau1701_remove,
  638. .resume = adau1701_resume,
  639. .suspend = adau1701_suspend,
  640. .set_bias_level = adau1701_set_bias_level,
  641. .controls = adau1701_controls,
  642. .num_controls = ARRAY_SIZE(adau1701_controls),
  643. .dapm_widgets = adau1701_dapm_widgets,
  644. .num_dapm_widgets = ARRAY_SIZE(adau1701_dapm_widgets),
  645. .dapm_routes = adau1701_dapm_routes,
  646. .num_dapm_routes = ARRAY_SIZE(adau1701_dapm_routes),
  647. .set_sysclk = adau1701_set_sysclk,
  648. .use_pmdown_time = 1,
  649. .endianness = 1,
  650. .non_legacy_dai_naming = 1,
  651. };
  652. static const struct regmap_config adau1701_regmap = {
  653. .reg_bits = 16,
  654. .val_bits = 32,
  655. .max_register = ADAU1701_MAX_REGISTER,
  656. .cache_type = REGCACHE_RBTREE,
  657. .volatile_reg = adau1701_volatile_reg,
  658. .reg_write = adau1701_reg_write,
  659. .reg_read = adau1701_reg_read,
  660. };
  661. static int adau1701_i2c_probe(struct i2c_client *client,
  662. const struct i2c_device_id *id)
  663. {
  664. struct adau1701 *adau1701;
  665. struct device *dev = &client->dev;
  666. int gpio_nreset = -EINVAL;
  667. int gpio_pll_mode[2] = { -EINVAL, -EINVAL };
  668. int ret, i;
  669. adau1701 = devm_kzalloc(dev, sizeof(*adau1701), GFP_KERNEL);
  670. if (!adau1701)
  671. return -ENOMEM;
  672. for (i = 0; i < ARRAY_SIZE(supply_names); i++)
  673. adau1701->supplies[i].supply = supply_names[i];
  674. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(adau1701->supplies),
  675. adau1701->supplies);
  676. if (ret < 0) {
  677. dev_err(dev, "Failed to get regulators: %d\n", ret);
  678. return ret;
  679. }
  680. ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
  681. adau1701->supplies);
  682. if (ret < 0) {
  683. dev_err(dev, "Failed to enable regulators: %d\n", ret);
  684. return ret;
  685. }
  686. adau1701->client = client;
  687. adau1701->regmap = devm_regmap_init(dev, NULL, client,
  688. &adau1701_regmap);
  689. if (IS_ERR(adau1701->regmap)) {
  690. ret = PTR_ERR(adau1701->regmap);
  691. goto exit_regulators_disable;
  692. }
  693. if (dev->of_node) {
  694. gpio_nreset = of_get_named_gpio(dev->of_node, "reset-gpio", 0);
  695. if (gpio_nreset < 0 && gpio_nreset != -ENOENT) {
  696. ret = gpio_nreset;
  697. goto exit_regulators_disable;
  698. }
  699. gpio_pll_mode[0] = of_get_named_gpio(dev->of_node,
  700. "adi,pll-mode-gpios", 0);
  701. if (gpio_pll_mode[0] < 0 && gpio_pll_mode[0] != -ENOENT) {
  702. ret = gpio_pll_mode[0];
  703. goto exit_regulators_disable;
  704. }
  705. gpio_pll_mode[1] = of_get_named_gpio(dev->of_node,
  706. "adi,pll-mode-gpios", 1);
  707. if (gpio_pll_mode[1] < 0 && gpio_pll_mode[1] != -ENOENT) {
  708. ret = gpio_pll_mode[1];
  709. goto exit_regulators_disable;
  710. }
  711. of_property_read_u32(dev->of_node, "adi,pll-clkdiv",
  712. &adau1701->pll_clkdiv);
  713. of_property_read_u8_array(dev->of_node, "adi,pin-config",
  714. adau1701->pin_config,
  715. ARRAY_SIZE(adau1701->pin_config));
  716. }
  717. if (gpio_is_valid(gpio_nreset)) {
  718. ret = devm_gpio_request_one(dev, gpio_nreset, GPIOF_OUT_INIT_LOW,
  719. "ADAU1701 Reset");
  720. if (ret < 0)
  721. goto exit_regulators_disable;
  722. }
  723. if (gpio_is_valid(gpio_pll_mode[0]) &&
  724. gpio_is_valid(gpio_pll_mode[1])) {
  725. ret = devm_gpio_request_one(dev, gpio_pll_mode[0],
  726. GPIOF_OUT_INIT_LOW,
  727. "ADAU1701 PLL mode 0");
  728. if (ret < 0)
  729. goto exit_regulators_disable;
  730. ret = devm_gpio_request_one(dev, gpio_pll_mode[1],
  731. GPIOF_OUT_INIT_LOW,
  732. "ADAU1701 PLL mode 1");
  733. if (ret < 0)
  734. goto exit_regulators_disable;
  735. }
  736. adau1701->gpio_nreset = gpio_nreset;
  737. adau1701->gpio_pll_mode[0] = gpio_pll_mode[0];
  738. adau1701->gpio_pll_mode[1] = gpio_pll_mode[1];
  739. i2c_set_clientdata(client, adau1701);
  740. adau1701->sigmadsp = devm_sigmadsp_init_i2c(client,
  741. &adau1701_sigmadsp_ops, ADAU1701_FIRMWARE);
  742. if (IS_ERR(adau1701->sigmadsp)) {
  743. ret = PTR_ERR(adau1701->sigmadsp);
  744. goto exit_regulators_disable;
  745. }
  746. ret = devm_snd_soc_register_component(&client->dev,
  747. &adau1701_component_drv,
  748. &adau1701_dai, 1);
  749. exit_regulators_disable:
  750. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
  751. return ret;
  752. }
  753. static const struct i2c_device_id adau1701_i2c_id[] = {
  754. { "adau1401", 0 },
  755. { "adau1401a", 0 },
  756. { "adau1701", 0 },
  757. { "adau1702", 0 },
  758. { }
  759. };
  760. MODULE_DEVICE_TABLE(i2c, adau1701_i2c_id);
  761. static struct i2c_driver adau1701_i2c_driver = {
  762. .driver = {
  763. .name = "adau1701",
  764. .of_match_table = of_match_ptr(adau1701_dt_ids),
  765. },
  766. .probe = adau1701_i2c_probe,
  767. .id_table = adau1701_i2c_id,
  768. };
  769. module_i2c_driver(adau1701_i2c_driver);
  770. MODULE_DESCRIPTION("ASoC ADAU1701 SigmaDSP driver");
  771. MODULE_AUTHOR("Cliff Cai <cliff.cai@analog.com>");
  772. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  773. MODULE_LICENSE("GPL");