adau1373.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Analog Devices ADAU1373 Audio Codec drive
  4. *
  5. * Copyright 2011 Analog Devices Inc.
  6. * Author: Lars-Peter Clausen <lars@metafoo.de>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/delay.h>
  11. #include <linux/pm.h>
  12. #include <linux/i2c.h>
  13. #include <linux/slab.h>
  14. #include <linux/gcd.h>
  15. #include <sound/core.h>
  16. #include <sound/pcm.h>
  17. #include <sound/pcm_params.h>
  18. #include <sound/tlv.h>
  19. #include <sound/soc.h>
  20. #include <sound/adau1373.h>
  21. #include "adau1373.h"
  22. #include "adau-utils.h"
  23. struct adau1373_dai {
  24. unsigned int clk_src;
  25. unsigned int sysclk;
  26. bool enable_src;
  27. bool master;
  28. };
  29. struct adau1373 {
  30. struct regmap *regmap;
  31. struct adau1373_dai dais[3];
  32. };
  33. #define ADAU1373_INPUT_MODE 0x00
  34. #define ADAU1373_AINL_CTRL(x) (0x01 + (x) * 2)
  35. #define ADAU1373_AINR_CTRL(x) (0x02 + (x) * 2)
  36. #define ADAU1373_LLINE_OUT(x) (0x9 + (x) * 2)
  37. #define ADAU1373_RLINE_OUT(x) (0xa + (x) * 2)
  38. #define ADAU1373_LSPK_OUT 0x0d
  39. #define ADAU1373_RSPK_OUT 0x0e
  40. #define ADAU1373_LHP_OUT 0x0f
  41. #define ADAU1373_RHP_OUT 0x10
  42. #define ADAU1373_ADC_GAIN 0x11
  43. #define ADAU1373_LADC_MIXER 0x12
  44. #define ADAU1373_RADC_MIXER 0x13
  45. #define ADAU1373_LLINE1_MIX 0x14
  46. #define ADAU1373_RLINE1_MIX 0x15
  47. #define ADAU1373_LLINE2_MIX 0x16
  48. #define ADAU1373_RLINE2_MIX 0x17
  49. #define ADAU1373_LSPK_MIX 0x18
  50. #define ADAU1373_RSPK_MIX 0x19
  51. #define ADAU1373_LHP_MIX 0x1a
  52. #define ADAU1373_RHP_MIX 0x1b
  53. #define ADAU1373_EP_MIX 0x1c
  54. #define ADAU1373_HP_CTRL 0x1d
  55. #define ADAU1373_HP_CTRL2 0x1e
  56. #define ADAU1373_LS_CTRL 0x1f
  57. #define ADAU1373_EP_CTRL 0x21
  58. #define ADAU1373_MICBIAS_CTRL1 0x22
  59. #define ADAU1373_MICBIAS_CTRL2 0x23
  60. #define ADAU1373_OUTPUT_CTRL 0x24
  61. #define ADAU1373_PWDN_CTRL1 0x25
  62. #define ADAU1373_PWDN_CTRL2 0x26
  63. #define ADAU1373_PWDN_CTRL3 0x27
  64. #define ADAU1373_DPLL_CTRL(x) (0x28 + (x) * 7)
  65. #define ADAU1373_PLL_CTRL1(x) (0x29 + (x) * 7)
  66. #define ADAU1373_PLL_CTRL2(x) (0x2a + (x) * 7)
  67. #define ADAU1373_PLL_CTRL3(x) (0x2b + (x) * 7)
  68. #define ADAU1373_PLL_CTRL4(x) (0x2c + (x) * 7)
  69. #define ADAU1373_PLL_CTRL5(x) (0x2d + (x) * 7)
  70. #define ADAU1373_PLL_CTRL6(x) (0x2e + (x) * 7)
  71. #define ADAU1373_HEADDECT 0x36
  72. #define ADAU1373_ADC_DAC_STATUS 0x37
  73. #define ADAU1373_ADC_CTRL 0x3c
  74. #define ADAU1373_DAI(x) (0x44 + (x))
  75. #define ADAU1373_CLK_SRC_DIV(x) (0x40 + (x) * 2)
  76. #define ADAU1373_BCLKDIV(x) (0x47 + (x))
  77. #define ADAU1373_SRC_RATIOA(x) (0x4a + (x) * 2)
  78. #define ADAU1373_SRC_RATIOB(x) (0x4b + (x) * 2)
  79. #define ADAU1373_DEEMP_CTRL 0x50
  80. #define ADAU1373_SRC_DAI_CTRL(x) (0x51 + (x))
  81. #define ADAU1373_DIN_MIX_CTRL(x) (0x56 + (x))
  82. #define ADAU1373_DOUT_MIX_CTRL(x) (0x5b + (x))
  83. #define ADAU1373_DAI_PBL_VOL(x) (0x62 + (x) * 2)
  84. #define ADAU1373_DAI_PBR_VOL(x) (0x63 + (x) * 2)
  85. #define ADAU1373_DAI_RECL_VOL(x) (0x68 + (x) * 2)
  86. #define ADAU1373_DAI_RECR_VOL(x) (0x69 + (x) * 2)
  87. #define ADAU1373_DAC1_PBL_VOL 0x6e
  88. #define ADAU1373_DAC1_PBR_VOL 0x6f
  89. #define ADAU1373_DAC2_PBL_VOL 0x70
  90. #define ADAU1373_DAC2_PBR_VOL 0x71
  91. #define ADAU1373_ADC_RECL_VOL 0x72
  92. #define ADAU1373_ADC_RECR_VOL 0x73
  93. #define ADAU1373_DMIC_RECL_VOL 0x74
  94. #define ADAU1373_DMIC_RECR_VOL 0x75
  95. #define ADAU1373_VOL_GAIN1 0x76
  96. #define ADAU1373_VOL_GAIN2 0x77
  97. #define ADAU1373_VOL_GAIN3 0x78
  98. #define ADAU1373_HPF_CTRL 0x7d
  99. #define ADAU1373_BASS1 0x7e
  100. #define ADAU1373_BASS2 0x7f
  101. #define ADAU1373_DRC(x) (0x80 + (x) * 0x10)
  102. #define ADAU1373_3D_CTRL1 0xc0
  103. #define ADAU1373_3D_CTRL2 0xc1
  104. #define ADAU1373_FDSP_SEL1 0xdc
  105. #define ADAU1373_FDSP_SEL2 0xdd
  106. #define ADAU1373_FDSP_SEL3 0xde
  107. #define ADAU1373_FDSP_SEL4 0xdf
  108. #define ADAU1373_DIGMICCTRL 0xe2
  109. #define ADAU1373_DIGEN 0xeb
  110. #define ADAU1373_SOFT_RESET 0xff
  111. #define ADAU1373_PLL_CTRL6_DPLL_BYPASS BIT(1)
  112. #define ADAU1373_PLL_CTRL6_PLL_EN BIT(0)
  113. #define ADAU1373_DAI_INVERT_BCLK BIT(7)
  114. #define ADAU1373_DAI_MASTER BIT(6)
  115. #define ADAU1373_DAI_INVERT_LRCLK BIT(4)
  116. #define ADAU1373_DAI_WLEN_16 0x0
  117. #define ADAU1373_DAI_WLEN_20 0x4
  118. #define ADAU1373_DAI_WLEN_24 0x8
  119. #define ADAU1373_DAI_WLEN_32 0xc
  120. #define ADAU1373_DAI_WLEN_MASK 0xc
  121. #define ADAU1373_DAI_FORMAT_RIGHT_J 0x0
  122. #define ADAU1373_DAI_FORMAT_LEFT_J 0x1
  123. #define ADAU1373_DAI_FORMAT_I2S 0x2
  124. #define ADAU1373_DAI_FORMAT_DSP 0x3
  125. #define ADAU1373_BCLKDIV_SOURCE BIT(5)
  126. #define ADAU1373_BCLKDIV_SR_MASK (0x07 << 2)
  127. #define ADAU1373_BCLKDIV_BCLK_MASK 0x03
  128. #define ADAU1373_BCLKDIV_32 0x03
  129. #define ADAU1373_BCLKDIV_64 0x02
  130. #define ADAU1373_BCLKDIV_128 0x01
  131. #define ADAU1373_BCLKDIV_256 0x00
  132. #define ADAU1373_ADC_CTRL_PEAK_DETECT BIT(0)
  133. #define ADAU1373_ADC_CTRL_RESET BIT(1)
  134. #define ADAU1373_ADC_CTRL_RESET_FORCE BIT(2)
  135. #define ADAU1373_OUTPUT_CTRL_LDIFF BIT(3)
  136. #define ADAU1373_OUTPUT_CTRL_LNFBEN BIT(2)
  137. #define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0)
  138. #define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4
  139. #define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2
  140. static const struct reg_default adau1373_reg_defaults[] = {
  141. { ADAU1373_INPUT_MODE, 0x00 },
  142. { ADAU1373_AINL_CTRL(0), 0x00 },
  143. { ADAU1373_AINR_CTRL(0), 0x00 },
  144. { ADAU1373_AINL_CTRL(1), 0x00 },
  145. { ADAU1373_AINR_CTRL(1), 0x00 },
  146. { ADAU1373_AINL_CTRL(2), 0x00 },
  147. { ADAU1373_AINR_CTRL(2), 0x00 },
  148. { ADAU1373_AINL_CTRL(3), 0x00 },
  149. { ADAU1373_AINR_CTRL(3), 0x00 },
  150. { ADAU1373_LLINE_OUT(0), 0x00 },
  151. { ADAU1373_RLINE_OUT(0), 0x00 },
  152. { ADAU1373_LLINE_OUT(1), 0x00 },
  153. { ADAU1373_RLINE_OUT(1), 0x00 },
  154. { ADAU1373_LSPK_OUT, 0x00 },
  155. { ADAU1373_RSPK_OUT, 0x00 },
  156. { ADAU1373_LHP_OUT, 0x00 },
  157. { ADAU1373_RHP_OUT, 0x00 },
  158. { ADAU1373_ADC_GAIN, 0x00 },
  159. { ADAU1373_LADC_MIXER, 0x00 },
  160. { ADAU1373_RADC_MIXER, 0x00 },
  161. { ADAU1373_LLINE1_MIX, 0x00 },
  162. { ADAU1373_RLINE1_MIX, 0x00 },
  163. { ADAU1373_LLINE2_MIX, 0x00 },
  164. { ADAU1373_RLINE2_MIX, 0x00 },
  165. { ADAU1373_LSPK_MIX, 0x00 },
  166. { ADAU1373_RSPK_MIX, 0x00 },
  167. { ADAU1373_LHP_MIX, 0x00 },
  168. { ADAU1373_RHP_MIX, 0x00 },
  169. { ADAU1373_EP_MIX, 0x00 },
  170. { ADAU1373_HP_CTRL, 0x00 },
  171. { ADAU1373_HP_CTRL2, 0x00 },
  172. { ADAU1373_LS_CTRL, 0x00 },
  173. { ADAU1373_EP_CTRL, 0x00 },
  174. { ADAU1373_MICBIAS_CTRL1, 0x00 },
  175. { ADAU1373_MICBIAS_CTRL2, 0x00 },
  176. { ADAU1373_OUTPUT_CTRL, 0x00 },
  177. { ADAU1373_PWDN_CTRL1, 0x00 },
  178. { ADAU1373_PWDN_CTRL2, 0x00 },
  179. { ADAU1373_PWDN_CTRL3, 0x00 },
  180. { ADAU1373_DPLL_CTRL(0), 0x00 },
  181. { ADAU1373_PLL_CTRL1(0), 0x00 },
  182. { ADAU1373_PLL_CTRL2(0), 0x00 },
  183. { ADAU1373_PLL_CTRL3(0), 0x00 },
  184. { ADAU1373_PLL_CTRL4(0), 0x00 },
  185. { ADAU1373_PLL_CTRL5(0), 0x00 },
  186. { ADAU1373_PLL_CTRL6(0), 0x02 },
  187. { ADAU1373_DPLL_CTRL(1), 0x00 },
  188. { ADAU1373_PLL_CTRL1(1), 0x00 },
  189. { ADAU1373_PLL_CTRL2(1), 0x00 },
  190. { ADAU1373_PLL_CTRL3(1), 0x00 },
  191. { ADAU1373_PLL_CTRL4(1), 0x00 },
  192. { ADAU1373_PLL_CTRL5(1), 0x00 },
  193. { ADAU1373_PLL_CTRL6(1), 0x02 },
  194. { ADAU1373_HEADDECT, 0x00 },
  195. { ADAU1373_ADC_CTRL, 0x00 },
  196. { ADAU1373_CLK_SRC_DIV(0), 0x00 },
  197. { ADAU1373_CLK_SRC_DIV(1), 0x00 },
  198. { ADAU1373_DAI(0), 0x0a },
  199. { ADAU1373_DAI(1), 0x0a },
  200. { ADAU1373_DAI(2), 0x0a },
  201. { ADAU1373_BCLKDIV(0), 0x00 },
  202. { ADAU1373_BCLKDIV(1), 0x00 },
  203. { ADAU1373_BCLKDIV(2), 0x00 },
  204. { ADAU1373_SRC_RATIOA(0), 0x00 },
  205. { ADAU1373_SRC_RATIOB(0), 0x00 },
  206. { ADAU1373_SRC_RATIOA(1), 0x00 },
  207. { ADAU1373_SRC_RATIOB(1), 0x00 },
  208. { ADAU1373_SRC_RATIOA(2), 0x00 },
  209. { ADAU1373_SRC_RATIOB(2), 0x00 },
  210. { ADAU1373_DEEMP_CTRL, 0x00 },
  211. { ADAU1373_SRC_DAI_CTRL(0), 0x08 },
  212. { ADAU1373_SRC_DAI_CTRL(1), 0x08 },
  213. { ADAU1373_SRC_DAI_CTRL(2), 0x08 },
  214. { ADAU1373_DIN_MIX_CTRL(0), 0x00 },
  215. { ADAU1373_DIN_MIX_CTRL(1), 0x00 },
  216. { ADAU1373_DIN_MIX_CTRL(2), 0x00 },
  217. { ADAU1373_DIN_MIX_CTRL(3), 0x00 },
  218. { ADAU1373_DIN_MIX_CTRL(4), 0x00 },
  219. { ADAU1373_DOUT_MIX_CTRL(0), 0x00 },
  220. { ADAU1373_DOUT_MIX_CTRL(1), 0x00 },
  221. { ADAU1373_DOUT_MIX_CTRL(2), 0x00 },
  222. { ADAU1373_DOUT_MIX_CTRL(3), 0x00 },
  223. { ADAU1373_DOUT_MIX_CTRL(4), 0x00 },
  224. { ADAU1373_DAI_PBL_VOL(0), 0x00 },
  225. { ADAU1373_DAI_PBR_VOL(0), 0x00 },
  226. { ADAU1373_DAI_PBL_VOL(1), 0x00 },
  227. { ADAU1373_DAI_PBR_VOL(1), 0x00 },
  228. { ADAU1373_DAI_PBL_VOL(2), 0x00 },
  229. { ADAU1373_DAI_PBR_VOL(2), 0x00 },
  230. { ADAU1373_DAI_RECL_VOL(0), 0x00 },
  231. { ADAU1373_DAI_RECR_VOL(0), 0x00 },
  232. { ADAU1373_DAI_RECL_VOL(1), 0x00 },
  233. { ADAU1373_DAI_RECR_VOL(1), 0x00 },
  234. { ADAU1373_DAI_RECL_VOL(2), 0x00 },
  235. { ADAU1373_DAI_RECR_VOL(2), 0x00 },
  236. { ADAU1373_DAC1_PBL_VOL, 0x00 },
  237. { ADAU1373_DAC1_PBR_VOL, 0x00 },
  238. { ADAU1373_DAC2_PBL_VOL, 0x00 },
  239. { ADAU1373_DAC2_PBR_VOL, 0x00 },
  240. { ADAU1373_ADC_RECL_VOL, 0x00 },
  241. { ADAU1373_ADC_RECR_VOL, 0x00 },
  242. { ADAU1373_DMIC_RECL_VOL, 0x00 },
  243. { ADAU1373_DMIC_RECR_VOL, 0x00 },
  244. { ADAU1373_VOL_GAIN1, 0x00 },
  245. { ADAU1373_VOL_GAIN2, 0x00 },
  246. { ADAU1373_VOL_GAIN3, 0x00 },
  247. { ADAU1373_HPF_CTRL, 0x00 },
  248. { ADAU1373_BASS1, 0x00 },
  249. { ADAU1373_BASS2, 0x00 },
  250. { ADAU1373_DRC(0) + 0x0, 0x78 },
  251. { ADAU1373_DRC(0) + 0x1, 0x18 },
  252. { ADAU1373_DRC(0) + 0x2, 0x00 },
  253. { ADAU1373_DRC(0) + 0x3, 0x00 },
  254. { ADAU1373_DRC(0) + 0x4, 0x00 },
  255. { ADAU1373_DRC(0) + 0x5, 0xc0 },
  256. { ADAU1373_DRC(0) + 0x6, 0x00 },
  257. { ADAU1373_DRC(0) + 0x7, 0x00 },
  258. { ADAU1373_DRC(0) + 0x8, 0x00 },
  259. { ADAU1373_DRC(0) + 0x9, 0xc0 },
  260. { ADAU1373_DRC(0) + 0xa, 0x88 },
  261. { ADAU1373_DRC(0) + 0xb, 0x7a },
  262. { ADAU1373_DRC(0) + 0xc, 0xdf },
  263. { ADAU1373_DRC(0) + 0xd, 0x20 },
  264. { ADAU1373_DRC(0) + 0xe, 0x00 },
  265. { ADAU1373_DRC(0) + 0xf, 0x00 },
  266. { ADAU1373_DRC(1) + 0x0, 0x78 },
  267. { ADAU1373_DRC(1) + 0x1, 0x18 },
  268. { ADAU1373_DRC(1) + 0x2, 0x00 },
  269. { ADAU1373_DRC(1) + 0x3, 0x00 },
  270. { ADAU1373_DRC(1) + 0x4, 0x00 },
  271. { ADAU1373_DRC(1) + 0x5, 0xc0 },
  272. { ADAU1373_DRC(1) + 0x6, 0x00 },
  273. { ADAU1373_DRC(1) + 0x7, 0x00 },
  274. { ADAU1373_DRC(1) + 0x8, 0x00 },
  275. { ADAU1373_DRC(1) + 0x9, 0xc0 },
  276. { ADAU1373_DRC(1) + 0xa, 0x88 },
  277. { ADAU1373_DRC(1) + 0xb, 0x7a },
  278. { ADAU1373_DRC(1) + 0xc, 0xdf },
  279. { ADAU1373_DRC(1) + 0xd, 0x20 },
  280. { ADAU1373_DRC(1) + 0xe, 0x00 },
  281. { ADAU1373_DRC(1) + 0xf, 0x00 },
  282. { ADAU1373_DRC(2) + 0x0, 0x78 },
  283. { ADAU1373_DRC(2) + 0x1, 0x18 },
  284. { ADAU1373_DRC(2) + 0x2, 0x00 },
  285. { ADAU1373_DRC(2) + 0x3, 0x00 },
  286. { ADAU1373_DRC(2) + 0x4, 0x00 },
  287. { ADAU1373_DRC(2) + 0x5, 0xc0 },
  288. { ADAU1373_DRC(2) + 0x6, 0x00 },
  289. { ADAU1373_DRC(2) + 0x7, 0x00 },
  290. { ADAU1373_DRC(2) + 0x8, 0x00 },
  291. { ADAU1373_DRC(2) + 0x9, 0xc0 },
  292. { ADAU1373_DRC(2) + 0xa, 0x88 },
  293. { ADAU1373_DRC(2) + 0xb, 0x7a },
  294. { ADAU1373_DRC(2) + 0xc, 0xdf },
  295. { ADAU1373_DRC(2) + 0xd, 0x20 },
  296. { ADAU1373_DRC(2) + 0xe, 0x00 },
  297. { ADAU1373_DRC(2) + 0xf, 0x00 },
  298. { ADAU1373_3D_CTRL1, 0x00 },
  299. { ADAU1373_3D_CTRL2, 0x00 },
  300. { ADAU1373_FDSP_SEL1, 0x00 },
  301. { ADAU1373_FDSP_SEL2, 0x00 },
  302. { ADAU1373_FDSP_SEL2, 0x00 },
  303. { ADAU1373_FDSP_SEL4, 0x00 },
  304. { ADAU1373_DIGMICCTRL, 0x00 },
  305. { ADAU1373_DIGEN, 0x00 },
  306. };
  307. static const DECLARE_TLV_DB_RANGE(adau1373_out_tlv,
  308. 0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
  309. 8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0),
  310. 16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0),
  311. 24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0)
  312. );
  313. static const DECLARE_TLV_DB_MINMAX(adau1373_digital_tlv, -9563, 0);
  314. static const DECLARE_TLV_DB_SCALE(adau1373_in_pga_tlv, -1300, 100, 1);
  315. static const DECLARE_TLV_DB_SCALE(adau1373_ep_tlv, -600, 600, 1);
  316. static const DECLARE_TLV_DB_SCALE(adau1373_input_boost_tlv, 0, 2000, 0);
  317. static const DECLARE_TLV_DB_SCALE(adau1373_gain_boost_tlv, 0, 600, 0);
  318. static const DECLARE_TLV_DB_SCALE(adau1373_speaker_boost_tlv, 1200, 600, 0);
  319. static const char *adau1373_fdsp_sel_text[] = {
  320. "None",
  321. "Channel 1",
  322. "Channel 2",
  323. "Channel 3",
  324. "Channel 4",
  325. "Channel 5",
  326. };
  327. static SOC_ENUM_SINGLE_DECL(adau1373_drc1_channel_enum,
  328. ADAU1373_FDSP_SEL1, 4, adau1373_fdsp_sel_text);
  329. static SOC_ENUM_SINGLE_DECL(adau1373_drc2_channel_enum,
  330. ADAU1373_FDSP_SEL1, 0, adau1373_fdsp_sel_text);
  331. static SOC_ENUM_SINGLE_DECL(adau1373_drc3_channel_enum,
  332. ADAU1373_FDSP_SEL2, 0, adau1373_fdsp_sel_text);
  333. static SOC_ENUM_SINGLE_DECL(adau1373_hpf_channel_enum,
  334. ADAU1373_FDSP_SEL3, 0, adau1373_fdsp_sel_text);
  335. static SOC_ENUM_SINGLE_DECL(adau1373_bass_channel_enum,
  336. ADAU1373_FDSP_SEL4, 4, adau1373_fdsp_sel_text);
  337. static const char *adau1373_hpf_cutoff_text[] = {
  338. "3.7Hz", "50Hz", "100Hz", "150Hz", "200Hz", "250Hz", "300Hz", "350Hz",
  339. "400Hz", "450Hz", "500Hz", "550Hz", "600Hz", "650Hz", "700Hz", "750Hz",
  340. "800Hz",
  341. };
  342. static SOC_ENUM_SINGLE_DECL(adau1373_hpf_cutoff_enum,
  343. ADAU1373_HPF_CTRL, 3, adau1373_hpf_cutoff_text);
  344. static const char *adau1373_bass_lpf_cutoff_text[] = {
  345. "801Hz", "1001Hz",
  346. };
  347. static const char *adau1373_bass_clip_level_text[] = {
  348. "0.125", "0.250", "0.370", "0.500", "0.625", "0.750", "0.875",
  349. };
  350. static const unsigned int adau1373_bass_clip_level_values[] = {
  351. 1, 2, 3, 4, 5, 6, 7,
  352. };
  353. static const char *adau1373_bass_hpf_cutoff_text[] = {
  354. "158Hz", "232Hz", "347Hz", "520Hz",
  355. };
  356. static const DECLARE_TLV_DB_RANGE(adau1373_bass_tlv,
  357. 0, 2, TLV_DB_SCALE_ITEM(-600, 600, 1),
  358. 3, 4, TLV_DB_SCALE_ITEM(950, 250, 0),
  359. 5, 7, TLV_DB_SCALE_ITEM(1400, 150, 0)
  360. );
  361. static SOC_ENUM_SINGLE_DECL(adau1373_bass_lpf_cutoff_enum,
  362. ADAU1373_BASS1, 5, adau1373_bass_lpf_cutoff_text);
  363. static SOC_VALUE_ENUM_SINGLE_DECL(adau1373_bass_clip_level_enum,
  364. ADAU1373_BASS1, 2, 7, adau1373_bass_clip_level_text,
  365. adau1373_bass_clip_level_values);
  366. static SOC_ENUM_SINGLE_DECL(adau1373_bass_hpf_cutoff_enum,
  367. ADAU1373_BASS1, 0, adau1373_bass_hpf_cutoff_text);
  368. static const char *adau1373_3d_level_text[] = {
  369. "0%", "6.67%", "13.33%", "20%", "26.67%", "33.33%",
  370. "40%", "46.67%", "53.33%", "60%", "66.67%", "73.33%",
  371. "80%", "86.67", "99.33%", "100%"
  372. };
  373. static const char *adau1373_3d_cutoff_text[] = {
  374. "No 3D", "0.03125 fs", "0.04583 fs", "0.075 fs", "0.11458 fs",
  375. "0.16875 fs", "0.27083 fs"
  376. };
  377. static SOC_ENUM_SINGLE_DECL(adau1373_3d_level_enum,
  378. ADAU1373_3D_CTRL1, 4, adau1373_3d_level_text);
  379. static SOC_ENUM_SINGLE_DECL(adau1373_3d_cutoff_enum,
  380. ADAU1373_3D_CTRL1, 0, adau1373_3d_cutoff_text);
  381. static const DECLARE_TLV_DB_RANGE(adau1373_3d_tlv,
  382. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  383. 1, 7, TLV_DB_LINEAR_ITEM(-1800, -120)
  384. );
  385. static const char *adau1373_lr_mux_text[] = {
  386. "Mute",
  387. "Right Channel (L+R)",
  388. "Left Channel (L+R)",
  389. "Stereo",
  390. };
  391. static SOC_ENUM_SINGLE_DECL(adau1373_lineout1_lr_mux_enum,
  392. ADAU1373_OUTPUT_CTRL, 4, adau1373_lr_mux_text);
  393. static SOC_ENUM_SINGLE_DECL(adau1373_lineout2_lr_mux_enum,
  394. ADAU1373_OUTPUT_CTRL, 6, adau1373_lr_mux_text);
  395. static SOC_ENUM_SINGLE_DECL(adau1373_speaker_lr_mux_enum,
  396. ADAU1373_LS_CTRL, 4, adau1373_lr_mux_text);
  397. static const struct snd_kcontrol_new adau1373_controls[] = {
  398. SOC_DOUBLE_R_TLV("AIF1 Capture Volume", ADAU1373_DAI_RECL_VOL(0),
  399. ADAU1373_DAI_RECR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
  400. SOC_DOUBLE_R_TLV("AIF2 Capture Volume", ADAU1373_DAI_RECL_VOL(1),
  401. ADAU1373_DAI_RECR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
  402. SOC_DOUBLE_R_TLV("AIF3 Capture Volume", ADAU1373_DAI_RECL_VOL(2),
  403. ADAU1373_DAI_RECR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
  404. SOC_DOUBLE_R_TLV("ADC Capture Volume", ADAU1373_ADC_RECL_VOL,
  405. ADAU1373_ADC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
  406. SOC_DOUBLE_R_TLV("DMIC Capture Volume", ADAU1373_DMIC_RECL_VOL,
  407. ADAU1373_DMIC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
  408. SOC_DOUBLE_R_TLV("AIF1 Playback Volume", ADAU1373_DAI_PBL_VOL(0),
  409. ADAU1373_DAI_PBR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
  410. SOC_DOUBLE_R_TLV("AIF2 Playback Volume", ADAU1373_DAI_PBL_VOL(1),
  411. ADAU1373_DAI_PBR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
  412. SOC_DOUBLE_R_TLV("AIF3 Playback Volume", ADAU1373_DAI_PBL_VOL(2),
  413. ADAU1373_DAI_PBR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
  414. SOC_DOUBLE_R_TLV("DAC1 Playback Volume", ADAU1373_DAC1_PBL_VOL,
  415. ADAU1373_DAC1_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
  416. SOC_DOUBLE_R_TLV("DAC2 Playback Volume", ADAU1373_DAC2_PBL_VOL,
  417. ADAU1373_DAC2_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
  418. SOC_DOUBLE_R_TLV("Lineout1 Playback Volume", ADAU1373_LLINE_OUT(0),
  419. ADAU1373_RLINE_OUT(0), 0, 0x1f, 0, adau1373_out_tlv),
  420. SOC_DOUBLE_R_TLV("Speaker Playback Volume", ADAU1373_LSPK_OUT,
  421. ADAU1373_RSPK_OUT, 0, 0x1f, 0, adau1373_out_tlv),
  422. SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1373_LHP_OUT,
  423. ADAU1373_RHP_OUT, 0, 0x1f, 0, adau1373_out_tlv),
  424. SOC_DOUBLE_R_TLV("Input 1 Capture Volume", ADAU1373_AINL_CTRL(0),
  425. ADAU1373_AINR_CTRL(0), 0, 0x1f, 0, adau1373_in_pga_tlv),
  426. SOC_DOUBLE_R_TLV("Input 2 Capture Volume", ADAU1373_AINL_CTRL(1),
  427. ADAU1373_AINR_CTRL(1), 0, 0x1f, 0, adau1373_in_pga_tlv),
  428. SOC_DOUBLE_R_TLV("Input 3 Capture Volume", ADAU1373_AINL_CTRL(2),
  429. ADAU1373_AINR_CTRL(2), 0, 0x1f, 0, adau1373_in_pga_tlv),
  430. SOC_DOUBLE_R_TLV("Input 4 Capture Volume", ADAU1373_AINL_CTRL(3),
  431. ADAU1373_AINR_CTRL(3), 0, 0x1f, 0, adau1373_in_pga_tlv),
  432. SOC_SINGLE_TLV("Earpiece Playback Volume", ADAU1373_EP_CTRL, 0, 3, 0,
  433. adau1373_ep_tlv),
  434. SOC_DOUBLE_TLV("AIF3 Boost Playback Volume", ADAU1373_VOL_GAIN1, 4, 5,
  435. 1, 0, adau1373_gain_boost_tlv),
  436. SOC_DOUBLE_TLV("AIF2 Boost Playback Volume", ADAU1373_VOL_GAIN1, 2, 3,
  437. 1, 0, adau1373_gain_boost_tlv),
  438. SOC_DOUBLE_TLV("AIF1 Boost Playback Volume", ADAU1373_VOL_GAIN1, 0, 1,
  439. 1, 0, adau1373_gain_boost_tlv),
  440. SOC_DOUBLE_TLV("AIF3 Boost Capture Volume", ADAU1373_VOL_GAIN2, 4, 5,
  441. 1, 0, adau1373_gain_boost_tlv),
  442. SOC_DOUBLE_TLV("AIF2 Boost Capture Volume", ADAU1373_VOL_GAIN2, 2, 3,
  443. 1, 0, adau1373_gain_boost_tlv),
  444. SOC_DOUBLE_TLV("AIF1 Boost Capture Volume", ADAU1373_VOL_GAIN2, 0, 1,
  445. 1, 0, adau1373_gain_boost_tlv),
  446. SOC_DOUBLE_TLV("DMIC Boost Capture Volume", ADAU1373_VOL_GAIN3, 6, 7,
  447. 1, 0, adau1373_gain_boost_tlv),
  448. SOC_DOUBLE_TLV("ADC Boost Capture Volume", ADAU1373_VOL_GAIN3, 4, 5,
  449. 1, 0, adau1373_gain_boost_tlv),
  450. SOC_DOUBLE_TLV("DAC2 Boost Playback Volume", ADAU1373_VOL_GAIN3, 2, 3,
  451. 1, 0, adau1373_gain_boost_tlv),
  452. SOC_DOUBLE_TLV("DAC1 Boost Playback Volume", ADAU1373_VOL_GAIN3, 0, 1,
  453. 1, 0, adau1373_gain_boost_tlv),
  454. SOC_DOUBLE_TLV("Input 1 Boost Capture Volume", ADAU1373_ADC_GAIN, 0, 4,
  455. 1, 0, adau1373_input_boost_tlv),
  456. SOC_DOUBLE_TLV("Input 2 Boost Capture Volume", ADAU1373_ADC_GAIN, 1, 5,
  457. 1, 0, adau1373_input_boost_tlv),
  458. SOC_DOUBLE_TLV("Input 3 Boost Capture Volume", ADAU1373_ADC_GAIN, 2, 6,
  459. 1, 0, adau1373_input_boost_tlv),
  460. SOC_DOUBLE_TLV("Input 4 Boost Capture Volume", ADAU1373_ADC_GAIN, 3, 7,
  461. 1, 0, adau1373_input_boost_tlv),
  462. SOC_DOUBLE_TLV("Speaker Boost Playback Volume", ADAU1373_LS_CTRL, 2, 3,
  463. 1, 0, adau1373_speaker_boost_tlv),
  464. SOC_ENUM("Lineout1 LR Mux", adau1373_lineout1_lr_mux_enum),
  465. SOC_ENUM("Speaker LR Mux", adau1373_speaker_lr_mux_enum),
  466. SOC_ENUM("HPF Cutoff", adau1373_hpf_cutoff_enum),
  467. SOC_DOUBLE("HPF Switch", ADAU1373_HPF_CTRL, 1, 0, 1, 0),
  468. SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum),
  469. SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum),
  470. SOC_ENUM("Bass Clip Level Threshold", adau1373_bass_clip_level_enum),
  471. SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum),
  472. SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2, 0, 1, 1, 0),
  473. SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2, 2, 7, 0,
  474. adau1373_bass_tlv),
  475. SOC_ENUM("Bass Channel", adau1373_bass_channel_enum),
  476. SOC_ENUM("3D Freq", adau1373_3d_cutoff_enum),
  477. SOC_ENUM("3D Level", adau1373_3d_level_enum),
  478. SOC_SINGLE("3D Playback Switch", ADAU1373_3D_CTRL2, 0, 1, 0),
  479. SOC_SINGLE_TLV("3D Playback Volume", ADAU1373_3D_CTRL2, 2, 7, 0,
  480. adau1373_3d_tlv),
  481. SOC_ENUM("3D Channel", adau1373_bass_channel_enum),
  482. SOC_SINGLE("Zero Cross Switch", ADAU1373_PWDN_CTRL3, 7, 1, 0),
  483. };
  484. static const struct snd_kcontrol_new adau1373_lineout2_controls[] = {
  485. SOC_DOUBLE_R_TLV("Lineout2 Playback Volume", ADAU1373_LLINE_OUT(1),
  486. ADAU1373_RLINE_OUT(1), 0, 0x1f, 0, adau1373_out_tlv),
  487. SOC_ENUM("Lineout2 LR Mux", adau1373_lineout2_lr_mux_enum),
  488. };
  489. static const struct snd_kcontrol_new adau1373_drc_controls[] = {
  490. SOC_ENUM("DRC1 Channel", adau1373_drc1_channel_enum),
  491. SOC_ENUM("DRC2 Channel", adau1373_drc2_channel_enum),
  492. SOC_ENUM("DRC3 Channel", adau1373_drc3_channel_enum),
  493. };
  494. static int adau1373_pll_event(struct snd_soc_dapm_widget *w,
  495. struct snd_kcontrol *kcontrol, int event)
  496. {
  497. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  498. struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
  499. unsigned int pll_id = w->name[3] - '1';
  500. unsigned int val;
  501. if (SND_SOC_DAPM_EVENT_ON(event))
  502. val = ADAU1373_PLL_CTRL6_PLL_EN;
  503. else
  504. val = 0;
  505. regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
  506. ADAU1373_PLL_CTRL6_PLL_EN, val);
  507. if (SND_SOC_DAPM_EVENT_ON(event))
  508. mdelay(5);
  509. return 0;
  510. }
  511. static const char *adau1373_decimator_text[] = {
  512. "ADC",
  513. "DMIC1",
  514. };
  515. static SOC_ENUM_SINGLE_VIRT_DECL(adau1373_decimator_enum,
  516. adau1373_decimator_text);
  517. static const struct snd_kcontrol_new adau1373_decimator_mux =
  518. SOC_DAPM_ENUM("Decimator Mux", adau1373_decimator_enum);
  519. static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = {
  520. SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER, 4, 1, 0),
  521. SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_LADC_MIXER, 3, 1, 0),
  522. SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_LADC_MIXER, 2, 1, 0),
  523. SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_LADC_MIXER, 1, 1, 0),
  524. SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_LADC_MIXER, 0, 1, 0),
  525. };
  526. static const struct snd_kcontrol_new adau1373_right_adc_mixer_controls[] = {
  527. SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_RADC_MIXER, 4, 1, 0),
  528. SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_RADC_MIXER, 3, 1, 0),
  529. SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_RADC_MIXER, 2, 1, 0),
  530. SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_RADC_MIXER, 1, 1, 0),
  531. SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_RADC_MIXER, 0, 1, 0),
  532. };
  533. #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \
  534. const struct snd_kcontrol_new _name[] = { \
  535. SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \
  536. SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \
  537. SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \
  538. SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \
  539. SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \
  540. SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \
  541. SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \
  542. SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \
  543. }
  544. static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line1_mixer_controls,
  545. ADAU1373_LLINE1_MIX);
  546. static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line1_mixer_controls,
  547. ADAU1373_RLINE1_MIX);
  548. static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line2_mixer_controls,
  549. ADAU1373_LLINE2_MIX);
  550. static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line2_mixer_controls,
  551. ADAU1373_RLINE2_MIX);
  552. static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_spk_mixer_controls,
  553. ADAU1373_LSPK_MIX);
  554. static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_spk_mixer_controls,
  555. ADAU1373_RSPK_MIX);
  556. static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_ep_mixer_controls,
  557. ADAU1373_EP_MIX);
  558. static const struct snd_kcontrol_new adau1373_left_hp_mixer_controls[] = {
  559. SOC_DAPM_SINGLE("Left DAC1 Switch", ADAU1373_LHP_MIX, 5, 1, 0),
  560. SOC_DAPM_SINGLE("Left DAC2 Switch", ADAU1373_LHP_MIX, 4, 1, 0),
  561. SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX, 3, 1, 0),
  562. SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX, 2, 1, 0),
  563. SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX, 1, 1, 0),
  564. SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX, 0, 1, 0),
  565. };
  566. static const struct snd_kcontrol_new adau1373_right_hp_mixer_controls[] = {
  567. SOC_DAPM_SINGLE("Right DAC1 Switch", ADAU1373_RHP_MIX, 5, 1, 0),
  568. SOC_DAPM_SINGLE("Right DAC2 Switch", ADAU1373_RHP_MIX, 4, 1, 0),
  569. SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX, 3, 1, 0),
  570. SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX, 2, 1, 0),
  571. SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_RHP_MIX, 1, 1, 0),
  572. SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_RHP_MIX, 0, 1, 0),
  573. };
  574. #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \
  575. const struct snd_kcontrol_new _name[] = { \
  576. SOC_DAPM_SINGLE("DMIC2 Swapped Switch", _reg, 6, 1, 0), \
  577. SOC_DAPM_SINGLE("DMIC2 Switch", _reg, 5, 1, 0), \
  578. SOC_DAPM_SINGLE("ADC/DMIC1 Swapped Switch", _reg, 4, 1, 0), \
  579. SOC_DAPM_SINGLE("ADC/DMIC1 Switch", _reg, 3, 1, 0), \
  580. SOC_DAPM_SINGLE("AIF3 Switch", _reg, 2, 1, 0), \
  581. SOC_DAPM_SINGLE("AIF2 Switch", _reg, 1, 1, 0), \
  582. SOC_DAPM_SINGLE("AIF1 Switch", _reg, 0, 1, 0), \
  583. }
  584. static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel1_mixer_controls,
  585. ADAU1373_DIN_MIX_CTRL(0));
  586. static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel2_mixer_controls,
  587. ADAU1373_DIN_MIX_CTRL(1));
  588. static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel3_mixer_controls,
  589. ADAU1373_DIN_MIX_CTRL(2));
  590. static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel4_mixer_controls,
  591. ADAU1373_DIN_MIX_CTRL(3));
  592. static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel5_mixer_controls,
  593. ADAU1373_DIN_MIX_CTRL(4));
  594. #define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \
  595. const struct snd_kcontrol_new _name[] = { \
  596. SOC_DAPM_SINGLE("DSP Channel5 Switch", _reg, 4, 1, 0), \
  597. SOC_DAPM_SINGLE("DSP Channel4 Switch", _reg, 3, 1, 0), \
  598. SOC_DAPM_SINGLE("DSP Channel3 Switch", _reg, 2, 1, 0), \
  599. SOC_DAPM_SINGLE("DSP Channel2 Switch", _reg, 1, 1, 0), \
  600. SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \
  601. }
  602. static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif1_mixer_controls,
  603. ADAU1373_DOUT_MIX_CTRL(0));
  604. static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif2_mixer_controls,
  605. ADAU1373_DOUT_MIX_CTRL(1));
  606. static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif3_mixer_controls,
  607. ADAU1373_DOUT_MIX_CTRL(2));
  608. static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac1_mixer_controls,
  609. ADAU1373_DOUT_MIX_CTRL(3));
  610. static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac2_mixer_controls,
  611. ADAU1373_DOUT_MIX_CTRL(4));
  612. static const struct snd_soc_dapm_widget adau1373_dapm_widgets[] = {
  613. /* Datasheet claims Left ADC is bit 6 and Right ADC is bit 7, but that
  614. * doesn't seem to be the case. */
  615. SND_SOC_DAPM_ADC("Left ADC", NULL, ADAU1373_PWDN_CTRL1, 7, 0),
  616. SND_SOC_DAPM_ADC("Right ADC", NULL, ADAU1373_PWDN_CTRL1, 6, 0),
  617. SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1373_DIGMICCTRL, 0, 0),
  618. SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1373_DIGMICCTRL, 2, 0),
  619. SND_SOC_DAPM_MUX("Decimator Mux", SND_SOC_NOPM, 0, 0,
  620. &adau1373_decimator_mux),
  621. SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1, 5, 0, NULL, 0),
  622. SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1373_PWDN_CTRL1, 4, 0, NULL, 0),
  623. SND_SOC_DAPM_PGA("IN4PGA", ADAU1373_PWDN_CTRL1, 3, 0, NULL, 0),
  624. SND_SOC_DAPM_PGA("IN3PGA", ADAU1373_PWDN_CTRL1, 2, 0, NULL, 0),
  625. SND_SOC_DAPM_PGA("IN2PGA", ADAU1373_PWDN_CTRL1, 1, 0, NULL, 0),
  626. SND_SOC_DAPM_PGA("IN1PGA", ADAU1373_PWDN_CTRL1, 0, 0, NULL, 0),
  627. SND_SOC_DAPM_DAC("Left DAC2", NULL, ADAU1373_PWDN_CTRL2, 7, 0),
  628. SND_SOC_DAPM_DAC("Right DAC2", NULL, ADAU1373_PWDN_CTRL2, 6, 0),
  629. SND_SOC_DAPM_DAC("Left DAC1", NULL, ADAU1373_PWDN_CTRL2, 5, 0),
  630. SND_SOC_DAPM_DAC("Right DAC1", NULL, ADAU1373_PWDN_CTRL2, 4, 0),
  631. SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
  632. adau1373_left_adc_mixer_controls),
  633. SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
  634. adau1373_right_adc_mixer_controls),
  635. SOC_MIXER_ARRAY("Left Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 3, 0,
  636. adau1373_left_line2_mixer_controls),
  637. SOC_MIXER_ARRAY("Right Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 2, 0,
  638. adau1373_right_line2_mixer_controls),
  639. SOC_MIXER_ARRAY("Left Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 1, 0,
  640. adau1373_left_line1_mixer_controls),
  641. SOC_MIXER_ARRAY("Right Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 0, 0,
  642. adau1373_right_line1_mixer_controls),
  643. SOC_MIXER_ARRAY("Earpiece Mixer", ADAU1373_PWDN_CTRL3, 4, 0,
  644. adau1373_ep_mixer_controls),
  645. SOC_MIXER_ARRAY("Left Speaker Mixer", ADAU1373_PWDN_CTRL3, 3, 0,
  646. adau1373_left_spk_mixer_controls),
  647. SOC_MIXER_ARRAY("Right Speaker Mixer", ADAU1373_PWDN_CTRL3, 2, 0,
  648. adau1373_right_spk_mixer_controls),
  649. SOC_MIXER_ARRAY("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
  650. adau1373_left_hp_mixer_controls),
  651. SOC_MIXER_ARRAY("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
  652. adau1373_right_hp_mixer_controls),
  653. SND_SOC_DAPM_SUPPLY("Headphone Enable", ADAU1373_PWDN_CTRL3, 1, 0,
  654. NULL, 0),
  655. SND_SOC_DAPM_SUPPLY("AIF1 CLK", ADAU1373_SRC_DAI_CTRL(0), 0, 0,
  656. NULL, 0),
  657. SND_SOC_DAPM_SUPPLY("AIF2 CLK", ADAU1373_SRC_DAI_CTRL(1), 0, 0,
  658. NULL, 0),
  659. SND_SOC_DAPM_SUPPLY("AIF3 CLK", ADAU1373_SRC_DAI_CTRL(2), 0, 0,
  660. NULL, 0),
  661. SND_SOC_DAPM_SUPPLY("AIF1 IN SRC", ADAU1373_SRC_DAI_CTRL(0), 2, 0,
  662. NULL, 0),
  663. SND_SOC_DAPM_SUPPLY("AIF1 OUT SRC", ADAU1373_SRC_DAI_CTRL(0), 1, 0,
  664. NULL, 0),
  665. SND_SOC_DAPM_SUPPLY("AIF2 IN SRC", ADAU1373_SRC_DAI_CTRL(1), 2, 0,
  666. NULL, 0),
  667. SND_SOC_DAPM_SUPPLY("AIF2 OUT SRC", ADAU1373_SRC_DAI_CTRL(1), 1, 0,
  668. NULL, 0),
  669. SND_SOC_DAPM_SUPPLY("AIF3 IN SRC", ADAU1373_SRC_DAI_CTRL(2), 2, 0,
  670. NULL, 0),
  671. SND_SOC_DAPM_SUPPLY("AIF3 OUT SRC", ADAU1373_SRC_DAI_CTRL(2), 1, 0,
  672. NULL, 0),
  673. SND_SOC_DAPM_AIF_IN("AIF1 IN", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  674. SND_SOC_DAPM_AIF_OUT("AIF1 OUT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  675. SND_SOC_DAPM_AIF_IN("AIF2 IN", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  676. SND_SOC_DAPM_AIF_OUT("AIF2 OUT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  677. SND_SOC_DAPM_AIF_IN("AIF3 IN", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
  678. SND_SOC_DAPM_AIF_OUT("AIF3 OUT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
  679. SOC_MIXER_ARRAY("DSP Channel1 Mixer", SND_SOC_NOPM, 0, 0,
  680. adau1373_dsp_channel1_mixer_controls),
  681. SOC_MIXER_ARRAY("DSP Channel2 Mixer", SND_SOC_NOPM, 0, 0,
  682. adau1373_dsp_channel2_mixer_controls),
  683. SOC_MIXER_ARRAY("DSP Channel3 Mixer", SND_SOC_NOPM, 0, 0,
  684. adau1373_dsp_channel3_mixer_controls),
  685. SOC_MIXER_ARRAY("DSP Channel4 Mixer", SND_SOC_NOPM, 0, 0,
  686. adau1373_dsp_channel4_mixer_controls),
  687. SOC_MIXER_ARRAY("DSP Channel5 Mixer", SND_SOC_NOPM, 0, 0,
  688. adau1373_dsp_channel5_mixer_controls),
  689. SOC_MIXER_ARRAY("AIF1 Mixer", SND_SOC_NOPM, 0, 0,
  690. adau1373_aif1_mixer_controls),
  691. SOC_MIXER_ARRAY("AIF2 Mixer", SND_SOC_NOPM, 0, 0,
  692. adau1373_aif2_mixer_controls),
  693. SOC_MIXER_ARRAY("AIF3 Mixer", SND_SOC_NOPM, 0, 0,
  694. adau1373_aif3_mixer_controls),
  695. SOC_MIXER_ARRAY("DAC1 Mixer", SND_SOC_NOPM, 0, 0,
  696. adau1373_dac1_mixer_controls),
  697. SOC_MIXER_ARRAY("DAC2 Mixer", SND_SOC_NOPM, 0, 0,
  698. adau1373_dac2_mixer_controls),
  699. SND_SOC_DAPM_SUPPLY("DSP", ADAU1373_DIGEN, 4, 0, NULL, 0),
  700. SND_SOC_DAPM_SUPPLY("Recording Engine B", ADAU1373_DIGEN, 3, 0, NULL, 0),
  701. SND_SOC_DAPM_SUPPLY("Recording Engine A", ADAU1373_DIGEN, 2, 0, NULL, 0),
  702. SND_SOC_DAPM_SUPPLY("Playback Engine B", ADAU1373_DIGEN, 1, 0, NULL, 0),
  703. SND_SOC_DAPM_SUPPLY("Playback Engine A", ADAU1373_DIGEN, 0, 0, NULL, 0),
  704. SND_SOC_DAPM_SUPPLY("PLL1", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
  705. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  706. SND_SOC_DAPM_SUPPLY("PLL2", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
  707. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  708. SND_SOC_DAPM_SUPPLY("SYSCLK1", ADAU1373_CLK_SRC_DIV(0), 7, 0, NULL, 0),
  709. SND_SOC_DAPM_SUPPLY("SYSCLK2", ADAU1373_CLK_SRC_DIV(1), 7, 0, NULL, 0),
  710. SND_SOC_DAPM_INPUT("AIN1L"),
  711. SND_SOC_DAPM_INPUT("AIN1R"),
  712. SND_SOC_DAPM_INPUT("AIN2L"),
  713. SND_SOC_DAPM_INPUT("AIN2R"),
  714. SND_SOC_DAPM_INPUT("AIN3L"),
  715. SND_SOC_DAPM_INPUT("AIN3R"),
  716. SND_SOC_DAPM_INPUT("AIN4L"),
  717. SND_SOC_DAPM_INPUT("AIN4R"),
  718. SND_SOC_DAPM_INPUT("DMIC1DAT"),
  719. SND_SOC_DAPM_INPUT("DMIC2DAT"),
  720. SND_SOC_DAPM_OUTPUT("LOUT1L"),
  721. SND_SOC_DAPM_OUTPUT("LOUT1R"),
  722. SND_SOC_DAPM_OUTPUT("LOUT2L"),
  723. SND_SOC_DAPM_OUTPUT("LOUT2R"),
  724. SND_SOC_DAPM_OUTPUT("HPL"),
  725. SND_SOC_DAPM_OUTPUT("HPR"),
  726. SND_SOC_DAPM_OUTPUT("SPKL"),
  727. SND_SOC_DAPM_OUTPUT("SPKR"),
  728. SND_SOC_DAPM_OUTPUT("EP"),
  729. };
  730. static int adau1373_check_aif_clk(struct snd_soc_dapm_widget *source,
  731. struct snd_soc_dapm_widget *sink)
  732. {
  733. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  734. struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
  735. unsigned int dai;
  736. const char *clk;
  737. dai = sink->name[3] - '1';
  738. if (!adau1373->dais[dai].master)
  739. return 0;
  740. if (adau1373->dais[dai].clk_src == ADAU1373_CLK_SRC_PLL1)
  741. clk = "SYSCLK1";
  742. else
  743. clk = "SYSCLK2";
  744. return strcmp(source->name, clk) == 0;
  745. }
  746. static int adau1373_check_src(struct snd_soc_dapm_widget *source,
  747. struct snd_soc_dapm_widget *sink)
  748. {
  749. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  750. struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
  751. unsigned int dai;
  752. dai = sink->name[3] - '1';
  753. return adau1373->dais[dai].enable_src;
  754. }
  755. #define DSP_CHANNEL_MIXER_ROUTES(_sink) \
  756. { _sink, "DMIC2 Swapped Switch", "DMIC2" }, \
  757. { _sink, "DMIC2 Switch", "DMIC2" }, \
  758. { _sink, "ADC/DMIC1 Swapped Switch", "Decimator Mux" }, \
  759. { _sink, "ADC/DMIC1 Switch", "Decimator Mux" }, \
  760. { _sink, "AIF1 Switch", "AIF1 IN" }, \
  761. { _sink, "AIF2 Switch", "AIF2 IN" }, \
  762. { _sink, "AIF3 Switch", "AIF3 IN" }
  763. #define DSP_OUTPUT_MIXER_ROUTES(_sink) \
  764. { _sink, "DSP Channel1 Switch", "DSP Channel1 Mixer" }, \
  765. { _sink, "DSP Channel2 Switch", "DSP Channel2 Mixer" }, \
  766. { _sink, "DSP Channel3 Switch", "DSP Channel3 Mixer" }, \
  767. { _sink, "DSP Channel4 Switch", "DSP Channel4 Mixer" }, \
  768. { _sink, "DSP Channel5 Switch", "DSP Channel5 Mixer" }
  769. #define LEFT_OUTPUT_MIXER_ROUTES(_sink) \
  770. { _sink, "Right DAC2 Switch", "Right DAC2" }, \
  771. { _sink, "Left DAC2 Switch", "Left DAC2" }, \
  772. { _sink, "Right DAC1 Switch", "Right DAC1" }, \
  773. { _sink, "Left DAC1 Switch", "Left DAC1" }, \
  774. { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
  775. { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
  776. { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
  777. { _sink, "Input 4 Bypass Switch", "IN4PGA" }
  778. #define RIGHT_OUTPUT_MIXER_ROUTES(_sink) \
  779. { _sink, "Right DAC2 Switch", "Right DAC2" }, \
  780. { _sink, "Left DAC2 Switch", "Left DAC2" }, \
  781. { _sink, "Right DAC1 Switch", "Right DAC1" }, \
  782. { _sink, "Left DAC1 Switch", "Left DAC1" }, \
  783. { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
  784. { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
  785. { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
  786. { _sink, "Input 4 Bypass Switch", "IN4PGA" }
  787. static const struct snd_soc_dapm_route adau1373_dapm_routes[] = {
  788. { "Left ADC Mixer", "DAC1 Switch", "Left DAC1" },
  789. { "Left ADC Mixer", "Input 1 Switch", "IN1PGA" },
  790. { "Left ADC Mixer", "Input 2 Switch", "IN2PGA" },
  791. { "Left ADC Mixer", "Input 3 Switch", "IN3PGA" },
  792. { "Left ADC Mixer", "Input 4 Switch", "IN4PGA" },
  793. { "Right ADC Mixer", "DAC1 Switch", "Right DAC1" },
  794. { "Right ADC Mixer", "Input 1 Switch", "IN1PGA" },
  795. { "Right ADC Mixer", "Input 2 Switch", "IN2PGA" },
  796. { "Right ADC Mixer", "Input 3 Switch", "IN3PGA" },
  797. { "Right ADC Mixer", "Input 4 Switch", "IN4PGA" },
  798. { "Left ADC", NULL, "Left ADC Mixer" },
  799. { "Right ADC", NULL, "Right ADC Mixer" },
  800. { "Decimator Mux", "ADC", "Left ADC" },
  801. { "Decimator Mux", "ADC", "Right ADC" },
  802. { "Decimator Mux", "DMIC1", "DMIC1" },
  803. DSP_CHANNEL_MIXER_ROUTES("DSP Channel1 Mixer"),
  804. DSP_CHANNEL_MIXER_ROUTES("DSP Channel2 Mixer"),
  805. DSP_CHANNEL_MIXER_ROUTES("DSP Channel3 Mixer"),
  806. DSP_CHANNEL_MIXER_ROUTES("DSP Channel4 Mixer"),
  807. DSP_CHANNEL_MIXER_ROUTES("DSP Channel5 Mixer"),
  808. DSP_OUTPUT_MIXER_ROUTES("AIF1 Mixer"),
  809. DSP_OUTPUT_MIXER_ROUTES("AIF2 Mixer"),
  810. DSP_OUTPUT_MIXER_ROUTES("AIF3 Mixer"),
  811. DSP_OUTPUT_MIXER_ROUTES("DAC1 Mixer"),
  812. DSP_OUTPUT_MIXER_ROUTES("DAC2 Mixer"),
  813. { "AIF1 OUT", NULL, "AIF1 Mixer" },
  814. { "AIF2 OUT", NULL, "AIF2 Mixer" },
  815. { "AIF3 OUT", NULL, "AIF3 Mixer" },
  816. { "Left DAC1", NULL, "DAC1 Mixer" },
  817. { "Right DAC1", NULL, "DAC1 Mixer" },
  818. { "Left DAC2", NULL, "DAC2 Mixer" },
  819. { "Right DAC2", NULL, "DAC2 Mixer" },
  820. LEFT_OUTPUT_MIXER_ROUTES("Left Lineout1 Mixer"),
  821. RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout1 Mixer"),
  822. LEFT_OUTPUT_MIXER_ROUTES("Left Lineout2 Mixer"),
  823. RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout2 Mixer"),
  824. LEFT_OUTPUT_MIXER_ROUTES("Left Speaker Mixer"),
  825. RIGHT_OUTPUT_MIXER_ROUTES("Right Speaker Mixer"),
  826. { "Left Headphone Mixer", "Left DAC2 Switch", "Left DAC2" },
  827. { "Left Headphone Mixer", "Left DAC1 Switch", "Left DAC1" },
  828. { "Left Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
  829. { "Left Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
  830. { "Left Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
  831. { "Left Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
  832. { "Right Headphone Mixer", "Right DAC2 Switch", "Right DAC2" },
  833. { "Right Headphone Mixer", "Right DAC1 Switch", "Right DAC1" },
  834. { "Right Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
  835. { "Right Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
  836. { "Right Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
  837. { "Right Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
  838. { "Left Headphone Mixer", NULL, "Headphone Enable" },
  839. { "Right Headphone Mixer", NULL, "Headphone Enable" },
  840. { "Earpiece Mixer", "Right DAC2 Switch", "Right DAC2" },
  841. { "Earpiece Mixer", "Left DAC2 Switch", "Left DAC2" },
  842. { "Earpiece Mixer", "Right DAC1 Switch", "Right DAC1" },
  843. { "Earpiece Mixer", "Left DAC1 Switch", "Left DAC1" },
  844. { "Earpiece Mixer", "Input 1 Bypass Switch", "IN1PGA" },
  845. { "Earpiece Mixer", "Input 2 Bypass Switch", "IN2PGA" },
  846. { "Earpiece Mixer", "Input 3 Bypass Switch", "IN3PGA" },
  847. { "Earpiece Mixer", "Input 4 Bypass Switch", "IN4PGA" },
  848. { "LOUT1L", NULL, "Left Lineout1 Mixer" },
  849. { "LOUT1R", NULL, "Right Lineout1 Mixer" },
  850. { "LOUT2L", NULL, "Left Lineout2 Mixer" },
  851. { "LOUT2R", NULL, "Right Lineout2 Mixer" },
  852. { "SPKL", NULL, "Left Speaker Mixer" },
  853. { "SPKR", NULL, "Right Speaker Mixer" },
  854. { "HPL", NULL, "Left Headphone Mixer" },
  855. { "HPR", NULL, "Right Headphone Mixer" },
  856. { "EP", NULL, "Earpiece Mixer" },
  857. { "IN1PGA", NULL, "AIN1L" },
  858. { "IN2PGA", NULL, "AIN2L" },
  859. { "IN3PGA", NULL, "AIN3L" },
  860. { "IN4PGA", NULL, "AIN4L" },
  861. { "IN1PGA", NULL, "AIN1R" },
  862. { "IN2PGA", NULL, "AIN2R" },
  863. { "IN3PGA", NULL, "AIN3R" },
  864. { "IN4PGA", NULL, "AIN4R" },
  865. { "SYSCLK1", NULL, "PLL1" },
  866. { "SYSCLK2", NULL, "PLL2" },
  867. { "Left DAC1", NULL, "SYSCLK1" },
  868. { "Right DAC1", NULL, "SYSCLK1" },
  869. { "Left DAC2", NULL, "SYSCLK1" },
  870. { "Right DAC2", NULL, "SYSCLK1" },
  871. { "Left ADC", NULL, "SYSCLK1" },
  872. { "Right ADC", NULL, "SYSCLK1" },
  873. { "DSP", NULL, "SYSCLK1" },
  874. { "AIF1 Mixer", NULL, "DSP" },
  875. { "AIF2 Mixer", NULL, "DSP" },
  876. { "AIF3 Mixer", NULL, "DSP" },
  877. { "DAC1 Mixer", NULL, "DSP" },
  878. { "DAC2 Mixer", NULL, "DSP" },
  879. { "DAC1 Mixer", NULL, "Playback Engine A" },
  880. { "DAC2 Mixer", NULL, "Playback Engine B" },
  881. { "Left ADC Mixer", NULL, "Recording Engine A" },
  882. { "Right ADC Mixer", NULL, "Recording Engine A" },
  883. { "AIF1 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
  884. { "AIF2 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
  885. { "AIF3 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
  886. { "AIF1 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
  887. { "AIF2 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
  888. { "AIF3 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
  889. { "AIF1 IN", NULL, "AIF1 CLK" },
  890. { "AIF1 OUT", NULL, "AIF1 CLK" },
  891. { "AIF2 IN", NULL, "AIF2 CLK" },
  892. { "AIF2 OUT", NULL, "AIF2 CLK" },
  893. { "AIF3 IN", NULL, "AIF3 CLK" },
  894. { "AIF3 OUT", NULL, "AIF3 CLK" },
  895. { "AIF1 IN", NULL, "AIF1 IN SRC", adau1373_check_src },
  896. { "AIF1 OUT", NULL, "AIF1 OUT SRC", adau1373_check_src },
  897. { "AIF2 IN", NULL, "AIF2 IN SRC", adau1373_check_src },
  898. { "AIF2 OUT", NULL, "AIF2 OUT SRC", adau1373_check_src },
  899. { "AIF3 IN", NULL, "AIF3 IN SRC", adau1373_check_src },
  900. { "AIF3 OUT", NULL, "AIF3 OUT SRC", adau1373_check_src },
  901. { "DMIC1", NULL, "DMIC1DAT" },
  902. { "DMIC1", NULL, "SYSCLK1" },
  903. { "DMIC1", NULL, "Recording Engine A" },
  904. { "DMIC2", NULL, "DMIC2DAT" },
  905. { "DMIC2", NULL, "SYSCLK1" },
  906. { "DMIC2", NULL, "Recording Engine B" },
  907. };
  908. static int adau1373_hw_params(struct snd_pcm_substream *substream,
  909. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  910. {
  911. struct snd_soc_component *component = dai->component;
  912. struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
  913. struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
  914. unsigned int div;
  915. unsigned int freq;
  916. unsigned int ctrl;
  917. freq = adau1373_dai->sysclk;
  918. if (freq % params_rate(params) != 0)
  919. return -EINVAL;
  920. switch (freq / params_rate(params)) {
  921. case 1024: /* sysclk / 256 */
  922. div = 0;
  923. break;
  924. case 1536: /* 2/3 sysclk / 256 */
  925. div = 1;
  926. break;
  927. case 2048: /* 1/2 sysclk / 256 */
  928. div = 2;
  929. break;
  930. case 3072: /* 1/3 sysclk / 256 */
  931. div = 3;
  932. break;
  933. case 4096: /* 1/4 sysclk / 256 */
  934. div = 4;
  935. break;
  936. case 6144: /* 1/6 sysclk / 256 */
  937. div = 5;
  938. break;
  939. case 5632: /* 2/11 sysclk / 256 */
  940. div = 6;
  941. break;
  942. default:
  943. return -EINVAL;
  944. }
  945. adau1373_dai->enable_src = (div != 0);
  946. regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
  947. ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK,
  948. (div << 2) | ADAU1373_BCLKDIV_64);
  949. switch (params_width(params)) {
  950. case 16:
  951. ctrl = ADAU1373_DAI_WLEN_16;
  952. break;
  953. case 20:
  954. ctrl = ADAU1373_DAI_WLEN_20;
  955. break;
  956. case 24:
  957. ctrl = ADAU1373_DAI_WLEN_24;
  958. break;
  959. case 32:
  960. ctrl = ADAU1373_DAI_WLEN_32;
  961. break;
  962. default:
  963. return -EINVAL;
  964. }
  965. return regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
  966. ADAU1373_DAI_WLEN_MASK, ctrl);
  967. }
  968. static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  969. {
  970. struct snd_soc_component *component = dai->component;
  971. struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
  972. struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
  973. unsigned int ctrl;
  974. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  975. case SND_SOC_DAIFMT_CBM_CFM:
  976. ctrl = ADAU1373_DAI_MASTER;
  977. adau1373_dai->master = true;
  978. break;
  979. case SND_SOC_DAIFMT_CBS_CFS:
  980. ctrl = 0;
  981. adau1373_dai->master = false;
  982. break;
  983. default:
  984. return -EINVAL;
  985. }
  986. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  987. case SND_SOC_DAIFMT_I2S:
  988. ctrl |= ADAU1373_DAI_FORMAT_I2S;
  989. break;
  990. case SND_SOC_DAIFMT_LEFT_J:
  991. ctrl |= ADAU1373_DAI_FORMAT_LEFT_J;
  992. break;
  993. case SND_SOC_DAIFMT_RIGHT_J:
  994. ctrl |= ADAU1373_DAI_FORMAT_RIGHT_J;
  995. break;
  996. case SND_SOC_DAIFMT_DSP_B:
  997. ctrl |= ADAU1373_DAI_FORMAT_DSP;
  998. break;
  999. default:
  1000. return -EINVAL;
  1001. }
  1002. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1003. case SND_SOC_DAIFMT_NB_NF:
  1004. break;
  1005. case SND_SOC_DAIFMT_IB_NF:
  1006. ctrl |= ADAU1373_DAI_INVERT_BCLK;
  1007. break;
  1008. case SND_SOC_DAIFMT_NB_IF:
  1009. ctrl |= ADAU1373_DAI_INVERT_LRCLK;
  1010. break;
  1011. case SND_SOC_DAIFMT_IB_IF:
  1012. ctrl |= ADAU1373_DAI_INVERT_LRCLK | ADAU1373_DAI_INVERT_BCLK;
  1013. break;
  1014. default:
  1015. return -EINVAL;
  1016. }
  1017. regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
  1018. ~ADAU1373_DAI_WLEN_MASK, ctrl);
  1019. return 0;
  1020. }
  1021. static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai,
  1022. int clk_id, unsigned int freq, int dir)
  1023. {
  1024. struct adau1373 *adau1373 = snd_soc_component_get_drvdata(dai->component);
  1025. struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
  1026. switch (clk_id) {
  1027. case ADAU1373_CLK_SRC_PLL1:
  1028. case ADAU1373_CLK_SRC_PLL2:
  1029. break;
  1030. default:
  1031. return -EINVAL;
  1032. }
  1033. adau1373_dai->sysclk = freq;
  1034. adau1373_dai->clk_src = clk_id;
  1035. regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
  1036. ADAU1373_BCLKDIV_SOURCE, clk_id << 5);
  1037. return 0;
  1038. }
  1039. static const struct snd_soc_dai_ops adau1373_dai_ops = {
  1040. .hw_params = adau1373_hw_params,
  1041. .set_sysclk = adau1373_set_dai_sysclk,
  1042. .set_fmt = adau1373_set_dai_fmt,
  1043. };
  1044. #define ADAU1373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  1045. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1046. static struct snd_soc_dai_driver adau1373_dai_driver[] = {
  1047. {
  1048. .id = 0,
  1049. .name = "adau1373-aif1",
  1050. .playback = {
  1051. .stream_name = "AIF1 Playback",
  1052. .channels_min = 2,
  1053. .channels_max = 2,
  1054. .rates = SNDRV_PCM_RATE_8000_48000,
  1055. .formats = ADAU1373_FORMATS,
  1056. },
  1057. .capture = {
  1058. .stream_name = "AIF1 Capture",
  1059. .channels_min = 2,
  1060. .channels_max = 2,
  1061. .rates = SNDRV_PCM_RATE_8000_48000,
  1062. .formats = ADAU1373_FORMATS,
  1063. },
  1064. .ops = &adau1373_dai_ops,
  1065. .symmetric_rates = 1,
  1066. },
  1067. {
  1068. .id = 1,
  1069. .name = "adau1373-aif2",
  1070. .playback = {
  1071. .stream_name = "AIF2 Playback",
  1072. .channels_min = 2,
  1073. .channels_max = 2,
  1074. .rates = SNDRV_PCM_RATE_8000_48000,
  1075. .formats = ADAU1373_FORMATS,
  1076. },
  1077. .capture = {
  1078. .stream_name = "AIF2 Capture",
  1079. .channels_min = 2,
  1080. .channels_max = 2,
  1081. .rates = SNDRV_PCM_RATE_8000_48000,
  1082. .formats = ADAU1373_FORMATS,
  1083. },
  1084. .ops = &adau1373_dai_ops,
  1085. .symmetric_rates = 1,
  1086. },
  1087. {
  1088. .id = 2,
  1089. .name = "adau1373-aif3",
  1090. .playback = {
  1091. .stream_name = "AIF3 Playback",
  1092. .channels_min = 2,
  1093. .channels_max = 2,
  1094. .rates = SNDRV_PCM_RATE_8000_48000,
  1095. .formats = ADAU1373_FORMATS,
  1096. },
  1097. .capture = {
  1098. .stream_name = "AIF3 Capture",
  1099. .channels_min = 2,
  1100. .channels_max = 2,
  1101. .rates = SNDRV_PCM_RATE_8000_48000,
  1102. .formats = ADAU1373_FORMATS,
  1103. },
  1104. .ops = &adau1373_dai_ops,
  1105. .symmetric_rates = 1,
  1106. },
  1107. };
  1108. static int adau1373_set_pll(struct snd_soc_component *component, int pll_id,
  1109. int source, unsigned int freq_in, unsigned int freq_out)
  1110. {
  1111. struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
  1112. unsigned int dpll_div = 0;
  1113. uint8_t pll_regs[5];
  1114. int ret;
  1115. switch (pll_id) {
  1116. case ADAU1373_PLL1:
  1117. case ADAU1373_PLL2:
  1118. break;
  1119. default:
  1120. return -EINVAL;
  1121. }
  1122. switch (source) {
  1123. case ADAU1373_PLL_SRC_BCLK1:
  1124. case ADAU1373_PLL_SRC_BCLK2:
  1125. case ADAU1373_PLL_SRC_BCLK3:
  1126. case ADAU1373_PLL_SRC_LRCLK1:
  1127. case ADAU1373_PLL_SRC_LRCLK2:
  1128. case ADAU1373_PLL_SRC_LRCLK3:
  1129. case ADAU1373_PLL_SRC_MCLK1:
  1130. case ADAU1373_PLL_SRC_MCLK2:
  1131. case ADAU1373_PLL_SRC_GPIO1:
  1132. case ADAU1373_PLL_SRC_GPIO2:
  1133. case ADAU1373_PLL_SRC_GPIO3:
  1134. case ADAU1373_PLL_SRC_GPIO4:
  1135. break;
  1136. default:
  1137. return -EINVAL;
  1138. }
  1139. if (freq_in < 7813 || freq_in > 27000000)
  1140. return -EINVAL;
  1141. if (freq_out < 45158000 || freq_out > 49152000)
  1142. return -EINVAL;
  1143. /* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the
  1144. * DPLL to get it there. DPLL_out = (DPLL_in / div) * 1024 */
  1145. while (freq_in < 8000000) {
  1146. freq_in *= 2;
  1147. dpll_div++;
  1148. }
  1149. ret = adau_calc_pll_cfg(freq_in, freq_out, pll_regs);
  1150. if (ret)
  1151. return -EINVAL;
  1152. if (dpll_div) {
  1153. dpll_div = 11 - dpll_div;
  1154. regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
  1155. ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0);
  1156. } else {
  1157. regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
  1158. ADAU1373_PLL_CTRL6_DPLL_BYPASS,
  1159. ADAU1373_PLL_CTRL6_DPLL_BYPASS);
  1160. }
  1161. regmap_write(adau1373->regmap, ADAU1373_DPLL_CTRL(pll_id),
  1162. (source << 4) | dpll_div);
  1163. regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), pll_regs[0]);
  1164. regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), pll_regs[1]);
  1165. regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), pll_regs[2]);
  1166. regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), pll_regs[3]);
  1167. regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id), pll_regs[4]);
  1168. /* Set sysclk to pll_rate / 4 */
  1169. regmap_update_bits(adau1373->regmap, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09);
  1170. return 0;
  1171. }
  1172. static void adau1373_load_drc_settings(struct adau1373 *adau1373,
  1173. unsigned int nr, uint8_t *drc)
  1174. {
  1175. unsigned int i;
  1176. for (i = 0; i < ADAU1373_DRC_SIZE; ++i)
  1177. regmap_write(adau1373->regmap, ADAU1373_DRC(nr) + i, drc[i]);
  1178. }
  1179. static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias)
  1180. {
  1181. switch (micbias) {
  1182. case ADAU1373_MICBIAS_2_9V:
  1183. case ADAU1373_MICBIAS_2_2V:
  1184. case ADAU1373_MICBIAS_2_6V:
  1185. case ADAU1373_MICBIAS_1_8V:
  1186. return true;
  1187. default:
  1188. break;
  1189. }
  1190. return false;
  1191. }
  1192. static int adau1373_probe(struct snd_soc_component *component)
  1193. {
  1194. struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
  1195. struct adau1373_platform_data *pdata = component->dev->platform_data;
  1196. bool lineout_differential = false;
  1197. unsigned int val;
  1198. int i;
  1199. if (pdata) {
  1200. if (pdata->num_drc > ARRAY_SIZE(pdata->drc_setting))
  1201. return -EINVAL;
  1202. if (!adau1373_valid_micbias(pdata->micbias1) ||
  1203. !adau1373_valid_micbias(pdata->micbias2))
  1204. return -EINVAL;
  1205. for (i = 0; i < pdata->num_drc; ++i) {
  1206. adau1373_load_drc_settings(adau1373, i,
  1207. pdata->drc_setting[i]);
  1208. }
  1209. snd_soc_add_component_controls(component, adau1373_drc_controls,
  1210. pdata->num_drc);
  1211. val = 0;
  1212. for (i = 0; i < 4; ++i) {
  1213. if (pdata->input_differential[i])
  1214. val |= BIT(i);
  1215. }
  1216. regmap_write(adau1373->regmap, ADAU1373_INPUT_MODE, val);
  1217. val = 0;
  1218. if (pdata->lineout_differential)
  1219. val |= ADAU1373_OUTPUT_CTRL_LDIFF;
  1220. if (pdata->lineout_ground_sense)
  1221. val |= ADAU1373_OUTPUT_CTRL_LNFBEN;
  1222. regmap_write(adau1373->regmap, ADAU1373_OUTPUT_CTRL, val);
  1223. lineout_differential = pdata->lineout_differential;
  1224. regmap_write(adau1373->regmap, ADAU1373_EP_CTRL,
  1225. (pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) |
  1226. (pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET));
  1227. }
  1228. if (!lineout_differential) {
  1229. snd_soc_add_component_controls(component, adau1373_lineout2_controls,
  1230. ARRAY_SIZE(adau1373_lineout2_controls));
  1231. }
  1232. regmap_write(adau1373->regmap, ADAU1373_ADC_CTRL,
  1233. ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT);
  1234. return 0;
  1235. }
  1236. static int adau1373_set_bias_level(struct snd_soc_component *component,
  1237. enum snd_soc_bias_level level)
  1238. {
  1239. struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
  1240. switch (level) {
  1241. case SND_SOC_BIAS_ON:
  1242. break;
  1243. case SND_SOC_BIAS_PREPARE:
  1244. break;
  1245. case SND_SOC_BIAS_STANDBY:
  1246. regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
  1247. ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN);
  1248. break;
  1249. case SND_SOC_BIAS_OFF:
  1250. regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
  1251. ADAU1373_PWDN_CTRL3_PWR_EN, 0);
  1252. break;
  1253. }
  1254. return 0;
  1255. }
  1256. static int adau1373_resume(struct snd_soc_component *component)
  1257. {
  1258. struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
  1259. regcache_sync(adau1373->regmap);
  1260. return 0;
  1261. }
  1262. static bool adau1373_register_volatile(struct device *dev, unsigned int reg)
  1263. {
  1264. switch (reg) {
  1265. case ADAU1373_SOFT_RESET:
  1266. case ADAU1373_ADC_DAC_STATUS:
  1267. return true;
  1268. default:
  1269. return false;
  1270. }
  1271. }
  1272. static const struct regmap_config adau1373_regmap_config = {
  1273. .val_bits = 8,
  1274. .reg_bits = 8,
  1275. .volatile_reg = adau1373_register_volatile,
  1276. .max_register = ADAU1373_SOFT_RESET,
  1277. .cache_type = REGCACHE_RBTREE,
  1278. .reg_defaults = adau1373_reg_defaults,
  1279. .num_reg_defaults = ARRAY_SIZE(adau1373_reg_defaults),
  1280. };
  1281. static const struct snd_soc_component_driver adau1373_component_driver = {
  1282. .probe = adau1373_probe,
  1283. .resume = adau1373_resume,
  1284. .set_bias_level = adau1373_set_bias_level,
  1285. .set_pll = adau1373_set_pll,
  1286. .controls = adau1373_controls,
  1287. .num_controls = ARRAY_SIZE(adau1373_controls),
  1288. .dapm_widgets = adau1373_dapm_widgets,
  1289. .num_dapm_widgets = ARRAY_SIZE(adau1373_dapm_widgets),
  1290. .dapm_routes = adau1373_dapm_routes,
  1291. .num_dapm_routes = ARRAY_SIZE(adau1373_dapm_routes),
  1292. .use_pmdown_time = 1,
  1293. .endianness = 1,
  1294. .non_legacy_dai_naming = 1,
  1295. };
  1296. static int adau1373_i2c_probe(struct i2c_client *client,
  1297. const struct i2c_device_id *id)
  1298. {
  1299. struct adau1373 *adau1373;
  1300. int ret;
  1301. adau1373 = devm_kzalloc(&client->dev, sizeof(*adau1373), GFP_KERNEL);
  1302. if (!adau1373)
  1303. return -ENOMEM;
  1304. adau1373->regmap = devm_regmap_init_i2c(client,
  1305. &adau1373_regmap_config);
  1306. if (IS_ERR(adau1373->regmap))
  1307. return PTR_ERR(adau1373->regmap);
  1308. regmap_write(adau1373->regmap, ADAU1373_SOFT_RESET, 0x00);
  1309. dev_set_drvdata(&client->dev, adau1373);
  1310. ret = devm_snd_soc_register_component(&client->dev,
  1311. &adau1373_component_driver,
  1312. adau1373_dai_driver, ARRAY_SIZE(adau1373_dai_driver));
  1313. return ret;
  1314. }
  1315. static const struct i2c_device_id adau1373_i2c_id[] = {
  1316. { "adau1373", 0 },
  1317. { }
  1318. };
  1319. MODULE_DEVICE_TABLE(i2c, adau1373_i2c_id);
  1320. static struct i2c_driver adau1373_i2c_driver = {
  1321. .driver = {
  1322. .name = "adau1373",
  1323. },
  1324. .probe = adau1373_i2c_probe,
  1325. .id_table = adau1373_i2c_id,
  1326. };
  1327. module_i2c_driver(adau1373_i2c_driver);
  1328. MODULE_DESCRIPTION("ASoC ADAU1373 driver");
  1329. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  1330. MODULE_LICENSE("GPL");