ab8500-codec.c 78 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) ST-Ericsson SA 2012
  4. *
  5. * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
  6. * Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
  7. * Roger Nilsson <roger.xr.nilsson@stericsson.com>,
  8. * for ST-Ericsson.
  9. *
  10. * Based on the early work done by:
  11. * Mikko J. Lehto <mikko.lehto@symbio.com>,
  12. * Mikko Sarmanne <mikko.sarmanne@symbio.com>,
  13. * Jarmo K. Kuronen <jarmo.kuronen@symbio.com>,
  14. * for ST-Ericsson.
  15. *
  16. * License terms:
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/device.h>
  21. #include <linux/slab.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/mutex.h>
  28. #include <linux/mfd/abx500/ab8500.h>
  29. #include <linux/mfd/abx500.h>
  30. #include <linux/mfd/abx500/ab8500-sysctrl.h>
  31. #include <linux/mfd/abx500/ab8500-codec.h>
  32. #include <linux/regulator/consumer.h>
  33. #include <linux/of.h>
  34. #include <sound/core.h>
  35. #include <sound/pcm.h>
  36. #include <sound/pcm_params.h>
  37. #include <sound/initval.h>
  38. #include <sound/soc.h>
  39. #include <sound/soc-dapm.h>
  40. #include <sound/tlv.h>
  41. #include "ab8500-codec.h"
  42. /* Macrocell value definitions */
  43. #define CLK_32K_OUT2_DISABLE 0x01
  44. #define INACTIVE_RESET_AUDIO 0x02
  45. #define ENABLE_AUDIO_CLK_TO_AUDIO_BLK 0x10
  46. #define ENABLE_VINTCORE12_SUPPLY 0x04
  47. #define GPIO27_DIR_OUTPUT 0x04
  48. #define GPIO29_DIR_OUTPUT 0x10
  49. #define GPIO31_DIR_OUTPUT 0x40
  50. /* Macrocell register definitions */
  51. #define AB8500_GPIO_DIR4_REG 0x13 /* Bank AB8500_MISC */
  52. /* Nr of FIR/IIR-coeff banks in ANC-block */
  53. #define AB8500_NR_OF_ANC_COEFF_BANKS 2
  54. /* Minimum duration to keep ANC IIR Init bit high or
  55. low before proceeding with the configuration sequence */
  56. #define AB8500_ANC_SM_DELAY 2000
  57. #define AB8500_FILTER_CONTROL(xname, xcount, xmin, xmax) \
  58. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  59. .info = filter_control_info, \
  60. .get = filter_control_get, .put = filter_control_put, \
  61. .private_value = (unsigned long)&(struct filter_control) \
  62. {.count = xcount, .min = xmin, .max = xmax} }
  63. struct filter_control {
  64. long min, max;
  65. unsigned int count;
  66. long value[128];
  67. };
  68. /* Sidetone states */
  69. static const char * const enum_sid_state[] = {
  70. "Unconfigured",
  71. "Apply FIR",
  72. "FIR is configured",
  73. };
  74. enum sid_state {
  75. SID_UNCONFIGURED = 0,
  76. SID_APPLY_FIR = 1,
  77. SID_FIR_CONFIGURED = 2,
  78. };
  79. static const char * const enum_anc_state[] = {
  80. "Unconfigured",
  81. "Apply FIR and IIR",
  82. "FIR and IIR are configured",
  83. "Apply FIR",
  84. "FIR is configured",
  85. "Apply IIR",
  86. "IIR is configured"
  87. };
  88. enum anc_state {
  89. ANC_UNCONFIGURED = 0,
  90. ANC_APPLY_FIR_IIR = 1,
  91. ANC_FIR_IIR_CONFIGURED = 2,
  92. ANC_APPLY_FIR = 3,
  93. ANC_FIR_CONFIGURED = 4,
  94. ANC_APPLY_IIR = 5,
  95. ANC_IIR_CONFIGURED = 6
  96. };
  97. /* Analog microphones */
  98. enum amic_idx {
  99. AMIC_IDX_1A,
  100. AMIC_IDX_1B,
  101. AMIC_IDX_2
  102. };
  103. struct ab8500_codec_drvdata_dbg {
  104. struct regulator *vaud;
  105. struct regulator *vamic1;
  106. struct regulator *vamic2;
  107. struct regulator *vdmic;
  108. };
  109. /* Private data for AB8500 device-driver */
  110. struct ab8500_codec_drvdata {
  111. struct regmap *regmap;
  112. struct mutex ctrl_lock;
  113. /* Sidetone */
  114. long *sid_fir_values;
  115. enum sid_state sid_status;
  116. /* ANC */
  117. long *anc_fir_values;
  118. long *anc_iir_values;
  119. enum anc_state anc_status;
  120. };
  121. static inline const char *amic_micbias_str(enum amic_micbias micbias)
  122. {
  123. switch (micbias) {
  124. case AMIC_MICBIAS_VAMIC1:
  125. return "VAMIC1";
  126. case AMIC_MICBIAS_VAMIC2:
  127. return "VAMIC2";
  128. default:
  129. return "Unknown";
  130. }
  131. }
  132. static inline const char *amic_type_str(enum amic_type type)
  133. {
  134. switch (type) {
  135. case AMIC_TYPE_DIFFERENTIAL:
  136. return "DIFFERENTIAL";
  137. case AMIC_TYPE_SINGLE_ENDED:
  138. return "SINGLE ENDED";
  139. default:
  140. return "Unknown";
  141. }
  142. }
  143. /*
  144. * Read'n'write functions
  145. */
  146. /* Read a register from the audio-bank of AB8500 */
  147. static int ab8500_codec_read_reg(void *context, unsigned int reg,
  148. unsigned int *value)
  149. {
  150. struct device *dev = context;
  151. int status;
  152. u8 value8;
  153. status = abx500_get_register_interruptible(dev, AB8500_AUDIO,
  154. reg, &value8);
  155. *value = (unsigned int)value8;
  156. return status;
  157. }
  158. /* Write to a register in the audio-bank of AB8500 */
  159. static int ab8500_codec_write_reg(void *context, unsigned int reg,
  160. unsigned int value)
  161. {
  162. struct device *dev = context;
  163. return abx500_set_register_interruptible(dev, AB8500_AUDIO,
  164. reg, value);
  165. }
  166. static const struct regmap_config ab8500_codec_regmap = {
  167. .reg_read = ab8500_codec_read_reg,
  168. .reg_write = ab8500_codec_write_reg,
  169. };
  170. /*
  171. * Controls - DAPM
  172. */
  173. /* Earpiece */
  174. /* Earpiece source selector */
  175. static const char * const enum_ear_lineout_source[] = {"Headset Left",
  176. "Speaker Left"};
  177. static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF,
  178. AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source);
  179. static const struct snd_kcontrol_new dapm_ear_lineout_source =
  180. SOC_DAPM_ENUM("Earpiece or LineOut Mono Source",
  181. dapm_enum_ear_lineout_source);
  182. /* LineOut */
  183. /* LineOut source selector */
  184. static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"};
  185. static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5,
  186. AB8500_ANACONF5_HSLDACTOLOL,
  187. AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source);
  188. static const struct snd_kcontrol_new dapm_lineout_source[] = {
  189. SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source),
  190. };
  191. /* Handsfree */
  192. /* Speaker Left - ANC selector */
  193. static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"};
  194. static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2,
  195. AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel);
  196. static const struct snd_kcontrol_new dapm_HFl_select[] = {
  197. SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel),
  198. };
  199. /* Speaker Right - ANC selector */
  200. static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2,
  201. AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel);
  202. static const struct snd_kcontrol_new dapm_HFr_select[] = {
  203. SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel),
  204. };
  205. /* Mic 1 */
  206. /* Mic 1 - Mic 1a or 1b selector */
  207. static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"};
  208. static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3,
  209. AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel);
  210. static const struct snd_kcontrol_new dapm_mic1ab_mux[] = {
  211. SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel),
  212. };
  213. /* Mic 1 - AD3 - Mic 1 or DMic 3 selector */
  214. static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"};
  215. static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1,
  216. AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel);
  217. static const struct snd_kcontrol_new dapm_ad3_select[] = {
  218. SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel),
  219. };
  220. /* Mic 1 - AD6 - Mic 1 or DMic 6 selector */
  221. static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"};
  222. static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1,
  223. AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel);
  224. static const struct snd_kcontrol_new dapm_ad6_select[] = {
  225. SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel),
  226. };
  227. /* Mic 2 */
  228. /* Mic 2 - AD5 - Mic 2 or DMic 5 selector */
  229. static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"};
  230. static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1,
  231. AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel);
  232. static const struct snd_kcontrol_new dapm_ad5_select[] = {
  233. SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel),
  234. };
  235. /* LineIn */
  236. /* LineIn left - AD1 - LineIn Left or DMic 1 selector */
  237. static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"};
  238. static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1,
  239. AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel);
  240. static const struct snd_kcontrol_new dapm_ad1_select[] = {
  241. SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel),
  242. };
  243. /* LineIn right - Mic 2 or LineIn Right selector */
  244. static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"};
  245. static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3,
  246. AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel);
  247. static const struct snd_kcontrol_new dapm_mic2lr_select[] = {
  248. SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel),
  249. };
  250. /* LineIn right - AD2 - LineIn Right or DMic2 selector */
  251. static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"};
  252. static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1,
  253. AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel);
  254. static const struct snd_kcontrol_new dapm_ad2_select[] = {
  255. SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel),
  256. };
  257. /* ANC */
  258. static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6",
  259. "Mic 2 / DMic 5"};
  260. static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF,
  261. AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel);
  262. static const struct snd_kcontrol_new dapm_anc_in_select[] = {
  263. SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel),
  264. };
  265. /* ANC - Enable/Disable */
  266. static const struct snd_kcontrol_new dapm_anc_enable[] = {
  267. SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1,
  268. AB8500_ANCCONF1_ENANC, 0, 0),
  269. };
  270. /* ANC to Earpiece - Mute */
  271. static const struct snd_kcontrol_new dapm_anc_ear_mute[] = {
  272. SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1,
  273. AB8500_DIGMULTCONF1_ANCSEL, 1, 0),
  274. };
  275. /* Sidetone left */
  276. /* Sidetone left - Input selector */
  277. static const char * const enum_stfir1_in_sel[] = {
  278. "LineIn Left", "LineIn Right", "Mic 1", "Headset Left"
  279. };
  280. static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2,
  281. AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel);
  282. static const struct snd_kcontrol_new dapm_stfir1_in_select[] = {
  283. SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel),
  284. };
  285. /* Sidetone right path */
  286. /* Sidetone right - Input selector */
  287. static const char * const enum_stfir2_in_sel[] = {
  288. "LineIn Right", "Mic 1", "DMic 4", "Headset Right"
  289. };
  290. static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2,
  291. AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel);
  292. static const struct snd_kcontrol_new dapm_stfir2_in_select[] = {
  293. SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel),
  294. };
  295. /* Vibra */
  296. static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"};
  297. static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1,
  298. AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx);
  299. static const struct snd_kcontrol_new dapm_pwm2vib1[] = {
  300. SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1),
  301. };
  302. static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1,
  303. AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx);
  304. static const struct snd_kcontrol_new dapm_pwm2vib2[] = {
  305. SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2),
  306. };
  307. /*
  308. * DAPM-widgets
  309. */
  310. static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = {
  311. /* Clocks */
  312. SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"),
  313. /* Regulators */
  314. SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0),
  315. SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0),
  316. SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0),
  317. SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0),
  318. /* Power */
  319. SND_SOC_DAPM_SUPPLY("Audio Power",
  320. AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0,
  321. NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  322. SND_SOC_DAPM_SUPPLY("Audio Analog Power",
  323. AB8500_POWERUP, AB8500_POWERUP_ENANA, 0,
  324. NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  325. /* Main supply node */
  326. SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0,
  327. NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  328. /* DA/AD */
  329. SND_SOC_DAPM_INPUT("ADC Input"),
  330. SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0),
  331. SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
  332. SND_SOC_DAPM_OUTPUT("DAC Output"),
  333. SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0),
  334. SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0),
  335. SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0),
  336. SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0),
  337. SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0),
  338. SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0),
  339. SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0),
  340. SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0),
  341. SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0),
  342. SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0),
  343. SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0),
  344. SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0),
  345. /* Headset path */
  346. SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5,
  347. AB8500_ANACONF5_ENCPHS, 0, NULL, 0),
  348. SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p",
  349. AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0),
  350. SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p",
  351. AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0),
  352. SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0,
  353. NULL, 0),
  354. SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0,
  355. NULL, 0),
  356. SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p",
  357. AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0),
  358. SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p",
  359. AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0),
  360. SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF,
  361. AB8500_MUTECONF_MUTDACHSL, 1,
  362. NULL, 0),
  363. SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF,
  364. AB8500_MUTECONF_MUTDACHSR, 1,
  365. NULL, 0),
  366. SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p",
  367. AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0),
  368. SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p",
  369. AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0),
  370. SND_SOC_DAPM_MIXER("HSL Mute",
  371. AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1,
  372. NULL, 0),
  373. SND_SOC_DAPM_MIXER("HSR Mute",
  374. AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1,
  375. NULL, 0),
  376. SND_SOC_DAPM_MIXER("HSL Enable",
  377. AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0,
  378. NULL, 0),
  379. SND_SOC_DAPM_MIXER("HSR Enable",
  380. AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0,
  381. NULL, 0),
  382. SND_SOC_DAPM_PGA("HSL Volume",
  383. SND_SOC_NOPM, 0, 0,
  384. NULL, 0),
  385. SND_SOC_DAPM_PGA("HSR Volume",
  386. SND_SOC_NOPM, 0, 0,
  387. NULL, 0),
  388. SND_SOC_DAPM_OUTPUT("Headset Left"),
  389. SND_SOC_DAPM_OUTPUT("Headset Right"),
  390. /* LineOut path */
  391. SND_SOC_DAPM_MUX("LineOut Source",
  392. SND_SOC_NOPM, 0, 0, dapm_lineout_source),
  393. SND_SOC_DAPM_MIXER("LOL Disable HFL",
  394. AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1,
  395. NULL, 0),
  396. SND_SOC_DAPM_MIXER("LOR Disable HFR",
  397. AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1,
  398. NULL, 0),
  399. SND_SOC_DAPM_MIXER("LOL Enable",
  400. AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0,
  401. NULL, 0),
  402. SND_SOC_DAPM_MIXER("LOR Enable",
  403. AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0,
  404. NULL, 0),
  405. SND_SOC_DAPM_OUTPUT("LineOut Left"),
  406. SND_SOC_DAPM_OUTPUT("LineOut Right"),
  407. /* Earpiece path */
  408. SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source",
  409. SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source),
  410. SND_SOC_DAPM_MIXER("EAR DAC",
  411. AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0,
  412. NULL, 0),
  413. SND_SOC_DAPM_MIXER("EAR Mute",
  414. AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1,
  415. NULL, 0),
  416. SND_SOC_DAPM_MIXER("EAR Enable",
  417. AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0,
  418. NULL, 0),
  419. SND_SOC_DAPM_OUTPUT("Earpiece"),
  420. /* Handsfree path */
  421. SND_SOC_DAPM_MIXER("DA3 Channel Volume",
  422. AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0,
  423. NULL, 0),
  424. SND_SOC_DAPM_MIXER("DA4 Channel Volume",
  425. AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0,
  426. NULL, 0),
  427. SND_SOC_DAPM_MUX("Speaker Left Source",
  428. SND_SOC_NOPM, 0, 0, dapm_HFl_select),
  429. SND_SOC_DAPM_MUX("Speaker Right Source",
  430. SND_SOC_NOPM, 0, 0, dapm_HFr_select),
  431. SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF,
  432. AB8500_DAPATHCONF_ENDACHFL, 0,
  433. NULL, 0),
  434. SND_SOC_DAPM_MIXER("HFR DAC",
  435. AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0,
  436. NULL, 0),
  437. SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR",
  438. AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0,
  439. NULL, 0),
  440. SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL",
  441. AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0,
  442. NULL, 0),
  443. SND_SOC_DAPM_MIXER("HFL Enable",
  444. AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0,
  445. NULL, 0),
  446. SND_SOC_DAPM_MIXER("HFR Enable",
  447. AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0,
  448. NULL, 0),
  449. SND_SOC_DAPM_OUTPUT("Speaker Left"),
  450. SND_SOC_DAPM_OUTPUT("Speaker Right"),
  451. /* Vibrator path */
  452. SND_SOC_DAPM_INPUT("PWMGEN1"),
  453. SND_SOC_DAPM_INPUT("PWMGEN2"),
  454. SND_SOC_DAPM_MIXER("DA5 Channel Volume",
  455. AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0,
  456. NULL, 0),
  457. SND_SOC_DAPM_MIXER("DA6 Channel Volume",
  458. AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0,
  459. NULL, 0),
  460. SND_SOC_DAPM_MIXER("VIB1 DAC",
  461. AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0,
  462. NULL, 0),
  463. SND_SOC_DAPM_MIXER("VIB2 DAC",
  464. AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0,
  465. NULL, 0),
  466. SND_SOC_DAPM_MUX("Vibra 1 Controller",
  467. SND_SOC_NOPM, 0, 0, dapm_pwm2vib1),
  468. SND_SOC_DAPM_MUX("Vibra 2 Controller",
  469. SND_SOC_NOPM, 0, 0, dapm_pwm2vib2),
  470. SND_SOC_DAPM_MIXER("VIB1 Enable",
  471. AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0,
  472. NULL, 0),
  473. SND_SOC_DAPM_MIXER("VIB2 Enable",
  474. AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0,
  475. NULL, 0),
  476. SND_SOC_DAPM_OUTPUT("Vibra 1"),
  477. SND_SOC_DAPM_OUTPUT("Vibra 2"),
  478. /* Mic 1 */
  479. SND_SOC_DAPM_INPUT("Mic 1"),
  480. SND_SOC_DAPM_MUX("Mic 1a or 1b Select",
  481. SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux),
  482. SND_SOC_DAPM_MIXER("MIC1 Mute",
  483. AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1,
  484. NULL, 0),
  485. SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable",
  486. AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
  487. NULL, 0),
  488. SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable",
  489. AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
  490. NULL, 0),
  491. SND_SOC_DAPM_MIXER("MIC1 ADC",
  492. AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0,
  493. NULL, 0),
  494. SND_SOC_DAPM_MUX("AD3 Source Select",
  495. SND_SOC_NOPM, 0, 0, dapm_ad3_select),
  496. SND_SOC_DAPM_MIXER("AD3 Channel Volume",
  497. SND_SOC_NOPM, 0, 0,
  498. NULL, 0),
  499. SND_SOC_DAPM_MIXER("AD3 Enable",
  500. AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0,
  501. NULL, 0),
  502. /* Mic 2 */
  503. SND_SOC_DAPM_INPUT("Mic 2"),
  504. SND_SOC_DAPM_MIXER("MIC2 Mute",
  505. AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1,
  506. NULL, 0),
  507. SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2,
  508. AB8500_ANACONF2_ENMIC2, 0,
  509. NULL, 0),
  510. /* LineIn */
  511. SND_SOC_DAPM_INPUT("LineIn Left"),
  512. SND_SOC_DAPM_INPUT("LineIn Right"),
  513. SND_SOC_DAPM_MIXER("LINL Mute",
  514. AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1,
  515. NULL, 0),
  516. SND_SOC_DAPM_MIXER("LINR Mute",
  517. AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1,
  518. NULL, 0),
  519. SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2,
  520. AB8500_ANACONF2_ENLINL, 0,
  521. NULL, 0),
  522. SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2,
  523. AB8500_ANACONF2_ENLINR, 0,
  524. NULL, 0),
  525. /* LineIn Bypass path */
  526. SND_SOC_DAPM_MIXER("LINL to HSL Volume",
  527. SND_SOC_NOPM, 0, 0,
  528. NULL, 0),
  529. SND_SOC_DAPM_MIXER("LINR to HSR Volume",
  530. SND_SOC_NOPM, 0, 0,
  531. NULL, 0),
  532. /* LineIn, Mic 2 */
  533. SND_SOC_DAPM_MUX("Mic 2 or LINR Select",
  534. SND_SOC_NOPM, 0, 0, dapm_mic2lr_select),
  535. SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3,
  536. AB8500_ANACONF3_ENADCLINL, 0,
  537. NULL, 0),
  538. SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3,
  539. AB8500_ANACONF3_ENADCLINR, 0,
  540. NULL, 0),
  541. SND_SOC_DAPM_MUX("AD1 Source Select",
  542. SND_SOC_NOPM, 0, 0, dapm_ad1_select),
  543. SND_SOC_DAPM_MUX("AD2 Source Select",
  544. SND_SOC_NOPM, 0, 0, dapm_ad2_select),
  545. SND_SOC_DAPM_MIXER("AD1 Channel Volume",
  546. SND_SOC_NOPM, 0, 0,
  547. NULL, 0),
  548. SND_SOC_DAPM_MIXER("AD2 Channel Volume",
  549. SND_SOC_NOPM, 0, 0,
  550. NULL, 0),
  551. SND_SOC_DAPM_MIXER("AD12 Enable",
  552. AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0,
  553. NULL, 0),
  554. /* HD Capture path */
  555. SND_SOC_DAPM_MUX("AD5 Source Select",
  556. SND_SOC_NOPM, 0, 0, dapm_ad5_select),
  557. SND_SOC_DAPM_MUX("AD6 Source Select",
  558. SND_SOC_NOPM, 0, 0, dapm_ad6_select),
  559. SND_SOC_DAPM_MIXER("AD5 Channel Volume",
  560. SND_SOC_NOPM, 0, 0,
  561. NULL, 0),
  562. SND_SOC_DAPM_MIXER("AD6 Channel Volume",
  563. SND_SOC_NOPM, 0, 0,
  564. NULL, 0),
  565. SND_SOC_DAPM_MIXER("AD57 Enable",
  566. AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
  567. NULL, 0),
  568. SND_SOC_DAPM_MIXER("AD68 Enable",
  569. AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
  570. NULL, 0),
  571. /* Digital Microphone path */
  572. SND_SOC_DAPM_INPUT("DMic 1"),
  573. SND_SOC_DAPM_INPUT("DMic 2"),
  574. SND_SOC_DAPM_INPUT("DMic 3"),
  575. SND_SOC_DAPM_INPUT("DMic 4"),
  576. SND_SOC_DAPM_INPUT("DMic 5"),
  577. SND_SOC_DAPM_INPUT("DMic 6"),
  578. SND_SOC_DAPM_MIXER("DMIC1",
  579. AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0,
  580. NULL, 0),
  581. SND_SOC_DAPM_MIXER("DMIC2",
  582. AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0,
  583. NULL, 0),
  584. SND_SOC_DAPM_MIXER("DMIC3",
  585. AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0,
  586. NULL, 0),
  587. SND_SOC_DAPM_MIXER("DMIC4",
  588. AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0,
  589. NULL, 0),
  590. SND_SOC_DAPM_MIXER("DMIC5",
  591. AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0,
  592. NULL, 0),
  593. SND_SOC_DAPM_MIXER("DMIC6",
  594. AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0,
  595. NULL, 0),
  596. SND_SOC_DAPM_MIXER("AD4 Channel Volume",
  597. SND_SOC_NOPM, 0, 0,
  598. NULL, 0),
  599. SND_SOC_DAPM_MIXER("AD4 Enable",
  600. AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34,
  601. 0, NULL, 0),
  602. /* Acoustical Noise Cancellation path */
  603. SND_SOC_DAPM_INPUT("ANC Configure Input"),
  604. SND_SOC_DAPM_OUTPUT("ANC Configure Output"),
  605. SND_SOC_DAPM_MUX("ANC Source",
  606. SND_SOC_NOPM, 0, 0,
  607. dapm_anc_in_select),
  608. SND_SOC_DAPM_SWITCH("ANC",
  609. SND_SOC_NOPM, 0, 0,
  610. dapm_anc_enable),
  611. SND_SOC_DAPM_SWITCH("ANC to Earpiece",
  612. SND_SOC_NOPM, 0, 0,
  613. dapm_anc_ear_mute),
  614. /* Sidetone Filter path */
  615. SND_SOC_DAPM_MUX("Sidetone Left Source",
  616. SND_SOC_NOPM, 0, 0,
  617. dapm_stfir1_in_select),
  618. SND_SOC_DAPM_MUX("Sidetone Right Source",
  619. SND_SOC_NOPM, 0, 0,
  620. dapm_stfir2_in_select),
  621. SND_SOC_DAPM_MIXER("STFIR1 Control",
  622. SND_SOC_NOPM, 0, 0,
  623. NULL, 0),
  624. SND_SOC_DAPM_MIXER("STFIR2 Control",
  625. SND_SOC_NOPM, 0, 0,
  626. NULL, 0),
  627. SND_SOC_DAPM_MIXER("STFIR1 Volume",
  628. SND_SOC_NOPM, 0, 0,
  629. NULL, 0),
  630. SND_SOC_DAPM_MIXER("STFIR2 Volume",
  631. SND_SOC_NOPM, 0, 0,
  632. NULL, 0),
  633. };
  634. /*
  635. * DAPM-routes
  636. */
  637. static const struct snd_soc_dapm_route ab8500_dapm_routes[] = {
  638. /* Power AB8500 audio-block when AD/DA is active */
  639. {"Main Supply", NULL, "V-AUD"},
  640. {"Main Supply", NULL, "audioclk"},
  641. {"Main Supply", NULL, "Audio Power"},
  642. {"Main Supply", NULL, "Audio Analog Power"},
  643. {"DAC", NULL, "ab8500_0p"},
  644. {"DAC", NULL, "Main Supply"},
  645. {"ADC", NULL, "ab8500_0c"},
  646. {"ADC", NULL, "Main Supply"},
  647. /* ANC Configure */
  648. {"ANC Configure Input", NULL, "Main Supply"},
  649. {"ANC Configure Output", NULL, "ANC Configure Input"},
  650. /* AD/DA */
  651. {"ADC", NULL, "ADC Input"},
  652. {"DAC Output", NULL, "DAC"},
  653. /* Powerup charge pump if DA1/2 is in use */
  654. {"DA_IN1", NULL, "ab8500_0p"},
  655. {"DA_IN1", NULL, "Charge Pump"},
  656. {"DA_IN2", NULL, "ab8500_0p"},
  657. {"DA_IN2", NULL, "Charge Pump"},
  658. /* Headset path */
  659. {"DA1 Enable", NULL, "DA_IN1"},
  660. {"DA2 Enable", NULL, "DA_IN2"},
  661. {"HSL Digital Volume", NULL, "DA1 Enable"},
  662. {"HSR Digital Volume", NULL, "DA2 Enable"},
  663. {"HSL DAC", NULL, "HSL Digital Volume"},
  664. {"HSR DAC", NULL, "HSR Digital Volume"},
  665. {"HSL DAC Mute", NULL, "HSL DAC"},
  666. {"HSR DAC Mute", NULL, "HSR DAC"},
  667. {"HSL DAC Driver", NULL, "HSL DAC Mute"},
  668. {"HSR DAC Driver", NULL, "HSR DAC Mute"},
  669. {"HSL Mute", NULL, "HSL DAC Driver"},
  670. {"HSR Mute", NULL, "HSR DAC Driver"},
  671. {"HSL Enable", NULL, "HSL Mute"},
  672. {"HSR Enable", NULL, "HSR Mute"},
  673. {"HSL Volume", NULL, "HSL Enable"},
  674. {"HSR Volume", NULL, "HSR Enable"},
  675. {"Headset Left", NULL, "HSL Volume"},
  676. {"Headset Right", NULL, "HSR Volume"},
  677. /* HF or LineOut path */
  678. {"DA_IN3", NULL, "ab8500_0p"},
  679. {"DA3 Channel Volume", NULL, "DA_IN3"},
  680. {"DA_IN4", NULL, "ab8500_0p"},
  681. {"DA4 Channel Volume", NULL, "DA_IN4"},
  682. {"Speaker Left Source", "Audio Path", "DA3 Channel Volume"},
  683. {"Speaker Right Source", "Audio Path", "DA4 Channel Volume"},
  684. {"DA3 or ANC path to HfL", NULL, "Speaker Left Source"},
  685. {"DA4 or ANC path to HfR", NULL, "Speaker Right Source"},
  686. /* HF path */
  687. {"HFL DAC", NULL, "DA3 or ANC path to HfL"},
  688. {"HFR DAC", NULL, "DA4 or ANC path to HfR"},
  689. {"HFL Enable", NULL, "HFL DAC"},
  690. {"HFR Enable", NULL, "HFR DAC"},
  691. {"Speaker Left", NULL, "HFL Enable"},
  692. {"Speaker Right", NULL, "HFR Enable"},
  693. /* Earpiece path */
  694. {"Earpiece or LineOut Mono Source", "Headset Left",
  695. "HSL Digital Volume"},
  696. {"Earpiece or LineOut Mono Source", "Speaker Left",
  697. "DA3 or ANC path to HfL"},
  698. {"EAR DAC", NULL, "Earpiece or LineOut Mono Source"},
  699. {"EAR Mute", NULL, "EAR DAC"},
  700. {"EAR Enable", NULL, "EAR Mute"},
  701. {"Earpiece", NULL, "EAR Enable"},
  702. /* LineOut path stereo */
  703. {"LineOut Source", "Stereo Path", "HSL DAC Driver"},
  704. {"LineOut Source", "Stereo Path", "HSR DAC Driver"},
  705. /* LineOut path mono */
  706. {"LineOut Source", "Mono Path", "EAR DAC"},
  707. /* LineOut path */
  708. {"LOL Disable HFL", NULL, "LineOut Source"},
  709. {"LOR Disable HFR", NULL, "LineOut Source"},
  710. {"LOL Enable", NULL, "LOL Disable HFL"},
  711. {"LOR Enable", NULL, "LOR Disable HFR"},
  712. {"LineOut Left", NULL, "LOL Enable"},
  713. {"LineOut Right", NULL, "LOR Enable"},
  714. /* Vibrator path */
  715. {"DA_IN5", NULL, "ab8500_0p"},
  716. {"DA5 Channel Volume", NULL, "DA_IN5"},
  717. {"DA_IN6", NULL, "ab8500_0p"},
  718. {"DA6 Channel Volume", NULL, "DA_IN6"},
  719. {"VIB1 DAC", NULL, "DA5 Channel Volume"},
  720. {"VIB2 DAC", NULL, "DA6 Channel Volume"},
  721. {"Vibra 1 Controller", "Audio Path", "VIB1 DAC"},
  722. {"Vibra 2 Controller", "Audio Path", "VIB2 DAC"},
  723. {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"},
  724. {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"},
  725. {"VIB1 Enable", NULL, "Vibra 1 Controller"},
  726. {"VIB2 Enable", NULL, "Vibra 2 Controller"},
  727. {"Vibra 1", NULL, "VIB1 Enable"},
  728. {"Vibra 2", NULL, "VIB2 Enable"},
  729. /* Mic 2 */
  730. {"MIC2 V-AMICx Enable", NULL, "Mic 2"},
  731. /* LineIn */
  732. {"LINL Mute", NULL, "LineIn Left"},
  733. {"LINR Mute", NULL, "LineIn Right"},
  734. {"LINL Enable", NULL, "LINL Mute"},
  735. {"LINR Enable", NULL, "LINR Mute"},
  736. /* LineIn, Mic 2 */
  737. {"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"},
  738. {"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"},
  739. {"LINL ADC", NULL, "LINL Enable"},
  740. {"LINR ADC", NULL, "Mic 2 or LINR Select"},
  741. {"AD1 Source Select", "LineIn Left", "LINL ADC"},
  742. {"AD2 Source Select", "LineIn Right", "LINR ADC"},
  743. {"AD1 Channel Volume", NULL, "AD1 Source Select"},
  744. {"AD2 Channel Volume", NULL, "AD2 Source Select"},
  745. {"AD12 Enable", NULL, "AD1 Channel Volume"},
  746. {"AD12 Enable", NULL, "AD2 Channel Volume"},
  747. {"AD_OUT1", NULL, "ab8500_0c"},
  748. {"AD_OUT1", NULL, "AD12 Enable"},
  749. {"AD_OUT2", NULL, "ab8500_0c"},
  750. {"AD_OUT2", NULL, "AD12 Enable"},
  751. /* Mic 1 */
  752. {"MIC1 Mute", NULL, "Mic 1"},
  753. {"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"},
  754. {"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"},
  755. {"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"},
  756. {"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"},
  757. {"MIC1 ADC", NULL, "Mic 1a or 1b Select"},
  758. {"AD3 Source Select", "Mic 1", "MIC1 ADC"},
  759. {"AD3 Channel Volume", NULL, "AD3 Source Select"},
  760. {"AD3 Enable", NULL, "AD3 Channel Volume"},
  761. {"AD_OUT3", NULL, "ab8500_0c"},
  762. {"AD_OUT3", NULL, "AD3 Enable"},
  763. /* HD Capture path */
  764. {"AD5 Source Select", "Mic 2", "LINR ADC"},
  765. {"AD6 Source Select", "Mic 1", "MIC1 ADC"},
  766. {"AD5 Channel Volume", NULL, "AD5 Source Select"},
  767. {"AD6 Channel Volume", NULL, "AD6 Source Select"},
  768. {"AD57 Enable", NULL, "AD5 Channel Volume"},
  769. {"AD68 Enable", NULL, "AD6 Channel Volume"},
  770. {"AD_OUT57", NULL, "ab8500_0c"},
  771. {"AD_OUT57", NULL, "AD57 Enable"},
  772. {"AD_OUT68", NULL, "ab8500_0c"},
  773. {"AD_OUT68", NULL, "AD68 Enable"},
  774. /* Digital Microphone path */
  775. {"DMic 1", NULL, "V-DMIC"},
  776. {"DMic 2", NULL, "V-DMIC"},
  777. {"DMic 3", NULL, "V-DMIC"},
  778. {"DMic 4", NULL, "V-DMIC"},
  779. {"DMic 5", NULL, "V-DMIC"},
  780. {"DMic 6", NULL, "V-DMIC"},
  781. {"AD1 Source Select", NULL, "DMic 1"},
  782. {"AD2 Source Select", NULL, "DMic 2"},
  783. {"AD3 Source Select", NULL, "DMic 3"},
  784. {"AD5 Source Select", NULL, "DMic 5"},
  785. {"AD6 Source Select", NULL, "DMic 6"},
  786. {"AD4 Channel Volume", NULL, "DMic 4"},
  787. {"AD4 Enable", NULL, "AD4 Channel Volume"},
  788. {"AD_OUT4", NULL, "ab8500_0c"},
  789. {"AD_OUT4", NULL, "AD4 Enable"},
  790. /* LineIn Bypass path */
  791. {"LINL to HSL Volume", NULL, "LINL Enable"},
  792. {"LINR to HSR Volume", NULL, "LINR Enable"},
  793. {"HSL DAC Driver", NULL, "LINL to HSL Volume"},
  794. {"HSR DAC Driver", NULL, "LINR to HSR Volume"},
  795. /* ANC path (Acoustic Noise Cancellation) */
  796. {"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"},
  797. {"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"},
  798. {"ANC", "Switch", "ANC Source"},
  799. {"Speaker Left Source", "ANC", "ANC"},
  800. {"Speaker Right Source", "ANC", "ANC"},
  801. {"ANC to Earpiece", "Switch", "ANC"},
  802. {"HSL Digital Volume", NULL, "ANC to Earpiece"},
  803. /* Sidetone Filter path */
  804. {"Sidetone Left Source", "LineIn Left", "AD12 Enable"},
  805. {"Sidetone Left Source", "LineIn Right", "AD12 Enable"},
  806. {"Sidetone Left Source", "Mic 1", "AD3 Enable"},
  807. {"Sidetone Left Source", "Headset Left", "DA_IN1"},
  808. {"Sidetone Right Source", "LineIn Right", "AD12 Enable"},
  809. {"Sidetone Right Source", "Mic 1", "AD3 Enable"},
  810. {"Sidetone Right Source", "DMic 4", "AD4 Enable"},
  811. {"Sidetone Right Source", "Headset Right", "DA_IN2"},
  812. {"STFIR1 Control", NULL, "Sidetone Left Source"},
  813. {"STFIR2 Control", NULL, "Sidetone Right Source"},
  814. {"STFIR1 Volume", NULL, "STFIR1 Control"},
  815. {"STFIR2 Volume", NULL, "STFIR2 Control"},
  816. {"DA1 Enable", NULL, "STFIR1 Volume"},
  817. {"DA2 Enable", NULL, "STFIR2 Volume"},
  818. };
  819. static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = {
  820. {"MIC1A V-AMICx Enable", NULL, "V-AMIC1"},
  821. {"MIC1A V-AMICx Enable", NULL, "V-AMIC2"},
  822. };
  823. static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = {
  824. {"MIC1B V-AMICx Enable", NULL, "V-AMIC1"},
  825. {"MIC1B V-AMICx Enable", NULL, "V-AMIC2"},
  826. };
  827. static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = {
  828. {"MIC2 V-AMICx Enable", NULL, "V-AMIC1"},
  829. {"MIC2 V-AMICx Enable", NULL, "V-AMIC2"},
  830. };
  831. /* ANC FIR-coefficients configuration sequence */
  832. static void anc_fir(struct snd_soc_component *component,
  833. unsigned int bnk, unsigned int par, unsigned int val)
  834. {
  835. if (par == 0 && bnk == 0)
  836. snd_soc_component_update_bits(component, AB8500_ANCCONF1,
  837. BIT(AB8500_ANCCONF1_ANCFIRUPDATE),
  838. BIT(AB8500_ANCCONF1_ANCFIRUPDATE));
  839. snd_soc_component_write(component, AB8500_ANCCONF5, val >> 8 & 0xff);
  840. snd_soc_component_write(component, AB8500_ANCCONF6, val & 0xff);
  841. if (par == AB8500_ANC_FIR_COEFFS - 1 && bnk == 1)
  842. snd_soc_component_update_bits(component, AB8500_ANCCONF1,
  843. BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 0);
  844. }
  845. /* ANC IIR-coefficients configuration sequence */
  846. static void anc_iir(struct snd_soc_component *component, unsigned int bnk,
  847. unsigned int par, unsigned int val)
  848. {
  849. if (par == 0) {
  850. if (bnk == 0) {
  851. snd_soc_component_update_bits(component, AB8500_ANCCONF1,
  852. BIT(AB8500_ANCCONF1_ANCIIRINIT),
  853. BIT(AB8500_ANCCONF1_ANCIIRINIT));
  854. usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY*2);
  855. snd_soc_component_update_bits(component, AB8500_ANCCONF1,
  856. BIT(AB8500_ANCCONF1_ANCIIRINIT), 0);
  857. usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY*2);
  858. } else {
  859. snd_soc_component_update_bits(component, AB8500_ANCCONF1,
  860. BIT(AB8500_ANCCONF1_ANCIIRUPDATE),
  861. BIT(AB8500_ANCCONF1_ANCIIRUPDATE));
  862. }
  863. } else if (par > 3) {
  864. snd_soc_component_write(component, AB8500_ANCCONF7, 0);
  865. snd_soc_component_write(component, AB8500_ANCCONF8, val >> 16 & 0xff);
  866. }
  867. snd_soc_component_write(component, AB8500_ANCCONF7, val >> 8 & 0xff);
  868. snd_soc_component_write(component, AB8500_ANCCONF8, val & 0xff);
  869. if (par == AB8500_ANC_IIR_COEFFS - 1 && bnk == 1)
  870. snd_soc_component_update_bits(component, AB8500_ANCCONF1,
  871. BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 0);
  872. }
  873. /* ANC IIR-/FIR-coefficients configuration sequence */
  874. static void anc_configure(struct snd_soc_component *component,
  875. bool apply_fir, bool apply_iir)
  876. {
  877. struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
  878. unsigned int bnk, par, val;
  879. dev_dbg(component->dev, "%s: Enter.\n", __func__);
  880. if (apply_fir)
  881. snd_soc_component_update_bits(component, AB8500_ANCCONF1,
  882. BIT(AB8500_ANCCONF1_ENANC), 0);
  883. snd_soc_component_update_bits(component, AB8500_ANCCONF1,
  884. BIT(AB8500_ANCCONF1_ENANC), BIT(AB8500_ANCCONF1_ENANC));
  885. if (apply_fir)
  886. for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
  887. for (par = 0; par < AB8500_ANC_FIR_COEFFS; par++) {
  888. val = snd_soc_component_read(component,
  889. drvdata->anc_fir_values[par]);
  890. anc_fir(component, bnk, par, val);
  891. }
  892. if (apply_iir)
  893. for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
  894. for (par = 0; par < AB8500_ANC_IIR_COEFFS; par++) {
  895. val = snd_soc_component_read(component,
  896. drvdata->anc_iir_values[par]);
  897. anc_iir(component, bnk, par, val);
  898. }
  899. dev_dbg(component->dev, "%s: Exit.\n", __func__);
  900. }
  901. /*
  902. * Control-events
  903. */
  904. static int sid_status_control_get(struct snd_kcontrol *kcontrol,
  905. struct snd_ctl_elem_value *ucontrol)
  906. {
  907. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  908. struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
  909. mutex_lock(&drvdata->ctrl_lock);
  910. ucontrol->value.enumerated.item[0] = drvdata->sid_status;
  911. mutex_unlock(&drvdata->ctrl_lock);
  912. return 0;
  913. }
  914. /* Write sidetone FIR-coefficients configuration sequence */
  915. static int sid_status_control_put(struct snd_kcontrol *kcontrol,
  916. struct snd_ctl_elem_value *ucontrol)
  917. {
  918. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  919. struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
  920. unsigned int param, sidconf, val;
  921. int status = 1;
  922. dev_dbg(component->dev, "%s: Enter\n", __func__);
  923. if (ucontrol->value.enumerated.item[0] != SID_APPLY_FIR) {
  924. dev_err(component->dev,
  925. "%s: ERROR: This control supports '%s' only!\n",
  926. __func__, enum_sid_state[SID_APPLY_FIR]);
  927. return -EIO;
  928. }
  929. mutex_lock(&drvdata->ctrl_lock);
  930. sidconf = snd_soc_component_read(component, AB8500_SIDFIRCONF);
  931. if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) {
  932. if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) {
  933. dev_err(component->dev, "%s: Sidetone busy while off!\n",
  934. __func__);
  935. status = -EPERM;
  936. } else {
  937. status = -EBUSY;
  938. }
  939. goto out;
  940. }
  941. snd_soc_component_write(component, AB8500_SIDFIRADR, 0);
  942. for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) {
  943. val = snd_soc_component_read(component, drvdata->sid_fir_values[param]);
  944. snd_soc_component_write(component, AB8500_SIDFIRCOEF1, val >> 8 & 0xff);
  945. snd_soc_component_write(component, AB8500_SIDFIRCOEF2, val & 0xff);
  946. }
  947. snd_soc_component_update_bits(component, AB8500_SIDFIRADR,
  948. BIT(AB8500_SIDFIRADR_FIRSIDSET),
  949. BIT(AB8500_SIDFIRADR_FIRSIDSET));
  950. snd_soc_component_update_bits(component, AB8500_SIDFIRADR,
  951. BIT(AB8500_SIDFIRADR_FIRSIDSET), 0);
  952. drvdata->sid_status = SID_FIR_CONFIGURED;
  953. out:
  954. mutex_unlock(&drvdata->ctrl_lock);
  955. dev_dbg(component->dev, "%s: Exit\n", __func__);
  956. return status;
  957. }
  958. static int anc_status_control_get(struct snd_kcontrol *kcontrol,
  959. struct snd_ctl_elem_value *ucontrol)
  960. {
  961. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  962. struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
  963. mutex_lock(&drvdata->ctrl_lock);
  964. ucontrol->value.enumerated.item[0] = drvdata->anc_status;
  965. mutex_unlock(&drvdata->ctrl_lock);
  966. return 0;
  967. }
  968. static int anc_status_control_put(struct snd_kcontrol *kcontrol,
  969. struct snd_ctl_elem_value *ucontrol)
  970. {
  971. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  972. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  973. struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
  974. struct device *dev = component->dev;
  975. bool apply_fir, apply_iir;
  976. unsigned int req;
  977. int status;
  978. dev_dbg(dev, "%s: Enter.\n", __func__);
  979. mutex_lock(&drvdata->ctrl_lock);
  980. req = ucontrol->value.enumerated.item[0];
  981. if (req >= ARRAY_SIZE(enum_anc_state)) {
  982. status = -EINVAL;
  983. goto cleanup;
  984. }
  985. if (req != ANC_APPLY_FIR_IIR && req != ANC_APPLY_FIR &&
  986. req != ANC_APPLY_IIR) {
  987. dev_err(dev, "%s: ERROR: Unsupported status to set '%s'!\n",
  988. __func__, enum_anc_state[req]);
  989. status = -EINVAL;
  990. goto cleanup;
  991. }
  992. apply_fir = req == ANC_APPLY_FIR || req == ANC_APPLY_FIR_IIR;
  993. apply_iir = req == ANC_APPLY_IIR || req == ANC_APPLY_FIR_IIR;
  994. status = snd_soc_dapm_force_enable_pin(dapm, "ANC Configure Input");
  995. if (status < 0) {
  996. dev_err(dev,
  997. "%s: ERROR: Failed to enable power (status = %d)!\n",
  998. __func__, status);
  999. goto cleanup;
  1000. }
  1001. snd_soc_dapm_sync(dapm);
  1002. anc_configure(component, apply_fir, apply_iir);
  1003. if (apply_fir) {
  1004. if (drvdata->anc_status == ANC_IIR_CONFIGURED)
  1005. drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
  1006. else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
  1007. drvdata->anc_status = ANC_FIR_CONFIGURED;
  1008. }
  1009. if (apply_iir) {
  1010. if (drvdata->anc_status == ANC_FIR_CONFIGURED)
  1011. drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
  1012. else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
  1013. drvdata->anc_status = ANC_IIR_CONFIGURED;
  1014. }
  1015. status = snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
  1016. snd_soc_dapm_sync(dapm);
  1017. cleanup:
  1018. mutex_unlock(&drvdata->ctrl_lock);
  1019. if (status < 0)
  1020. dev_err(dev, "%s: Unable to configure ANC! (status = %d)\n",
  1021. __func__, status);
  1022. dev_dbg(dev, "%s: Exit.\n", __func__);
  1023. return (status < 0) ? status : 1;
  1024. }
  1025. static int filter_control_info(struct snd_kcontrol *kcontrol,
  1026. struct snd_ctl_elem_info *uinfo)
  1027. {
  1028. struct filter_control *fc =
  1029. (struct filter_control *)kcontrol->private_value;
  1030. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1031. uinfo->count = fc->count;
  1032. uinfo->value.integer.min = fc->min;
  1033. uinfo->value.integer.max = fc->max;
  1034. return 0;
  1035. }
  1036. static int filter_control_get(struct snd_kcontrol *kcontrol,
  1037. struct snd_ctl_elem_value *ucontrol)
  1038. {
  1039. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1040. struct ab8500_codec_drvdata *drvdata = snd_soc_component_get_drvdata(component);
  1041. struct filter_control *fc =
  1042. (struct filter_control *)kcontrol->private_value;
  1043. unsigned int i;
  1044. mutex_lock(&drvdata->ctrl_lock);
  1045. for (i = 0; i < fc->count; i++)
  1046. ucontrol->value.integer.value[i] = fc->value[i];
  1047. mutex_unlock(&drvdata->ctrl_lock);
  1048. return 0;
  1049. }
  1050. static int filter_control_put(struct snd_kcontrol *kcontrol,
  1051. struct snd_ctl_elem_value *ucontrol)
  1052. {
  1053. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1054. struct ab8500_codec_drvdata *drvdata = snd_soc_component_get_drvdata(component);
  1055. struct filter_control *fc =
  1056. (struct filter_control *)kcontrol->private_value;
  1057. unsigned int i;
  1058. mutex_lock(&drvdata->ctrl_lock);
  1059. for (i = 0; i < fc->count; i++)
  1060. fc->value[i] = ucontrol->value.integer.value[i];
  1061. mutex_unlock(&drvdata->ctrl_lock);
  1062. return 0;
  1063. }
  1064. /*
  1065. * Controls - Non-DAPM ASoC
  1066. */
  1067. static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1);
  1068. /* -32dB = Mute */
  1069. static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1);
  1070. /* -63dB = Mute */
  1071. static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1);
  1072. /* -1dB = Mute */
  1073. static const DECLARE_TLV_DB_RANGE(hs_gain_tlv,
  1074. 0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0),
  1075. 4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0)
  1076. );
  1077. static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
  1078. static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0);
  1079. static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1);
  1080. /* -38dB = Mute */
  1081. static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms",
  1082. "5ms"};
  1083. static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed,
  1084. AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed);
  1085. static const char * const enum_envdetthre[] = {
  1086. "250mV", "300mV", "350mV", "400mV",
  1087. "450mV", "500mV", "550mV", "600mV",
  1088. "650mV", "700mV", "750mV", "800mV",
  1089. "850mV", "900mV", "950mV", "1.00V" };
  1090. static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre,
  1091. AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre);
  1092. static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre,
  1093. AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre);
  1094. static const char * const enum_envdettime[] = {
  1095. "26.6us", "53.2us", "106us", "213us",
  1096. "426us", "851us", "1.70ms", "3.40ms",
  1097. "6.81ms", "13.6ms", "27.2ms", "54.5ms",
  1098. "109ms", "218ms", "436ms", "872ms" };
  1099. static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime,
  1100. AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime);
  1101. static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"};
  1102. static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN,
  1103. AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31);
  1104. static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"};
  1105. static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN,
  1106. AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed);
  1107. /* Earpiece */
  1108. static const char * const enum_lowpow[] = {"Normal", "Low Power"};
  1109. static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1,
  1110. AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow);
  1111. static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1,
  1112. AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow);
  1113. static const char * const enum_av_mode[] = {"Audio", "Voice"};
  1114. static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF,
  1115. AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode);
  1116. static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF,
  1117. AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode);
  1118. /* DA */
  1119. static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice,
  1120. AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE,
  1121. enum_av_mode);
  1122. static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice,
  1123. AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE,
  1124. enum_av_mode);
  1125. static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice,
  1126. AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE,
  1127. enum_av_mode);
  1128. static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"};
  1129. static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1,
  1130. AB8500_DIGMULTCONF1_DATOHSLEN,
  1131. AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr);
  1132. static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"};
  1133. static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF,
  1134. AB8500_DMICFILTCONF_DMIC1SINC3,
  1135. AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53);
  1136. static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF,
  1137. AB8500_DMICFILTCONF_DMIC3SINC3,
  1138. AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53);
  1139. static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF,
  1140. AB8500_DMICFILTCONF_DMIC5SINC3,
  1141. AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53);
  1142. /* Digital interface - DA from slot mapping */
  1143. static const char * const enum_da_from_slot_map[] = {"SLOT0",
  1144. "SLOT1",
  1145. "SLOT2",
  1146. "SLOT3",
  1147. "SLOT4",
  1148. "SLOT5",
  1149. "SLOT6",
  1150. "SLOT7",
  1151. "SLOT8",
  1152. "SLOT9",
  1153. "SLOT10",
  1154. "SLOT11",
  1155. "SLOT12",
  1156. "SLOT13",
  1157. "SLOT14",
  1158. "SLOT15",
  1159. "SLOT16",
  1160. "SLOT17",
  1161. "SLOT18",
  1162. "SLOT19",
  1163. "SLOT20",
  1164. "SLOT21",
  1165. "SLOT22",
  1166. "SLOT23",
  1167. "SLOT24",
  1168. "SLOT25",
  1169. "SLOT26",
  1170. "SLOT27",
  1171. "SLOT28",
  1172. "SLOT29",
  1173. "SLOT30",
  1174. "SLOT31"};
  1175. static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap,
  1176. AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
  1177. enum_da_from_slot_map);
  1178. static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap,
  1179. AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
  1180. enum_da_from_slot_map);
  1181. static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap,
  1182. AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
  1183. enum_da_from_slot_map);
  1184. static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap,
  1185. AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
  1186. enum_da_from_slot_map);
  1187. static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap,
  1188. AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
  1189. enum_da_from_slot_map);
  1190. static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap,
  1191. AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
  1192. enum_da_from_slot_map);
  1193. static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap,
  1194. AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
  1195. enum_da_from_slot_map);
  1196. static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap,
  1197. AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
  1198. enum_da_from_slot_map);
  1199. /* Digital interface - AD to slot mapping */
  1200. static const char * const enum_ad_to_slot_map[] = {"AD_OUT1",
  1201. "AD_OUT2",
  1202. "AD_OUT3",
  1203. "AD_OUT4",
  1204. "AD_OUT5",
  1205. "AD_OUT6",
  1206. "AD_OUT7",
  1207. "AD_OUT8",
  1208. "zeroes",
  1209. "zeroes",
  1210. "zeroes",
  1211. "zeroes",
  1212. "tristate",
  1213. "tristate",
  1214. "tristate",
  1215. "tristate"};
  1216. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map,
  1217. AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1218. enum_ad_to_slot_map);
  1219. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map,
  1220. AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT,
  1221. enum_ad_to_slot_map);
  1222. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map,
  1223. AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1224. enum_ad_to_slot_map);
  1225. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map,
  1226. AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT,
  1227. enum_ad_to_slot_map);
  1228. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map,
  1229. AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1230. enum_ad_to_slot_map);
  1231. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map,
  1232. AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT,
  1233. enum_ad_to_slot_map);
  1234. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map,
  1235. AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1236. enum_ad_to_slot_map);
  1237. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map,
  1238. AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT,
  1239. enum_ad_to_slot_map);
  1240. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map,
  1241. AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1242. enum_ad_to_slot_map);
  1243. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map,
  1244. AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT,
  1245. enum_ad_to_slot_map);
  1246. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map,
  1247. AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1248. enum_ad_to_slot_map);
  1249. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map,
  1250. AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT,
  1251. enum_ad_to_slot_map);
  1252. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map,
  1253. AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1254. enum_ad_to_slot_map);
  1255. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map,
  1256. AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT,
  1257. enum_ad_to_slot_map);
  1258. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map,
  1259. AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1260. enum_ad_to_slot_map);
  1261. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map,
  1262. AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT,
  1263. enum_ad_to_slot_map);
  1264. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map,
  1265. AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1266. enum_ad_to_slot_map);
  1267. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map,
  1268. AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT,
  1269. enum_ad_to_slot_map);
  1270. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map,
  1271. AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1272. enum_ad_to_slot_map);
  1273. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map,
  1274. AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT,
  1275. enum_ad_to_slot_map);
  1276. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map,
  1277. AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1278. enum_ad_to_slot_map);
  1279. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map,
  1280. AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT,
  1281. enum_ad_to_slot_map);
  1282. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map,
  1283. AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1284. enum_ad_to_slot_map);
  1285. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map,
  1286. AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT,
  1287. enum_ad_to_slot_map);
  1288. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map,
  1289. AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1290. enum_ad_to_slot_map);
  1291. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map,
  1292. AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT,
  1293. enum_ad_to_slot_map);
  1294. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map,
  1295. AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1296. enum_ad_to_slot_map);
  1297. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map,
  1298. AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT,
  1299. enum_ad_to_slot_map);
  1300. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map,
  1301. AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1302. enum_ad_to_slot_map);
  1303. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map,
  1304. AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT,
  1305. enum_ad_to_slot_map);
  1306. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map,
  1307. AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT,
  1308. enum_ad_to_slot_map);
  1309. static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map,
  1310. AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT,
  1311. enum_ad_to_slot_map);
  1312. /* Digital interface - Burst mode */
  1313. static const char * const enum_mask[] = {"Unmasked", "Masked"};
  1314. static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask,
  1315. AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK,
  1316. enum_mask);
  1317. static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"};
  1318. static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2,
  1319. AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2,
  1320. enum_bitclk0);
  1321. static const char * const enum_slavemaster[] = {"Slave", "Master"};
  1322. static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast,
  1323. AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT,
  1324. enum_slavemaster);
  1325. /* Sidetone */
  1326. static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state);
  1327. /* ANC */
  1328. static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_ancstate, enum_anc_state);
  1329. static struct snd_kcontrol_new ab8500_ctrls[] = {
  1330. /* Charge pump */
  1331. SOC_ENUM("Charge Pump High Threshold For Low Voltage",
  1332. soc_enum_envdeththre),
  1333. SOC_ENUM("Charge Pump Low Threshold For Low Voltage",
  1334. soc_enum_envdetlthre),
  1335. SOC_SINGLE("Charge Pump Envelope Detection Switch",
  1336. AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN,
  1337. 1, 0),
  1338. SOC_ENUM("Charge Pump Envelope Detection Decay Time",
  1339. soc_enum_envdettime),
  1340. /* Headset */
  1341. SOC_ENUM("Headset Mode", soc_enum_da12voice),
  1342. SOC_SINGLE("Headset High Pass Switch",
  1343. AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN,
  1344. 1, 0),
  1345. SOC_SINGLE("Headset Low Power Switch",
  1346. AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW,
  1347. 1, 0),
  1348. SOC_SINGLE("Headset DAC Low Power Switch",
  1349. AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1,
  1350. 1, 0),
  1351. SOC_SINGLE("Headset DAC Drv Low Power Switch",
  1352. AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0,
  1353. 1, 0),
  1354. SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed),
  1355. SOC_ENUM("Headset Source", soc_enum_da2hslr),
  1356. SOC_ENUM("Headset Filter", soc_enum_hsesinc),
  1357. SOC_DOUBLE_R_TLV("Headset Master Volume",
  1358. AB8500_DADIGGAIN1, AB8500_DADIGGAIN2,
  1359. 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
  1360. SOC_DOUBLE_R_TLV("Headset Digital Volume",
  1361. AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN,
  1362. 0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv),
  1363. SOC_DOUBLE_TLV("Headset Volume",
  1364. AB8500_ANAGAIN3,
  1365. AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN,
  1366. AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv),
  1367. /* Earpiece */
  1368. SOC_ENUM("Earpiece DAC Mode",
  1369. soc_enum_eardaclowpow),
  1370. SOC_ENUM("Earpiece DAC Drv Mode",
  1371. soc_enum_eardrvlowpow),
  1372. /* HandsFree */
  1373. SOC_ENUM("HF Mode", soc_enum_da34voice),
  1374. SOC_SINGLE("HF and Headset Swap Switch",
  1375. AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34,
  1376. 1, 0),
  1377. SOC_DOUBLE("HF Low EMI Mode Switch",
  1378. AB8500_CLASSDCONF1,
  1379. AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN,
  1380. 1, 0),
  1381. SOC_DOUBLE("HF FIR Bypass Switch",
  1382. AB8500_CLASSDCONF2,
  1383. AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1,
  1384. 1, 0),
  1385. SOC_DOUBLE("HF High Volume Switch",
  1386. AB8500_CLASSDCONF2,
  1387. AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1,
  1388. 1, 0),
  1389. SOC_SINGLE("HF L and R Bridge Switch",
  1390. AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF,
  1391. 1, 0),
  1392. SOC_DOUBLE_R_TLV("HF Master Volume",
  1393. AB8500_DADIGGAIN3, AB8500_DADIGGAIN4,
  1394. 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
  1395. /* Vibra */
  1396. SOC_DOUBLE("Vibra High Volume Switch",
  1397. AB8500_CLASSDCONF2,
  1398. AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3,
  1399. 1, 0),
  1400. SOC_DOUBLE("Vibra Low EMI Mode Switch",
  1401. AB8500_CLASSDCONF1,
  1402. AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN,
  1403. 1, 0),
  1404. SOC_DOUBLE("Vibra FIR Bypass Switch",
  1405. AB8500_CLASSDCONF2,
  1406. AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3,
  1407. 1, 0),
  1408. SOC_ENUM("Vibra Mode", soc_enum_da56voice),
  1409. SOC_DOUBLE_R("Vibra PWM Duty Cycle N",
  1410. AB8500_PWMGENCONF3, AB8500_PWMGENCONF5,
  1411. AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
  1412. AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
  1413. SOC_DOUBLE_R("Vibra PWM Duty Cycle P",
  1414. AB8500_PWMGENCONF2, AB8500_PWMGENCONF4,
  1415. AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
  1416. AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
  1417. SOC_SINGLE("Vibra 1 and 2 Bridge Switch",
  1418. AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB,
  1419. 1, 0),
  1420. SOC_DOUBLE_R_TLV("Vibra Master Volume",
  1421. AB8500_DADIGGAIN5, AB8500_DADIGGAIN6,
  1422. 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
  1423. /* HandsFree, Vibra */
  1424. SOC_SINGLE("ClassD High Pass Volume",
  1425. AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN,
  1426. AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0),
  1427. SOC_SINGLE("ClassD White Volume",
  1428. AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN,
  1429. AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0),
  1430. /* Mic 1, Mic 2, LineIn */
  1431. SOC_DOUBLE_R_TLV("Mic Master Volume",
  1432. AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4,
  1433. 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
  1434. /* Mic 1 */
  1435. SOC_SINGLE_TLV("Mic 1",
  1436. AB8500_ANAGAIN1,
  1437. AB8500_ANAGAINX_MICXGAIN,
  1438. AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
  1439. SOC_SINGLE("Mic 1 Low Power Switch",
  1440. AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX,
  1441. 1, 0),
  1442. /* Mic 2 */
  1443. SOC_DOUBLE("Mic High Pass Switch",
  1444. AB8500_ADFILTCONF,
  1445. AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH,
  1446. 1, 1),
  1447. SOC_ENUM("Mic Mode", soc_enum_ad34voice),
  1448. SOC_ENUM("Mic Filter", soc_enum_dmic34sinc),
  1449. SOC_SINGLE_TLV("Mic 2",
  1450. AB8500_ANAGAIN2,
  1451. AB8500_ANAGAINX_MICXGAIN,
  1452. AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
  1453. SOC_SINGLE("Mic 2 Low Power Switch",
  1454. AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX,
  1455. 1, 0),
  1456. /* LineIn */
  1457. SOC_DOUBLE("LineIn High Pass Switch",
  1458. AB8500_ADFILTCONF,
  1459. AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH,
  1460. 1, 1),
  1461. SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc),
  1462. SOC_ENUM("LineIn Mode", soc_enum_ad12voice),
  1463. SOC_DOUBLE_R_TLV("LineIn Master Volume",
  1464. AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2,
  1465. 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
  1466. SOC_DOUBLE_TLV("LineIn",
  1467. AB8500_ANAGAIN4,
  1468. AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN,
  1469. AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv),
  1470. SOC_DOUBLE_R_TLV("LineIn to Headset Volume",
  1471. AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN,
  1472. AB8500_DIGLINHSXGAIN_LINTOHSXGAIN,
  1473. AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX,
  1474. 1, lin2hs_gain_tlv),
  1475. /* DMic */
  1476. SOC_ENUM("DMic Filter", soc_enum_dmic56sinc),
  1477. SOC_DOUBLE_R_TLV("DMic Master Volume",
  1478. AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6,
  1479. 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
  1480. /* Digital gains */
  1481. SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed),
  1482. /* Analog loopback */
  1483. SOC_DOUBLE_R_TLV("Analog Loopback Volume",
  1484. AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2,
  1485. 0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv),
  1486. /* Digital interface - DA from slot mapping */
  1487. SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap),
  1488. SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap),
  1489. SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap),
  1490. SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap),
  1491. SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap),
  1492. SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap),
  1493. SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap),
  1494. SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap),
  1495. /* Digital interface - AD to slot mapping */
  1496. SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map),
  1497. SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map),
  1498. SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map),
  1499. SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map),
  1500. SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map),
  1501. SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map),
  1502. SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map),
  1503. SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map),
  1504. SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map),
  1505. SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map),
  1506. SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map),
  1507. SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map),
  1508. SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map),
  1509. SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map),
  1510. SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map),
  1511. SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map),
  1512. SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map),
  1513. SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map),
  1514. SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map),
  1515. SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map),
  1516. SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map),
  1517. SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map),
  1518. SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map),
  1519. SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map),
  1520. SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map),
  1521. SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map),
  1522. SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map),
  1523. SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map),
  1524. SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map),
  1525. SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map),
  1526. SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map),
  1527. SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map),
  1528. /* Digital interface - Loopback */
  1529. SOC_SINGLE("Digital Interface AD 1 Loopback Switch",
  1530. AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1,
  1531. 1, 0),
  1532. SOC_SINGLE("Digital Interface AD 2 Loopback Switch",
  1533. AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2,
  1534. 1, 0),
  1535. SOC_SINGLE("Digital Interface AD 3 Loopback Switch",
  1536. AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3,
  1537. 1, 0),
  1538. SOC_SINGLE("Digital Interface AD 4 Loopback Switch",
  1539. AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4,
  1540. 1, 0),
  1541. SOC_SINGLE("Digital Interface AD 5 Loopback Switch",
  1542. AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5,
  1543. 1, 0),
  1544. SOC_SINGLE("Digital Interface AD 6 Loopback Switch",
  1545. AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6,
  1546. 1, 0),
  1547. SOC_SINGLE("Digital Interface AD 7 Loopback Switch",
  1548. AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7,
  1549. 1, 0),
  1550. SOC_SINGLE("Digital Interface AD 8 Loopback Switch",
  1551. AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8,
  1552. 1, 0),
  1553. /* Digital interface - Burst FIFO */
  1554. SOC_SINGLE("Digital Interface 0 FIFO Enable Switch",
  1555. AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN,
  1556. 1, 0),
  1557. SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask),
  1558. SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2),
  1559. SOC_SINGLE("Burst FIFO Threshold",
  1560. AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT,
  1561. AB8500_FIFOCONF1_BFIFOINT_MAX, 0),
  1562. SOC_SINGLE("Burst FIFO Length",
  1563. AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT,
  1564. AB8500_FIFOCONF2_BFIFOTX_MAX, 0),
  1565. SOC_SINGLE("Burst FIFO EOS Extra Slots",
  1566. AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT,
  1567. AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0),
  1568. SOC_SINGLE("Burst FIFO FS Extra Bit-clocks",
  1569. AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT,
  1570. AB8500_FIFOCONF3_PREBITCLK0_MAX, 0),
  1571. SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast),
  1572. SOC_SINGLE("Burst FIFO Interface Switch",
  1573. AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT,
  1574. 1, 0),
  1575. SOC_SINGLE("Burst FIFO Switch Frame Number",
  1576. AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT,
  1577. AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0),
  1578. SOC_SINGLE("Burst FIFO Wake Up Delay",
  1579. AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT,
  1580. AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0),
  1581. SOC_SINGLE("Burst FIFO Samples In FIFO",
  1582. AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT,
  1583. AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0),
  1584. /* ANC */
  1585. SOC_ENUM_EXT("ANC Status", soc_enum_ancstate,
  1586. anc_status_control_get, anc_status_control_put),
  1587. SOC_SINGLE_XR_SX("ANC Warp Delay Shift",
  1588. AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT,
  1589. AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0),
  1590. SOC_SINGLE_XR_SX("ANC FIR Output Shift",
  1591. AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT,
  1592. AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0),
  1593. SOC_SINGLE_XR_SX("ANC IIR Output Shift",
  1594. AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT,
  1595. AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0),
  1596. SOC_SINGLE_XR_SX("ANC Warp Delay",
  1597. AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT,
  1598. AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0),
  1599. /* Sidetone */
  1600. SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate,
  1601. sid_status_control_get, sid_status_control_put),
  1602. SOC_SINGLE_STROBE("Sidetone Reset",
  1603. AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0),
  1604. };
  1605. static struct snd_kcontrol_new ab8500_filter_controls[] = {
  1606. AB8500_FILTER_CONTROL("ANC FIR Coefficients", AB8500_ANC_FIR_COEFFS,
  1607. AB8500_ANC_FIR_COEFF_MIN, AB8500_ANC_FIR_COEFF_MAX),
  1608. AB8500_FILTER_CONTROL("ANC IIR Coefficients", AB8500_ANC_IIR_COEFFS,
  1609. AB8500_ANC_IIR_COEFF_MIN, AB8500_ANC_IIR_COEFF_MAX),
  1610. AB8500_FILTER_CONTROL("Sidetone FIR Coefficients",
  1611. AB8500_SID_FIR_COEFFS, AB8500_SID_FIR_COEFF_MIN,
  1612. AB8500_SID_FIR_COEFF_MAX)
  1613. };
  1614. enum ab8500_filter {
  1615. AB8500_FILTER_ANC_FIR = 0,
  1616. AB8500_FILTER_ANC_IIR = 1,
  1617. AB8500_FILTER_SID_FIR = 2,
  1618. };
  1619. /*
  1620. * Extended interface for codec-driver
  1621. */
  1622. static int ab8500_audio_init_audioblock(struct snd_soc_component *component)
  1623. {
  1624. int status;
  1625. dev_dbg(component->dev, "%s: Enter.\n", __func__);
  1626. /* Reset audio-registers and disable 32kHz-clock output 2 */
  1627. status = ab8500_sysctrl_write(AB8500_STW4500CTRL3,
  1628. AB8500_STW4500CTRL3_CLK32KOUT2DIS |
  1629. AB8500_STW4500CTRL3_RESETAUDN,
  1630. AB8500_STW4500CTRL3_RESETAUDN);
  1631. if (status < 0)
  1632. return status;
  1633. return 0;
  1634. }
  1635. static int ab8500_audio_setup_mics(struct snd_soc_component *component,
  1636. struct amic_settings *amics)
  1637. {
  1638. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  1639. u8 value8;
  1640. unsigned int value;
  1641. int status;
  1642. const struct snd_soc_dapm_route *route;
  1643. dev_dbg(component->dev, "%s: Enter.\n", __func__);
  1644. /* Set DMic-clocks to outputs */
  1645. status = abx500_get_register_interruptible(component->dev, AB8500_MISC,
  1646. AB8500_GPIO_DIR4_REG,
  1647. &value8);
  1648. if (status < 0)
  1649. return status;
  1650. value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT |
  1651. GPIO31_DIR_OUTPUT;
  1652. status = abx500_set_register_interruptible(component->dev,
  1653. AB8500_MISC,
  1654. AB8500_GPIO_DIR4_REG,
  1655. value);
  1656. if (status < 0)
  1657. return status;
  1658. /* Attach regulators to AMic DAPM-paths */
  1659. dev_dbg(component->dev, "%s: Mic 1a regulator: %s\n", __func__,
  1660. amic_micbias_str(amics->mic1a_micbias));
  1661. route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias];
  1662. status = snd_soc_dapm_add_routes(dapm, route, 1);
  1663. dev_dbg(component->dev, "%s: Mic 1b regulator: %s\n", __func__,
  1664. amic_micbias_str(amics->mic1b_micbias));
  1665. route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias];
  1666. status |= snd_soc_dapm_add_routes(dapm, route, 1);
  1667. dev_dbg(component->dev, "%s: Mic 2 regulator: %s\n", __func__,
  1668. amic_micbias_str(amics->mic2_micbias));
  1669. route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias];
  1670. status |= snd_soc_dapm_add_routes(dapm, route, 1);
  1671. if (status < 0) {
  1672. dev_err(component->dev,
  1673. "%s: Failed to add AMic-regulator DAPM-routes (%d).\n",
  1674. __func__, status);
  1675. return status;
  1676. }
  1677. /* Set AMic-configuration */
  1678. dev_dbg(component->dev, "%s: Mic 1 mic-type: %s\n", __func__,
  1679. amic_type_str(amics->mic1_type));
  1680. snd_soc_component_update_bits(component, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX,
  1681. amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ?
  1682. 0 : AB8500_ANAGAINX_ENSEMICX);
  1683. dev_dbg(component->dev, "%s: Mic 2 mic-type: %s\n", __func__,
  1684. amic_type_str(amics->mic2_type));
  1685. snd_soc_component_update_bits(component, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX,
  1686. amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ?
  1687. 0 : AB8500_ANAGAINX_ENSEMICX);
  1688. return 0;
  1689. }
  1690. static int ab8500_audio_set_ear_cmv(struct snd_soc_component *component,
  1691. enum ear_cm_voltage ear_cmv)
  1692. {
  1693. char *cmv_str;
  1694. switch (ear_cmv) {
  1695. case EAR_CMV_0_95V:
  1696. cmv_str = "0.95V";
  1697. break;
  1698. case EAR_CMV_1_10V:
  1699. cmv_str = "1.10V";
  1700. break;
  1701. case EAR_CMV_1_27V:
  1702. cmv_str = "1.27V";
  1703. break;
  1704. case EAR_CMV_1_58V:
  1705. cmv_str = "1.58V";
  1706. break;
  1707. default:
  1708. dev_err(component->dev,
  1709. "%s: Unknown earpiece CM-voltage (%d)!\n",
  1710. __func__, (int)ear_cmv);
  1711. return -EINVAL;
  1712. }
  1713. dev_dbg(component->dev, "%s: Earpiece CM-voltage: %s\n", __func__,
  1714. cmv_str);
  1715. snd_soc_component_update_bits(component, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM,
  1716. ear_cmv);
  1717. return 0;
  1718. }
  1719. static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai,
  1720. unsigned int delay)
  1721. {
  1722. unsigned int mask, val;
  1723. struct snd_soc_component *component = dai->component;
  1724. mask = BIT(AB8500_DIGIFCONF2_IF0DEL);
  1725. val = 0;
  1726. switch (delay) {
  1727. case 0:
  1728. break;
  1729. case 1:
  1730. val |= BIT(AB8500_DIGIFCONF2_IF0DEL);
  1731. break;
  1732. default:
  1733. dev_err(dai->component->dev,
  1734. "%s: ERROR: Unsupported bit-delay (0x%x)!\n",
  1735. __func__, delay);
  1736. return -EINVAL;
  1737. }
  1738. dev_dbg(dai->component->dev, "%s: IF0 Bit-delay: %d bits.\n",
  1739. __func__, delay);
  1740. snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
  1741. return 0;
  1742. }
  1743. /* Gates clocking according format mask */
  1744. static int ab8500_codec_set_dai_clock_gate(struct snd_soc_component *component,
  1745. unsigned int fmt)
  1746. {
  1747. unsigned int mask;
  1748. unsigned int val;
  1749. mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
  1750. BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
  1751. val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
  1752. switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
  1753. case SND_SOC_DAIFMT_CONT: /* continuous clock */
  1754. dev_dbg(component->dev, "%s: IF0 Clock is continuous.\n",
  1755. __func__);
  1756. val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
  1757. break;
  1758. case SND_SOC_DAIFMT_GATED: /* clock is gated */
  1759. dev_dbg(component->dev, "%s: IF0 Clock is gated.\n",
  1760. __func__);
  1761. break;
  1762. default:
  1763. dev_err(component->dev,
  1764. "%s: ERROR: Unsupported clock mask (0x%x)!\n",
  1765. __func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
  1766. return -EINVAL;
  1767. }
  1768. snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val);
  1769. return 0;
  1770. }
  1771. static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1772. {
  1773. unsigned int mask;
  1774. unsigned int val;
  1775. struct snd_soc_component *component = dai->component;
  1776. int status;
  1777. dev_dbg(component->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt);
  1778. mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
  1779. BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) |
  1780. BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) |
  1781. BIT(AB8500_DIGIFCONF3_IF0MASTER);
  1782. val = 0;
  1783. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1784. case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & FRM master */
  1785. dev_dbg(dai->component->dev,
  1786. "%s: IF0 Master-mode: AB8500 master.\n", __func__);
  1787. val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
  1788. break;
  1789. case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & FRM slave */
  1790. dev_dbg(dai->component->dev,
  1791. "%s: IF0 Master-mode: AB8500 slave.\n", __func__);
  1792. break;
  1793. case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slave & FRM master */
  1794. case SND_SOC_DAIFMT_CBM_CFS: /* codec clk master & frame slave */
  1795. dev_err(dai->component->dev,
  1796. "%s: ERROR: The device is either a master or a slave.\n",
  1797. __func__);
  1798. fallthrough;
  1799. default:
  1800. dev_err(dai->component->dev,
  1801. "%s: ERROR: Unsupporter master mask 0x%x\n",
  1802. __func__, fmt & SND_SOC_DAIFMT_MASTER_MASK);
  1803. return -EINVAL;
  1804. }
  1805. snd_soc_component_update_bits(component, AB8500_DIGIFCONF3, mask, val);
  1806. /* Set clock gating */
  1807. status = ab8500_codec_set_dai_clock_gate(component, fmt);
  1808. if (status) {
  1809. dev_err(dai->component->dev,
  1810. "%s: ERROR: Failed to set clock gate (%d).\n",
  1811. __func__, status);
  1812. return status;
  1813. }
  1814. /* Setting data transfer format */
  1815. mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
  1816. BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
  1817. BIT(AB8500_DIGIFCONF2_FSYNC0P) |
  1818. BIT(AB8500_DIGIFCONF2_BITCLK0P);
  1819. val = 0;
  1820. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1821. case SND_SOC_DAIFMT_I2S: /* I2S mode */
  1822. dev_dbg(dai->component->dev, "%s: IF0 Protocol: I2S\n", __func__);
  1823. val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1);
  1824. ab8500_audio_set_bit_delay(dai, 0);
  1825. break;
  1826. case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */
  1827. dev_dbg(dai->component->dev,
  1828. "%s: IF0 Protocol: DSP A (TDM)\n", __func__);
  1829. val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
  1830. ab8500_audio_set_bit_delay(dai, 1);
  1831. break;
  1832. case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */
  1833. dev_dbg(dai->component->dev,
  1834. "%s: IF0 Protocol: DSP B (TDM)\n", __func__);
  1835. val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
  1836. ab8500_audio_set_bit_delay(dai, 0);
  1837. break;
  1838. default:
  1839. dev_err(dai->component->dev,
  1840. "%s: ERROR: Unsupported format (0x%x)!\n",
  1841. __func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  1842. return -EINVAL;
  1843. }
  1844. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1845. case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
  1846. dev_dbg(dai->component->dev,
  1847. "%s: IF0: Normal bit clock, normal frame\n",
  1848. __func__);
  1849. break;
  1850. case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */
  1851. dev_dbg(dai->component->dev,
  1852. "%s: IF0: Normal bit clock, inverted frame\n",
  1853. __func__);
  1854. val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
  1855. break;
  1856. case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */
  1857. dev_dbg(dai->component->dev,
  1858. "%s: IF0: Inverted bit clock, normal frame\n",
  1859. __func__);
  1860. val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
  1861. break;
  1862. case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */
  1863. dev_dbg(dai->component->dev,
  1864. "%s: IF0: Inverted bit clock, inverted frame\n",
  1865. __func__);
  1866. val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
  1867. val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
  1868. break;
  1869. default:
  1870. dev_err(dai->component->dev,
  1871. "%s: ERROR: Unsupported INV mask 0x%x\n",
  1872. __func__, fmt & SND_SOC_DAIFMT_INV_MASK);
  1873. return -EINVAL;
  1874. }
  1875. snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
  1876. return 0;
  1877. }
  1878. static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
  1879. unsigned int tx_mask, unsigned int rx_mask,
  1880. int slots, int slot_width)
  1881. {
  1882. struct snd_soc_component *component = dai->component;
  1883. unsigned int val, mask, slot, slots_active;
  1884. mask = BIT(AB8500_DIGIFCONF2_IF0WL0) |
  1885. BIT(AB8500_DIGIFCONF2_IF0WL1);
  1886. val = 0;
  1887. switch (slot_width) {
  1888. case 16:
  1889. break;
  1890. case 20:
  1891. val |= BIT(AB8500_DIGIFCONF2_IF0WL0);
  1892. break;
  1893. case 24:
  1894. val |= BIT(AB8500_DIGIFCONF2_IF0WL1);
  1895. break;
  1896. case 32:
  1897. val |= BIT(AB8500_DIGIFCONF2_IF0WL1) |
  1898. BIT(AB8500_DIGIFCONF2_IF0WL0);
  1899. break;
  1900. default:
  1901. dev_err(dai->component->dev, "%s: Unsupported slot-width 0x%x\n",
  1902. __func__, slot_width);
  1903. return -EINVAL;
  1904. }
  1905. dev_dbg(dai->component->dev, "%s: IF0 slot-width: %d bits.\n",
  1906. __func__, slot_width);
  1907. snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
  1908. /* Setup TDM clocking according to slot count */
  1909. dev_dbg(dai->component->dev, "%s: Slots, total: %d\n", __func__, slots);
  1910. mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
  1911. BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
  1912. switch (slots) {
  1913. case 2:
  1914. val = AB8500_MASK_NONE;
  1915. break;
  1916. case 4:
  1917. val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0);
  1918. break;
  1919. case 8:
  1920. val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
  1921. break;
  1922. case 16:
  1923. val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
  1924. BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
  1925. break;
  1926. default:
  1927. dev_err(dai->component->dev,
  1928. "%s: ERROR: Unsupported number of slots (%d)!\n",
  1929. __func__, slots);
  1930. return -EINVAL;
  1931. }
  1932. snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val);
  1933. /* Setup TDM DA according to active tx slots */
  1934. if (tx_mask & ~0xff)
  1935. return -EINVAL;
  1936. mask = AB8500_DASLOTCONFX_SLTODAX_MASK;
  1937. tx_mask = tx_mask << AB8500_DA_DATA0_OFFSET;
  1938. slots_active = hweight32(tx_mask);
  1939. dev_dbg(dai->component->dev, "%s: Slots, active, TX: %d\n", __func__,
  1940. slots_active);
  1941. switch (slots_active) {
  1942. case 0:
  1943. break;
  1944. case 1:
  1945. slot = ffs(tx_mask);
  1946. snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot);
  1947. snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot);
  1948. snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot);
  1949. snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot);
  1950. break;
  1951. case 2:
  1952. slot = ffs(tx_mask);
  1953. snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot);
  1954. snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot);
  1955. slot = fls(tx_mask);
  1956. snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot);
  1957. snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot);
  1958. break;
  1959. case 8:
  1960. dev_dbg(dai->component->dev,
  1961. "%s: In 8-channel mode DA-from-slot mapping is set manually.",
  1962. __func__);
  1963. break;
  1964. default:
  1965. dev_err(dai->component->dev,
  1966. "%s: Unsupported number of active TX-slots (%d)!\n",
  1967. __func__, slots_active);
  1968. return -EINVAL;
  1969. }
  1970. /* Setup TDM AD according to active RX-slots */
  1971. if (rx_mask & ~0xff)
  1972. return -EINVAL;
  1973. rx_mask = rx_mask << AB8500_AD_DATA0_OFFSET;
  1974. slots_active = hweight32(rx_mask);
  1975. dev_dbg(dai->component->dev, "%s: Slots, active, RX: %d\n", __func__,
  1976. slots_active);
  1977. switch (slots_active) {
  1978. case 0:
  1979. break;
  1980. case 1:
  1981. slot = ffs(rx_mask);
  1982. snd_soc_component_update_bits(component, AB8500_ADSLOTSEL(slot),
  1983. AB8500_MASK_SLOT(slot),
  1984. AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
  1985. break;
  1986. case 2:
  1987. slot = ffs(rx_mask);
  1988. snd_soc_component_update_bits(component,
  1989. AB8500_ADSLOTSEL(slot),
  1990. AB8500_MASK_SLOT(slot),
  1991. AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
  1992. slot = fls(rx_mask);
  1993. snd_soc_component_update_bits(component,
  1994. AB8500_ADSLOTSEL(slot),
  1995. AB8500_MASK_SLOT(slot),
  1996. AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2, slot));
  1997. break;
  1998. case 8:
  1999. dev_dbg(dai->component->dev,
  2000. "%s: In 8-channel mode AD-to-slot mapping is set manually.",
  2001. __func__);
  2002. break;
  2003. default:
  2004. dev_err(dai->component->dev,
  2005. "%s: Unsupported number of active RX-slots (%d)!\n",
  2006. __func__, slots_active);
  2007. return -EINVAL;
  2008. }
  2009. return 0;
  2010. }
  2011. static const struct snd_soc_dai_ops ab8500_codec_ops = {
  2012. .set_fmt = ab8500_codec_set_dai_fmt,
  2013. .set_tdm_slot = ab8500_codec_set_dai_tdm_slot,
  2014. };
  2015. static struct snd_soc_dai_driver ab8500_codec_dai[] = {
  2016. {
  2017. .name = "ab8500-codec-dai.0",
  2018. .id = 0,
  2019. .playback = {
  2020. .stream_name = "ab8500_0p",
  2021. .channels_min = 1,
  2022. .channels_max = 8,
  2023. .rates = AB8500_SUPPORTED_RATE,
  2024. .formats = AB8500_SUPPORTED_FMT,
  2025. },
  2026. .ops = &ab8500_codec_ops,
  2027. .symmetric_rates = 1
  2028. },
  2029. {
  2030. .name = "ab8500-codec-dai.1",
  2031. .id = 1,
  2032. .capture = {
  2033. .stream_name = "ab8500_0c",
  2034. .channels_min = 1,
  2035. .channels_max = 8,
  2036. .rates = AB8500_SUPPORTED_RATE,
  2037. .formats = AB8500_SUPPORTED_FMT,
  2038. },
  2039. .ops = &ab8500_codec_ops,
  2040. .symmetric_rates = 1
  2041. }
  2042. };
  2043. static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
  2044. struct ab8500_codec_platform_data *codec)
  2045. {
  2046. u32 value;
  2047. if (of_property_read_bool(np, "stericsson,amic1-type-single-ended"))
  2048. codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
  2049. else
  2050. codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
  2051. if (of_property_read_bool(np, "stericsson,amic2-type-single-ended"))
  2052. codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
  2053. else
  2054. codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
  2055. /* Has a non-standard Vamic been requested? */
  2056. if (of_property_read_bool(np, "stericsson,amic1a-bias-vamic2"))
  2057. codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
  2058. else
  2059. codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
  2060. if (of_property_read_bool(np, "stericsson,amic1b-bias-vamic2"))
  2061. codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
  2062. else
  2063. codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
  2064. if (of_property_read_bool(np, "stericsson,amic2-bias-vamic1"))
  2065. codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
  2066. else
  2067. codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
  2068. if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
  2069. switch (value) {
  2070. case 950 :
  2071. codec->ear_cmv = EAR_CMV_0_95V;
  2072. break;
  2073. case 1100 :
  2074. codec->ear_cmv = EAR_CMV_1_10V;
  2075. break;
  2076. case 1270 :
  2077. codec->ear_cmv = EAR_CMV_1_27V;
  2078. break;
  2079. case 1580 :
  2080. codec->ear_cmv = EAR_CMV_1_58V;
  2081. break;
  2082. default :
  2083. codec->ear_cmv = EAR_CMV_UNKNOWN;
  2084. dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
  2085. }
  2086. } else {
  2087. dev_warn(dev, "No earpiece voltage found in DT - using default\n");
  2088. codec->ear_cmv = EAR_CMV_0_95V;
  2089. }
  2090. }
  2091. static int ab8500_codec_probe(struct snd_soc_component *component)
  2092. {
  2093. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  2094. struct device *dev = component->dev;
  2095. struct device_node *np = dev->of_node;
  2096. struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
  2097. struct ab8500_codec_platform_data codec_pdata;
  2098. struct filter_control *fc;
  2099. int status;
  2100. dev_dbg(dev, "%s: Enter.\n", __func__);
  2101. ab8500_codec_of_probe(dev, np, &codec_pdata);
  2102. status = ab8500_audio_setup_mics(component, &codec_pdata.amics);
  2103. if (status < 0) {
  2104. pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
  2105. return status;
  2106. }
  2107. status = ab8500_audio_set_ear_cmv(component, codec_pdata.ear_cmv);
  2108. if (status < 0) {
  2109. pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n",
  2110. __func__, status);
  2111. return status;
  2112. }
  2113. status = ab8500_audio_init_audioblock(component);
  2114. if (status < 0) {
  2115. dev_err(dev, "%s: failed to init audio-block (%d)!\n",
  2116. __func__, status);
  2117. return status;
  2118. }
  2119. /* Override HW-defaults */
  2120. snd_soc_component_write(component, AB8500_ANACONF5,
  2121. BIT(AB8500_ANACONF5_HSAUTOEN));
  2122. snd_soc_component_write(component, AB8500_SHORTCIRCONF,
  2123. BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
  2124. /* Add filter controls */
  2125. status = snd_soc_add_component_controls(component, ab8500_filter_controls,
  2126. ARRAY_SIZE(ab8500_filter_controls));
  2127. if (status < 0) {
  2128. dev_err(dev,
  2129. "%s: failed to add ab8500 filter controls (%d).\n",
  2130. __func__, status);
  2131. return status;
  2132. }
  2133. fc = (struct filter_control *)
  2134. &ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value;
  2135. drvdata->anc_fir_values = (long *)fc->value;
  2136. fc = (struct filter_control *)
  2137. &ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value;
  2138. drvdata->anc_iir_values = (long *)fc->value;
  2139. fc = (struct filter_control *)
  2140. &ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value;
  2141. drvdata->sid_fir_values = (long *)fc->value;
  2142. snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
  2143. mutex_init(&drvdata->ctrl_lock);
  2144. return status;
  2145. }
  2146. static const struct snd_soc_component_driver ab8500_component_driver = {
  2147. .probe = ab8500_codec_probe,
  2148. .controls = ab8500_ctrls,
  2149. .num_controls = ARRAY_SIZE(ab8500_ctrls),
  2150. .dapm_widgets = ab8500_dapm_widgets,
  2151. .num_dapm_widgets = ARRAY_SIZE(ab8500_dapm_widgets),
  2152. .dapm_routes = ab8500_dapm_routes,
  2153. .num_dapm_routes = ARRAY_SIZE(ab8500_dapm_routes),
  2154. .idle_bias_on = 1,
  2155. .use_pmdown_time = 1,
  2156. .endianness = 1,
  2157. .non_legacy_dai_naming = 1,
  2158. };
  2159. static int ab8500_codec_driver_probe(struct platform_device *pdev)
  2160. {
  2161. int status;
  2162. struct ab8500_codec_drvdata *drvdata;
  2163. dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
  2164. /* Create driver private-data struct */
  2165. drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata),
  2166. GFP_KERNEL);
  2167. if (!drvdata)
  2168. return -ENOMEM;
  2169. drvdata->sid_status = SID_UNCONFIGURED;
  2170. drvdata->anc_status = ANC_UNCONFIGURED;
  2171. dev_set_drvdata(&pdev->dev, drvdata);
  2172. drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev,
  2173. &ab8500_codec_regmap);
  2174. if (IS_ERR(drvdata->regmap)) {
  2175. status = PTR_ERR(drvdata->regmap);
  2176. dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
  2177. __func__, status);
  2178. return status;
  2179. }
  2180. dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__);
  2181. status = devm_snd_soc_register_component(&pdev->dev,
  2182. &ab8500_component_driver,
  2183. ab8500_codec_dai,
  2184. ARRAY_SIZE(ab8500_codec_dai));
  2185. if (status < 0)
  2186. dev_err(&pdev->dev,
  2187. "%s: Error: Failed to register codec (%d).\n",
  2188. __func__, status);
  2189. return status;
  2190. }
  2191. static struct platform_driver ab8500_codec_platform_driver = {
  2192. .driver = {
  2193. .name = "ab8500-codec",
  2194. },
  2195. .probe = ab8500_codec_driver_probe,
  2196. };
  2197. module_platform_driver(ab8500_codec_platform_driver);
  2198. MODULE_LICENSE("GPL v2");