rme32.c 56 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
  4. *
  5. * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
  6. * Pilo Chambert <pilo.c@wanadoo.fr>
  7. *
  8. * Thanks to : Anders Torger <torger@ludd.luth.se>,
  9. * Henk Hesselink <henk@anda.nl>
  10. * for writing the digi96-driver
  11. * and RME for all informations.
  12. *
  13. * ****************************************************************************
  14. *
  15. * Note #1 "Sek'd models" ................................... martin 2002-12-07
  16. *
  17. * Identical soundcards by Sek'd were labeled:
  18. * RME Digi 32 = Sek'd Prodif 32
  19. * RME Digi 32 Pro = Sek'd Prodif 96
  20. * RME Digi 32/8 = Sek'd Prodif Gold
  21. *
  22. * ****************************************************************************
  23. *
  24. * Note #2 "full duplex mode" ............................... martin 2002-12-07
  25. *
  26. * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
  27. * in this mode. Rec data and play data are using the same buffer therefore. At
  28. * first you have got the playing bits in the buffer and then (after playing
  29. * them) they were overwitten by the captured sound of the CS8412/14. Both
  30. * modes (play/record) are running harmonically hand in hand in the same buffer
  31. * and you have only one start bit plus one interrupt bit to control this
  32. * paired action.
  33. * This is opposite to the latter rme96 where playing and capturing is totally
  34. * separated and so their full duplex mode is supported by alsa (using two
  35. * start bits and two interrupts for two different buffers).
  36. * But due to the wrong sequence of playing and capturing ALSA shows no solved
  37. * full duplex support for the rme32 at the moment. That's bad, but I'm not
  38. * able to solve it. Are you motivated enough to solve this problem now? Your
  39. * patch would be welcome!
  40. *
  41. * ****************************************************************************
  42. *
  43. * "The story after the long seeking" -- tiwai
  44. *
  45. * Ok, the situation regarding the full duplex is now improved a bit.
  46. * In the fullduplex mode (given by the module parameter), the hardware buffer
  47. * is split to halves for read and write directions at the DMA pointer.
  48. * That is, the half above the current DMA pointer is used for write, and
  49. * the half below is used for read. To mangle this strange behavior, an
  50. * software intermediate buffer is introduced. This is, of course, not good
  51. * from the viewpoint of the data transfer efficiency. However, this allows
  52. * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
  53. *
  54. * ****************************************************************************
  55. */
  56. #include <linux/delay.h>
  57. #include <linux/gfp.h>
  58. #include <linux/init.h>
  59. #include <linux/interrupt.h>
  60. #include <linux/pci.h>
  61. #include <linux/module.h>
  62. #include <linux/io.h>
  63. #include <sound/core.h>
  64. #include <sound/info.h>
  65. #include <sound/control.h>
  66. #include <sound/pcm.h>
  67. #include <sound/pcm_params.h>
  68. #include <sound/pcm-indirect.h>
  69. #include <sound/asoundef.h>
  70. #include <sound/initval.h>
  71. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  72. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  73. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  74. static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
  75. module_param_array(index, int, NULL, 0444);
  76. MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
  77. module_param_array(id, charp, NULL, 0444);
  78. MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
  79. module_param_array(enable, bool, NULL, 0444);
  80. MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
  81. module_param_array(fullduplex, bool, NULL, 0444);
  82. MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
  83. MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
  84. MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
  85. MODULE_LICENSE("GPL");
  86. MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
  87. /* Defines for RME Digi32 series */
  88. #define RME32_SPDIF_NCHANNELS 2
  89. /* Playback and capture buffer size */
  90. #define RME32_BUFFER_SIZE 0x20000
  91. /* IO area size */
  92. #define RME32_IO_SIZE 0x30000
  93. /* IO area offsets */
  94. #define RME32_IO_DATA_BUFFER 0x0
  95. #define RME32_IO_CONTROL_REGISTER 0x20000
  96. #define RME32_IO_GET_POS 0x20000
  97. #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
  98. #define RME32_IO_RESET_POS 0x20100
  99. /* Write control register bits */
  100. #define RME32_WCR_START (1 << 0) /* startbit */
  101. #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
  102. Setting the whole card to mono
  103. doesn't seem to be very useful.
  104. A software-solution can handle
  105. full-duplex with one direction in
  106. stereo and the other way in mono.
  107. So, the hardware should work all
  108. the time in stereo! */
  109. #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
  110. #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
  111. #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
  112. #define RME32_WCR_FREQ_1 (1 << 5)
  113. #define RME32_WCR_INP_0 (1 << 6) /* input switch */
  114. #define RME32_WCR_INP_1 (1 << 7)
  115. #define RME32_WCR_RESET (1 << 8) /* Reset address */
  116. #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
  117. #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
  118. #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
  119. #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
  120. #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
  121. #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
  122. #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
  123. #define RME32_WCR_BITPOS_FREQ_0 4
  124. #define RME32_WCR_BITPOS_FREQ_1 5
  125. #define RME32_WCR_BITPOS_INP_0 6
  126. #define RME32_WCR_BITPOS_INP_1 7
  127. /* Read control register bits */
  128. #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
  129. #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
  130. #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
  131. #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
  132. #define RME32_RCR_FREQ_1 (1 << 28)
  133. #define RME32_RCR_FREQ_2 (1 << 29)
  134. #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
  135. #define RME32_RCR_IRQ (1 << 31) /* interrupt */
  136. #define RME32_RCR_BITPOS_F0 27
  137. #define RME32_RCR_BITPOS_F1 28
  138. #define RME32_RCR_BITPOS_F2 29
  139. /* Input types */
  140. #define RME32_INPUT_OPTICAL 0
  141. #define RME32_INPUT_COAXIAL 1
  142. #define RME32_INPUT_INTERNAL 2
  143. #define RME32_INPUT_XLR 3
  144. /* Clock modes */
  145. #define RME32_CLOCKMODE_SLAVE 0
  146. #define RME32_CLOCKMODE_MASTER_32 1
  147. #define RME32_CLOCKMODE_MASTER_44 2
  148. #define RME32_CLOCKMODE_MASTER_48 3
  149. /* Block sizes in bytes */
  150. #define RME32_BLOCK_SIZE 8192
  151. /* Software intermediate buffer (max) size */
  152. #define RME32_MID_BUFFER_SIZE (1024*1024)
  153. /* Hardware revisions */
  154. #define RME32_32_REVISION 192
  155. #define RME32_328_REVISION_OLD 100
  156. #define RME32_328_REVISION_NEW 101
  157. #define RME32_PRO_REVISION_WITH_8412 192
  158. #define RME32_PRO_REVISION_WITH_8414 150
  159. struct rme32 {
  160. spinlock_t lock;
  161. int irq;
  162. unsigned long port;
  163. void __iomem *iobase;
  164. u32 wcreg; /* cached write control register value */
  165. u32 wcreg_spdif; /* S/PDIF setup */
  166. u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
  167. u32 rcreg; /* cached read control register value */
  168. u8 rev; /* card revision number */
  169. struct snd_pcm_substream *playback_substream;
  170. struct snd_pcm_substream *capture_substream;
  171. int playback_frlog; /* log2 of framesize */
  172. int capture_frlog;
  173. size_t playback_periodsize; /* in bytes, zero if not used */
  174. size_t capture_periodsize; /* in bytes, zero if not used */
  175. unsigned int fullduplex_mode;
  176. int running;
  177. struct snd_pcm_indirect playback_pcm;
  178. struct snd_pcm_indirect capture_pcm;
  179. struct snd_card *card;
  180. struct snd_pcm *spdif_pcm;
  181. struct snd_pcm *adat_pcm;
  182. struct pci_dev *pci;
  183. struct snd_kcontrol *spdif_ctl;
  184. };
  185. static const struct pci_device_id snd_rme32_ids[] = {
  186. {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,},
  187. {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,},
  188. {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,},
  189. {0,}
  190. };
  191. MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
  192. #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
  193. #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
  194. static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
  195. static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
  196. static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
  197. static void snd_rme32_proc_init(struct rme32 * rme32);
  198. static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
  199. static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
  200. {
  201. return (readl(rme32->iobase + RME32_IO_GET_POS)
  202. & RME32_RCR_AUDIO_ADDR_MASK);
  203. }
  204. /* silence callback for halfduplex mode */
  205. static int snd_rme32_playback_silence(struct snd_pcm_substream *substream,
  206. int channel, unsigned long pos,
  207. unsigned long count)
  208. {
  209. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  210. memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
  211. return 0;
  212. }
  213. /* copy callback for halfduplex mode */
  214. static int snd_rme32_playback_copy(struct snd_pcm_substream *substream,
  215. int channel, unsigned long pos,
  216. void __user *src, unsigned long count)
  217. {
  218. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  219. if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
  220. src, count))
  221. return -EFAULT;
  222. return 0;
  223. }
  224. static int snd_rme32_playback_copy_kernel(struct snd_pcm_substream *substream,
  225. int channel, unsigned long pos,
  226. void *src, unsigned long count)
  227. {
  228. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  229. memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, src, count);
  230. return 0;
  231. }
  232. /* copy callback for halfduplex mode */
  233. static int snd_rme32_capture_copy(struct snd_pcm_substream *substream,
  234. int channel, unsigned long pos,
  235. void __user *dst, unsigned long count)
  236. {
  237. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  238. if (copy_to_user_fromio(dst,
  239. rme32->iobase + RME32_IO_DATA_BUFFER + pos,
  240. count))
  241. return -EFAULT;
  242. return 0;
  243. }
  244. static int snd_rme32_capture_copy_kernel(struct snd_pcm_substream *substream,
  245. int channel, unsigned long pos,
  246. void *dst, unsigned long count)
  247. {
  248. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  249. memcpy_fromio(dst, rme32->iobase + RME32_IO_DATA_BUFFER + pos, count);
  250. return 0;
  251. }
  252. /*
  253. * SPDIF I/O capabilities (half-duplex mode)
  254. */
  255. static const struct snd_pcm_hardware snd_rme32_spdif_info = {
  256. .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
  257. SNDRV_PCM_INFO_MMAP_VALID |
  258. SNDRV_PCM_INFO_INTERLEAVED |
  259. SNDRV_PCM_INFO_PAUSE |
  260. SNDRV_PCM_INFO_SYNC_START |
  261. SNDRV_PCM_INFO_SYNC_APPLPTR),
  262. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  263. SNDRV_PCM_FMTBIT_S32_LE),
  264. .rates = (SNDRV_PCM_RATE_32000 |
  265. SNDRV_PCM_RATE_44100 |
  266. SNDRV_PCM_RATE_48000),
  267. .rate_min = 32000,
  268. .rate_max = 48000,
  269. .channels_min = 2,
  270. .channels_max = 2,
  271. .buffer_bytes_max = RME32_BUFFER_SIZE,
  272. .period_bytes_min = RME32_BLOCK_SIZE,
  273. .period_bytes_max = RME32_BLOCK_SIZE,
  274. .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  275. .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  276. .fifo_size = 0,
  277. };
  278. /*
  279. * ADAT I/O capabilities (half-duplex mode)
  280. */
  281. static const struct snd_pcm_hardware snd_rme32_adat_info =
  282. {
  283. .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
  284. SNDRV_PCM_INFO_MMAP_VALID |
  285. SNDRV_PCM_INFO_INTERLEAVED |
  286. SNDRV_PCM_INFO_PAUSE |
  287. SNDRV_PCM_INFO_SYNC_START |
  288. SNDRV_PCM_INFO_SYNC_APPLPTR),
  289. .formats= SNDRV_PCM_FMTBIT_S16_LE,
  290. .rates = (SNDRV_PCM_RATE_44100 |
  291. SNDRV_PCM_RATE_48000),
  292. .rate_min = 44100,
  293. .rate_max = 48000,
  294. .channels_min = 8,
  295. .channels_max = 8,
  296. .buffer_bytes_max = RME32_BUFFER_SIZE,
  297. .period_bytes_min = RME32_BLOCK_SIZE,
  298. .period_bytes_max = RME32_BLOCK_SIZE,
  299. .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  300. .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  301. .fifo_size = 0,
  302. };
  303. /*
  304. * SPDIF I/O capabilities (full-duplex mode)
  305. */
  306. static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
  307. .info = (SNDRV_PCM_INFO_MMAP |
  308. SNDRV_PCM_INFO_MMAP_VALID |
  309. SNDRV_PCM_INFO_INTERLEAVED |
  310. SNDRV_PCM_INFO_PAUSE |
  311. SNDRV_PCM_INFO_SYNC_START |
  312. SNDRV_PCM_INFO_SYNC_APPLPTR),
  313. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  314. SNDRV_PCM_FMTBIT_S32_LE),
  315. .rates = (SNDRV_PCM_RATE_32000 |
  316. SNDRV_PCM_RATE_44100 |
  317. SNDRV_PCM_RATE_48000),
  318. .rate_min = 32000,
  319. .rate_max = 48000,
  320. .channels_min = 2,
  321. .channels_max = 2,
  322. .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
  323. .period_bytes_min = RME32_BLOCK_SIZE,
  324. .period_bytes_max = RME32_BLOCK_SIZE,
  325. .periods_min = 2,
  326. .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
  327. .fifo_size = 0,
  328. };
  329. /*
  330. * ADAT I/O capabilities (full-duplex mode)
  331. */
  332. static const struct snd_pcm_hardware snd_rme32_adat_fd_info =
  333. {
  334. .info = (SNDRV_PCM_INFO_MMAP |
  335. SNDRV_PCM_INFO_MMAP_VALID |
  336. SNDRV_PCM_INFO_INTERLEAVED |
  337. SNDRV_PCM_INFO_PAUSE |
  338. SNDRV_PCM_INFO_SYNC_START |
  339. SNDRV_PCM_INFO_SYNC_APPLPTR),
  340. .formats= SNDRV_PCM_FMTBIT_S16_LE,
  341. .rates = (SNDRV_PCM_RATE_44100 |
  342. SNDRV_PCM_RATE_48000),
  343. .rate_min = 44100,
  344. .rate_max = 48000,
  345. .channels_min = 8,
  346. .channels_max = 8,
  347. .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
  348. .period_bytes_min = RME32_BLOCK_SIZE,
  349. .period_bytes_max = RME32_BLOCK_SIZE,
  350. .periods_min = 2,
  351. .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
  352. .fifo_size = 0,
  353. };
  354. static void snd_rme32_reset_dac(struct rme32 *rme32)
  355. {
  356. writel(rme32->wcreg | RME32_WCR_PD,
  357. rme32->iobase + RME32_IO_CONTROL_REGISTER);
  358. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  359. }
  360. static int snd_rme32_playback_getrate(struct rme32 * rme32)
  361. {
  362. int rate;
  363. rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
  364. (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
  365. switch (rate) {
  366. case 1:
  367. rate = 32000;
  368. break;
  369. case 2:
  370. rate = 44100;
  371. break;
  372. case 3:
  373. rate = 48000;
  374. break;
  375. default:
  376. return -1;
  377. }
  378. return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
  379. }
  380. static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
  381. {
  382. int n;
  383. *is_adat = 0;
  384. if (rme32->rcreg & RME32_RCR_LOCK) {
  385. /* ADAT rate */
  386. *is_adat = 1;
  387. }
  388. if (rme32->rcreg & RME32_RCR_ERF) {
  389. return -1;
  390. }
  391. /* S/PDIF rate */
  392. n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
  393. (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
  394. (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
  395. if (RME32_PRO_WITH_8414(rme32))
  396. switch (n) { /* supporting the CS8414 */
  397. case 0:
  398. case 1:
  399. case 2:
  400. return -1;
  401. case 3:
  402. return 96000;
  403. case 4:
  404. return 88200;
  405. case 5:
  406. return 48000;
  407. case 6:
  408. return 44100;
  409. case 7:
  410. return 32000;
  411. default:
  412. return -1;
  413. break;
  414. }
  415. else
  416. switch (n) { /* supporting the CS8412 */
  417. case 0:
  418. return -1;
  419. case 1:
  420. return 48000;
  421. case 2:
  422. return 44100;
  423. case 3:
  424. return 32000;
  425. case 4:
  426. return 48000;
  427. case 5:
  428. return 44100;
  429. case 6:
  430. return 44056;
  431. case 7:
  432. return 32000;
  433. default:
  434. break;
  435. }
  436. return -1;
  437. }
  438. static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
  439. {
  440. int ds;
  441. ds = rme32->wcreg & RME32_WCR_DS_BM;
  442. switch (rate) {
  443. case 32000:
  444. rme32->wcreg &= ~RME32_WCR_DS_BM;
  445. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
  446. ~RME32_WCR_FREQ_1;
  447. break;
  448. case 44100:
  449. rme32->wcreg &= ~RME32_WCR_DS_BM;
  450. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
  451. ~RME32_WCR_FREQ_0;
  452. break;
  453. case 48000:
  454. rme32->wcreg &= ~RME32_WCR_DS_BM;
  455. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
  456. RME32_WCR_FREQ_1;
  457. break;
  458. case 64000:
  459. if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
  460. return -EINVAL;
  461. rme32->wcreg |= RME32_WCR_DS_BM;
  462. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
  463. ~RME32_WCR_FREQ_1;
  464. break;
  465. case 88200:
  466. if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
  467. return -EINVAL;
  468. rme32->wcreg |= RME32_WCR_DS_BM;
  469. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
  470. ~RME32_WCR_FREQ_0;
  471. break;
  472. case 96000:
  473. if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
  474. return -EINVAL;
  475. rme32->wcreg |= RME32_WCR_DS_BM;
  476. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
  477. RME32_WCR_FREQ_1;
  478. break;
  479. default:
  480. return -EINVAL;
  481. }
  482. if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
  483. (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
  484. {
  485. /* change to/from double-speed: reset the DAC (if available) */
  486. snd_rme32_reset_dac(rme32);
  487. } else {
  488. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  489. }
  490. return 0;
  491. }
  492. static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
  493. {
  494. switch (mode) {
  495. case RME32_CLOCKMODE_SLAVE:
  496. /* AutoSync */
  497. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
  498. ~RME32_WCR_FREQ_1;
  499. break;
  500. case RME32_CLOCKMODE_MASTER_32:
  501. /* Internal 32.0kHz */
  502. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
  503. ~RME32_WCR_FREQ_1;
  504. break;
  505. case RME32_CLOCKMODE_MASTER_44:
  506. /* Internal 44.1kHz */
  507. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
  508. RME32_WCR_FREQ_1;
  509. break;
  510. case RME32_CLOCKMODE_MASTER_48:
  511. /* Internal 48.0kHz */
  512. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
  513. RME32_WCR_FREQ_1;
  514. break;
  515. default:
  516. return -EINVAL;
  517. }
  518. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  519. return 0;
  520. }
  521. static int snd_rme32_getclockmode(struct rme32 * rme32)
  522. {
  523. return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
  524. (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
  525. }
  526. static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
  527. {
  528. switch (type) {
  529. case RME32_INPUT_OPTICAL:
  530. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
  531. ~RME32_WCR_INP_1;
  532. break;
  533. case RME32_INPUT_COAXIAL:
  534. rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
  535. ~RME32_WCR_INP_1;
  536. break;
  537. case RME32_INPUT_INTERNAL:
  538. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
  539. RME32_WCR_INP_1;
  540. break;
  541. case RME32_INPUT_XLR:
  542. rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
  543. RME32_WCR_INP_1;
  544. break;
  545. default:
  546. return -EINVAL;
  547. }
  548. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  549. return 0;
  550. }
  551. static int snd_rme32_getinputtype(struct rme32 * rme32)
  552. {
  553. return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
  554. (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
  555. }
  556. static void
  557. snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
  558. {
  559. int frlog;
  560. if (n_channels == 2) {
  561. frlog = 1;
  562. } else {
  563. /* assume 8 channels */
  564. frlog = 3;
  565. }
  566. if (is_playback) {
  567. frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
  568. rme32->playback_frlog = frlog;
  569. } else {
  570. frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
  571. rme32->capture_frlog = frlog;
  572. }
  573. }
  574. static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format)
  575. {
  576. switch (format) {
  577. case SNDRV_PCM_FORMAT_S16_LE:
  578. rme32->wcreg &= ~RME32_WCR_MODE24;
  579. break;
  580. case SNDRV_PCM_FORMAT_S32_LE:
  581. rme32->wcreg |= RME32_WCR_MODE24;
  582. break;
  583. default:
  584. return -EINVAL;
  585. }
  586. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  587. return 0;
  588. }
  589. static int
  590. snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
  591. struct snd_pcm_hw_params *params)
  592. {
  593. int err, rate, dummy;
  594. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  595. struct snd_pcm_runtime *runtime = substream->runtime;
  596. if (!rme32->fullduplex_mode) {
  597. runtime->dma_area = (void __force *)(rme32->iobase +
  598. RME32_IO_DATA_BUFFER);
  599. runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
  600. runtime->dma_bytes = RME32_BUFFER_SIZE;
  601. }
  602. spin_lock_irq(&rme32->lock);
  603. if ((rme32->rcreg & RME32_RCR_KMODE) &&
  604. (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
  605. /* AutoSync */
  606. if ((int)params_rate(params) != rate) {
  607. spin_unlock_irq(&rme32->lock);
  608. return -EIO;
  609. }
  610. } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
  611. spin_unlock_irq(&rme32->lock);
  612. return err;
  613. }
  614. if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
  615. spin_unlock_irq(&rme32->lock);
  616. return err;
  617. }
  618. snd_rme32_setframelog(rme32, params_channels(params), 1);
  619. if (rme32->capture_periodsize != 0) {
  620. if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
  621. spin_unlock_irq(&rme32->lock);
  622. return -EBUSY;
  623. }
  624. }
  625. rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
  626. /* S/PDIF setup */
  627. if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
  628. rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
  629. rme32->wcreg |= rme32->wcreg_spdif_stream;
  630. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  631. }
  632. spin_unlock_irq(&rme32->lock);
  633. return 0;
  634. }
  635. static int
  636. snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
  637. struct snd_pcm_hw_params *params)
  638. {
  639. int err, isadat, rate;
  640. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  641. struct snd_pcm_runtime *runtime = substream->runtime;
  642. if (!rme32->fullduplex_mode) {
  643. runtime->dma_area = (void __force *)rme32->iobase +
  644. RME32_IO_DATA_BUFFER;
  645. runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
  646. runtime->dma_bytes = RME32_BUFFER_SIZE;
  647. }
  648. spin_lock_irq(&rme32->lock);
  649. /* enable AutoSync for record-preparing */
  650. rme32->wcreg |= RME32_WCR_AUTOSYNC;
  651. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  652. if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
  653. spin_unlock_irq(&rme32->lock);
  654. return err;
  655. }
  656. if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
  657. spin_unlock_irq(&rme32->lock);
  658. return err;
  659. }
  660. if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
  661. if ((int)params_rate(params) != rate) {
  662. spin_unlock_irq(&rme32->lock);
  663. return -EIO;
  664. }
  665. if ((isadat && runtime->hw.channels_min == 2) ||
  666. (!isadat && runtime->hw.channels_min == 8)) {
  667. spin_unlock_irq(&rme32->lock);
  668. return -EIO;
  669. }
  670. }
  671. /* AutoSync off for recording */
  672. rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
  673. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  674. snd_rme32_setframelog(rme32, params_channels(params), 0);
  675. if (rme32->playback_periodsize != 0) {
  676. if (params_period_size(params) << rme32->capture_frlog !=
  677. rme32->playback_periodsize) {
  678. spin_unlock_irq(&rme32->lock);
  679. return -EBUSY;
  680. }
  681. }
  682. rme32->capture_periodsize =
  683. params_period_size(params) << rme32->capture_frlog;
  684. spin_unlock_irq(&rme32->lock);
  685. return 0;
  686. }
  687. static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
  688. {
  689. if (!from_pause) {
  690. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  691. }
  692. rme32->wcreg |= RME32_WCR_START;
  693. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  694. }
  695. static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
  696. {
  697. /*
  698. * Check if there is an unconfirmed IRQ, if so confirm it, or else
  699. * the hardware will not stop generating interrupts
  700. */
  701. rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
  702. if (rme32->rcreg & RME32_RCR_IRQ) {
  703. writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
  704. }
  705. rme32->wcreg &= ~RME32_WCR_START;
  706. if (rme32->wcreg & RME32_WCR_SEL)
  707. rme32->wcreg |= RME32_WCR_MUTE;
  708. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  709. if (! to_pause)
  710. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  711. }
  712. static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
  713. {
  714. struct rme32 *rme32 = (struct rme32 *) dev_id;
  715. rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
  716. if (!(rme32->rcreg & RME32_RCR_IRQ)) {
  717. return IRQ_NONE;
  718. } else {
  719. if (rme32->capture_substream) {
  720. snd_pcm_period_elapsed(rme32->capture_substream);
  721. }
  722. if (rme32->playback_substream) {
  723. snd_pcm_period_elapsed(rme32->playback_substream);
  724. }
  725. writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
  726. }
  727. return IRQ_HANDLED;
  728. }
  729. static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
  730. static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
  731. .count = ARRAY_SIZE(period_bytes),
  732. .list = period_bytes,
  733. .mask = 0
  734. };
  735. static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
  736. {
  737. if (! rme32->fullduplex_mode) {
  738. snd_pcm_hw_constraint_single(runtime,
  739. SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  740. RME32_BUFFER_SIZE);
  741. snd_pcm_hw_constraint_list(runtime, 0,
  742. SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  743. &hw_constraints_period_bytes);
  744. }
  745. }
  746. static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
  747. {
  748. int rate, dummy;
  749. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  750. struct snd_pcm_runtime *runtime = substream->runtime;
  751. snd_pcm_set_sync(substream);
  752. spin_lock_irq(&rme32->lock);
  753. if (rme32->playback_substream != NULL) {
  754. spin_unlock_irq(&rme32->lock);
  755. return -EBUSY;
  756. }
  757. rme32->wcreg &= ~RME32_WCR_ADAT;
  758. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  759. rme32->playback_substream = substream;
  760. spin_unlock_irq(&rme32->lock);
  761. if (rme32->fullduplex_mode)
  762. runtime->hw = snd_rme32_spdif_fd_info;
  763. else
  764. runtime->hw = snd_rme32_spdif_info;
  765. if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
  766. runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
  767. runtime->hw.rate_max = 96000;
  768. }
  769. if ((rme32->rcreg & RME32_RCR_KMODE) &&
  770. (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
  771. /* AutoSync */
  772. runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
  773. runtime->hw.rate_min = rate;
  774. runtime->hw.rate_max = rate;
  775. }
  776. snd_rme32_set_buffer_constraint(rme32, runtime);
  777. rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
  778. rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  779. snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
  780. SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
  781. return 0;
  782. }
  783. static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
  784. {
  785. int isadat, rate;
  786. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  787. struct snd_pcm_runtime *runtime = substream->runtime;
  788. snd_pcm_set_sync(substream);
  789. spin_lock_irq(&rme32->lock);
  790. if (rme32->capture_substream != NULL) {
  791. spin_unlock_irq(&rme32->lock);
  792. return -EBUSY;
  793. }
  794. rme32->capture_substream = substream;
  795. spin_unlock_irq(&rme32->lock);
  796. if (rme32->fullduplex_mode)
  797. runtime->hw = snd_rme32_spdif_fd_info;
  798. else
  799. runtime->hw = snd_rme32_spdif_info;
  800. if (RME32_PRO_WITH_8414(rme32)) {
  801. runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
  802. runtime->hw.rate_max = 96000;
  803. }
  804. if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
  805. if (isadat) {
  806. return -EIO;
  807. }
  808. runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
  809. runtime->hw.rate_min = rate;
  810. runtime->hw.rate_max = rate;
  811. }
  812. snd_rme32_set_buffer_constraint(rme32, runtime);
  813. return 0;
  814. }
  815. static int
  816. snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
  817. {
  818. int rate, dummy;
  819. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  820. struct snd_pcm_runtime *runtime = substream->runtime;
  821. snd_pcm_set_sync(substream);
  822. spin_lock_irq(&rme32->lock);
  823. if (rme32->playback_substream != NULL) {
  824. spin_unlock_irq(&rme32->lock);
  825. return -EBUSY;
  826. }
  827. rme32->wcreg |= RME32_WCR_ADAT;
  828. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  829. rme32->playback_substream = substream;
  830. spin_unlock_irq(&rme32->lock);
  831. if (rme32->fullduplex_mode)
  832. runtime->hw = snd_rme32_adat_fd_info;
  833. else
  834. runtime->hw = snd_rme32_adat_info;
  835. if ((rme32->rcreg & RME32_RCR_KMODE) &&
  836. (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
  837. /* AutoSync */
  838. runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
  839. runtime->hw.rate_min = rate;
  840. runtime->hw.rate_max = rate;
  841. }
  842. snd_rme32_set_buffer_constraint(rme32, runtime);
  843. return 0;
  844. }
  845. static int
  846. snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
  847. {
  848. int isadat, rate;
  849. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  850. struct snd_pcm_runtime *runtime = substream->runtime;
  851. if (rme32->fullduplex_mode)
  852. runtime->hw = snd_rme32_adat_fd_info;
  853. else
  854. runtime->hw = snd_rme32_adat_info;
  855. if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
  856. if (!isadat) {
  857. return -EIO;
  858. }
  859. runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
  860. runtime->hw.rate_min = rate;
  861. runtime->hw.rate_max = rate;
  862. }
  863. snd_pcm_set_sync(substream);
  864. spin_lock_irq(&rme32->lock);
  865. if (rme32->capture_substream != NULL) {
  866. spin_unlock_irq(&rme32->lock);
  867. return -EBUSY;
  868. }
  869. rme32->capture_substream = substream;
  870. spin_unlock_irq(&rme32->lock);
  871. snd_rme32_set_buffer_constraint(rme32, runtime);
  872. return 0;
  873. }
  874. static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
  875. {
  876. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  877. int spdif = 0;
  878. spin_lock_irq(&rme32->lock);
  879. rme32->playback_substream = NULL;
  880. rme32->playback_periodsize = 0;
  881. spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
  882. spin_unlock_irq(&rme32->lock);
  883. if (spdif) {
  884. rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  885. snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
  886. SNDRV_CTL_EVENT_MASK_INFO,
  887. &rme32->spdif_ctl->id);
  888. }
  889. return 0;
  890. }
  891. static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
  892. {
  893. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  894. spin_lock_irq(&rme32->lock);
  895. rme32->capture_substream = NULL;
  896. rme32->capture_periodsize = 0;
  897. spin_unlock_irq(&rme32->lock);
  898. return 0;
  899. }
  900. static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
  901. {
  902. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  903. spin_lock_irq(&rme32->lock);
  904. if (rme32->fullduplex_mode) {
  905. memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
  906. rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
  907. rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
  908. } else {
  909. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  910. }
  911. if (rme32->wcreg & RME32_WCR_SEL)
  912. rme32->wcreg &= ~RME32_WCR_MUTE;
  913. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  914. spin_unlock_irq(&rme32->lock);
  915. return 0;
  916. }
  917. static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
  918. {
  919. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  920. spin_lock_irq(&rme32->lock);
  921. if (rme32->fullduplex_mode) {
  922. memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
  923. rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
  924. rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
  925. rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
  926. } else {
  927. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  928. }
  929. spin_unlock_irq(&rme32->lock);
  930. return 0;
  931. }
  932. static int
  933. snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  934. {
  935. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  936. struct snd_pcm_substream *s;
  937. spin_lock(&rme32->lock);
  938. snd_pcm_group_for_each_entry(s, substream) {
  939. if (s != rme32->playback_substream &&
  940. s != rme32->capture_substream)
  941. continue;
  942. switch (cmd) {
  943. case SNDRV_PCM_TRIGGER_START:
  944. rme32->running |= (1 << s->stream);
  945. if (rme32->fullduplex_mode) {
  946. /* remember the current DMA position */
  947. if (s == rme32->playback_substream) {
  948. rme32->playback_pcm.hw_io =
  949. rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
  950. } else {
  951. rme32->capture_pcm.hw_io =
  952. rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
  953. }
  954. }
  955. break;
  956. case SNDRV_PCM_TRIGGER_STOP:
  957. rme32->running &= ~(1 << s->stream);
  958. break;
  959. }
  960. snd_pcm_trigger_done(s, substream);
  961. }
  962. switch (cmd) {
  963. case SNDRV_PCM_TRIGGER_START:
  964. if (rme32->running && ! RME32_ISWORKING(rme32))
  965. snd_rme32_pcm_start(rme32, 0);
  966. break;
  967. case SNDRV_PCM_TRIGGER_STOP:
  968. if (! rme32->running && RME32_ISWORKING(rme32))
  969. snd_rme32_pcm_stop(rme32, 0);
  970. break;
  971. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  972. if (rme32->running && RME32_ISWORKING(rme32))
  973. snd_rme32_pcm_stop(rme32, 1);
  974. break;
  975. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  976. if (rme32->running && ! RME32_ISWORKING(rme32))
  977. snd_rme32_pcm_start(rme32, 1);
  978. break;
  979. }
  980. spin_unlock(&rme32->lock);
  981. return 0;
  982. }
  983. /* pointer callback for halfduplex mode */
  984. static snd_pcm_uframes_t
  985. snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
  986. {
  987. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  988. return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
  989. }
  990. static snd_pcm_uframes_t
  991. snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
  992. {
  993. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  994. return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
  995. }
  996. /* ack and pointer callbacks for fullduplex mode */
  997. static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
  998. struct snd_pcm_indirect *rec, size_t bytes)
  999. {
  1000. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1001. memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
  1002. substream->runtime->dma_area + rec->sw_data, bytes);
  1003. }
  1004. static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
  1005. {
  1006. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1007. struct snd_pcm_indirect *rec, *cprec;
  1008. rec = &rme32->playback_pcm;
  1009. cprec = &rme32->capture_pcm;
  1010. spin_lock(&rme32->lock);
  1011. rec->hw_queue_size = RME32_BUFFER_SIZE;
  1012. if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
  1013. rec->hw_queue_size -= cprec->hw_ready;
  1014. spin_unlock(&rme32->lock);
  1015. return snd_pcm_indirect_playback_transfer(substream, rec,
  1016. snd_rme32_pb_trans_copy);
  1017. }
  1018. static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
  1019. struct snd_pcm_indirect *rec, size_t bytes)
  1020. {
  1021. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1022. memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
  1023. rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
  1024. bytes);
  1025. }
  1026. static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
  1027. {
  1028. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1029. return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
  1030. snd_rme32_cp_trans_copy);
  1031. }
  1032. static snd_pcm_uframes_t
  1033. snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
  1034. {
  1035. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1036. return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
  1037. snd_rme32_pcm_byteptr(rme32));
  1038. }
  1039. static snd_pcm_uframes_t
  1040. snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
  1041. {
  1042. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1043. return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
  1044. snd_rme32_pcm_byteptr(rme32));
  1045. }
  1046. /* for halfduplex mode */
  1047. static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
  1048. .open = snd_rme32_playback_spdif_open,
  1049. .close = snd_rme32_playback_close,
  1050. .hw_params = snd_rme32_playback_hw_params,
  1051. .prepare = snd_rme32_playback_prepare,
  1052. .trigger = snd_rme32_pcm_trigger,
  1053. .pointer = snd_rme32_playback_pointer,
  1054. .copy_user = snd_rme32_playback_copy,
  1055. .copy_kernel = snd_rme32_playback_copy_kernel,
  1056. .fill_silence = snd_rme32_playback_silence,
  1057. .mmap = snd_pcm_lib_mmap_iomem,
  1058. };
  1059. static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
  1060. .open = snd_rme32_capture_spdif_open,
  1061. .close = snd_rme32_capture_close,
  1062. .hw_params = snd_rme32_capture_hw_params,
  1063. .prepare = snd_rme32_capture_prepare,
  1064. .trigger = snd_rme32_pcm_trigger,
  1065. .pointer = snd_rme32_capture_pointer,
  1066. .copy_user = snd_rme32_capture_copy,
  1067. .copy_kernel = snd_rme32_capture_copy_kernel,
  1068. .mmap = snd_pcm_lib_mmap_iomem,
  1069. };
  1070. static const struct snd_pcm_ops snd_rme32_playback_adat_ops = {
  1071. .open = snd_rme32_playback_adat_open,
  1072. .close = snd_rme32_playback_close,
  1073. .hw_params = snd_rme32_playback_hw_params,
  1074. .prepare = snd_rme32_playback_prepare,
  1075. .trigger = snd_rme32_pcm_trigger,
  1076. .pointer = snd_rme32_playback_pointer,
  1077. .copy_user = snd_rme32_playback_copy,
  1078. .copy_kernel = snd_rme32_playback_copy_kernel,
  1079. .fill_silence = snd_rme32_playback_silence,
  1080. .mmap = snd_pcm_lib_mmap_iomem,
  1081. };
  1082. static const struct snd_pcm_ops snd_rme32_capture_adat_ops = {
  1083. .open = snd_rme32_capture_adat_open,
  1084. .close = snd_rme32_capture_close,
  1085. .hw_params = snd_rme32_capture_hw_params,
  1086. .prepare = snd_rme32_capture_prepare,
  1087. .trigger = snd_rme32_pcm_trigger,
  1088. .pointer = snd_rme32_capture_pointer,
  1089. .copy_user = snd_rme32_capture_copy,
  1090. .copy_kernel = snd_rme32_capture_copy_kernel,
  1091. .mmap = snd_pcm_lib_mmap_iomem,
  1092. };
  1093. /* for fullduplex mode */
  1094. static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
  1095. .open = snd_rme32_playback_spdif_open,
  1096. .close = snd_rme32_playback_close,
  1097. .hw_params = snd_rme32_playback_hw_params,
  1098. .prepare = snd_rme32_playback_prepare,
  1099. .trigger = snd_rme32_pcm_trigger,
  1100. .pointer = snd_rme32_playback_fd_pointer,
  1101. .ack = snd_rme32_playback_fd_ack,
  1102. };
  1103. static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
  1104. .open = snd_rme32_capture_spdif_open,
  1105. .close = snd_rme32_capture_close,
  1106. .hw_params = snd_rme32_capture_hw_params,
  1107. .prepare = snd_rme32_capture_prepare,
  1108. .trigger = snd_rme32_pcm_trigger,
  1109. .pointer = snd_rme32_capture_fd_pointer,
  1110. .ack = snd_rme32_capture_fd_ack,
  1111. };
  1112. static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
  1113. .open = snd_rme32_playback_adat_open,
  1114. .close = snd_rme32_playback_close,
  1115. .hw_params = snd_rme32_playback_hw_params,
  1116. .prepare = snd_rme32_playback_prepare,
  1117. .trigger = snd_rme32_pcm_trigger,
  1118. .pointer = snd_rme32_playback_fd_pointer,
  1119. .ack = snd_rme32_playback_fd_ack,
  1120. };
  1121. static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
  1122. .open = snd_rme32_capture_adat_open,
  1123. .close = snd_rme32_capture_close,
  1124. .hw_params = snd_rme32_capture_hw_params,
  1125. .prepare = snd_rme32_capture_prepare,
  1126. .trigger = snd_rme32_pcm_trigger,
  1127. .pointer = snd_rme32_capture_fd_pointer,
  1128. .ack = snd_rme32_capture_fd_ack,
  1129. };
  1130. static void snd_rme32_free(void *private_data)
  1131. {
  1132. struct rme32 *rme32 = (struct rme32 *) private_data;
  1133. if (rme32 == NULL) {
  1134. return;
  1135. }
  1136. if (rme32->irq >= 0) {
  1137. snd_rme32_pcm_stop(rme32, 0);
  1138. free_irq(rme32->irq, (void *) rme32);
  1139. rme32->irq = -1;
  1140. }
  1141. if (rme32->iobase) {
  1142. iounmap(rme32->iobase);
  1143. rme32->iobase = NULL;
  1144. }
  1145. if (rme32->port) {
  1146. pci_release_regions(rme32->pci);
  1147. rme32->port = 0;
  1148. }
  1149. pci_disable_device(rme32->pci);
  1150. }
  1151. static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
  1152. {
  1153. struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
  1154. rme32->spdif_pcm = NULL;
  1155. }
  1156. static void
  1157. snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
  1158. {
  1159. struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
  1160. rme32->adat_pcm = NULL;
  1161. }
  1162. static int snd_rme32_create(struct rme32 *rme32)
  1163. {
  1164. struct pci_dev *pci = rme32->pci;
  1165. int err;
  1166. rme32->irq = -1;
  1167. spin_lock_init(&rme32->lock);
  1168. if ((err = pci_enable_device(pci)) < 0)
  1169. return err;
  1170. if ((err = pci_request_regions(pci, "RME32")) < 0)
  1171. return err;
  1172. rme32->port = pci_resource_start(rme32->pci, 0);
  1173. rme32->iobase = ioremap(rme32->port, RME32_IO_SIZE);
  1174. if (!rme32->iobase) {
  1175. dev_err(rme32->card->dev,
  1176. "unable to remap memory region 0x%lx-0x%lx\n",
  1177. rme32->port, rme32->port + RME32_IO_SIZE - 1);
  1178. return -ENOMEM;
  1179. }
  1180. if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED,
  1181. KBUILD_MODNAME, rme32)) {
  1182. dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq);
  1183. return -EBUSY;
  1184. }
  1185. rme32->irq = pci->irq;
  1186. rme32->card->sync_irq = rme32->irq;
  1187. /* read the card's revision number */
  1188. pci_read_config_byte(pci, 8, &rme32->rev);
  1189. /* set up ALSA pcm device for S/PDIF */
  1190. if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
  1191. return err;
  1192. }
  1193. rme32->spdif_pcm->private_data = rme32;
  1194. rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
  1195. strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
  1196. if (rme32->fullduplex_mode) {
  1197. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1198. &snd_rme32_playback_spdif_fd_ops);
  1199. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1200. &snd_rme32_capture_spdif_fd_ops);
  1201. snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
  1202. NULL, 0, RME32_MID_BUFFER_SIZE);
  1203. rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1204. } else {
  1205. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1206. &snd_rme32_playback_spdif_ops);
  1207. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1208. &snd_rme32_capture_spdif_ops);
  1209. rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
  1210. }
  1211. /* set up ALSA pcm device for ADAT */
  1212. if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
  1213. (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
  1214. /* ADAT is not available on DIGI32 and DIGI32 Pro */
  1215. rme32->adat_pcm = NULL;
  1216. }
  1217. else {
  1218. if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
  1219. 1, 1, &rme32->adat_pcm)) < 0)
  1220. {
  1221. return err;
  1222. }
  1223. rme32->adat_pcm->private_data = rme32;
  1224. rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
  1225. strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
  1226. if (rme32->fullduplex_mode) {
  1227. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1228. &snd_rme32_playback_adat_fd_ops);
  1229. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1230. &snd_rme32_capture_adat_fd_ops);
  1231. snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
  1232. NULL,
  1233. 0, RME32_MID_BUFFER_SIZE);
  1234. rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1235. } else {
  1236. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1237. &snd_rme32_playback_adat_ops);
  1238. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1239. &snd_rme32_capture_adat_ops);
  1240. rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
  1241. }
  1242. }
  1243. rme32->playback_periodsize = 0;
  1244. rme32->capture_periodsize = 0;
  1245. /* make sure playback/capture is stopped, if by some reason active */
  1246. snd_rme32_pcm_stop(rme32, 0);
  1247. /* reset DAC */
  1248. snd_rme32_reset_dac(rme32);
  1249. /* reset buffer pointer */
  1250. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  1251. /* set default values in registers */
  1252. rme32->wcreg = RME32_WCR_SEL | /* normal playback */
  1253. RME32_WCR_INP_0 | /* input select */
  1254. RME32_WCR_MUTE; /* muting on */
  1255. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1256. /* init switch interface */
  1257. if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
  1258. return err;
  1259. }
  1260. /* init proc interface */
  1261. snd_rme32_proc_init(rme32);
  1262. rme32->capture_substream = NULL;
  1263. rme32->playback_substream = NULL;
  1264. return 0;
  1265. }
  1266. /*
  1267. * proc interface
  1268. */
  1269. static void
  1270. snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
  1271. {
  1272. int n;
  1273. struct rme32 *rme32 = (struct rme32 *) entry->private_data;
  1274. rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1275. snd_iprintf(buffer, rme32->card->longname);
  1276. snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
  1277. snd_iprintf(buffer, "\nGeneral settings\n");
  1278. if (rme32->fullduplex_mode)
  1279. snd_iprintf(buffer, " Full-duplex mode\n");
  1280. else
  1281. snd_iprintf(buffer, " Half-duplex mode\n");
  1282. if (RME32_PRO_WITH_8414(rme32)) {
  1283. snd_iprintf(buffer, " receiver: CS8414\n");
  1284. } else {
  1285. snd_iprintf(buffer, " receiver: CS8412\n");
  1286. }
  1287. if (rme32->wcreg & RME32_WCR_MODE24) {
  1288. snd_iprintf(buffer, " format: 24 bit");
  1289. } else {
  1290. snd_iprintf(buffer, " format: 16 bit");
  1291. }
  1292. if (rme32->wcreg & RME32_WCR_MONO) {
  1293. snd_iprintf(buffer, ", Mono\n");
  1294. } else {
  1295. snd_iprintf(buffer, ", Stereo\n");
  1296. }
  1297. snd_iprintf(buffer, "\nInput settings\n");
  1298. switch (snd_rme32_getinputtype(rme32)) {
  1299. case RME32_INPUT_OPTICAL:
  1300. snd_iprintf(buffer, " input: optical");
  1301. break;
  1302. case RME32_INPUT_COAXIAL:
  1303. snd_iprintf(buffer, " input: coaxial");
  1304. break;
  1305. case RME32_INPUT_INTERNAL:
  1306. snd_iprintf(buffer, " input: internal");
  1307. break;
  1308. case RME32_INPUT_XLR:
  1309. snd_iprintf(buffer, " input: XLR");
  1310. break;
  1311. }
  1312. if (snd_rme32_capture_getrate(rme32, &n) < 0) {
  1313. snd_iprintf(buffer, "\n sample rate: no valid signal\n");
  1314. } else {
  1315. if (n) {
  1316. snd_iprintf(buffer, " (8 channels)\n");
  1317. } else {
  1318. snd_iprintf(buffer, " (2 channels)\n");
  1319. }
  1320. snd_iprintf(buffer, " sample rate: %d Hz\n",
  1321. snd_rme32_capture_getrate(rme32, &n));
  1322. }
  1323. snd_iprintf(buffer, "\nOutput settings\n");
  1324. if (rme32->wcreg & RME32_WCR_SEL) {
  1325. snd_iprintf(buffer, " output signal: normal playback");
  1326. } else {
  1327. snd_iprintf(buffer, " output signal: same as input");
  1328. }
  1329. if (rme32->wcreg & RME32_WCR_MUTE) {
  1330. snd_iprintf(buffer, " (muted)\n");
  1331. } else {
  1332. snd_iprintf(buffer, "\n");
  1333. }
  1334. /* master output frequency */
  1335. if (!
  1336. ((!(rme32->wcreg & RME32_WCR_FREQ_0))
  1337. && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
  1338. snd_iprintf(buffer, " sample rate: %d Hz\n",
  1339. snd_rme32_playback_getrate(rme32));
  1340. }
  1341. if (rme32->rcreg & RME32_RCR_KMODE) {
  1342. snd_iprintf(buffer, " sample clock source: AutoSync\n");
  1343. } else {
  1344. snd_iprintf(buffer, " sample clock source: Internal\n");
  1345. }
  1346. if (rme32->wcreg & RME32_WCR_PRO) {
  1347. snd_iprintf(buffer, " format: AES/EBU (professional)\n");
  1348. } else {
  1349. snd_iprintf(buffer, " format: IEC958 (consumer)\n");
  1350. }
  1351. if (rme32->wcreg & RME32_WCR_EMP) {
  1352. snd_iprintf(buffer, " emphasis: on\n");
  1353. } else {
  1354. snd_iprintf(buffer, " emphasis: off\n");
  1355. }
  1356. }
  1357. static void snd_rme32_proc_init(struct rme32 *rme32)
  1358. {
  1359. snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read);
  1360. }
  1361. /*
  1362. * control interface
  1363. */
  1364. #define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info
  1365. static int
  1366. snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
  1367. struct snd_ctl_elem_value *ucontrol)
  1368. {
  1369. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1370. spin_lock_irq(&rme32->lock);
  1371. ucontrol->value.integer.value[0] =
  1372. rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
  1373. spin_unlock_irq(&rme32->lock);
  1374. return 0;
  1375. }
  1376. static int
  1377. snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
  1378. struct snd_ctl_elem_value *ucontrol)
  1379. {
  1380. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1381. unsigned int val;
  1382. int change;
  1383. val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
  1384. spin_lock_irq(&rme32->lock);
  1385. val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
  1386. change = val != rme32->wcreg;
  1387. if (ucontrol->value.integer.value[0])
  1388. val &= ~RME32_WCR_MUTE;
  1389. else
  1390. val |= RME32_WCR_MUTE;
  1391. rme32->wcreg = val;
  1392. writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1393. spin_unlock_irq(&rme32->lock);
  1394. return change;
  1395. }
  1396. static int
  1397. snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
  1398. struct snd_ctl_elem_info *uinfo)
  1399. {
  1400. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1401. static const char * const texts[4] = {
  1402. "Optical", "Coaxial", "Internal", "XLR"
  1403. };
  1404. int num_items;
  1405. switch (rme32->pci->device) {
  1406. case PCI_DEVICE_ID_RME_DIGI32:
  1407. case PCI_DEVICE_ID_RME_DIGI32_8:
  1408. num_items = 3;
  1409. break;
  1410. case PCI_DEVICE_ID_RME_DIGI32_PRO:
  1411. num_items = 4;
  1412. break;
  1413. default:
  1414. snd_BUG();
  1415. return -EINVAL;
  1416. }
  1417. return snd_ctl_enum_info(uinfo, 1, num_items, texts);
  1418. }
  1419. static int
  1420. snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
  1421. struct snd_ctl_elem_value *ucontrol)
  1422. {
  1423. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1424. unsigned int items = 3;
  1425. spin_lock_irq(&rme32->lock);
  1426. ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
  1427. switch (rme32->pci->device) {
  1428. case PCI_DEVICE_ID_RME_DIGI32:
  1429. case PCI_DEVICE_ID_RME_DIGI32_8:
  1430. items = 3;
  1431. break;
  1432. case PCI_DEVICE_ID_RME_DIGI32_PRO:
  1433. items = 4;
  1434. break;
  1435. default:
  1436. snd_BUG();
  1437. break;
  1438. }
  1439. if (ucontrol->value.enumerated.item[0] >= items) {
  1440. ucontrol->value.enumerated.item[0] = items - 1;
  1441. }
  1442. spin_unlock_irq(&rme32->lock);
  1443. return 0;
  1444. }
  1445. static int
  1446. snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
  1447. struct snd_ctl_elem_value *ucontrol)
  1448. {
  1449. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1450. unsigned int val;
  1451. int change, items = 3;
  1452. switch (rme32->pci->device) {
  1453. case PCI_DEVICE_ID_RME_DIGI32:
  1454. case PCI_DEVICE_ID_RME_DIGI32_8:
  1455. items = 3;
  1456. break;
  1457. case PCI_DEVICE_ID_RME_DIGI32_PRO:
  1458. items = 4;
  1459. break;
  1460. default:
  1461. snd_BUG();
  1462. break;
  1463. }
  1464. val = ucontrol->value.enumerated.item[0] % items;
  1465. spin_lock_irq(&rme32->lock);
  1466. change = val != (unsigned int)snd_rme32_getinputtype(rme32);
  1467. snd_rme32_setinputtype(rme32, val);
  1468. spin_unlock_irq(&rme32->lock);
  1469. return change;
  1470. }
  1471. static int
  1472. snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
  1473. struct snd_ctl_elem_info *uinfo)
  1474. {
  1475. static const char * const texts[4] = { "AutoSync",
  1476. "Internal 32.0kHz",
  1477. "Internal 44.1kHz",
  1478. "Internal 48.0kHz" };
  1479. return snd_ctl_enum_info(uinfo, 1, 4, texts);
  1480. }
  1481. static int
  1482. snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
  1483. struct snd_ctl_elem_value *ucontrol)
  1484. {
  1485. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1486. spin_lock_irq(&rme32->lock);
  1487. ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
  1488. spin_unlock_irq(&rme32->lock);
  1489. return 0;
  1490. }
  1491. static int
  1492. snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
  1493. struct snd_ctl_elem_value *ucontrol)
  1494. {
  1495. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1496. unsigned int val;
  1497. int change;
  1498. val = ucontrol->value.enumerated.item[0] % 3;
  1499. spin_lock_irq(&rme32->lock);
  1500. change = val != (unsigned int)snd_rme32_getclockmode(rme32);
  1501. snd_rme32_setclockmode(rme32, val);
  1502. spin_unlock_irq(&rme32->lock);
  1503. return change;
  1504. }
  1505. static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
  1506. {
  1507. u32 val = 0;
  1508. val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
  1509. if (val & RME32_WCR_PRO)
  1510. val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
  1511. else
  1512. val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
  1513. return val;
  1514. }
  1515. static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
  1516. {
  1517. aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
  1518. if (val & RME32_WCR_PRO)
  1519. aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
  1520. else
  1521. aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
  1522. }
  1523. static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
  1524. struct snd_ctl_elem_info *uinfo)
  1525. {
  1526. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1527. uinfo->count = 1;
  1528. return 0;
  1529. }
  1530. static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
  1531. struct snd_ctl_elem_value *ucontrol)
  1532. {
  1533. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1534. snd_rme32_convert_to_aes(&ucontrol->value.iec958,
  1535. rme32->wcreg_spdif);
  1536. return 0;
  1537. }
  1538. static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
  1539. struct snd_ctl_elem_value *ucontrol)
  1540. {
  1541. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1542. int change;
  1543. u32 val;
  1544. val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
  1545. spin_lock_irq(&rme32->lock);
  1546. change = val != rme32->wcreg_spdif;
  1547. rme32->wcreg_spdif = val;
  1548. spin_unlock_irq(&rme32->lock);
  1549. return change;
  1550. }
  1551. static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
  1552. struct snd_ctl_elem_info *uinfo)
  1553. {
  1554. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1555. uinfo->count = 1;
  1556. return 0;
  1557. }
  1558. static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1559. struct snd_ctl_elem_value *
  1560. ucontrol)
  1561. {
  1562. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1563. snd_rme32_convert_to_aes(&ucontrol->value.iec958,
  1564. rme32->wcreg_spdif_stream);
  1565. return 0;
  1566. }
  1567. static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1568. struct snd_ctl_elem_value *
  1569. ucontrol)
  1570. {
  1571. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1572. int change;
  1573. u32 val;
  1574. val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
  1575. spin_lock_irq(&rme32->lock);
  1576. change = val != rme32->wcreg_spdif_stream;
  1577. rme32->wcreg_spdif_stream = val;
  1578. rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
  1579. rme32->wcreg |= val;
  1580. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1581. spin_unlock_irq(&rme32->lock);
  1582. return change;
  1583. }
  1584. static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
  1585. struct snd_ctl_elem_info *uinfo)
  1586. {
  1587. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1588. uinfo->count = 1;
  1589. return 0;
  1590. }
  1591. static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1592. struct snd_ctl_elem_value *
  1593. ucontrol)
  1594. {
  1595. ucontrol->value.iec958.status[0] = kcontrol->private_value;
  1596. return 0;
  1597. }
  1598. static const struct snd_kcontrol_new snd_rme32_controls[] = {
  1599. {
  1600. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1601. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1602. .info = snd_rme32_control_spdif_info,
  1603. .get = snd_rme32_control_spdif_get,
  1604. .put = snd_rme32_control_spdif_put
  1605. },
  1606. {
  1607. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1608. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1609. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
  1610. .info = snd_rme32_control_spdif_stream_info,
  1611. .get = snd_rme32_control_spdif_stream_get,
  1612. .put = snd_rme32_control_spdif_stream_put
  1613. },
  1614. {
  1615. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1616. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1617. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1618. .info = snd_rme32_control_spdif_mask_info,
  1619. .get = snd_rme32_control_spdif_mask_get,
  1620. .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
  1621. },
  1622. {
  1623. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1624. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1625. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1626. .info = snd_rme32_control_spdif_mask_info,
  1627. .get = snd_rme32_control_spdif_mask_get,
  1628. .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
  1629. },
  1630. {
  1631. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1632. .name = "Input Connector",
  1633. .info = snd_rme32_info_inputtype_control,
  1634. .get = snd_rme32_get_inputtype_control,
  1635. .put = snd_rme32_put_inputtype_control
  1636. },
  1637. {
  1638. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1639. .name = "Loopback Input",
  1640. .info = snd_rme32_info_loopback_control,
  1641. .get = snd_rme32_get_loopback_control,
  1642. .put = snd_rme32_put_loopback_control
  1643. },
  1644. {
  1645. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1646. .name = "Sample Clock Source",
  1647. .info = snd_rme32_info_clockmode_control,
  1648. .get = snd_rme32_get_clockmode_control,
  1649. .put = snd_rme32_put_clockmode_control
  1650. }
  1651. };
  1652. static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
  1653. {
  1654. int idx, err;
  1655. struct snd_kcontrol *kctl;
  1656. for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
  1657. if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
  1658. return err;
  1659. if (idx == 1) /* IEC958 (S/PDIF) Stream */
  1660. rme32->spdif_ctl = kctl;
  1661. }
  1662. return 0;
  1663. }
  1664. /*
  1665. * Card initialisation
  1666. */
  1667. static void snd_rme32_card_free(struct snd_card *card)
  1668. {
  1669. snd_rme32_free(card->private_data);
  1670. }
  1671. static int
  1672. snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1673. {
  1674. static int dev;
  1675. struct rme32 *rme32;
  1676. struct snd_card *card;
  1677. int err;
  1678. if (dev >= SNDRV_CARDS) {
  1679. return -ENODEV;
  1680. }
  1681. if (!enable[dev]) {
  1682. dev++;
  1683. return -ENOENT;
  1684. }
  1685. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  1686. sizeof(struct rme32), &card);
  1687. if (err < 0)
  1688. return err;
  1689. card->private_free = snd_rme32_card_free;
  1690. rme32 = (struct rme32 *) card->private_data;
  1691. rme32->card = card;
  1692. rme32->pci = pci;
  1693. if (fullduplex[dev])
  1694. rme32->fullduplex_mode = 1;
  1695. if ((err = snd_rme32_create(rme32)) < 0) {
  1696. snd_card_free(card);
  1697. return err;
  1698. }
  1699. strcpy(card->driver, "Digi32");
  1700. switch (rme32->pci->device) {
  1701. case PCI_DEVICE_ID_RME_DIGI32:
  1702. strcpy(card->shortname, "RME Digi32");
  1703. break;
  1704. case PCI_DEVICE_ID_RME_DIGI32_8:
  1705. strcpy(card->shortname, "RME Digi32/8");
  1706. break;
  1707. case PCI_DEVICE_ID_RME_DIGI32_PRO:
  1708. strcpy(card->shortname, "RME Digi32 PRO");
  1709. break;
  1710. }
  1711. sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
  1712. card->shortname, rme32->rev, rme32->port, rme32->irq);
  1713. if ((err = snd_card_register(card)) < 0) {
  1714. snd_card_free(card);
  1715. return err;
  1716. }
  1717. pci_set_drvdata(pci, card);
  1718. dev++;
  1719. return 0;
  1720. }
  1721. static void snd_rme32_remove(struct pci_dev *pci)
  1722. {
  1723. snd_card_free(pci_get_drvdata(pci));
  1724. }
  1725. static struct pci_driver rme32_driver = {
  1726. .name = KBUILD_MODNAME,
  1727. .id_table = snd_rme32_ids,
  1728. .probe = snd_rme32_probe,
  1729. .remove = snd_rme32_remove,
  1730. };
  1731. module_pci_driver(rme32_driver);