maestro3.c 81 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
  4. * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
  5. * Takashi Iwai <tiwai@suse.de>
  6. *
  7. * Most of the hardware init stuffs are based on maestro3 driver for
  8. * OSS/Free by Zach Brown. Many thanks to Zach!
  9. *
  10. * ChangeLog:
  11. * Aug. 27, 2001
  12. * - Fixed deadlock on capture
  13. * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  14. */
  15. #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  16. #define DRIVER_NAME "Maestro3"
  17. #include <linux/io.h>
  18. #include <linux/delay.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/init.h>
  21. #include <linux/pci.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/slab.h>
  24. #include <linux/vmalloc.h>
  25. #include <linux/module.h>
  26. #include <linux/firmware.h>
  27. #include <linux/input.h>
  28. #include <sound/core.h>
  29. #include <sound/info.h>
  30. #include <sound/control.h>
  31. #include <sound/pcm.h>
  32. #include <sound/mpu401.h>
  33. #include <sound/ac97_codec.h>
  34. #include <sound/initval.h>
  35. #include <asm/byteorder.h>
  36. MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  37. MODULE_DESCRIPTION("ESS Maestro3 PCI");
  38. MODULE_LICENSE("GPL");
  39. MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  40. "{ESS,ES1988},"
  41. "{ESS,Allegro PCI},"
  42. "{ESS,Allegro-1 PCI},"
  43. "{ESS,Canyon3D-2/LE PCI}}");
  44. MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
  45. MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
  46. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  47. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  48. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  49. static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  50. static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  51. module_param_array(index, int, NULL, 0444);
  52. MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  53. module_param_array(id, charp, NULL, 0444);
  54. MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  55. module_param_array(enable, bool, NULL, 0444);
  56. MODULE_PARM_DESC(enable, "Enable this soundcard.");
  57. module_param_array(external_amp, bool, NULL, 0444);
  58. MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  59. module_param_array(amp_gpio, int, NULL, 0444);
  60. MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  61. #define MAX_PLAYBACKS 2
  62. #define MAX_CAPTURES 1
  63. #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
  64. /*
  65. * maestro3 registers
  66. */
  67. /* Allegro PCI configuration registers */
  68. #define PCI_LEGACY_AUDIO_CTRL 0x40
  69. #define SOUND_BLASTER_ENABLE 0x00000001
  70. #define FM_SYNTHESIS_ENABLE 0x00000002
  71. #define GAME_PORT_ENABLE 0x00000004
  72. #define MPU401_IO_ENABLE 0x00000008
  73. #define MPU401_IRQ_ENABLE 0x00000010
  74. #define ALIAS_10BIT_IO 0x00000020
  75. #define SB_DMA_MASK 0x000000C0
  76. #define SB_DMA_0 0x00000040
  77. #define SB_DMA_1 0x00000040
  78. #define SB_DMA_R 0x00000080
  79. #define SB_DMA_3 0x000000C0
  80. #define SB_IRQ_MASK 0x00000700
  81. #define SB_IRQ_5 0x00000000
  82. #define SB_IRQ_7 0x00000100
  83. #define SB_IRQ_9 0x00000200
  84. #define SB_IRQ_10 0x00000300
  85. #define MIDI_IRQ_MASK 0x00003800
  86. #define SERIAL_IRQ_ENABLE 0x00004000
  87. #define DISABLE_LEGACY 0x00008000
  88. #define PCI_ALLEGRO_CONFIG 0x50
  89. #define SB_ADDR_240 0x00000004
  90. #define MPU_ADDR_MASK 0x00000018
  91. #define MPU_ADDR_330 0x00000000
  92. #define MPU_ADDR_300 0x00000008
  93. #define MPU_ADDR_320 0x00000010
  94. #define MPU_ADDR_340 0x00000018
  95. #define USE_PCI_TIMING 0x00000040
  96. #define POSTED_WRITE_ENABLE 0x00000080
  97. #define DMA_POLICY_MASK 0x00000700
  98. #define DMA_DDMA 0x00000000
  99. #define DMA_TDMA 0x00000100
  100. #define DMA_PCPCI 0x00000200
  101. #define DMA_WBDMA16 0x00000400
  102. #define DMA_WBDMA4 0x00000500
  103. #define DMA_WBDMA2 0x00000600
  104. #define DMA_WBDMA1 0x00000700
  105. #define DMA_SAFE_GUARD 0x00000800
  106. #define HI_PERF_GP_ENABLE 0x00001000
  107. #define PIC_SNOOP_MODE_0 0x00002000
  108. #define PIC_SNOOP_MODE_1 0x00004000
  109. #define SOUNDBLASTER_IRQ_MASK 0x00008000
  110. #define RING_IN_ENABLE 0x00010000
  111. #define SPDIF_TEST_MODE 0x00020000
  112. #define CLK_MULT_MODE_SELECT_2 0x00040000
  113. #define EEPROM_WRITE_ENABLE 0x00080000
  114. #define CODEC_DIR_IN 0x00100000
  115. #define HV_BUTTON_FROM_GD 0x00200000
  116. #define REDUCED_DEBOUNCE 0x00400000
  117. #define HV_CTRL_ENABLE 0x00800000
  118. #define SPDIF_ENABLE 0x01000000
  119. #define CLK_DIV_SELECT 0x06000000
  120. #define CLK_DIV_BY_48 0x00000000
  121. #define CLK_DIV_BY_49 0x02000000
  122. #define CLK_DIV_BY_50 0x04000000
  123. #define CLK_DIV_RESERVED 0x06000000
  124. #define PM_CTRL_ENABLE 0x08000000
  125. #define CLK_MULT_MODE_SELECT 0x30000000
  126. #define CLK_MULT_MODE_SHIFT 28
  127. #define CLK_MULT_MODE_0 0x00000000
  128. #define CLK_MULT_MODE_1 0x10000000
  129. #define CLK_MULT_MODE_2 0x20000000
  130. #define CLK_MULT_MODE_3 0x30000000
  131. #define INT_CLK_SELECT 0x40000000
  132. #define INT_CLK_MULT_RESET 0x80000000
  133. /* M3 */
  134. #define INT_CLK_SRC_NOT_PCI 0x00100000
  135. #define INT_CLK_MULT_ENABLE 0x80000000
  136. #define PCI_ACPI_CONTROL 0x54
  137. #define PCI_ACPI_D0 0x00000000
  138. #define PCI_ACPI_D1 0xB4F70000
  139. #define PCI_ACPI_D2 0xB4F7B4F7
  140. #define PCI_USER_CONFIG 0x58
  141. #define EXT_PCI_MASTER_ENABLE 0x00000001
  142. #define SPDIF_OUT_SELECT 0x00000002
  143. #define TEST_PIN_DIR_CTRL 0x00000004
  144. #define AC97_CODEC_TEST 0x00000020
  145. #define TRI_STATE_BUFFER 0x00000080
  146. #define IN_CLK_12MHZ_SELECT 0x00000100
  147. #define MULTI_FUNC_DISABLE 0x00000200
  148. #define EXT_MASTER_PAIR_SEL 0x00000400
  149. #define PCI_MASTER_SUPPORT 0x00000800
  150. #define STOP_CLOCK_ENABLE 0x00001000
  151. #define EAPD_DRIVE_ENABLE 0x00002000
  152. #define REQ_TRI_STATE_ENABLE 0x00004000
  153. #define REQ_LOW_ENABLE 0x00008000
  154. #define MIDI_1_ENABLE 0x00010000
  155. #define MIDI_2_ENABLE 0x00020000
  156. #define SB_AUDIO_SYNC 0x00040000
  157. #define HV_CTRL_TEST 0x00100000
  158. #define SOUNDBLASTER_TEST 0x00400000
  159. #define PCI_USER_CONFIG_C 0x5C
  160. #define PCI_DDMA_CTRL 0x60
  161. #define DDMA_ENABLE 0x00000001
  162. /* Allegro registers */
  163. #define HOST_INT_CTRL 0x18
  164. #define SB_INT_ENABLE 0x0001
  165. #define MPU401_INT_ENABLE 0x0002
  166. #define ASSP_INT_ENABLE 0x0010
  167. #define RING_INT_ENABLE 0x0020
  168. #define HV_INT_ENABLE 0x0040
  169. #define CLKRUN_GEN_ENABLE 0x0100
  170. #define HV_CTRL_TO_PME 0x0400
  171. #define SOFTWARE_RESET_ENABLE 0x8000
  172. /*
  173. * should be using the above defines, probably.
  174. */
  175. #define REGB_ENABLE_RESET 0x01
  176. #define REGB_STOP_CLOCK 0x10
  177. #define HOST_INT_STATUS 0x1A
  178. #define SB_INT_PENDING 0x01
  179. #define MPU401_INT_PENDING 0x02
  180. #define ASSP_INT_PENDING 0x10
  181. #define RING_INT_PENDING 0x20
  182. #define HV_INT_PENDING 0x40
  183. #define HARDWARE_VOL_CTRL 0x1B
  184. #define SHADOW_MIX_REG_VOICE 0x1C
  185. #define HW_VOL_COUNTER_VOICE 0x1D
  186. #define SHADOW_MIX_REG_MASTER 0x1E
  187. #define HW_VOL_COUNTER_MASTER 0x1F
  188. #define CODEC_COMMAND 0x30
  189. #define CODEC_READ_B 0x80
  190. #define CODEC_STATUS 0x30
  191. #define CODEC_BUSY_B 0x01
  192. #define CODEC_DATA 0x32
  193. #define RING_BUS_CTRL_A 0x36
  194. #define RAC_PME_ENABLE 0x0100
  195. #define RAC_SDFS_ENABLE 0x0200
  196. #define LAC_PME_ENABLE 0x0400
  197. #define LAC_SDFS_ENABLE 0x0800
  198. #define SERIAL_AC_LINK_ENABLE 0x1000
  199. #define IO_SRAM_ENABLE 0x2000
  200. #define IIS_INPUT_ENABLE 0x8000
  201. #define RING_BUS_CTRL_B 0x38
  202. #define SECOND_CODEC_ID_MASK 0x0003
  203. #define SPDIF_FUNC_ENABLE 0x0010
  204. #define SECOND_AC_ENABLE 0x0020
  205. #define SB_MODULE_INTF_ENABLE 0x0040
  206. #define SSPE_ENABLE 0x0040
  207. #define M3I_DOCK_ENABLE 0x0080
  208. #define SDO_OUT_DEST_CTRL 0x3A
  209. #define COMMAND_ADDR_OUT 0x0003
  210. #define PCM_LR_OUT_LOCAL 0x0000
  211. #define PCM_LR_OUT_REMOTE 0x0004
  212. #define PCM_LR_OUT_MUTE 0x0008
  213. #define PCM_LR_OUT_BOTH 0x000C
  214. #define LINE1_DAC_OUT_LOCAL 0x0000
  215. #define LINE1_DAC_OUT_REMOTE 0x0010
  216. #define LINE1_DAC_OUT_MUTE 0x0020
  217. #define LINE1_DAC_OUT_BOTH 0x0030
  218. #define PCM_CLS_OUT_LOCAL 0x0000
  219. #define PCM_CLS_OUT_REMOTE 0x0040
  220. #define PCM_CLS_OUT_MUTE 0x0080
  221. #define PCM_CLS_OUT_BOTH 0x00C0
  222. #define PCM_RLF_OUT_LOCAL 0x0000
  223. #define PCM_RLF_OUT_REMOTE 0x0100
  224. #define PCM_RLF_OUT_MUTE 0x0200
  225. #define PCM_RLF_OUT_BOTH 0x0300
  226. #define LINE2_DAC_OUT_LOCAL 0x0000
  227. #define LINE2_DAC_OUT_REMOTE 0x0400
  228. #define LINE2_DAC_OUT_MUTE 0x0800
  229. #define LINE2_DAC_OUT_BOTH 0x0C00
  230. #define HANDSET_OUT_LOCAL 0x0000
  231. #define HANDSET_OUT_REMOTE 0x1000
  232. #define HANDSET_OUT_MUTE 0x2000
  233. #define HANDSET_OUT_BOTH 0x3000
  234. #define IO_CTRL_OUT_LOCAL 0x0000
  235. #define IO_CTRL_OUT_REMOTE 0x4000
  236. #define IO_CTRL_OUT_MUTE 0x8000
  237. #define IO_CTRL_OUT_BOTH 0xC000
  238. #define SDO_IN_DEST_CTRL 0x3C
  239. #define STATUS_ADDR_IN 0x0003
  240. #define PCM_LR_IN_LOCAL 0x0000
  241. #define PCM_LR_IN_REMOTE 0x0004
  242. #define PCM_LR_RESERVED 0x0008
  243. #define PCM_LR_IN_BOTH 0x000C
  244. #define LINE1_ADC_IN_LOCAL 0x0000
  245. #define LINE1_ADC_IN_REMOTE 0x0010
  246. #define LINE1_ADC_IN_MUTE 0x0020
  247. #define MIC_ADC_IN_LOCAL 0x0000
  248. #define MIC_ADC_IN_REMOTE 0x0040
  249. #define MIC_ADC_IN_MUTE 0x0080
  250. #define LINE2_DAC_IN_LOCAL 0x0000
  251. #define LINE2_DAC_IN_REMOTE 0x0400
  252. #define LINE2_DAC_IN_MUTE 0x0800
  253. #define HANDSET_IN_LOCAL 0x0000
  254. #define HANDSET_IN_REMOTE 0x1000
  255. #define HANDSET_IN_MUTE 0x2000
  256. #define IO_STATUS_IN_LOCAL 0x0000
  257. #define IO_STATUS_IN_REMOTE 0x4000
  258. #define SPDIF_IN_CTRL 0x3E
  259. #define SPDIF_IN_ENABLE 0x0001
  260. #define GPIO_DATA 0x60
  261. #define GPIO_DATA_MASK 0x0FFF
  262. #define GPIO_HV_STATUS 0x3000
  263. #define GPIO_PME_STATUS 0x4000
  264. #define GPIO_MASK 0x64
  265. #define GPIO_DIRECTION 0x68
  266. #define GPO_PRIMARY_AC97 0x0001
  267. #define GPI_LINEOUT_SENSE 0x0004
  268. #define GPO_SECONDARY_AC97 0x0008
  269. #define GPI_VOL_DOWN 0x0010
  270. #define GPI_VOL_UP 0x0020
  271. #define GPI_IIS_CLK 0x0040
  272. #define GPI_IIS_LRCLK 0x0080
  273. #define GPI_IIS_DATA 0x0100
  274. #define GPI_DOCKING_STATUS 0x0100
  275. #define GPI_HEADPHONE_SENSE 0x0200
  276. #define GPO_EXT_AMP_SHUTDOWN 0x1000
  277. #define GPO_EXT_AMP_M3 1 /* default m3 amp */
  278. #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
  279. /* M3 */
  280. #define GPO_M3_EXT_AMP_SHUTDN 0x0002
  281. #define ASSP_INDEX_PORT 0x80
  282. #define ASSP_MEMORY_PORT 0x82
  283. #define ASSP_DATA_PORT 0x84
  284. #define MPU401_DATA_PORT 0x98
  285. #define MPU401_STATUS_PORT 0x99
  286. #define CLK_MULT_DATA_PORT 0x9C
  287. #define ASSP_CONTROL_A 0xA2
  288. #define ASSP_0_WS_ENABLE 0x01
  289. #define ASSP_CTRL_A_RESERVED1 0x02
  290. #define ASSP_CTRL_A_RESERVED2 0x04
  291. #define ASSP_CLK_49MHZ_SELECT 0x08
  292. #define FAST_PLU_ENABLE 0x10
  293. #define ASSP_CTRL_A_RESERVED3 0x20
  294. #define DSP_CLK_36MHZ_SELECT 0x40
  295. #define ASSP_CONTROL_B 0xA4
  296. #define RESET_ASSP 0x00
  297. #define RUN_ASSP 0x01
  298. #define ENABLE_ASSP_CLOCK 0x00
  299. #define STOP_ASSP_CLOCK 0x10
  300. #define RESET_TOGGLE 0x40
  301. #define ASSP_CONTROL_C 0xA6
  302. #define ASSP_HOST_INT_ENABLE 0x01
  303. #define FM_ADDR_REMAP_DISABLE 0x02
  304. #define HOST_WRITE_PORT_ENABLE 0x08
  305. #define ASSP_HOST_INT_STATUS 0xAC
  306. #define DSP2HOST_REQ_PIORECORD 0x01
  307. #define DSP2HOST_REQ_I2SRATE 0x02
  308. #define DSP2HOST_REQ_TIMER 0x04
  309. /*
  310. * ASSP control regs
  311. */
  312. #define DSP_PORT_TIMER_COUNT 0x06
  313. #define DSP_PORT_MEMORY_INDEX 0x80
  314. #define DSP_PORT_MEMORY_TYPE 0x82
  315. #define MEMTYPE_INTERNAL_CODE 0x0002
  316. #define MEMTYPE_INTERNAL_DATA 0x0003
  317. #define MEMTYPE_MASK 0x0003
  318. #define DSP_PORT_MEMORY_DATA 0x84
  319. #define DSP_PORT_CONTROL_REG_A 0xA2
  320. #define DSP_PORT_CONTROL_REG_B 0xA4
  321. #define DSP_PORT_CONTROL_REG_C 0xA6
  322. #define REV_A_CODE_MEMORY_BEGIN 0x0000
  323. #define REV_A_CODE_MEMORY_END 0x0FFF
  324. #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
  325. #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
  326. #define REV_B_CODE_MEMORY_BEGIN 0x0000
  327. #define REV_B_CODE_MEMORY_END 0x0BFF
  328. #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
  329. #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
  330. #define REV_A_DATA_MEMORY_BEGIN 0x1000
  331. #define REV_A_DATA_MEMORY_END 0x2FFF
  332. #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
  333. #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
  334. #define REV_B_DATA_MEMORY_BEGIN 0x1000
  335. #define REV_B_DATA_MEMORY_END 0x2BFF
  336. #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
  337. #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
  338. #define NUM_UNITS_KERNEL_CODE 16
  339. #define NUM_UNITS_KERNEL_DATA 2
  340. #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
  341. #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
  342. /*
  343. * Kernel data layout
  344. */
  345. #define DP_SHIFT_COUNT 7
  346. #define KDATA_BASE_ADDR 0x1000
  347. #define KDATA_BASE_ADDR2 0x1080
  348. #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
  349. #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
  350. #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
  351. #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
  352. #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
  353. #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
  354. #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
  355. #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
  356. #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
  357. #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
  358. #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
  359. #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
  360. #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
  361. #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
  362. #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
  363. #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
  364. #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
  365. #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
  366. #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
  367. #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
  368. #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
  369. #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
  370. #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
  371. #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
  372. #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
  373. #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
  374. #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
  375. #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
  376. #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
  377. #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
  378. #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
  379. #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
  380. #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
  381. #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
  382. #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
  383. #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
  384. #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
  385. #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
  386. #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
  387. #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
  388. #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
  389. #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
  390. #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
  391. #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
  392. #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
  393. #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
  394. #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
  395. #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
  396. #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
  397. #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
  398. #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
  399. #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
  400. #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
  401. #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
  402. #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
  403. #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
  404. #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
  405. #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
  406. #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
  407. #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
  408. #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
  409. #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
  410. #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
  411. #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
  412. #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
  413. #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
  414. #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
  415. #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
  416. #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
  417. #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
  418. #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
  419. #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
  420. #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
  421. #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
  422. #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
  423. #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
  424. #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
  425. #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
  426. #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
  427. #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
  428. #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
  429. #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
  430. #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
  431. #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
  432. #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
  433. #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
  434. #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
  435. #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
  436. #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
  437. #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
  438. #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
  439. #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
  440. #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
  441. #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
  442. #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
  443. #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
  444. #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
  445. #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
  446. #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
  447. #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
  448. #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
  449. #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
  450. #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
  451. #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
  452. #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
  453. #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
  454. #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
  455. #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
  456. #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
  457. #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
  458. #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
  459. #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
  460. #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
  461. #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
  462. #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
  463. #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
  464. #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
  465. #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
  466. #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
  467. #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
  468. #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
  469. #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
  470. #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
  471. #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
  472. #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
  473. /*
  474. * second 'segment' (?) reserved for mixer
  475. * buffers..
  476. */
  477. #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
  478. #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
  479. #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
  480. #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
  481. #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
  482. #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
  483. #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
  484. #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
  485. #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
  486. #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
  487. #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
  488. #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
  489. #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
  490. #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
  491. #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
  492. #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
  493. #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
  494. #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
  495. #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
  496. #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
  497. #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
  498. #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
  499. #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
  500. #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
  501. #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
  502. #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
  503. #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
  504. #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
  505. #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
  506. #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
  507. #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
  508. #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
  509. #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
  510. #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
  511. #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
  512. #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
  513. #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
  514. /*
  515. * client data area offsets
  516. */
  517. #define CDATA_INSTANCE_READY 0x00
  518. #define CDATA_HOST_SRC_ADDRL 0x01
  519. #define CDATA_HOST_SRC_ADDRH 0x02
  520. #define CDATA_HOST_SRC_END_PLUS_1L 0x03
  521. #define CDATA_HOST_SRC_END_PLUS_1H 0x04
  522. #define CDATA_HOST_SRC_CURRENTL 0x05
  523. #define CDATA_HOST_SRC_CURRENTH 0x06
  524. #define CDATA_IN_BUF_CONNECT 0x07
  525. #define CDATA_OUT_BUF_CONNECT 0x08
  526. #define CDATA_IN_BUF_BEGIN 0x09
  527. #define CDATA_IN_BUF_END_PLUS_1 0x0A
  528. #define CDATA_IN_BUF_HEAD 0x0B
  529. #define CDATA_IN_BUF_TAIL 0x0C
  530. #define CDATA_OUT_BUF_BEGIN 0x0D
  531. #define CDATA_OUT_BUF_END_PLUS_1 0x0E
  532. #define CDATA_OUT_BUF_HEAD 0x0F
  533. #define CDATA_OUT_BUF_TAIL 0x10
  534. #define CDATA_DMA_CONTROL 0x11
  535. #define CDATA_RESERVED 0x12
  536. #define CDATA_FREQUENCY 0x13
  537. #define CDATA_LEFT_VOLUME 0x14
  538. #define CDATA_RIGHT_VOLUME 0x15
  539. #define CDATA_LEFT_SUR_VOL 0x16
  540. #define CDATA_RIGHT_SUR_VOL 0x17
  541. #define CDATA_HEADER_LEN 0x18
  542. #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
  543. #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
  544. #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
  545. #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
  546. #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
  547. #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
  548. #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
  549. #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
  550. #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
  551. #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
  552. #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
  553. #define MINISRC_BIQUAD_STAGE 2
  554. #define MINISRC_COEF_LOC 0x175
  555. #define DMACONTROL_BLOCK_MASK 0x000F
  556. #define DMAC_BLOCK0_SELECTOR 0x0000
  557. #define DMAC_BLOCK1_SELECTOR 0x0001
  558. #define DMAC_BLOCK2_SELECTOR 0x0002
  559. #define DMAC_BLOCK3_SELECTOR 0x0003
  560. #define DMAC_BLOCK4_SELECTOR 0x0004
  561. #define DMAC_BLOCK5_SELECTOR 0x0005
  562. #define DMAC_BLOCK6_SELECTOR 0x0006
  563. #define DMAC_BLOCK7_SELECTOR 0x0007
  564. #define DMAC_BLOCK8_SELECTOR 0x0008
  565. #define DMAC_BLOCK9_SELECTOR 0x0009
  566. #define DMAC_BLOCKA_SELECTOR 0x000A
  567. #define DMAC_BLOCKB_SELECTOR 0x000B
  568. #define DMAC_BLOCKC_SELECTOR 0x000C
  569. #define DMAC_BLOCKD_SELECTOR 0x000D
  570. #define DMAC_BLOCKE_SELECTOR 0x000E
  571. #define DMAC_BLOCKF_SELECTOR 0x000F
  572. #define DMACONTROL_PAGE_MASK 0x00F0
  573. #define DMAC_PAGE0_SELECTOR 0x0030
  574. #define DMAC_PAGE1_SELECTOR 0x0020
  575. #define DMAC_PAGE2_SELECTOR 0x0010
  576. #define DMAC_PAGE3_SELECTOR 0x0000
  577. #define DMACONTROL_AUTOREPEAT 0x1000
  578. #define DMACONTROL_STOPPED 0x2000
  579. #define DMACONTROL_DIRECTION 0x0100
  580. /*
  581. * an arbitrary volume we set the internal
  582. * volume settings to so that the ac97 volume
  583. * range is a little less insane. 0x7fff is
  584. * max.
  585. */
  586. #define ARB_VOLUME ( 0x6800 )
  587. /*
  588. */
  589. struct m3_list {
  590. int curlen;
  591. int mem_addr;
  592. int max;
  593. };
  594. struct m3_dma {
  595. int number;
  596. struct snd_pcm_substream *substream;
  597. struct assp_instance {
  598. unsigned short code, data;
  599. } inst;
  600. int running;
  601. int opened;
  602. unsigned long buffer_addr;
  603. int dma_size;
  604. int period_size;
  605. unsigned int hwptr;
  606. int count;
  607. int index[3];
  608. struct m3_list *index_list[3];
  609. int in_lists;
  610. struct list_head list;
  611. };
  612. struct snd_m3 {
  613. struct snd_card *card;
  614. unsigned long iobase;
  615. int irq;
  616. unsigned int allegro_flag : 1;
  617. struct snd_ac97 *ac97;
  618. struct snd_pcm *pcm;
  619. struct pci_dev *pci;
  620. int dacs_active;
  621. int timer_users;
  622. struct m3_list msrc_list;
  623. struct m3_list mixer_list;
  624. struct m3_list adc1_list;
  625. struct m3_list dma_list;
  626. /* for storing reset state..*/
  627. u8 reset_state;
  628. int external_amp;
  629. int amp_gpio; /* gpio pin # for external amp, -1 = default */
  630. unsigned int hv_config; /* hardware-volume config bits */
  631. unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
  632. (e.g. for IrDA on Dell Inspirons) */
  633. unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
  634. /* midi */
  635. struct snd_rawmidi *rmidi;
  636. /* pcm streams */
  637. int num_substreams;
  638. struct m3_dma *substreams;
  639. spinlock_t reg_lock;
  640. #ifdef CONFIG_SND_MAESTRO3_INPUT
  641. struct input_dev *input_dev;
  642. char phys[64]; /* physical device path */
  643. #else
  644. struct snd_kcontrol *master_switch;
  645. struct snd_kcontrol *master_volume;
  646. #endif
  647. struct work_struct hwvol_work;
  648. unsigned int in_suspend;
  649. #ifdef CONFIG_PM_SLEEP
  650. u16 *suspend_mem;
  651. #endif
  652. const struct firmware *assp_kernel_image;
  653. const struct firmware *assp_minisrc_image;
  654. };
  655. /*
  656. * pci ids
  657. */
  658. static const struct pci_device_id snd_m3_ids[] = {
  659. {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
  660. PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
  661. {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
  662. PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
  663. {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
  664. PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
  665. {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
  666. PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
  667. {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
  668. PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
  669. {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
  670. PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
  671. {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
  672. PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
  673. {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
  674. PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
  675. {0,},
  676. };
  677. MODULE_DEVICE_TABLE(pci, snd_m3_ids);
  678. static const struct snd_pci_quirk m3_amp_quirk_list[] = {
  679. SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
  680. SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
  681. SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
  682. SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
  683. SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
  684. { } /* END */
  685. };
  686. static const struct snd_pci_quirk m3_irda_quirk_list[] = {
  687. SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
  688. SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
  689. SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
  690. { } /* END */
  691. };
  692. /* hardware volume quirks */
  693. static const struct snd_pci_quirk m3_hv_quirk_list[] = {
  694. /* Allegro chips */
  695. SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  696. SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  697. SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  698. SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  699. SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  700. SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  701. SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  702. SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  703. SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  704. SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  705. SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  706. SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  707. SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  708. SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  709. SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  710. SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  711. SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  712. SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  713. SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  714. SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  715. SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  716. SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  717. SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  718. SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  719. SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
  720. SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
  721. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  722. SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
  723. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  724. SND_PCI_QUIRK(0x107B, 0x340A, NULL,
  725. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  726. SND_PCI_QUIRK(0x107B, 0x3450, NULL,
  727. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  728. SND_PCI_QUIRK(0x109F, 0x3134, NULL,
  729. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  730. SND_PCI_QUIRK(0x109F, 0x3161, NULL,
  731. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  732. SND_PCI_QUIRK(0x144D, 0x3280, NULL,
  733. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  734. SND_PCI_QUIRK(0x144D, 0x3281, NULL,
  735. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  736. SND_PCI_QUIRK(0x144D, 0xC002, NULL,
  737. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  738. SND_PCI_QUIRK(0x144D, 0xC003, NULL,
  739. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  740. SND_PCI_QUIRK(0x1509, 0x1740, NULL,
  741. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  742. SND_PCI_QUIRK(0x1610, 0x0010, NULL,
  743. HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
  744. SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
  745. SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
  746. SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
  747. SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
  748. SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
  749. /* Maestro3 chips */
  750. SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
  751. SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
  752. SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
  753. SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
  754. SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
  755. SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
  756. SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
  757. SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
  758. SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
  759. SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
  760. SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
  761. SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
  762. SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
  763. SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
  764. SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
  765. SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
  766. SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
  767. { } /* END */
  768. };
  769. /* HP Omnibook quirks */
  770. static const struct snd_pci_quirk m3_omnibook_quirk_list[] = {
  771. SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
  772. SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
  773. { } /* END */
  774. };
  775. /*
  776. * lowlevel functions
  777. */
  778. static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
  779. {
  780. outw(value, chip->iobase + reg);
  781. }
  782. static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
  783. {
  784. return inw(chip->iobase + reg);
  785. }
  786. static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
  787. {
  788. outb(value, chip->iobase + reg);
  789. }
  790. static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
  791. {
  792. return inb(chip->iobase + reg);
  793. }
  794. /*
  795. * access 16bit words to the code or data regions of the dsp's memory.
  796. * index addresses 16bit words.
  797. */
  798. static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
  799. {
  800. snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
  801. snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
  802. return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
  803. }
  804. static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
  805. {
  806. snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
  807. snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
  808. snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
  809. }
  810. static void snd_m3_assp_halt(struct snd_m3 *chip)
  811. {
  812. chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
  813. msleep(10);
  814. snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
  815. }
  816. static void snd_m3_assp_continue(struct snd_m3 *chip)
  817. {
  818. snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
  819. }
  820. /*
  821. * This makes me sad. the maestro3 has lists
  822. * internally that must be packed.. 0 terminates,
  823. * apparently, or maybe all unused entries have
  824. * to be 0, the lists have static lengths set
  825. * by the binary code images.
  826. */
  827. static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
  828. {
  829. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  830. list->mem_addr + list->curlen,
  831. val);
  832. return list->curlen++;
  833. }
  834. static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
  835. {
  836. u16 val;
  837. int lastindex = list->curlen - 1;
  838. if (index != lastindex) {
  839. val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
  840. list->mem_addr + lastindex);
  841. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  842. list->mem_addr + index,
  843. val);
  844. }
  845. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  846. list->mem_addr + lastindex,
  847. 0);
  848. list->curlen--;
  849. }
  850. static void snd_m3_inc_timer_users(struct snd_m3 *chip)
  851. {
  852. chip->timer_users++;
  853. if (chip->timer_users != 1)
  854. return;
  855. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  856. KDATA_TIMER_COUNT_RELOAD,
  857. 240);
  858. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  859. KDATA_TIMER_COUNT_CURRENT,
  860. 240);
  861. snd_m3_outw(chip,
  862. snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
  863. HOST_INT_CTRL);
  864. }
  865. static void snd_m3_dec_timer_users(struct snd_m3 *chip)
  866. {
  867. chip->timer_users--;
  868. if (chip->timer_users > 0)
  869. return;
  870. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  871. KDATA_TIMER_COUNT_RELOAD,
  872. 0);
  873. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  874. KDATA_TIMER_COUNT_CURRENT,
  875. 0);
  876. snd_m3_outw(chip,
  877. snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
  878. HOST_INT_CTRL);
  879. }
  880. /*
  881. * start/stop
  882. */
  883. /* spinlock held! */
  884. static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
  885. struct snd_pcm_substream *subs)
  886. {
  887. if (! s || ! subs)
  888. return -EINVAL;
  889. snd_m3_inc_timer_users(chip);
  890. switch (subs->stream) {
  891. case SNDRV_PCM_STREAM_PLAYBACK:
  892. chip->dacs_active++;
  893. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  894. s->inst.data + CDATA_INSTANCE_READY, 1);
  895. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  896. KDATA_MIXER_TASK_NUMBER,
  897. chip->dacs_active);
  898. break;
  899. case SNDRV_PCM_STREAM_CAPTURE:
  900. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  901. KDATA_ADC1_REQUEST, 1);
  902. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  903. s->inst.data + CDATA_INSTANCE_READY, 1);
  904. break;
  905. }
  906. return 0;
  907. }
  908. /* spinlock held! */
  909. static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
  910. struct snd_pcm_substream *subs)
  911. {
  912. if (! s || ! subs)
  913. return -EINVAL;
  914. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  915. s->inst.data + CDATA_INSTANCE_READY, 0);
  916. snd_m3_dec_timer_users(chip);
  917. switch (subs->stream) {
  918. case SNDRV_PCM_STREAM_PLAYBACK:
  919. chip->dacs_active--;
  920. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  921. KDATA_MIXER_TASK_NUMBER,
  922. chip->dacs_active);
  923. break;
  924. case SNDRV_PCM_STREAM_CAPTURE:
  925. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  926. KDATA_ADC1_REQUEST, 0);
  927. break;
  928. }
  929. return 0;
  930. }
  931. static int
  932. snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
  933. {
  934. struct snd_m3 *chip = snd_pcm_substream_chip(subs);
  935. struct m3_dma *s = subs->runtime->private_data;
  936. int err = -EINVAL;
  937. if (snd_BUG_ON(!s))
  938. return -ENXIO;
  939. spin_lock(&chip->reg_lock);
  940. switch (cmd) {
  941. case SNDRV_PCM_TRIGGER_START:
  942. case SNDRV_PCM_TRIGGER_RESUME:
  943. if (s->running)
  944. err = -EBUSY;
  945. else {
  946. s->running = 1;
  947. err = snd_m3_pcm_start(chip, s, subs);
  948. }
  949. break;
  950. case SNDRV_PCM_TRIGGER_STOP:
  951. case SNDRV_PCM_TRIGGER_SUSPEND:
  952. if (! s->running)
  953. err = 0; /* should return error? */
  954. else {
  955. s->running = 0;
  956. err = snd_m3_pcm_stop(chip, s, subs);
  957. }
  958. break;
  959. }
  960. spin_unlock(&chip->reg_lock);
  961. return err;
  962. }
  963. /*
  964. * setup
  965. */
  966. static void
  967. snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
  968. {
  969. int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
  970. struct snd_pcm_runtime *runtime = subs->runtime;
  971. if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  972. dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
  973. dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
  974. } else {
  975. dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
  976. dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
  977. }
  978. dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
  979. dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
  980. s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
  981. s->period_size = frames_to_bytes(runtime, runtime->period_size);
  982. s->hwptr = 0;
  983. s->count = 0;
  984. #define LO(x) ((x) & 0xffff)
  985. #define HI(x) LO((x) >> 16)
  986. /* host dma buffer pointers */
  987. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  988. s->inst.data + CDATA_HOST_SRC_ADDRL,
  989. LO(s->buffer_addr));
  990. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  991. s->inst.data + CDATA_HOST_SRC_ADDRH,
  992. HI(s->buffer_addr));
  993. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  994. s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
  995. LO(s->buffer_addr + s->dma_size));
  996. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  997. s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
  998. HI(s->buffer_addr + s->dma_size));
  999. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1000. s->inst.data + CDATA_HOST_SRC_CURRENTL,
  1001. LO(s->buffer_addr));
  1002. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1003. s->inst.data + CDATA_HOST_SRC_CURRENTH,
  1004. HI(s->buffer_addr));
  1005. #undef LO
  1006. #undef HI
  1007. /* dsp buffers */
  1008. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1009. s->inst.data + CDATA_IN_BUF_BEGIN,
  1010. dsp_in_buffer);
  1011. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1012. s->inst.data + CDATA_IN_BUF_END_PLUS_1,
  1013. dsp_in_buffer + (dsp_in_size / 2));
  1014. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1015. s->inst.data + CDATA_IN_BUF_HEAD,
  1016. dsp_in_buffer);
  1017. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1018. s->inst.data + CDATA_IN_BUF_TAIL,
  1019. dsp_in_buffer);
  1020. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1021. s->inst.data + CDATA_OUT_BUF_BEGIN,
  1022. dsp_out_buffer);
  1023. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1024. s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
  1025. dsp_out_buffer + (dsp_out_size / 2));
  1026. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1027. s->inst.data + CDATA_OUT_BUF_HEAD,
  1028. dsp_out_buffer);
  1029. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1030. s->inst.data + CDATA_OUT_BUF_TAIL,
  1031. dsp_out_buffer);
  1032. }
  1033. static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
  1034. struct snd_pcm_runtime *runtime)
  1035. {
  1036. u32 freq;
  1037. /*
  1038. * put us in the lists if we're not already there
  1039. */
  1040. if (! s->in_lists) {
  1041. s->index[0] = snd_m3_add_list(chip, s->index_list[0],
  1042. s->inst.data >> DP_SHIFT_COUNT);
  1043. s->index[1] = snd_m3_add_list(chip, s->index_list[1],
  1044. s->inst.data >> DP_SHIFT_COUNT);
  1045. s->index[2] = snd_m3_add_list(chip, s->index_list[2],
  1046. s->inst.data >> DP_SHIFT_COUNT);
  1047. s->in_lists = 1;
  1048. }
  1049. /* write to 'mono' word */
  1050. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1051. s->inst.data + SRC3_DIRECTION_OFFSET + 1,
  1052. runtime->channels == 2 ? 0 : 1);
  1053. /* write to '8bit' word */
  1054. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1055. s->inst.data + SRC3_DIRECTION_OFFSET + 2,
  1056. snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
  1057. /* set up dac/adc rate */
  1058. freq = ((runtime->rate << 15) + 24000 ) / 48000;
  1059. if (freq)
  1060. freq--;
  1061. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1062. s->inst.data + CDATA_FREQUENCY,
  1063. freq);
  1064. }
  1065. static const struct play_vals {
  1066. u16 addr, val;
  1067. } pv[] = {
  1068. {CDATA_LEFT_VOLUME, ARB_VOLUME},
  1069. {CDATA_RIGHT_VOLUME, ARB_VOLUME},
  1070. {SRC3_DIRECTION_OFFSET, 0} ,
  1071. /* +1, +2 are stereo/16 bit */
  1072. {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
  1073. {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
  1074. {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
  1075. {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
  1076. {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
  1077. {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
  1078. {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
  1079. {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
  1080. {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
  1081. {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
  1082. {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
  1083. {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
  1084. {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
  1085. {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
  1086. {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
  1087. {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
  1088. {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
  1089. };
  1090. /* the mode passed should be already shifted and masked */
  1091. static void
  1092. snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
  1093. struct snd_pcm_substream *subs)
  1094. {
  1095. unsigned int i;
  1096. /*
  1097. * some per client initializers
  1098. */
  1099. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1100. s->inst.data + SRC3_DIRECTION_OFFSET + 12,
  1101. s->inst.data + 40 + 8);
  1102. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1103. s->inst.data + SRC3_DIRECTION_OFFSET + 19,
  1104. s->inst.code + MINISRC_COEF_LOC);
  1105. /* enable or disable low pass filter? */
  1106. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1107. s->inst.data + SRC3_DIRECTION_OFFSET + 22,
  1108. subs->runtime->rate > 45000 ? 0xff : 0);
  1109. /* tell it which way dma is going? */
  1110. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1111. s->inst.data + CDATA_DMA_CONTROL,
  1112. DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
  1113. /*
  1114. * set an armload of static initializers
  1115. */
  1116. for (i = 0; i < ARRAY_SIZE(pv); i++)
  1117. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1118. s->inst.data + pv[i].addr, pv[i].val);
  1119. }
  1120. /*
  1121. * Native record driver
  1122. */
  1123. static const struct rec_vals {
  1124. u16 addr, val;
  1125. } rv[] = {
  1126. {CDATA_LEFT_VOLUME, ARB_VOLUME},
  1127. {CDATA_RIGHT_VOLUME, ARB_VOLUME},
  1128. {SRC3_DIRECTION_OFFSET, 1} ,
  1129. /* +1, +2 are stereo/16 bit */
  1130. {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
  1131. {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
  1132. {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
  1133. {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
  1134. {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
  1135. {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
  1136. {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
  1137. {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
  1138. {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
  1139. {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
  1140. {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
  1141. {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
  1142. {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
  1143. {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
  1144. {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
  1145. {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
  1146. {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
  1147. {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
  1148. {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
  1149. };
  1150. static void
  1151. snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
  1152. {
  1153. unsigned int i;
  1154. /*
  1155. * some per client initializers
  1156. */
  1157. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1158. s->inst.data + SRC3_DIRECTION_OFFSET + 12,
  1159. s->inst.data + 40 + 8);
  1160. /* tell it which way dma is going? */
  1161. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1162. s->inst.data + CDATA_DMA_CONTROL,
  1163. DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
  1164. DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
  1165. /*
  1166. * set an armload of static initializers
  1167. */
  1168. for (i = 0; i < ARRAY_SIZE(rv); i++)
  1169. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1170. s->inst.data + rv[i].addr, rv[i].val);
  1171. }
  1172. static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
  1173. struct snd_pcm_hw_params *hw_params)
  1174. {
  1175. struct m3_dma *s = substream->runtime->private_data;
  1176. /* set buffer address */
  1177. s->buffer_addr = substream->runtime->dma_addr;
  1178. if (s->buffer_addr & 0x3) {
  1179. dev_err(substream->pcm->card->dev, "oh my, not aligned\n");
  1180. s->buffer_addr = s->buffer_addr & ~0x3;
  1181. }
  1182. return 0;
  1183. }
  1184. static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
  1185. {
  1186. struct m3_dma *s;
  1187. if (substream->runtime->private_data == NULL)
  1188. return 0;
  1189. s = substream->runtime->private_data;
  1190. s->buffer_addr = 0;
  1191. return 0;
  1192. }
  1193. static int
  1194. snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
  1195. {
  1196. struct snd_m3 *chip = snd_pcm_substream_chip(subs);
  1197. struct snd_pcm_runtime *runtime = subs->runtime;
  1198. struct m3_dma *s = runtime->private_data;
  1199. if (snd_BUG_ON(!s))
  1200. return -ENXIO;
  1201. if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
  1202. runtime->format != SNDRV_PCM_FORMAT_S16_LE)
  1203. return -EINVAL;
  1204. if (runtime->rate > 48000 ||
  1205. runtime->rate < 8000)
  1206. return -EINVAL;
  1207. spin_lock_irq(&chip->reg_lock);
  1208. snd_m3_pcm_setup1(chip, s, subs);
  1209. if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
  1210. snd_m3_playback_setup(chip, s, subs);
  1211. else
  1212. snd_m3_capture_setup(chip, s, subs);
  1213. snd_m3_pcm_setup2(chip, s, runtime);
  1214. spin_unlock_irq(&chip->reg_lock);
  1215. return 0;
  1216. }
  1217. /*
  1218. * get current pointer
  1219. */
  1220. static unsigned int
  1221. snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
  1222. {
  1223. u16 hi = 0, lo = 0;
  1224. int retry = 10;
  1225. u32 addr;
  1226. /*
  1227. * try and get a valid answer
  1228. */
  1229. while (retry--) {
  1230. hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
  1231. s->inst.data + CDATA_HOST_SRC_CURRENTH);
  1232. lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
  1233. s->inst.data + CDATA_HOST_SRC_CURRENTL);
  1234. if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
  1235. s->inst.data + CDATA_HOST_SRC_CURRENTH))
  1236. break;
  1237. }
  1238. addr = lo | ((u32)hi<<16);
  1239. return (unsigned int)(addr - s->buffer_addr);
  1240. }
  1241. static snd_pcm_uframes_t
  1242. snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
  1243. {
  1244. struct snd_m3 *chip = snd_pcm_substream_chip(subs);
  1245. unsigned int ptr;
  1246. struct m3_dma *s = subs->runtime->private_data;
  1247. if (snd_BUG_ON(!s))
  1248. return 0;
  1249. spin_lock(&chip->reg_lock);
  1250. ptr = snd_m3_get_pointer(chip, s, subs);
  1251. spin_unlock(&chip->reg_lock);
  1252. return bytes_to_frames(subs->runtime, ptr);
  1253. }
  1254. /* update pointer */
  1255. /* spinlock held! */
  1256. static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
  1257. {
  1258. struct snd_pcm_substream *subs = s->substream;
  1259. unsigned int hwptr;
  1260. int diff;
  1261. if (! s->running)
  1262. return;
  1263. hwptr = snd_m3_get_pointer(chip, s, subs);
  1264. /* try to avoid expensive modulo divisions */
  1265. if (hwptr >= s->dma_size)
  1266. hwptr %= s->dma_size;
  1267. diff = s->dma_size + hwptr - s->hwptr;
  1268. if (diff >= s->dma_size)
  1269. diff %= s->dma_size;
  1270. s->hwptr = hwptr;
  1271. s->count += diff;
  1272. if (s->count >= (signed)s->period_size) {
  1273. if (s->count < 2 * (signed)s->period_size)
  1274. s->count -= (signed)s->period_size;
  1275. else
  1276. s->count %= s->period_size;
  1277. spin_unlock(&chip->reg_lock);
  1278. snd_pcm_period_elapsed(subs);
  1279. spin_lock(&chip->reg_lock);
  1280. }
  1281. }
  1282. /* The m3's hardware volume works by incrementing / decrementing 2 counters
  1283. (without wrap around) in response to volume button presses and then
  1284. generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
  1285. of a byte wide register. The meaning of bits 0 and 4 is unknown. */
  1286. static void snd_m3_update_hw_volume(struct work_struct *work)
  1287. {
  1288. struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work);
  1289. int x, val;
  1290. /* Figure out which volume control button was pushed,
  1291. based on differences from the default register
  1292. values. */
  1293. x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
  1294. /* Reset the volume counters to 4. Tests on the allegro integrated
  1295. into a Compaq N600C laptop, have revealed that:
  1296. 1) Writing any value will result in the 2 counters being reset to
  1297. 4 so writing 0x88 is not strictly necessary
  1298. 2) Writing to any of the 4 involved registers will reset all 4
  1299. of them (and reading them always returns the same value for all
  1300. of them)
  1301. It could be that a maestro deviates from this, so leave the code
  1302. as is. */
  1303. outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
  1304. outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
  1305. outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
  1306. outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
  1307. /* Ignore spurious HV interrupts during suspend / resume, this avoids
  1308. mistaking them for a mute button press. */
  1309. if (chip->in_suspend)
  1310. return;
  1311. #ifndef CONFIG_SND_MAESTRO3_INPUT
  1312. if (!chip->master_switch || !chip->master_volume)
  1313. return;
  1314. val = snd_ac97_read(chip->ac97, AC97_MASTER);
  1315. switch (x) {
  1316. case 0x88:
  1317. /* The counters have not changed, yet we've received a HV
  1318. interrupt. According to tests run by various people this
  1319. happens when pressing the mute button. */
  1320. val ^= 0x8000;
  1321. break;
  1322. case 0xaa:
  1323. /* counters increased by 1 -> volume up */
  1324. if ((val & 0x7f) > 0)
  1325. val--;
  1326. if ((val & 0x7f00) > 0)
  1327. val -= 0x0100;
  1328. break;
  1329. case 0x66:
  1330. /* counters decreased by 1 -> volume down */
  1331. if ((val & 0x7f) < 0x1f)
  1332. val++;
  1333. if ((val & 0x7f00) < 0x1f00)
  1334. val += 0x0100;
  1335. break;
  1336. }
  1337. if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
  1338. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
  1339. &chip->master_switch->id);
  1340. #else
  1341. if (!chip->input_dev)
  1342. return;
  1343. val = 0;
  1344. switch (x) {
  1345. case 0x88:
  1346. /* The counters have not changed, yet we've received a HV
  1347. interrupt. According to tests run by various people this
  1348. happens when pressing the mute button. */
  1349. val = KEY_MUTE;
  1350. break;
  1351. case 0xaa:
  1352. /* counters increased by 1 -> volume up */
  1353. val = KEY_VOLUMEUP;
  1354. break;
  1355. case 0x66:
  1356. /* counters decreased by 1 -> volume down */
  1357. val = KEY_VOLUMEDOWN;
  1358. break;
  1359. }
  1360. if (val) {
  1361. input_report_key(chip->input_dev, val, 1);
  1362. input_sync(chip->input_dev);
  1363. input_report_key(chip->input_dev, val, 0);
  1364. input_sync(chip->input_dev);
  1365. }
  1366. #endif
  1367. }
  1368. static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
  1369. {
  1370. struct snd_m3 *chip = dev_id;
  1371. u8 status;
  1372. int i;
  1373. status = inb(chip->iobase + HOST_INT_STATUS);
  1374. if (status == 0xff)
  1375. return IRQ_NONE;
  1376. if (status & HV_INT_PENDING)
  1377. schedule_work(&chip->hwvol_work);
  1378. /*
  1379. * ack an assp int if its running
  1380. * and has an int pending
  1381. */
  1382. if (status & ASSP_INT_PENDING) {
  1383. u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
  1384. if (!(ctl & STOP_ASSP_CLOCK)) {
  1385. ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
  1386. if (ctl & DSP2HOST_REQ_TIMER) {
  1387. outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
  1388. /* update adc/dac info if it was a timer int */
  1389. spin_lock(&chip->reg_lock);
  1390. for (i = 0; i < chip->num_substreams; i++) {
  1391. struct m3_dma *s = &chip->substreams[i];
  1392. if (s->running)
  1393. snd_m3_update_ptr(chip, s);
  1394. }
  1395. spin_unlock(&chip->reg_lock);
  1396. }
  1397. }
  1398. }
  1399. #if 0 /* TODO: not supported yet */
  1400. if ((status & MPU401_INT_PENDING) && chip->rmidi)
  1401. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
  1402. #endif
  1403. /* ack ints */
  1404. outb(status, chip->iobase + HOST_INT_STATUS);
  1405. return IRQ_HANDLED;
  1406. }
  1407. /*
  1408. */
  1409. static const struct snd_pcm_hardware snd_m3_playback =
  1410. {
  1411. .info = (SNDRV_PCM_INFO_MMAP |
  1412. SNDRV_PCM_INFO_INTERLEAVED |
  1413. SNDRV_PCM_INFO_MMAP_VALID |
  1414. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1415. /*SNDRV_PCM_INFO_PAUSE |*/
  1416. SNDRV_PCM_INFO_RESUME),
  1417. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  1418. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  1419. .rate_min = 8000,
  1420. .rate_max = 48000,
  1421. .channels_min = 1,
  1422. .channels_max = 2,
  1423. .buffer_bytes_max = (512*1024),
  1424. .period_bytes_min = 64,
  1425. .period_bytes_max = (512*1024),
  1426. .periods_min = 1,
  1427. .periods_max = 1024,
  1428. };
  1429. static const struct snd_pcm_hardware snd_m3_capture =
  1430. {
  1431. .info = (SNDRV_PCM_INFO_MMAP |
  1432. SNDRV_PCM_INFO_INTERLEAVED |
  1433. SNDRV_PCM_INFO_MMAP_VALID |
  1434. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1435. /*SNDRV_PCM_INFO_PAUSE |*/
  1436. SNDRV_PCM_INFO_RESUME),
  1437. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  1438. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  1439. .rate_min = 8000,
  1440. .rate_max = 48000,
  1441. .channels_min = 1,
  1442. .channels_max = 2,
  1443. .buffer_bytes_max = (512*1024),
  1444. .period_bytes_min = 64,
  1445. .period_bytes_max = (512*1024),
  1446. .periods_min = 1,
  1447. .periods_max = 1024,
  1448. };
  1449. /*
  1450. */
  1451. static int
  1452. snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
  1453. {
  1454. int i;
  1455. struct m3_dma *s;
  1456. spin_lock_irq(&chip->reg_lock);
  1457. for (i = 0; i < chip->num_substreams; i++) {
  1458. s = &chip->substreams[i];
  1459. if (! s->opened)
  1460. goto __found;
  1461. }
  1462. spin_unlock_irq(&chip->reg_lock);
  1463. return -ENOMEM;
  1464. __found:
  1465. s->opened = 1;
  1466. s->running = 0;
  1467. spin_unlock_irq(&chip->reg_lock);
  1468. subs->runtime->private_data = s;
  1469. s->substream = subs;
  1470. /* set list owners */
  1471. if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  1472. s->index_list[0] = &chip->mixer_list;
  1473. } else
  1474. s->index_list[0] = &chip->adc1_list;
  1475. s->index_list[1] = &chip->msrc_list;
  1476. s->index_list[2] = &chip->dma_list;
  1477. return 0;
  1478. }
  1479. static void
  1480. snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
  1481. {
  1482. struct m3_dma *s = subs->runtime->private_data;
  1483. if (s == NULL)
  1484. return; /* not opened properly */
  1485. spin_lock_irq(&chip->reg_lock);
  1486. if (s->substream && s->running)
  1487. snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
  1488. if (s->in_lists) {
  1489. snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
  1490. snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
  1491. snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
  1492. s->in_lists = 0;
  1493. }
  1494. s->running = 0;
  1495. s->opened = 0;
  1496. spin_unlock_irq(&chip->reg_lock);
  1497. }
  1498. static int
  1499. snd_m3_playback_open(struct snd_pcm_substream *subs)
  1500. {
  1501. struct snd_m3 *chip = snd_pcm_substream_chip(subs);
  1502. struct snd_pcm_runtime *runtime = subs->runtime;
  1503. int err;
  1504. if ((err = snd_m3_substream_open(chip, subs)) < 0)
  1505. return err;
  1506. runtime->hw = snd_m3_playback;
  1507. return 0;
  1508. }
  1509. static int
  1510. snd_m3_playback_close(struct snd_pcm_substream *subs)
  1511. {
  1512. struct snd_m3 *chip = snd_pcm_substream_chip(subs);
  1513. snd_m3_substream_close(chip, subs);
  1514. return 0;
  1515. }
  1516. static int
  1517. snd_m3_capture_open(struct snd_pcm_substream *subs)
  1518. {
  1519. struct snd_m3 *chip = snd_pcm_substream_chip(subs);
  1520. struct snd_pcm_runtime *runtime = subs->runtime;
  1521. int err;
  1522. if ((err = snd_m3_substream_open(chip, subs)) < 0)
  1523. return err;
  1524. runtime->hw = snd_m3_capture;
  1525. return 0;
  1526. }
  1527. static int
  1528. snd_m3_capture_close(struct snd_pcm_substream *subs)
  1529. {
  1530. struct snd_m3 *chip = snd_pcm_substream_chip(subs);
  1531. snd_m3_substream_close(chip, subs);
  1532. return 0;
  1533. }
  1534. /*
  1535. * create pcm instance
  1536. */
  1537. static const struct snd_pcm_ops snd_m3_playback_ops = {
  1538. .open = snd_m3_playback_open,
  1539. .close = snd_m3_playback_close,
  1540. .hw_params = snd_m3_pcm_hw_params,
  1541. .hw_free = snd_m3_pcm_hw_free,
  1542. .prepare = snd_m3_pcm_prepare,
  1543. .trigger = snd_m3_pcm_trigger,
  1544. .pointer = snd_m3_pcm_pointer,
  1545. };
  1546. static const struct snd_pcm_ops snd_m3_capture_ops = {
  1547. .open = snd_m3_capture_open,
  1548. .close = snd_m3_capture_close,
  1549. .hw_params = snd_m3_pcm_hw_params,
  1550. .hw_free = snd_m3_pcm_hw_free,
  1551. .prepare = snd_m3_pcm_prepare,
  1552. .trigger = snd_m3_pcm_trigger,
  1553. .pointer = snd_m3_pcm_pointer,
  1554. };
  1555. static int
  1556. snd_m3_pcm(struct snd_m3 * chip, int device)
  1557. {
  1558. struct snd_pcm *pcm;
  1559. int err;
  1560. err = snd_pcm_new(chip->card, chip->card->driver, device,
  1561. MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
  1562. if (err < 0)
  1563. return err;
  1564. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
  1565. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
  1566. pcm->private_data = chip;
  1567. pcm->info_flags = 0;
  1568. strcpy(pcm->name, chip->card->driver);
  1569. chip->pcm = pcm;
  1570. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1571. &chip->pci->dev, 64*1024, 64*1024);
  1572. return 0;
  1573. }
  1574. /*
  1575. * ac97 interface
  1576. */
  1577. /*
  1578. * Wait for the ac97 serial bus to be free.
  1579. * return nonzero if the bus is still busy.
  1580. */
  1581. static int snd_m3_ac97_wait(struct snd_m3 *chip)
  1582. {
  1583. int i = 10000;
  1584. do {
  1585. if (! (snd_m3_inb(chip, 0x30) & 1))
  1586. return 0;
  1587. cpu_relax();
  1588. } while (i-- > 0);
  1589. dev_err(chip->card->dev, "ac97 serial bus busy\n");
  1590. return 1;
  1591. }
  1592. static unsigned short
  1593. snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  1594. {
  1595. struct snd_m3 *chip = ac97->private_data;
  1596. unsigned short data = 0xffff;
  1597. if (snd_m3_ac97_wait(chip))
  1598. goto fail;
  1599. snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
  1600. if (snd_m3_ac97_wait(chip))
  1601. goto fail;
  1602. data = snd_m3_inw(chip, CODEC_DATA);
  1603. fail:
  1604. return data;
  1605. }
  1606. static void
  1607. snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
  1608. {
  1609. struct snd_m3 *chip = ac97->private_data;
  1610. if (snd_m3_ac97_wait(chip))
  1611. return;
  1612. snd_m3_outw(chip, val, CODEC_DATA);
  1613. snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
  1614. /*
  1615. * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent
  1616. * until the MASTER volume or mute is touched (alsactl restore does not
  1617. * work).
  1618. */
  1619. if (ac97->id == 0x45838308 && reg == AC97_MASTER) {
  1620. snd_m3_ac97_wait(chip);
  1621. snd_m3_outw(chip, val, CODEC_DATA);
  1622. snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
  1623. }
  1624. }
  1625. static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote)
  1626. {
  1627. int io = chip->iobase;
  1628. u16 tmp;
  1629. isremote = isremote ? 1 : 0;
  1630. tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK;
  1631. /* enable dock on Dell Latitude C810 */
  1632. if (chip->pci->subsystem_vendor == 0x1028 &&
  1633. chip->pci->subsystem_device == 0x00e5)
  1634. tmp |= M3I_DOCK_ENABLE;
  1635. outw(tmp | isremote, io + RING_BUS_CTRL_B);
  1636. outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
  1637. io + SDO_OUT_DEST_CTRL);
  1638. outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
  1639. io + SDO_IN_DEST_CTRL);
  1640. }
  1641. /*
  1642. * hack, returns non zero on err
  1643. */
  1644. static int snd_m3_try_read_vendor(struct snd_m3 *chip)
  1645. {
  1646. u16 ret;
  1647. if (snd_m3_ac97_wait(chip))
  1648. return 1;
  1649. snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
  1650. if (snd_m3_ac97_wait(chip))
  1651. return 1;
  1652. ret = snd_m3_inw(chip, 0x32);
  1653. return (ret == 0) || (ret == 0xffff);
  1654. }
  1655. static void snd_m3_ac97_reset(struct snd_m3 *chip)
  1656. {
  1657. u16 dir;
  1658. int delay1 = 0, delay2 = 0, i;
  1659. int io = chip->iobase;
  1660. if (chip->allegro_flag) {
  1661. /*
  1662. * the onboard codec on the allegro seems
  1663. * to want to wait a very long time before
  1664. * coming back to life
  1665. */
  1666. delay1 = 50;
  1667. delay2 = 800;
  1668. } else {
  1669. /* maestro3 */
  1670. delay1 = 20;
  1671. delay2 = 500;
  1672. }
  1673. for (i = 0; i < 5; i++) {
  1674. dir = inw(io + GPIO_DIRECTION);
  1675. if (!chip->irda_workaround)
  1676. dir |= 0x10; /* assuming pci bus master? */
  1677. snd_m3_remote_codec_config(chip, 0);
  1678. outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
  1679. udelay(20);
  1680. outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
  1681. outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
  1682. outw(0, io + GPIO_DATA);
  1683. outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
  1684. schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
  1685. outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
  1686. udelay(5);
  1687. /* ok, bring back the ac-link */
  1688. outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
  1689. outw(~0, io + GPIO_MASK);
  1690. schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
  1691. if (! snd_m3_try_read_vendor(chip))
  1692. break;
  1693. delay1 += 10;
  1694. delay2 += 100;
  1695. dev_dbg(chip->card->dev,
  1696. "retrying codec reset with delays of %d and %d ms\n",
  1697. delay1, delay2);
  1698. }
  1699. #if 0
  1700. /* more gung-ho reset that doesn't
  1701. * seem to work anywhere :)
  1702. */
  1703. tmp = inw(io + RING_BUS_CTRL_A);
  1704. outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
  1705. msleep(20);
  1706. outw(tmp, io + RING_BUS_CTRL_A);
  1707. msleep(50);
  1708. #endif
  1709. }
  1710. static int snd_m3_mixer(struct snd_m3 *chip)
  1711. {
  1712. struct snd_ac97_bus *pbus;
  1713. struct snd_ac97_template ac97;
  1714. #ifndef CONFIG_SND_MAESTRO3_INPUT
  1715. struct snd_ctl_elem_id elem_id;
  1716. #endif
  1717. int err;
  1718. static const struct snd_ac97_bus_ops ops = {
  1719. .write = snd_m3_ac97_write,
  1720. .read = snd_m3_ac97_read,
  1721. };
  1722. if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
  1723. return err;
  1724. memset(&ac97, 0, sizeof(ac97));
  1725. ac97.private_data = chip;
  1726. if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
  1727. return err;
  1728. /* seems ac97 PCM needs initialization.. hack hack.. */
  1729. snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
  1730. schedule_timeout_uninterruptible(msecs_to_jiffies(100));
  1731. snd_ac97_write(chip->ac97, AC97_PCM, 0);
  1732. #ifndef CONFIG_SND_MAESTRO3_INPUT
  1733. memset(&elem_id, 0, sizeof(elem_id));
  1734. elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1735. strcpy(elem_id.name, "Master Playback Switch");
  1736. chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
  1737. memset(&elem_id, 0, sizeof(elem_id));
  1738. elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1739. strcpy(elem_id.name, "Master Playback Volume");
  1740. chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
  1741. #endif
  1742. return 0;
  1743. }
  1744. /*
  1745. * initialize ASSP
  1746. */
  1747. #define MINISRC_LPF_LEN 10
  1748. static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
  1749. 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
  1750. 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
  1751. };
  1752. static void snd_m3_assp_init(struct snd_m3 *chip)
  1753. {
  1754. unsigned int i;
  1755. const __le16 *data;
  1756. /* zero kernel data */
  1757. for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
  1758. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1759. KDATA_BASE_ADDR + i, 0);
  1760. /* zero mixer data? */
  1761. for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
  1762. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1763. KDATA_BASE_ADDR2 + i, 0);
  1764. /* init dma pointer */
  1765. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1766. KDATA_CURRENT_DMA,
  1767. KDATA_DMA_XFER0);
  1768. /* write kernel into code memory.. */
  1769. data = (const __le16 *)chip->assp_kernel_image->data;
  1770. for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
  1771. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
  1772. REV_B_CODE_MEMORY_BEGIN + i,
  1773. le16_to_cpu(data[i]));
  1774. }
  1775. /*
  1776. * We only have this one client and we know that 0x400
  1777. * is free in our kernel's mem map, so lets just
  1778. * drop it there. It seems that the minisrc doesn't
  1779. * need vectors, so we won't bother with them..
  1780. */
  1781. data = (const __le16 *)chip->assp_minisrc_image->data;
  1782. for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
  1783. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
  1784. 0x400 + i, le16_to_cpu(data[i]));
  1785. }
  1786. /*
  1787. * write the coefficients for the low pass filter?
  1788. */
  1789. for (i = 0; i < MINISRC_LPF_LEN ; i++) {
  1790. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
  1791. 0x400 + MINISRC_COEF_LOC + i,
  1792. minisrc_lpf[i]);
  1793. }
  1794. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
  1795. 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
  1796. 0x8000);
  1797. /*
  1798. * the minisrc is the only thing on
  1799. * our task list..
  1800. */
  1801. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1802. KDATA_TASK0,
  1803. 0x400);
  1804. /*
  1805. * init the mixer number..
  1806. */
  1807. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1808. KDATA_MIXER_TASK_NUMBER,0);
  1809. /*
  1810. * EXTREME KERNEL MASTER VOLUME
  1811. */
  1812. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1813. KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
  1814. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1815. KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
  1816. chip->mixer_list.curlen = 0;
  1817. chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
  1818. chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
  1819. chip->adc1_list.curlen = 0;
  1820. chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
  1821. chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
  1822. chip->dma_list.curlen = 0;
  1823. chip->dma_list.mem_addr = KDATA_DMA_XFER0;
  1824. chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
  1825. chip->msrc_list.curlen = 0;
  1826. chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
  1827. chip->msrc_list.max = MAX_INSTANCE_MINISRC;
  1828. }
  1829. static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
  1830. {
  1831. int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
  1832. MINISRC_IN_BUFFER_SIZE / 2 +
  1833. 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
  1834. int address, i;
  1835. /*
  1836. * the revb memory map has 0x1100 through 0x1c00
  1837. * free.
  1838. */
  1839. /*
  1840. * align instance address to 256 bytes so that its
  1841. * shifted list address is aligned.
  1842. * list address = (mem address >> 1) >> 7;
  1843. */
  1844. data_bytes = ALIGN(data_bytes, 256);
  1845. address = 0x1100 + ((data_bytes/2) * index);
  1846. if ((address + (data_bytes/2)) >= 0x1c00) {
  1847. dev_err(chip->card->dev,
  1848. "no memory for %d bytes at ind %d (addr 0x%x)\n",
  1849. data_bytes, index, address);
  1850. return -ENOMEM;
  1851. }
  1852. s->number = index;
  1853. s->inst.code = 0x400;
  1854. s->inst.data = address;
  1855. for (i = data_bytes / 2; i > 0; address++, i--) {
  1856. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  1857. address, 0);
  1858. }
  1859. return 0;
  1860. }
  1861. /*
  1862. * this works for the reference board, have to find
  1863. * out about others
  1864. *
  1865. * this needs more magic for 4 speaker, but..
  1866. */
  1867. static void
  1868. snd_m3_amp_enable(struct snd_m3 *chip, int enable)
  1869. {
  1870. int io = chip->iobase;
  1871. u16 gpo, polarity;
  1872. if (! chip->external_amp)
  1873. return;
  1874. polarity = enable ? 0 : 1;
  1875. polarity = polarity << chip->amp_gpio;
  1876. gpo = 1 << chip->amp_gpio;
  1877. outw(~gpo, io + GPIO_MASK);
  1878. outw(inw(io + GPIO_DIRECTION) | gpo,
  1879. io + GPIO_DIRECTION);
  1880. outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
  1881. io + GPIO_DATA);
  1882. outw(0xffff, io + GPIO_MASK);
  1883. }
  1884. static void
  1885. snd_m3_hv_init(struct snd_m3 *chip)
  1886. {
  1887. unsigned long io = chip->iobase;
  1888. u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
  1889. if (!chip->is_omnibook)
  1890. return;
  1891. /*
  1892. * Volume buttons on some HP OmniBook laptops
  1893. * require some GPIO magic to work correctly.
  1894. */
  1895. outw(0xffff, io + GPIO_MASK);
  1896. outw(0x0000, io + GPIO_DATA);
  1897. outw(~val, io + GPIO_MASK);
  1898. outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
  1899. outw(val, io + GPIO_MASK);
  1900. outw(0xffff, io + GPIO_MASK);
  1901. }
  1902. static int
  1903. snd_m3_chip_init(struct snd_m3 *chip)
  1904. {
  1905. struct pci_dev *pcidev = chip->pci;
  1906. unsigned long io = chip->iobase;
  1907. u32 n;
  1908. u16 w;
  1909. u8 t; /* makes as much sense as 'n', no? */
  1910. pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
  1911. w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
  1912. MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
  1913. DISABLE_LEGACY);
  1914. pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
  1915. pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
  1916. n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
  1917. n |= chip->hv_config;
  1918. /* For some reason we must always use reduced debounce. */
  1919. n |= REDUCED_DEBOUNCE;
  1920. n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
  1921. pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
  1922. outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
  1923. pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
  1924. n &= ~INT_CLK_SELECT;
  1925. if (!chip->allegro_flag) {
  1926. n &= ~INT_CLK_MULT_ENABLE;
  1927. n |= INT_CLK_SRC_NOT_PCI;
  1928. }
  1929. n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
  1930. pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
  1931. if (chip->allegro_flag) {
  1932. pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
  1933. n |= IN_CLK_12MHZ_SELECT;
  1934. pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
  1935. }
  1936. t = inb(chip->iobase + ASSP_CONTROL_A);
  1937. t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
  1938. t |= ASSP_CLK_49MHZ_SELECT;
  1939. t |= ASSP_0_WS_ENABLE;
  1940. outb(t, chip->iobase + ASSP_CONTROL_A);
  1941. snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
  1942. outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
  1943. outb(0x00, io + HARDWARE_VOL_CTRL);
  1944. outb(0x88, io + SHADOW_MIX_REG_VOICE);
  1945. outb(0x88, io + HW_VOL_COUNTER_VOICE);
  1946. outb(0x88, io + SHADOW_MIX_REG_MASTER);
  1947. outb(0x88, io + HW_VOL_COUNTER_MASTER);
  1948. return 0;
  1949. }
  1950. static void
  1951. snd_m3_enable_ints(struct snd_m3 *chip)
  1952. {
  1953. unsigned long io = chip->iobase;
  1954. unsigned short val;
  1955. /* TODO: MPU401 not supported yet */
  1956. val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
  1957. if (chip->hv_config & HV_CTRL_ENABLE)
  1958. val |= HV_INT_ENABLE;
  1959. outb(val, chip->iobase + HOST_INT_STATUS);
  1960. outw(val, io + HOST_INT_CTRL);
  1961. outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
  1962. io + ASSP_CONTROL_C);
  1963. }
  1964. /*
  1965. */
  1966. static int snd_m3_free(struct snd_m3 *chip)
  1967. {
  1968. struct m3_dma *s;
  1969. int i;
  1970. cancel_work_sync(&chip->hwvol_work);
  1971. #ifdef CONFIG_SND_MAESTRO3_INPUT
  1972. if (chip->input_dev)
  1973. input_unregister_device(chip->input_dev);
  1974. #endif
  1975. if (chip->substreams) {
  1976. spin_lock_irq(&chip->reg_lock);
  1977. for (i = 0; i < chip->num_substreams; i++) {
  1978. s = &chip->substreams[i];
  1979. /* check surviving pcms; this should not happen though.. */
  1980. if (s->substream && s->running)
  1981. snd_m3_pcm_stop(chip, s, s->substream);
  1982. }
  1983. spin_unlock_irq(&chip->reg_lock);
  1984. kfree(chip->substreams);
  1985. }
  1986. if (chip->iobase) {
  1987. outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
  1988. }
  1989. #ifdef CONFIG_PM_SLEEP
  1990. vfree(chip->suspend_mem);
  1991. #endif
  1992. if (chip->irq >= 0)
  1993. free_irq(chip->irq, chip);
  1994. if (chip->iobase)
  1995. pci_release_regions(chip->pci);
  1996. release_firmware(chip->assp_kernel_image);
  1997. release_firmware(chip->assp_minisrc_image);
  1998. pci_disable_device(chip->pci);
  1999. kfree(chip);
  2000. return 0;
  2001. }
  2002. /*
  2003. * APM support
  2004. */
  2005. #ifdef CONFIG_PM_SLEEP
  2006. static int m3_suspend(struct device *dev)
  2007. {
  2008. struct snd_card *card = dev_get_drvdata(dev);
  2009. struct snd_m3 *chip = card->private_data;
  2010. int i, dsp_index;
  2011. if (chip->suspend_mem == NULL)
  2012. return 0;
  2013. chip->in_suspend = 1;
  2014. cancel_work_sync(&chip->hwvol_work);
  2015. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2016. snd_ac97_suspend(chip->ac97);
  2017. msleep(10); /* give the assp a chance to idle.. */
  2018. snd_m3_assp_halt(chip);
  2019. /* save dsp image */
  2020. dsp_index = 0;
  2021. for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
  2022. chip->suspend_mem[dsp_index++] =
  2023. snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
  2024. for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
  2025. chip->suspend_mem[dsp_index++] =
  2026. snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
  2027. return 0;
  2028. }
  2029. static int m3_resume(struct device *dev)
  2030. {
  2031. struct snd_card *card = dev_get_drvdata(dev);
  2032. struct snd_m3 *chip = card->private_data;
  2033. int i, dsp_index;
  2034. if (chip->suspend_mem == NULL)
  2035. return 0;
  2036. /* first lets just bring everything back. .*/
  2037. snd_m3_outw(chip, 0, 0x54);
  2038. snd_m3_outw(chip, 0, 0x56);
  2039. snd_m3_chip_init(chip);
  2040. snd_m3_assp_halt(chip);
  2041. snd_m3_ac97_reset(chip);
  2042. /* restore dsp image */
  2043. dsp_index = 0;
  2044. for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
  2045. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
  2046. chip->suspend_mem[dsp_index++]);
  2047. for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
  2048. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
  2049. chip->suspend_mem[dsp_index++]);
  2050. /* tell the dma engine to restart itself */
  2051. snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
  2052. KDATA_DMA_ACTIVE, 0);
  2053. /* restore ac97 registers */
  2054. snd_ac97_resume(chip->ac97);
  2055. snd_m3_assp_continue(chip);
  2056. snd_m3_enable_ints(chip);
  2057. snd_m3_amp_enable(chip, 1);
  2058. snd_m3_hv_init(chip);
  2059. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2060. chip->in_suspend = 0;
  2061. return 0;
  2062. }
  2063. static SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume);
  2064. #define M3_PM_OPS &m3_pm
  2065. #else
  2066. #define M3_PM_OPS NULL
  2067. #endif /* CONFIG_PM_SLEEP */
  2068. #ifdef CONFIG_SND_MAESTRO3_INPUT
  2069. static int snd_m3_input_register(struct snd_m3 *chip)
  2070. {
  2071. struct input_dev *input_dev;
  2072. int err;
  2073. input_dev = input_allocate_device();
  2074. if (!input_dev)
  2075. return -ENOMEM;
  2076. snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
  2077. pci_name(chip->pci));
  2078. input_dev->name = chip->card->driver;
  2079. input_dev->phys = chip->phys;
  2080. input_dev->id.bustype = BUS_PCI;
  2081. input_dev->id.vendor = chip->pci->vendor;
  2082. input_dev->id.product = chip->pci->device;
  2083. input_dev->dev.parent = &chip->pci->dev;
  2084. __set_bit(EV_KEY, input_dev->evbit);
  2085. __set_bit(KEY_MUTE, input_dev->keybit);
  2086. __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
  2087. __set_bit(KEY_VOLUMEUP, input_dev->keybit);
  2088. err = input_register_device(input_dev);
  2089. if (err) {
  2090. input_free_device(input_dev);
  2091. return err;
  2092. }
  2093. chip->input_dev = input_dev;
  2094. return 0;
  2095. }
  2096. #endif /* CONFIG_INPUT */
  2097. /*
  2098. */
  2099. static int snd_m3_dev_free(struct snd_device *device)
  2100. {
  2101. struct snd_m3 *chip = device->device_data;
  2102. return snd_m3_free(chip);
  2103. }
  2104. static int
  2105. snd_m3_create(struct snd_card *card, struct pci_dev *pci,
  2106. int enable_amp,
  2107. int amp_gpio,
  2108. struct snd_m3 **chip_ret)
  2109. {
  2110. struct snd_m3 *chip;
  2111. int i, err;
  2112. const struct snd_pci_quirk *quirk;
  2113. static const struct snd_device_ops ops = {
  2114. .dev_free = snd_m3_dev_free,
  2115. };
  2116. *chip_ret = NULL;
  2117. if (pci_enable_device(pci))
  2118. return -EIO;
  2119. /* check, if we can restrict PCI DMA transfers to 28 bits */
  2120. if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
  2121. dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
  2122. dev_err(card->dev,
  2123. "architecture does not support 28bit PCI busmaster DMA\n");
  2124. pci_disable_device(pci);
  2125. return -ENXIO;
  2126. }
  2127. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2128. if (chip == NULL) {
  2129. pci_disable_device(pci);
  2130. return -ENOMEM;
  2131. }
  2132. spin_lock_init(&chip->reg_lock);
  2133. switch (pci->device) {
  2134. case PCI_DEVICE_ID_ESS_ALLEGRO:
  2135. case PCI_DEVICE_ID_ESS_ALLEGRO_1:
  2136. case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
  2137. case PCI_DEVICE_ID_ESS_CANYON3D_2:
  2138. chip->allegro_flag = 1;
  2139. break;
  2140. }
  2141. chip->card = card;
  2142. chip->pci = pci;
  2143. chip->irq = -1;
  2144. INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume);
  2145. chip->external_amp = enable_amp;
  2146. if (amp_gpio >= 0 && amp_gpio <= 0x0f)
  2147. chip->amp_gpio = amp_gpio;
  2148. else {
  2149. quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
  2150. if (quirk) {
  2151. dev_info(card->dev, "set amp-gpio for '%s'\n",
  2152. snd_pci_quirk_name(quirk));
  2153. chip->amp_gpio = quirk->value;
  2154. } else if (chip->allegro_flag)
  2155. chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
  2156. else /* presumably this is for all 'maestro3's.. */
  2157. chip->amp_gpio = GPO_EXT_AMP_M3;
  2158. }
  2159. quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
  2160. if (quirk) {
  2161. dev_info(card->dev, "enabled irda workaround for '%s'\n",
  2162. snd_pci_quirk_name(quirk));
  2163. chip->irda_workaround = 1;
  2164. }
  2165. quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
  2166. if (quirk)
  2167. chip->hv_config = quirk->value;
  2168. if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
  2169. chip->is_omnibook = 1;
  2170. chip->num_substreams = NR_DSPS;
  2171. chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
  2172. GFP_KERNEL);
  2173. if (chip->substreams == NULL) {
  2174. kfree(chip);
  2175. pci_disable_device(pci);
  2176. return -ENOMEM;
  2177. }
  2178. err = request_firmware(&chip->assp_kernel_image,
  2179. "ess/maestro3_assp_kernel.fw", &pci->dev);
  2180. if (err < 0)
  2181. goto free_chip;
  2182. err = request_firmware(&chip->assp_minisrc_image,
  2183. "ess/maestro3_assp_minisrc.fw", &pci->dev);
  2184. if (err < 0)
  2185. goto free_chip;
  2186. err = pci_request_regions(pci, card->driver);
  2187. if (err < 0)
  2188. goto free_chip;
  2189. chip->iobase = pci_resource_start(pci, 0);
  2190. /* just to be sure */
  2191. pci_set_master(pci);
  2192. snd_m3_chip_init(chip);
  2193. snd_m3_assp_halt(chip);
  2194. snd_m3_ac97_reset(chip);
  2195. snd_m3_amp_enable(chip, 1);
  2196. snd_m3_hv_init(chip);
  2197. if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
  2198. KBUILD_MODNAME, chip)) {
  2199. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2200. err = -ENOMEM;
  2201. goto free_chip;
  2202. }
  2203. chip->irq = pci->irq;
  2204. card->sync_irq = chip->irq;
  2205. #ifdef CONFIG_PM_SLEEP
  2206. chip->suspend_mem =
  2207. vmalloc(array_size(sizeof(u16),
  2208. REV_B_CODE_MEMORY_LENGTH +
  2209. REV_B_DATA_MEMORY_LENGTH));
  2210. if (chip->suspend_mem == NULL)
  2211. dev_warn(card->dev, "can't allocate apm buffer\n");
  2212. #endif
  2213. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
  2214. if (err < 0)
  2215. goto free_chip;
  2216. if ((err = snd_m3_mixer(chip)) < 0)
  2217. return err;
  2218. for (i = 0; i < chip->num_substreams; i++) {
  2219. struct m3_dma *s = &chip->substreams[i];
  2220. if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
  2221. return err;
  2222. }
  2223. if ((err = snd_m3_pcm(chip, 0)) < 0)
  2224. return err;
  2225. #ifdef CONFIG_SND_MAESTRO3_INPUT
  2226. if (chip->hv_config & HV_CTRL_ENABLE) {
  2227. err = snd_m3_input_register(chip);
  2228. if (err)
  2229. dev_warn(card->dev,
  2230. "Input device registration failed with error %i",
  2231. err);
  2232. }
  2233. #endif
  2234. snd_m3_enable_ints(chip);
  2235. snd_m3_assp_continue(chip);
  2236. *chip_ret = chip;
  2237. return 0;
  2238. free_chip:
  2239. snd_m3_free(chip);
  2240. return err;
  2241. }
  2242. /*
  2243. */
  2244. static int
  2245. snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  2246. {
  2247. static int dev;
  2248. struct snd_card *card;
  2249. struct snd_m3 *chip;
  2250. int err;
  2251. /* don't pick up modems */
  2252. if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
  2253. return -ENODEV;
  2254. if (dev >= SNDRV_CARDS)
  2255. return -ENODEV;
  2256. if (!enable[dev]) {
  2257. dev++;
  2258. return -ENOENT;
  2259. }
  2260. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  2261. 0, &card);
  2262. if (err < 0)
  2263. return err;
  2264. switch (pci->device) {
  2265. case PCI_DEVICE_ID_ESS_ALLEGRO:
  2266. case PCI_DEVICE_ID_ESS_ALLEGRO_1:
  2267. strcpy(card->driver, "Allegro");
  2268. break;
  2269. case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
  2270. case PCI_DEVICE_ID_ESS_CANYON3D_2:
  2271. strcpy(card->driver, "Canyon3D-2");
  2272. break;
  2273. default:
  2274. strcpy(card->driver, "Maestro3");
  2275. break;
  2276. }
  2277. err = snd_m3_create(card, pci, external_amp[dev], amp_gpio[dev], &chip);
  2278. if (err < 0)
  2279. goto free_card;
  2280. card->private_data = chip;
  2281. sprintf(card->shortname, "ESS %s PCI", card->driver);
  2282. sprintf(card->longname, "%s at 0x%lx, irq %d",
  2283. card->shortname, chip->iobase, chip->irq);
  2284. err = snd_card_register(card);
  2285. if (err < 0)
  2286. goto free_card;
  2287. #if 0 /* TODO: not supported yet */
  2288. /* TODO enable MIDI IRQ and I/O */
  2289. err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
  2290. chip->iobase + MPU401_DATA_PORT,
  2291. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2292. -1, &chip->rmidi);
  2293. if (err < 0)
  2294. dev_warn(card->dev, "no MIDI support.\n");
  2295. #endif
  2296. pci_set_drvdata(pci, card);
  2297. dev++;
  2298. return 0;
  2299. free_card:
  2300. snd_card_free(card);
  2301. return err;
  2302. }
  2303. static void snd_m3_remove(struct pci_dev *pci)
  2304. {
  2305. snd_card_free(pci_get_drvdata(pci));
  2306. }
  2307. static struct pci_driver m3_driver = {
  2308. .name = KBUILD_MODNAME,
  2309. .id_table = snd_m3_ids,
  2310. .probe = snd_m3_probe,
  2311. .remove = snd_m3_remove,
  2312. .driver = {
  2313. .pm = M3_PM_OPS,
  2314. },
  2315. };
  2316. module_pci_driver(m3_driver);