intel8x0m.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ALSA modem driver for Intel ICH (i8x0) chipsets
  4. *
  5. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  6. *
  7. * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version
  8. * of ALSA ICH sound driver intel8x0.c .
  9. */
  10. #include <linux/io.h>
  11. #include <linux/delay.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/init.h>
  14. #include <linux/pci.h>
  15. #include <linux/slab.h>
  16. #include <linux/module.h>
  17. #include <sound/core.h>
  18. #include <sound/pcm.h>
  19. #include <sound/ac97_codec.h>
  20. #include <sound/info.h>
  21. #include <sound/initval.h>
  22. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  23. MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; "
  24. "SiS 7013; NVidia MCP/2/2S/3 modems");
  25. MODULE_LICENSE("GPL");
  26. MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  27. "{Intel,82901AB-ICH0},"
  28. "{Intel,82801BA-ICH2},"
  29. "{Intel,82801CA-ICH3},"
  30. "{Intel,82801DB-ICH4},"
  31. "{Intel,ICH5},"
  32. "{Intel,ICH6},"
  33. "{Intel,ICH7},"
  34. "{Intel,MX440},"
  35. "{SiS,7013},"
  36. "{NVidia,NForce Modem},"
  37. "{NVidia,NForce2 Modem},"
  38. "{NVidia,NForce2s Modem},"
  39. "{NVidia,NForce3 Modem},"
  40. "{AMD,AMD768}}");
  41. static int index = -2; /* Exclude the first card */
  42. static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
  43. static int ac97_clock;
  44. module_param(index, int, 0444);
  45. MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
  46. module_param(id, charp, 0444);
  47. MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
  48. module_param(ac97_clock, int, 0444);
  49. MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  50. /* just for backward compatibility */
  51. static bool enable;
  52. module_param(enable, bool, 0444);
  53. /*
  54. * Direct registers
  55. */
  56. enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
  57. #define ICHREG(x) ICH_REG_##x
  58. #define DEFINE_REGSET(name,base) \
  59. enum { \
  60. ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
  61. ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
  62. ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
  63. ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
  64. ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
  65. ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
  66. ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
  67. };
  68. /* busmaster blocks */
  69. DEFINE_REGSET(OFF, 0); /* offset */
  70. /* values for each busmaster block */
  71. /* LVI */
  72. #define ICH_REG_LVI_MASK 0x1f
  73. /* SR */
  74. #define ICH_FIFOE 0x10 /* FIFO error */
  75. #define ICH_BCIS 0x08 /* buffer completion interrupt status */
  76. #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
  77. #define ICH_CELV 0x02 /* current equals last valid */
  78. #define ICH_DCH 0x01 /* DMA controller halted */
  79. /* PIV */
  80. #define ICH_REG_PIV_MASK 0x1f /* mask */
  81. /* CR */
  82. #define ICH_IOCE 0x10 /* interrupt on completion enable */
  83. #define ICH_FEIE 0x08 /* fifo error interrupt enable */
  84. #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
  85. #define ICH_RESETREGS 0x02 /* reset busmaster registers */
  86. #define ICH_STARTBM 0x01 /* start busmaster operation */
  87. /* global block */
  88. #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */
  89. #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
  90. #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
  91. #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
  92. #define ICH_ACLINK 0x00000008 /* AClink shut off */
  93. #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
  94. #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
  95. #define ICH_GIE 0x00000001 /* GPI interrupt enable */
  96. #define ICH_REG_GLOB_STA 0x40 /* dword - global status */
  97. #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
  98. #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
  99. #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
  100. #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
  101. #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
  102. #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
  103. #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
  104. #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
  105. #define ICH_MD3 0x00020000 /* modem power down semaphore */
  106. #define ICH_AD3 0x00010000 /* audio power down semaphore */
  107. #define ICH_RCS 0x00008000 /* read completion status */
  108. #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
  109. #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
  110. #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
  111. #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
  112. #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
  113. #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
  114. #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
  115. #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
  116. #define ICH_POINT 0x00000040 /* playback interrupt */
  117. #define ICH_PIINT 0x00000020 /* capture interrupt */
  118. #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
  119. #define ICH_MOINT 0x00000004 /* modem playback interrupt */
  120. #define ICH_MIINT 0x00000002 /* modem capture interrupt */
  121. #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
  122. #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */
  123. #define ICH_CAS 0x01 /* codec access semaphore */
  124. #define ICH_MAX_FRAGS 32 /* max hw frags */
  125. /*
  126. *
  127. */
  128. enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
  129. enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
  130. #define get_ichdev(substream) (substream->runtime->private_data)
  131. struct ichdev {
  132. unsigned int ichd; /* ich device number */
  133. unsigned long reg_offset; /* offset to bmaddr */
  134. __le32 *bdbar; /* CPU address (32bit) */
  135. unsigned int bdbar_addr; /* PCI bus address (32bit) */
  136. struct snd_pcm_substream *substream;
  137. unsigned int physbuf; /* physical address (32bit) */
  138. unsigned int size;
  139. unsigned int fragsize;
  140. unsigned int fragsize1;
  141. unsigned int position;
  142. int frags;
  143. int lvi;
  144. int lvi_frag;
  145. int civ;
  146. int ack;
  147. int ack_reload;
  148. unsigned int ack_bit;
  149. unsigned int roff_sr;
  150. unsigned int roff_picb;
  151. unsigned int int_sta_mask; /* interrupt status mask */
  152. unsigned int ali_slot; /* ALI DMA slot */
  153. struct snd_ac97 *ac97;
  154. };
  155. struct intel8x0m {
  156. unsigned int device_type;
  157. int irq;
  158. void __iomem *addr;
  159. void __iomem *bmaddr;
  160. struct pci_dev *pci;
  161. struct snd_card *card;
  162. int pcm_devs;
  163. struct snd_pcm *pcm[2];
  164. struct ichdev ichd[2];
  165. unsigned int in_ac97_init: 1;
  166. struct snd_ac97_bus *ac97_bus;
  167. struct snd_ac97 *ac97;
  168. spinlock_t reg_lock;
  169. struct snd_dma_buffer bdbars;
  170. u32 bdbars_count;
  171. u32 int_sta_reg; /* interrupt status register */
  172. u32 int_sta_mask; /* interrupt status mask */
  173. unsigned int pcm_pos_shift;
  174. };
  175. static const struct pci_device_id snd_intel8x0m_ids[] = {
  176. { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL }, /* 82801AA */
  177. { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL }, /* 82901AB */
  178. { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL }, /* 82801BA */
  179. { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL }, /* ICH3 */
  180. { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL }, /* ICH4 */
  181. { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL }, /* ICH5 */
  182. { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL }, /* ICH6 */
  183. { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL }, /* ICH7 */
  184. { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL }, /* 440MX */
  185. { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL }, /* AMD768 */
  186. { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS }, /* SI7013 */
  187. { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE }, /* NFORCE */
  188. { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE }, /* NFORCE2 */
  189. { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE }, /* NFORCE2s */
  190. { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE }, /* NFORCE3 */
  191. { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL }, /* AMD8111 */
  192. #if 0
  193. { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
  194. #endif
  195. { 0, }
  196. };
  197. MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
  198. /*
  199. * Lowlevel I/O - busmaster
  200. */
  201. static inline u8 igetbyte(struct intel8x0m *chip, u32 offset)
  202. {
  203. return ioread8(chip->bmaddr + offset);
  204. }
  205. static inline u16 igetword(struct intel8x0m *chip, u32 offset)
  206. {
  207. return ioread16(chip->bmaddr + offset);
  208. }
  209. static inline u32 igetdword(struct intel8x0m *chip, u32 offset)
  210. {
  211. return ioread32(chip->bmaddr + offset);
  212. }
  213. static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)
  214. {
  215. iowrite8(val, chip->bmaddr + offset);
  216. }
  217. static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val)
  218. {
  219. iowrite16(val, chip->bmaddr + offset);
  220. }
  221. static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val)
  222. {
  223. iowrite32(val, chip->bmaddr + offset);
  224. }
  225. /*
  226. * Lowlevel I/O - AC'97 registers
  227. */
  228. static inline u16 iagetword(struct intel8x0m *chip, u32 offset)
  229. {
  230. return ioread16(chip->addr + offset);
  231. }
  232. static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)
  233. {
  234. iowrite16(val, chip->addr + offset);
  235. }
  236. /*
  237. * Basic I/O
  238. */
  239. /*
  240. * access to AC97 codec via normal i/o (for ICH and SIS7013)
  241. */
  242. /* return the GLOB_STA bit for the corresponding codec */
  243. static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec)
  244. {
  245. static const unsigned int codec_bit[3] = {
  246. ICH_PCR, ICH_SCR, ICH_TCR
  247. };
  248. if (snd_BUG_ON(codec >= 3))
  249. return ICH_PCR;
  250. return codec_bit[codec];
  251. }
  252. static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec)
  253. {
  254. int time;
  255. if (codec > 1)
  256. return -EIO;
  257. codec = get_ich_codec_bit(chip, codec);
  258. /* codec ready ? */
  259. if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
  260. return -EIO;
  261. /* Anyone holding a semaphore for 1 msec should be shot... */
  262. time = 100;
  263. do {
  264. if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
  265. return 0;
  266. udelay(10);
  267. } while (time--);
  268. /* access to some forbidden (non existent) ac97 registers will not
  269. * reset the semaphore. So even if you don't get the semaphore, still
  270. * continue the access. We don't need the semaphore anyway. */
  271. dev_err(chip->card->dev,
  272. "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
  273. igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
  274. iagetword(chip, 0); /* clear semaphore flag */
  275. /* I don't care about the semaphore */
  276. return -EBUSY;
  277. }
  278. static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97,
  279. unsigned short reg,
  280. unsigned short val)
  281. {
  282. struct intel8x0m *chip = ac97->private_data;
  283. if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
  284. if (! chip->in_ac97_init)
  285. dev_err(chip->card->dev,
  286. "codec_write %d: semaphore is not ready for register 0x%x\n",
  287. ac97->num, reg);
  288. }
  289. iaputword(chip, reg + ac97->num * 0x80, val);
  290. }
  291. static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97,
  292. unsigned short reg)
  293. {
  294. struct intel8x0m *chip = ac97->private_data;
  295. unsigned short res;
  296. unsigned int tmp;
  297. if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
  298. if (! chip->in_ac97_init)
  299. dev_err(chip->card->dev,
  300. "codec_read %d: semaphore is not ready for register 0x%x\n",
  301. ac97->num, reg);
  302. res = 0xffff;
  303. } else {
  304. res = iagetword(chip, reg + ac97->num * 0x80);
  305. if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
  306. /* reset RCS and preserve other R/WC bits */
  307. iputdword(chip, ICHREG(GLOB_STA),
  308. tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
  309. if (! chip->in_ac97_init)
  310. dev_err(chip->card->dev,
  311. "codec_read %d: read timeout for register 0x%x\n",
  312. ac97->num, reg);
  313. res = 0xffff;
  314. }
  315. }
  316. if (reg == AC97_GPIO_STATUS)
  317. iagetword(chip, 0); /* clear semaphore */
  318. return res;
  319. }
  320. /*
  321. * DMA I/O
  322. */
  323. static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev)
  324. {
  325. int idx;
  326. __le32 *bdbar = ichdev->bdbar;
  327. unsigned long port = ichdev->reg_offset;
  328. iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
  329. if (ichdev->size == ichdev->fragsize) {
  330. ichdev->ack_reload = ichdev->ack = 2;
  331. ichdev->fragsize1 = ichdev->fragsize >> 1;
  332. for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
  333. bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
  334. bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  335. ichdev->fragsize1 >> chip->pcm_pos_shift);
  336. bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
  337. bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  338. ichdev->fragsize1 >> chip->pcm_pos_shift);
  339. }
  340. ichdev->frags = 2;
  341. } else {
  342. ichdev->ack_reload = ichdev->ack = 1;
  343. ichdev->fragsize1 = ichdev->fragsize;
  344. for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
  345. bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
  346. bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  347. ichdev->fragsize >> chip->pcm_pos_shift);
  348. /*
  349. dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
  350. idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
  351. */
  352. }
  353. ichdev->frags = ichdev->size / ichdev->fragsize;
  354. }
  355. iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
  356. ichdev->civ = 0;
  357. iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
  358. ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
  359. ichdev->position = 0;
  360. #if 0
  361. dev_dbg(chip->card->dev,
  362. "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
  363. ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
  364. ichdev->fragsize1);
  365. #endif
  366. /* clear interrupts */
  367. iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
  368. }
  369. /*
  370. * Interrupt handler
  371. */
  372. static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev)
  373. {
  374. unsigned long port = ichdev->reg_offset;
  375. int civ, i, step;
  376. int ack = 0;
  377. civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
  378. if (civ == ichdev->civ) {
  379. // snd_printd("civ same %d\n", civ);
  380. step = 1;
  381. ichdev->civ++;
  382. ichdev->civ &= ICH_REG_LVI_MASK;
  383. } else {
  384. step = civ - ichdev->civ;
  385. if (step < 0)
  386. step += ICH_REG_LVI_MASK + 1;
  387. // if (step != 1)
  388. // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
  389. ichdev->civ = civ;
  390. }
  391. ichdev->position += step * ichdev->fragsize1;
  392. ichdev->position %= ichdev->size;
  393. ichdev->lvi += step;
  394. ichdev->lvi &= ICH_REG_LVI_MASK;
  395. iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
  396. for (i = 0; i < step; i++) {
  397. ichdev->lvi_frag++;
  398. ichdev->lvi_frag %= ichdev->frags;
  399. ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf +
  400. ichdev->lvi_frag *
  401. ichdev->fragsize1);
  402. #if 0
  403. dev_dbg(chip->card->dev,
  404. "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
  405. ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
  406. ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
  407. inl(port + 4), inb(port + ICH_REG_OFF_CR));
  408. #endif
  409. if (--ichdev->ack == 0) {
  410. ichdev->ack = ichdev->ack_reload;
  411. ack = 1;
  412. }
  413. }
  414. if (ack && ichdev->substream) {
  415. spin_unlock(&chip->reg_lock);
  416. snd_pcm_period_elapsed(ichdev->substream);
  417. spin_lock(&chip->reg_lock);
  418. }
  419. iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
  420. }
  421. static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id)
  422. {
  423. struct intel8x0m *chip = dev_id;
  424. struct ichdev *ichdev;
  425. unsigned int status;
  426. unsigned int i;
  427. spin_lock(&chip->reg_lock);
  428. status = igetdword(chip, chip->int_sta_reg);
  429. if (status == 0xffffffff) { /* we are not yet resumed */
  430. spin_unlock(&chip->reg_lock);
  431. return IRQ_NONE;
  432. }
  433. if ((status & chip->int_sta_mask) == 0) {
  434. if (status)
  435. iputdword(chip, chip->int_sta_reg, status);
  436. spin_unlock(&chip->reg_lock);
  437. return IRQ_NONE;
  438. }
  439. for (i = 0; i < chip->bdbars_count; i++) {
  440. ichdev = &chip->ichd[i];
  441. if (status & ichdev->int_sta_mask)
  442. snd_intel8x0m_update(chip, ichdev);
  443. }
  444. /* ack them */
  445. iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
  446. spin_unlock(&chip->reg_lock);
  447. return IRQ_HANDLED;
  448. }
  449. /*
  450. * PCM part
  451. */
  452. static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  453. {
  454. struct intel8x0m *chip = snd_pcm_substream_chip(substream);
  455. struct ichdev *ichdev = get_ichdev(substream);
  456. unsigned char val = 0;
  457. unsigned long port = ichdev->reg_offset;
  458. switch (cmd) {
  459. case SNDRV_PCM_TRIGGER_START:
  460. case SNDRV_PCM_TRIGGER_RESUME:
  461. val = ICH_IOCE | ICH_STARTBM;
  462. break;
  463. case SNDRV_PCM_TRIGGER_STOP:
  464. case SNDRV_PCM_TRIGGER_SUSPEND:
  465. val = 0;
  466. break;
  467. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  468. val = ICH_IOCE;
  469. break;
  470. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  471. val = ICH_IOCE | ICH_STARTBM;
  472. break;
  473. default:
  474. return -EINVAL;
  475. }
  476. iputbyte(chip, port + ICH_REG_OFF_CR, val);
  477. if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  478. /* wait until DMA stopped */
  479. while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
  480. /* reset whole DMA things */
  481. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
  482. }
  483. return 0;
  484. }
  485. static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream)
  486. {
  487. struct intel8x0m *chip = snd_pcm_substream_chip(substream);
  488. struct ichdev *ichdev = get_ichdev(substream);
  489. size_t ptr1, ptr;
  490. ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
  491. if (ptr1 != 0)
  492. ptr = ichdev->fragsize1 - ptr1;
  493. else
  494. ptr = 0;
  495. ptr += ichdev->position;
  496. if (ptr >= ichdev->size)
  497. return 0;
  498. return bytes_to_frames(substream->runtime, ptr);
  499. }
  500. static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream)
  501. {
  502. struct intel8x0m *chip = snd_pcm_substream_chip(substream);
  503. struct snd_pcm_runtime *runtime = substream->runtime;
  504. struct ichdev *ichdev = get_ichdev(substream);
  505. ichdev->physbuf = runtime->dma_addr;
  506. ichdev->size = snd_pcm_lib_buffer_bytes(substream);
  507. ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
  508. snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
  509. snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
  510. snd_intel8x0m_setup_periods(chip, ichdev);
  511. return 0;
  512. }
  513. static const struct snd_pcm_hardware snd_intel8x0m_stream =
  514. {
  515. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  516. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  517. SNDRV_PCM_INFO_MMAP_VALID |
  518. SNDRV_PCM_INFO_PAUSE |
  519. SNDRV_PCM_INFO_RESUME),
  520. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  521. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
  522. .rate_min = 8000,
  523. .rate_max = 16000,
  524. .channels_min = 1,
  525. .channels_max = 1,
  526. .buffer_bytes_max = 64 * 1024,
  527. .period_bytes_min = 32,
  528. .period_bytes_max = 64 * 1024,
  529. .periods_min = 1,
  530. .periods_max = 1024,
  531. .fifo_size = 0,
  532. };
  533. static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
  534. {
  535. static const unsigned int rates[] = { 8000, 9600, 12000, 16000 };
  536. static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  537. .count = ARRAY_SIZE(rates),
  538. .list = rates,
  539. .mask = 0,
  540. };
  541. struct snd_pcm_runtime *runtime = substream->runtime;
  542. int err;
  543. ichdev->substream = substream;
  544. runtime->hw = snd_intel8x0m_stream;
  545. err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  546. &hw_constraints_rates);
  547. if ( err < 0 )
  548. return err;
  549. runtime->private_data = ichdev;
  550. return 0;
  551. }
  552. static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream)
  553. {
  554. struct intel8x0m *chip = snd_pcm_substream_chip(substream);
  555. return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
  556. }
  557. static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream)
  558. {
  559. struct intel8x0m *chip = snd_pcm_substream_chip(substream);
  560. chip->ichd[ICHD_MDMOUT].substream = NULL;
  561. return 0;
  562. }
  563. static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream)
  564. {
  565. struct intel8x0m *chip = snd_pcm_substream_chip(substream);
  566. return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
  567. }
  568. static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream)
  569. {
  570. struct intel8x0m *chip = snd_pcm_substream_chip(substream);
  571. chip->ichd[ICHD_MDMIN].substream = NULL;
  572. return 0;
  573. }
  574. static const struct snd_pcm_ops snd_intel8x0m_playback_ops = {
  575. .open = snd_intel8x0m_playback_open,
  576. .close = snd_intel8x0m_playback_close,
  577. .prepare = snd_intel8x0m_pcm_prepare,
  578. .trigger = snd_intel8x0m_pcm_trigger,
  579. .pointer = snd_intel8x0m_pcm_pointer,
  580. };
  581. static const struct snd_pcm_ops snd_intel8x0m_capture_ops = {
  582. .open = snd_intel8x0m_capture_open,
  583. .close = snd_intel8x0m_capture_close,
  584. .prepare = snd_intel8x0m_pcm_prepare,
  585. .trigger = snd_intel8x0m_pcm_trigger,
  586. .pointer = snd_intel8x0m_pcm_pointer,
  587. };
  588. struct ich_pcm_table {
  589. char *suffix;
  590. const struct snd_pcm_ops *playback_ops;
  591. const struct snd_pcm_ops *capture_ops;
  592. size_t prealloc_size;
  593. size_t prealloc_max_size;
  594. int ac97_idx;
  595. };
  596. static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device,
  597. const struct ich_pcm_table *rec)
  598. {
  599. struct snd_pcm *pcm;
  600. int err;
  601. char name[32];
  602. if (rec->suffix)
  603. sprintf(name, "Intel ICH - %s", rec->suffix);
  604. else
  605. strcpy(name, "Intel ICH");
  606. err = snd_pcm_new(chip->card, name, device,
  607. rec->playback_ops ? 1 : 0,
  608. rec->capture_ops ? 1 : 0, &pcm);
  609. if (err < 0)
  610. return err;
  611. if (rec->playback_ops)
  612. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
  613. if (rec->capture_ops)
  614. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
  615. pcm->private_data = chip;
  616. pcm->info_flags = 0;
  617. pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
  618. if (rec->suffix)
  619. sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
  620. else
  621. strcpy(pcm->name, chip->card->shortname);
  622. chip->pcm[device] = pcm;
  623. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  624. &chip->pci->dev,
  625. rec->prealloc_size,
  626. rec->prealloc_max_size);
  627. return 0;
  628. }
  629. static const struct ich_pcm_table intel_pcms[] = {
  630. {
  631. .suffix = "Modem",
  632. .playback_ops = &snd_intel8x0m_playback_ops,
  633. .capture_ops = &snd_intel8x0m_capture_ops,
  634. .prealloc_size = 32 * 1024,
  635. .prealloc_max_size = 64 * 1024,
  636. },
  637. };
  638. static int snd_intel8x0m_pcm(struct intel8x0m *chip)
  639. {
  640. int i, tblsize, device, err;
  641. const struct ich_pcm_table *tbl, *rec;
  642. #if 1
  643. tbl = intel_pcms;
  644. tblsize = 1;
  645. #else
  646. switch (chip->device_type) {
  647. case DEVICE_NFORCE:
  648. tbl = nforce_pcms;
  649. tblsize = ARRAY_SIZE(nforce_pcms);
  650. break;
  651. case DEVICE_ALI:
  652. tbl = ali_pcms;
  653. tblsize = ARRAY_SIZE(ali_pcms);
  654. break;
  655. default:
  656. tbl = intel_pcms;
  657. tblsize = 2;
  658. break;
  659. }
  660. #endif
  661. device = 0;
  662. for (i = 0; i < tblsize; i++) {
  663. rec = tbl + i;
  664. if (i > 0 && rec->ac97_idx) {
  665. /* activate PCM only when associated AC'97 codec */
  666. if (! chip->ichd[rec->ac97_idx].ac97)
  667. continue;
  668. }
  669. err = snd_intel8x0m_pcm1(chip, device, rec);
  670. if (err < 0)
  671. return err;
  672. device++;
  673. }
  674. chip->pcm_devs = device;
  675. return 0;
  676. }
  677. /*
  678. * Mixer part
  679. */
  680. static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  681. {
  682. struct intel8x0m *chip = bus->private_data;
  683. chip->ac97_bus = NULL;
  684. }
  685. static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97)
  686. {
  687. struct intel8x0m *chip = ac97->private_data;
  688. chip->ac97 = NULL;
  689. }
  690. static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock)
  691. {
  692. struct snd_ac97_bus *pbus;
  693. struct snd_ac97_template ac97;
  694. struct snd_ac97 *x97;
  695. int err;
  696. unsigned int glob_sta = 0;
  697. static const struct snd_ac97_bus_ops ops = {
  698. .write = snd_intel8x0m_codec_write,
  699. .read = snd_intel8x0m_codec_read,
  700. };
  701. chip->in_ac97_init = 1;
  702. memset(&ac97, 0, sizeof(ac97));
  703. ac97.private_data = chip;
  704. ac97.private_free = snd_intel8x0m_mixer_free_ac97;
  705. ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;
  706. glob_sta = igetdword(chip, ICHREG(GLOB_STA));
  707. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
  708. goto __err;
  709. pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus;
  710. if (ac97_clock >= 8000 && ac97_clock <= 48000)
  711. pbus->clock = ac97_clock;
  712. chip->ac97_bus = pbus;
  713. ac97.pci = chip->pci;
  714. ac97.num = glob_sta & ICH_SCR ? 1 : 0;
  715. if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
  716. dev_err(chip->card->dev,
  717. "Unable to initialize codec #%d\n", ac97.num);
  718. if (ac97.num == 0)
  719. goto __err;
  720. return err;
  721. }
  722. chip->ac97 = x97;
  723. if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
  724. chip->ichd[ICHD_MDMIN].ac97 = x97;
  725. chip->ichd[ICHD_MDMOUT].ac97 = x97;
  726. }
  727. chip->in_ac97_init = 0;
  728. return 0;
  729. __err:
  730. /* clear the cold-reset bit for the next chance */
  731. if (chip->device_type != DEVICE_ALI)
  732. iputdword(chip, ICHREG(GLOB_CNT),
  733. igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
  734. return err;
  735. }
  736. /*
  737. *
  738. */
  739. static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing)
  740. {
  741. unsigned long end_time;
  742. unsigned int cnt, status, nstatus;
  743. /* put logic to right state */
  744. /* first clear status bits */
  745. status = ICH_RCS | ICH_MIINT | ICH_MOINT;
  746. cnt = igetdword(chip, ICHREG(GLOB_STA));
  747. iputdword(chip, ICHREG(GLOB_STA), cnt & status);
  748. /* ACLink on, 2 channels */
  749. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  750. cnt &= ~(ICH_ACLINK);
  751. /* finish cold or do warm reset */
  752. cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
  753. iputdword(chip, ICHREG(GLOB_CNT), cnt);
  754. usleep_range(500, 1000); /* give warm reset some time */
  755. end_time = jiffies + HZ / 4;
  756. do {
  757. if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
  758. goto __ok;
  759. schedule_timeout_uninterruptible(1);
  760. } while (time_after_eq(end_time, jiffies));
  761. dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
  762. igetdword(chip, ICHREG(GLOB_CNT)));
  763. return -EIO;
  764. __ok:
  765. if (probing) {
  766. /* wait for any codec ready status.
  767. * Once it becomes ready it should remain ready
  768. * as long as we do not disable the ac97 link.
  769. */
  770. end_time = jiffies + HZ;
  771. do {
  772. status = igetdword(chip, ICHREG(GLOB_STA)) &
  773. (ICH_PCR | ICH_SCR | ICH_TCR);
  774. if (status)
  775. break;
  776. schedule_timeout_uninterruptible(1);
  777. } while (time_after_eq(end_time, jiffies));
  778. if (! status) {
  779. /* no codec is found */
  780. dev_err(chip->card->dev,
  781. "codec_ready: codec is not ready [0x%x]\n",
  782. igetdword(chip, ICHREG(GLOB_STA)));
  783. return -EIO;
  784. }
  785. /* up to two codecs (modem cannot be tertiary with ICH4) */
  786. nstatus = ICH_PCR | ICH_SCR;
  787. /* wait for other codecs ready status. */
  788. end_time = jiffies + HZ / 4;
  789. while (status != nstatus && time_after_eq(end_time, jiffies)) {
  790. schedule_timeout_uninterruptible(1);
  791. status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
  792. }
  793. } else {
  794. /* resume phase */
  795. status = 0;
  796. if (chip->ac97)
  797. status |= get_ich_codec_bit(chip, chip->ac97->num);
  798. /* wait until all the probed codecs are ready */
  799. end_time = jiffies + HZ;
  800. do {
  801. nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
  802. (ICH_PCR | ICH_SCR | ICH_TCR);
  803. if (status == nstatus)
  804. break;
  805. schedule_timeout_uninterruptible(1);
  806. } while (time_after_eq(end_time, jiffies));
  807. }
  808. if (chip->device_type == DEVICE_SIS) {
  809. /* unmute the output on SIS7012 */
  810. iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
  811. }
  812. return 0;
  813. }
  814. static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing)
  815. {
  816. unsigned int i;
  817. int err;
  818. if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
  819. return err;
  820. iagetword(chip, 0); /* clear semaphore flag */
  821. /* disable interrupts */
  822. for (i = 0; i < chip->bdbars_count; i++)
  823. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
  824. /* reset channels */
  825. for (i = 0; i < chip->bdbars_count; i++)
  826. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
  827. /* initialize Buffer Descriptor Lists */
  828. for (i = 0; i < chip->bdbars_count; i++)
  829. iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
  830. return 0;
  831. }
  832. static int snd_intel8x0m_free(struct intel8x0m *chip)
  833. {
  834. unsigned int i;
  835. if (chip->irq < 0)
  836. goto __hw_end;
  837. /* disable interrupts */
  838. for (i = 0; i < chip->bdbars_count; i++)
  839. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
  840. /* reset channels */
  841. for (i = 0; i < chip->bdbars_count; i++)
  842. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
  843. __hw_end:
  844. if (chip->irq >= 0)
  845. free_irq(chip->irq, chip);
  846. if (chip->bdbars.area)
  847. snd_dma_free_pages(&chip->bdbars);
  848. if (chip->addr)
  849. pci_iounmap(chip->pci, chip->addr);
  850. if (chip->bmaddr)
  851. pci_iounmap(chip->pci, chip->bmaddr);
  852. pci_release_regions(chip->pci);
  853. pci_disable_device(chip->pci);
  854. kfree(chip);
  855. return 0;
  856. }
  857. #ifdef CONFIG_PM_SLEEP
  858. /*
  859. * power management
  860. */
  861. static int intel8x0m_suspend(struct device *dev)
  862. {
  863. struct snd_card *card = dev_get_drvdata(dev);
  864. struct intel8x0m *chip = card->private_data;
  865. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  866. snd_ac97_suspend(chip->ac97);
  867. if (chip->irq >= 0) {
  868. free_irq(chip->irq, chip);
  869. chip->irq = -1;
  870. card->sync_irq = -1;
  871. }
  872. return 0;
  873. }
  874. static int intel8x0m_resume(struct device *dev)
  875. {
  876. struct pci_dev *pci = to_pci_dev(dev);
  877. struct snd_card *card = dev_get_drvdata(dev);
  878. struct intel8x0m *chip = card->private_data;
  879. if (request_irq(pci->irq, snd_intel8x0m_interrupt,
  880. IRQF_SHARED, KBUILD_MODNAME, chip)) {
  881. dev_err(dev, "unable to grab IRQ %d, disabling device\n",
  882. pci->irq);
  883. snd_card_disconnect(card);
  884. return -EIO;
  885. }
  886. chip->irq = pci->irq;
  887. card->sync_irq = chip->irq;
  888. snd_intel8x0m_chip_init(chip, 0);
  889. snd_ac97_resume(chip->ac97);
  890. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  891. return 0;
  892. }
  893. static SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume);
  894. #define INTEL8X0M_PM_OPS &intel8x0m_pm
  895. #else
  896. #define INTEL8X0M_PM_OPS NULL
  897. #endif /* CONFIG_PM_SLEEP */
  898. static void snd_intel8x0m_proc_read(struct snd_info_entry * entry,
  899. struct snd_info_buffer *buffer)
  900. {
  901. struct intel8x0m *chip = entry->private_data;
  902. unsigned int tmp;
  903. snd_iprintf(buffer, "Intel8x0m\n\n");
  904. if (chip->device_type == DEVICE_ALI)
  905. return;
  906. tmp = igetdword(chip, ICHREG(GLOB_STA));
  907. snd_iprintf(buffer, "Global control : 0x%08x\n",
  908. igetdword(chip, ICHREG(GLOB_CNT)));
  909. snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
  910. snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
  911. tmp & ICH_PCR ? " primary" : "",
  912. tmp & ICH_SCR ? " secondary" : "",
  913. tmp & ICH_TCR ? " tertiary" : "",
  914. (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
  915. }
  916. static void snd_intel8x0m_proc_init(struct intel8x0m *chip)
  917. {
  918. snd_card_ro_proc_new(chip->card, "intel8x0m", chip,
  919. snd_intel8x0m_proc_read);
  920. }
  921. static int snd_intel8x0m_dev_free(struct snd_device *device)
  922. {
  923. struct intel8x0m *chip = device->device_data;
  924. return snd_intel8x0m_free(chip);
  925. }
  926. struct ich_reg_info {
  927. unsigned int int_sta_mask;
  928. unsigned int offset;
  929. };
  930. static int snd_intel8x0m_create(struct snd_card *card,
  931. struct pci_dev *pci,
  932. unsigned long device_type,
  933. struct intel8x0m **r_intel8x0m)
  934. {
  935. struct intel8x0m *chip;
  936. int err;
  937. unsigned int i;
  938. unsigned int int_sta_masks;
  939. struct ichdev *ichdev;
  940. static const struct snd_device_ops ops = {
  941. .dev_free = snd_intel8x0m_dev_free,
  942. };
  943. static const struct ich_reg_info intel_regs[2] = {
  944. { ICH_MIINT, 0 },
  945. { ICH_MOINT, 0x10 },
  946. };
  947. const struct ich_reg_info *tbl;
  948. *r_intel8x0m = NULL;
  949. if ((err = pci_enable_device(pci)) < 0)
  950. return err;
  951. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  952. if (chip == NULL) {
  953. pci_disable_device(pci);
  954. return -ENOMEM;
  955. }
  956. spin_lock_init(&chip->reg_lock);
  957. chip->device_type = device_type;
  958. chip->card = card;
  959. chip->pci = pci;
  960. chip->irq = -1;
  961. if ((err = pci_request_regions(pci, card->shortname)) < 0) {
  962. kfree(chip);
  963. pci_disable_device(pci);
  964. return err;
  965. }
  966. if (device_type == DEVICE_ALI) {
  967. /* ALI5455 has no ac97 region */
  968. chip->bmaddr = pci_iomap(pci, 0, 0);
  969. goto port_inited;
  970. }
  971. if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
  972. chip->addr = pci_iomap(pci, 2, 0);
  973. else
  974. chip->addr = pci_iomap(pci, 0, 0);
  975. if (!chip->addr) {
  976. dev_err(card->dev, "AC'97 space ioremap problem\n");
  977. snd_intel8x0m_free(chip);
  978. return -EIO;
  979. }
  980. if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
  981. chip->bmaddr = pci_iomap(pci, 3, 0);
  982. else
  983. chip->bmaddr = pci_iomap(pci, 1, 0);
  984. if (!chip->bmaddr) {
  985. dev_err(card->dev, "Controller space ioremap problem\n");
  986. snd_intel8x0m_free(chip);
  987. return -EIO;
  988. }
  989. port_inited:
  990. /* initialize offsets */
  991. chip->bdbars_count = 2;
  992. tbl = intel_regs;
  993. for (i = 0; i < chip->bdbars_count; i++) {
  994. ichdev = &chip->ichd[i];
  995. ichdev->ichd = i;
  996. ichdev->reg_offset = tbl[i].offset;
  997. ichdev->int_sta_mask = tbl[i].int_sta_mask;
  998. if (device_type == DEVICE_SIS) {
  999. /* SiS 7013 swaps the registers */
  1000. ichdev->roff_sr = ICH_REG_OFF_PICB;
  1001. ichdev->roff_picb = ICH_REG_OFF_SR;
  1002. } else {
  1003. ichdev->roff_sr = ICH_REG_OFF_SR;
  1004. ichdev->roff_picb = ICH_REG_OFF_PICB;
  1005. }
  1006. if (device_type == DEVICE_ALI)
  1007. ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
  1008. }
  1009. /* SIS7013 handles the pcm data in bytes, others are in words */
  1010. chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
  1011. /* allocate buffer descriptor lists */
  1012. /* the start of each lists must be aligned to 8 bytes */
  1013. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
  1014. chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
  1015. &chip->bdbars) < 0) {
  1016. snd_intel8x0m_free(chip);
  1017. return -ENOMEM;
  1018. }
  1019. /* tables must be aligned to 8 bytes here, but the kernel pages
  1020. are much bigger, so we don't care (on i386) */
  1021. int_sta_masks = 0;
  1022. for (i = 0; i < chip->bdbars_count; i++) {
  1023. ichdev = &chip->ichd[i];
  1024. ichdev->bdbar = ((__le32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
  1025. ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
  1026. int_sta_masks |= ichdev->int_sta_mask;
  1027. }
  1028. chip->int_sta_reg = ICH_REG_GLOB_STA;
  1029. chip->int_sta_mask = int_sta_masks;
  1030. pci_set_master(pci);
  1031. if ((err = snd_intel8x0m_chip_init(chip, 1)) < 0) {
  1032. snd_intel8x0m_free(chip);
  1033. return err;
  1034. }
  1035. if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED,
  1036. KBUILD_MODNAME, chip)) {
  1037. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  1038. snd_intel8x0m_free(chip);
  1039. return -EBUSY;
  1040. }
  1041. chip->irq = pci->irq;
  1042. card->sync_irq = chip->irq;
  1043. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1044. snd_intel8x0m_free(chip);
  1045. return err;
  1046. }
  1047. *r_intel8x0m = chip;
  1048. return 0;
  1049. }
  1050. static struct shortname_table {
  1051. unsigned int id;
  1052. const char *s;
  1053. } shortnames[] = {
  1054. { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
  1055. { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
  1056. { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
  1057. { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
  1058. { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
  1059. { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
  1060. { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
  1061. { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
  1062. { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
  1063. { 0x7446, "AMD AMD768" },
  1064. { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
  1065. { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
  1066. { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
  1067. { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
  1068. { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
  1069. { 0x746e, "AMD AMD8111" },
  1070. #if 0
  1071. { 0x5455, "ALi M5455" },
  1072. #endif
  1073. { 0 },
  1074. };
  1075. static int snd_intel8x0m_probe(struct pci_dev *pci,
  1076. const struct pci_device_id *pci_id)
  1077. {
  1078. struct snd_card *card;
  1079. struct intel8x0m *chip;
  1080. int err;
  1081. struct shortname_table *name;
  1082. err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
  1083. if (err < 0)
  1084. return err;
  1085. strcpy(card->driver, "ICH-MODEM");
  1086. strcpy(card->shortname, "Intel ICH");
  1087. for (name = shortnames; name->id; name++) {
  1088. if (pci->device == name->id) {
  1089. strcpy(card->shortname, name->s);
  1090. break;
  1091. }
  1092. }
  1093. strcat(card->shortname," Modem");
  1094. if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
  1095. snd_card_free(card);
  1096. return err;
  1097. }
  1098. card->private_data = chip;
  1099. if ((err = snd_intel8x0m_mixer(chip, ac97_clock)) < 0) {
  1100. snd_card_free(card);
  1101. return err;
  1102. }
  1103. if ((err = snd_intel8x0m_pcm(chip)) < 0) {
  1104. snd_card_free(card);
  1105. return err;
  1106. }
  1107. snd_intel8x0m_proc_init(chip);
  1108. sprintf(card->longname, "%s at irq %i",
  1109. card->shortname, chip->irq);
  1110. if ((err = snd_card_register(card)) < 0) {
  1111. snd_card_free(card);
  1112. return err;
  1113. }
  1114. pci_set_drvdata(pci, card);
  1115. return 0;
  1116. }
  1117. static void snd_intel8x0m_remove(struct pci_dev *pci)
  1118. {
  1119. snd_card_free(pci_get_drvdata(pci));
  1120. }
  1121. static struct pci_driver intel8x0m_driver = {
  1122. .name = KBUILD_MODNAME,
  1123. .id_table = snd_intel8x0m_ids,
  1124. .probe = snd_intel8x0m_probe,
  1125. .remove = snd_intel8x0m_remove,
  1126. .driver = {
  1127. .pm = INTEL8X0M_PM_OPS,
  1128. },
  1129. };
  1130. module_pci_driver(intel8x0m_driver);