intel8x0.c 89 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ALSA driver for Intel ICH (i8x0) chipsets
  4. *
  5. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  6. *
  7. * This code also contains alpha support for SiS 735 chipsets provided
  8. * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
  9. * for SiS735, so the code is not fully functional.
  10. *
  11. */
  12. #include <linux/io.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/init.h>
  16. #include <linux/pci.h>
  17. #include <linux/slab.h>
  18. #include <linux/module.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/ac97_codec.h>
  22. #include <sound/info.h>
  23. #include <sound/initval.h>
  24. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  25. MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  26. MODULE_LICENSE("GPL");
  27. MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  28. "{Intel,82901AB-ICH0},"
  29. "{Intel,82801BA-ICH2},"
  30. "{Intel,82801CA-ICH3},"
  31. "{Intel,82801DB-ICH4},"
  32. "{Intel,ICH5},"
  33. "{Intel,ICH6},"
  34. "{Intel,ICH7},"
  35. "{Intel,6300ESB},"
  36. "{Intel,ESB2},"
  37. "{Intel,MX440},"
  38. "{SiS,SI7012},"
  39. "{NVidia,nForce Audio},"
  40. "{NVidia,nForce2 Audio},"
  41. "{NVidia,nForce3 Audio},"
  42. "{NVidia,MCP04},"
  43. "{NVidia,MCP501},"
  44. "{NVidia,CK804},"
  45. "{NVidia,CK8},"
  46. "{NVidia,CK8S},"
  47. "{AMD,AMD768},"
  48. "{AMD,AMD8111},"
  49. "{ALI,M5455}}");
  50. static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
  51. static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
  52. static int ac97_clock;
  53. static char *ac97_quirk;
  54. static bool buggy_semaphore;
  55. static int buggy_irq = -1; /* auto-check */
  56. static bool xbox;
  57. static int spdif_aclink = -1;
  58. static int inside_vm = -1;
  59. module_param(index, int, 0444);
  60. MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  61. module_param(id, charp, 0444);
  62. MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  63. module_param(ac97_clock, int, 0444);
  64. MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect).");
  65. module_param(ac97_quirk, charp, 0444);
  66. MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  67. module_param(buggy_semaphore, bool, 0444);
  68. MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  69. module_param(buggy_irq, bint, 0444);
  70. MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  71. module_param(xbox, bool, 0444);
  72. MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  73. module_param(spdif_aclink, int, 0444);
  74. MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  75. module_param(inside_vm, bint, 0444);
  76. MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
  77. /* just for backward compatibility */
  78. static bool enable;
  79. module_param(enable, bool, 0444);
  80. static int joystick;
  81. module_param(joystick, int, 0444);
  82. /*
  83. * Direct registers
  84. */
  85. enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
  86. #define ICHREG(x) ICH_REG_##x
  87. #define DEFINE_REGSET(name,base) \
  88. enum { \
  89. ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
  90. ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
  91. ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
  92. ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
  93. ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
  94. ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
  95. ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
  96. };
  97. /* busmaster blocks */
  98. DEFINE_REGSET(OFF, 0); /* offset */
  99. DEFINE_REGSET(PI, 0x00); /* PCM in */
  100. DEFINE_REGSET(PO, 0x10); /* PCM out */
  101. DEFINE_REGSET(MC, 0x20); /* Mic in */
  102. /* ICH4 busmaster blocks */
  103. DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
  104. DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
  105. DEFINE_REGSET(SP, 0x60); /* SPDIF out */
  106. /* values for each busmaster block */
  107. /* LVI */
  108. #define ICH_REG_LVI_MASK 0x1f
  109. /* SR */
  110. #define ICH_FIFOE 0x10 /* FIFO error */
  111. #define ICH_BCIS 0x08 /* buffer completion interrupt status */
  112. #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
  113. #define ICH_CELV 0x02 /* current equals last valid */
  114. #define ICH_DCH 0x01 /* DMA controller halted */
  115. /* PIV */
  116. #define ICH_REG_PIV_MASK 0x1f /* mask */
  117. /* CR */
  118. #define ICH_IOCE 0x10 /* interrupt on completion enable */
  119. #define ICH_FEIE 0x08 /* fifo error interrupt enable */
  120. #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
  121. #define ICH_RESETREGS 0x02 /* reset busmaster registers */
  122. #define ICH_STARTBM 0x01 /* start busmaster operation */
  123. /* global block */
  124. #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
  125. #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
  126. #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
  127. #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
  128. #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
  129. #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
  130. #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
  131. #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
  132. #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
  133. #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
  134. #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
  135. #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
  136. #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
  137. #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
  138. #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
  139. #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
  140. #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
  141. #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
  142. #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
  143. #define ICH_ACLINK 0x00000008 /* AClink shut off */
  144. #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
  145. #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
  146. #define ICH_GIE 0x00000001 /* GPI interrupt enable */
  147. #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
  148. #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
  149. #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
  150. #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
  151. #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
  152. #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
  153. #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
  154. #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
  155. #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
  156. #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
  157. #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
  158. #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
  159. #define ICH_MD3 0x00020000 /* modem power down semaphore */
  160. #define ICH_AD3 0x00010000 /* audio power down semaphore */
  161. #define ICH_RCS 0x00008000 /* read completion status */
  162. #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
  163. #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
  164. #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
  165. #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
  166. #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
  167. #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
  168. #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
  169. #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
  170. #define ICH_POINT 0x00000040 /* playback interrupt */
  171. #define ICH_PIINT 0x00000020 /* capture interrupt */
  172. #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
  173. #define ICH_MOINT 0x00000004 /* modem playback interrupt */
  174. #define ICH_MIINT 0x00000002 /* modem capture interrupt */
  175. #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
  176. #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
  177. #define ICH_CAS 0x01 /* codec access semaphore */
  178. #define ICH_REG_SDM 0x80
  179. #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
  180. #define ICH_DI2L_SHIFT 6
  181. #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
  182. #define ICH_DI1L_SHIFT 4
  183. #define ICH_SE 0x00000008 /* steer enable */
  184. #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
  185. #define ICH_MAX_FRAGS 32 /* max hw frags */
  186. /*
  187. * registers for Ali5455
  188. */
  189. /* ALi 5455 busmaster blocks */
  190. DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
  191. DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
  192. DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
  193. DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
  194. DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
  195. DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
  196. DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
  197. DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
  198. DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
  199. DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
  200. DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
  201. enum {
  202. ICH_REG_ALI_SCR = 0x00, /* System Control Register */
  203. ICH_REG_ALI_SSR = 0x04, /* System Status Register */
  204. ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
  205. ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
  206. ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
  207. ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
  208. ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
  209. ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
  210. ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
  211. ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
  212. ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
  213. ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
  214. ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
  215. ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
  216. ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
  217. ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
  218. ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
  219. ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
  220. ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
  221. ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
  222. ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
  223. };
  224. #define ALI_CAS_SEM_BUSY 0x80000000
  225. #define ALI_CPR_ADDR_SECONDARY 0x100
  226. #define ALI_CPR_ADDR_READ 0x80
  227. #define ALI_CSPSR_CODEC_READY 0x08
  228. #define ALI_CSPSR_READ_OK 0x02
  229. #define ALI_CSPSR_WRITE_OK 0x01
  230. /* interrupts for the whole chip by interrupt status register finish */
  231. #define ALI_INT_MICIN2 (1<<26)
  232. #define ALI_INT_PCMIN2 (1<<25)
  233. #define ALI_INT_I2SIN (1<<24)
  234. #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
  235. #define ALI_INT_SPDIFIN (1<<22)
  236. #define ALI_INT_LFEOUT (1<<21)
  237. #define ALI_INT_CENTEROUT (1<<20)
  238. #define ALI_INT_CODECSPDIFOUT (1<<19)
  239. #define ALI_INT_MICIN (1<<18)
  240. #define ALI_INT_PCMOUT (1<<17)
  241. #define ALI_INT_PCMIN (1<<16)
  242. #define ALI_INT_CPRAIS (1<<7) /* command port available */
  243. #define ALI_INT_SPRAIS (1<<5) /* status port available */
  244. #define ALI_INT_GPIO (1<<1)
  245. #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
  246. ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
  247. #define ICH_ALI_SC_RESET (1<<31) /* master reset */
  248. #define ICH_ALI_SC_AC97_DBL (1<<30)
  249. #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
  250. #define ICH_ALI_SC_IN_BITS (3<<18)
  251. #define ICH_ALI_SC_OUT_BITS (3<<16)
  252. #define ICH_ALI_SC_6CH_CFG (3<<14)
  253. #define ICH_ALI_SC_PCM_4 (1<<8)
  254. #define ICH_ALI_SC_PCM_6 (2<<8)
  255. #define ICH_ALI_SC_PCM_246_MASK (3<<8)
  256. #define ICH_ALI_SS_SEC_ID (3<<5)
  257. #define ICH_ALI_SS_PRI_ID (3<<3)
  258. #define ICH_ALI_IF_AC97SP (1<<21)
  259. #define ICH_ALI_IF_MC (1<<20)
  260. #define ICH_ALI_IF_PI (1<<19)
  261. #define ICH_ALI_IF_MC2 (1<<18)
  262. #define ICH_ALI_IF_PI2 (1<<17)
  263. #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
  264. #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
  265. #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
  266. #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
  267. #define ICH_ALI_IF_PO_SPDF (1<<3)
  268. #define ICH_ALI_IF_PO (1<<1)
  269. /*
  270. *
  271. */
  272. enum {
  273. ICHD_PCMIN,
  274. ICHD_PCMOUT,
  275. ICHD_MIC,
  276. ICHD_MIC2,
  277. ICHD_PCM2IN,
  278. ICHD_SPBAR,
  279. ICHD_LAST = ICHD_SPBAR
  280. };
  281. enum {
  282. NVD_PCMIN,
  283. NVD_PCMOUT,
  284. NVD_MIC,
  285. NVD_SPBAR,
  286. NVD_LAST = NVD_SPBAR
  287. };
  288. enum {
  289. ALID_PCMIN,
  290. ALID_PCMOUT,
  291. ALID_MIC,
  292. ALID_AC97SPDIFOUT,
  293. ALID_SPDIFIN,
  294. ALID_SPDIFOUT,
  295. ALID_LAST = ALID_SPDIFOUT
  296. };
  297. #define get_ichdev(substream) (substream->runtime->private_data)
  298. struct ichdev {
  299. unsigned int ichd; /* ich device number */
  300. unsigned long reg_offset; /* offset to bmaddr */
  301. __le32 *bdbar; /* CPU address (32bit) */
  302. unsigned int bdbar_addr; /* PCI bus address (32bit) */
  303. struct snd_pcm_substream *substream;
  304. unsigned int physbuf; /* physical address (32bit) */
  305. unsigned int size;
  306. unsigned int fragsize;
  307. unsigned int fragsize1;
  308. unsigned int position;
  309. unsigned int pos_shift;
  310. unsigned int last_pos;
  311. int frags;
  312. int lvi;
  313. int lvi_frag;
  314. int civ;
  315. int ack;
  316. int ack_reload;
  317. unsigned int ack_bit;
  318. unsigned int roff_sr;
  319. unsigned int roff_picb;
  320. unsigned int int_sta_mask; /* interrupt status mask */
  321. unsigned int ali_slot; /* ALI DMA slot */
  322. struct ac97_pcm *pcm;
  323. int pcm_open_flag;
  324. unsigned int prepared:1;
  325. unsigned int suspended: 1;
  326. };
  327. struct intel8x0 {
  328. unsigned int device_type;
  329. int irq;
  330. void __iomem *addr;
  331. void __iomem *bmaddr;
  332. struct pci_dev *pci;
  333. struct snd_card *card;
  334. int pcm_devs;
  335. struct snd_pcm *pcm[6];
  336. struct ichdev ichd[6];
  337. unsigned multi4: 1,
  338. multi6: 1,
  339. multi8 :1,
  340. dra: 1,
  341. smp20bit: 1;
  342. unsigned in_ac97_init: 1,
  343. in_sdin_init: 1;
  344. unsigned in_measurement: 1; /* during ac97 clock measurement */
  345. unsigned fix_nocache: 1; /* workaround for 440MX */
  346. unsigned buggy_irq: 1; /* workaround for buggy mobos */
  347. unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
  348. unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
  349. unsigned inside_vm: 1; /* enable VM optimization */
  350. int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
  351. unsigned int sdm_saved; /* SDM reg value */
  352. struct snd_ac97_bus *ac97_bus;
  353. struct snd_ac97 *ac97[3];
  354. unsigned int ac97_sdin[3];
  355. unsigned int max_codecs, ncodecs;
  356. const unsigned int *codec_bit;
  357. unsigned int codec_isr_bits;
  358. unsigned int codec_ready_bits;
  359. spinlock_t reg_lock;
  360. u32 bdbars_count;
  361. struct snd_dma_buffer bdbars;
  362. u32 int_sta_reg; /* interrupt status register */
  363. u32 int_sta_mask; /* interrupt status mask */
  364. };
  365. static const struct pci_device_id snd_intel8x0_ids[] = {
  366. { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
  367. { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
  368. { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
  369. { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
  370. { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
  371. { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
  372. { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
  373. { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
  374. { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
  375. { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
  376. { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
  377. { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
  378. { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
  379. { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
  380. { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
  381. { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
  382. { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
  383. { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
  384. { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
  385. { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
  386. { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
  387. { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
  388. { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
  389. { 0, }
  390. };
  391. MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
  392. /*
  393. * Lowlevel I/O - busmaster
  394. */
  395. static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
  396. {
  397. return ioread8(chip->bmaddr + offset);
  398. }
  399. static inline u16 igetword(struct intel8x0 *chip, u32 offset)
  400. {
  401. return ioread16(chip->bmaddr + offset);
  402. }
  403. static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
  404. {
  405. return ioread32(chip->bmaddr + offset);
  406. }
  407. static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
  408. {
  409. iowrite8(val, chip->bmaddr + offset);
  410. }
  411. static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
  412. {
  413. iowrite16(val, chip->bmaddr + offset);
  414. }
  415. static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
  416. {
  417. iowrite32(val, chip->bmaddr + offset);
  418. }
  419. /*
  420. * Lowlevel I/O - AC'97 registers
  421. */
  422. static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
  423. {
  424. return ioread16(chip->addr + offset);
  425. }
  426. static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
  427. {
  428. iowrite16(val, chip->addr + offset);
  429. }
  430. /*
  431. * Basic I/O
  432. */
  433. /*
  434. * access to AC97 codec via normal i/o (for ICH and SIS7012)
  435. */
  436. static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
  437. {
  438. int time;
  439. if (codec > 2)
  440. return -EIO;
  441. if (chip->in_sdin_init) {
  442. /* we don't know the ready bit assignment at the moment */
  443. /* so we check any */
  444. codec = chip->codec_isr_bits;
  445. } else {
  446. codec = chip->codec_bit[chip->ac97_sdin[codec]];
  447. }
  448. /* codec ready ? */
  449. if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
  450. return -EIO;
  451. if (chip->buggy_semaphore)
  452. return 0; /* just ignore ... */
  453. /* Anyone holding a semaphore for 1 msec should be shot... */
  454. time = 100;
  455. do {
  456. if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
  457. return 0;
  458. udelay(10);
  459. } while (time--);
  460. /* access to some forbidden (non existent) ac97 registers will not
  461. * reset the semaphore. So even if you don't get the semaphore, still
  462. * continue the access. We don't need the semaphore anyway. */
  463. dev_err(chip->card->dev,
  464. "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
  465. igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
  466. iagetword(chip, 0); /* clear semaphore flag */
  467. /* I don't care about the semaphore */
  468. return -EBUSY;
  469. }
  470. static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
  471. unsigned short reg,
  472. unsigned short val)
  473. {
  474. struct intel8x0 *chip = ac97->private_data;
  475. if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
  476. if (! chip->in_ac97_init)
  477. dev_err(chip->card->dev,
  478. "codec_write %d: semaphore is not ready for register 0x%x\n",
  479. ac97->num, reg);
  480. }
  481. iaputword(chip, reg + ac97->num * 0x80, val);
  482. }
  483. static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
  484. unsigned short reg)
  485. {
  486. struct intel8x0 *chip = ac97->private_data;
  487. unsigned short res;
  488. unsigned int tmp;
  489. if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
  490. if (! chip->in_ac97_init)
  491. dev_err(chip->card->dev,
  492. "codec_read %d: semaphore is not ready for register 0x%x\n",
  493. ac97->num, reg);
  494. res = 0xffff;
  495. } else {
  496. res = iagetword(chip, reg + ac97->num * 0x80);
  497. if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
  498. /* reset RCS and preserve other R/WC bits */
  499. iputdword(chip, ICHREG(GLOB_STA), tmp &
  500. ~(chip->codec_ready_bits | ICH_GSCI));
  501. if (! chip->in_ac97_init)
  502. dev_err(chip->card->dev,
  503. "codec_read %d: read timeout for register 0x%x\n",
  504. ac97->num, reg);
  505. res = 0xffff;
  506. }
  507. }
  508. return res;
  509. }
  510. static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
  511. unsigned int codec)
  512. {
  513. unsigned int tmp;
  514. if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
  515. iagetword(chip, codec * 0x80);
  516. if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
  517. /* reset RCS and preserve other R/WC bits */
  518. iputdword(chip, ICHREG(GLOB_STA), tmp &
  519. ~(chip->codec_ready_bits | ICH_GSCI));
  520. }
  521. }
  522. }
  523. /*
  524. * access to AC97 for Ali5455
  525. */
  526. static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
  527. {
  528. int count = 0;
  529. for (count = 0; count < 0x7f; count++) {
  530. int val = igetbyte(chip, ICHREG(ALI_CSPSR));
  531. if (val & mask)
  532. return 0;
  533. }
  534. if (! chip->in_ac97_init)
  535. dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
  536. return -EBUSY;
  537. }
  538. static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
  539. {
  540. int time = 100;
  541. if (chip->buggy_semaphore)
  542. return 0; /* just ignore ... */
  543. while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
  544. udelay(1);
  545. if (! time && ! chip->in_ac97_init)
  546. dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
  547. return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
  548. }
  549. static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
  550. {
  551. struct intel8x0 *chip = ac97->private_data;
  552. unsigned short data = 0xffff;
  553. if (snd_intel8x0_ali_codec_semaphore(chip))
  554. goto __err;
  555. reg |= ALI_CPR_ADDR_READ;
  556. if (ac97->num)
  557. reg |= ALI_CPR_ADDR_SECONDARY;
  558. iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
  559. if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
  560. goto __err;
  561. data = igetword(chip, ICHREG(ALI_SPR));
  562. __err:
  563. return data;
  564. }
  565. static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
  566. unsigned short val)
  567. {
  568. struct intel8x0 *chip = ac97->private_data;
  569. if (snd_intel8x0_ali_codec_semaphore(chip))
  570. return;
  571. iputword(chip, ICHREG(ALI_CPR), val);
  572. if (ac97->num)
  573. reg |= ALI_CPR_ADDR_SECONDARY;
  574. iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
  575. snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
  576. }
  577. /*
  578. * DMA I/O
  579. */
  580. static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
  581. {
  582. int idx;
  583. __le32 *bdbar = ichdev->bdbar;
  584. unsigned long port = ichdev->reg_offset;
  585. iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
  586. if (ichdev->size == ichdev->fragsize) {
  587. ichdev->ack_reload = ichdev->ack = 2;
  588. ichdev->fragsize1 = ichdev->fragsize >> 1;
  589. for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
  590. bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
  591. bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  592. ichdev->fragsize1 >> ichdev->pos_shift);
  593. bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
  594. bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  595. ichdev->fragsize1 >> ichdev->pos_shift);
  596. }
  597. ichdev->frags = 2;
  598. } else {
  599. ichdev->ack_reload = ichdev->ack = 1;
  600. ichdev->fragsize1 = ichdev->fragsize;
  601. for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
  602. bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
  603. (((idx >> 1) * ichdev->fragsize) %
  604. ichdev->size));
  605. bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  606. ichdev->fragsize >> ichdev->pos_shift);
  607. #if 0
  608. dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
  609. idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
  610. #endif
  611. }
  612. ichdev->frags = ichdev->size / ichdev->fragsize;
  613. }
  614. iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
  615. ichdev->civ = 0;
  616. iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
  617. ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
  618. ichdev->position = 0;
  619. #if 0
  620. dev_dbg(chip->card->dev,
  621. "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
  622. ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
  623. ichdev->fragsize1);
  624. #endif
  625. /* clear interrupts */
  626. iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
  627. }
  628. /*
  629. * Interrupt handler
  630. */
  631. static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
  632. {
  633. unsigned long port = ichdev->reg_offset;
  634. unsigned long flags;
  635. int status, civ, i, step;
  636. int ack = 0;
  637. if (!(ichdev->prepared || chip->in_measurement) || ichdev->suspended)
  638. return;
  639. spin_lock_irqsave(&chip->reg_lock, flags);
  640. status = igetbyte(chip, port + ichdev->roff_sr);
  641. civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
  642. if (!(status & ICH_BCIS)) {
  643. step = 0;
  644. } else if (civ == ichdev->civ) {
  645. // snd_printd("civ same %d\n", civ);
  646. step = 1;
  647. ichdev->civ++;
  648. ichdev->civ &= ICH_REG_LVI_MASK;
  649. } else {
  650. step = civ - ichdev->civ;
  651. if (step < 0)
  652. step += ICH_REG_LVI_MASK + 1;
  653. // if (step != 1)
  654. // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
  655. ichdev->civ = civ;
  656. }
  657. ichdev->position += step * ichdev->fragsize1;
  658. if (! chip->in_measurement)
  659. ichdev->position %= ichdev->size;
  660. ichdev->lvi += step;
  661. ichdev->lvi &= ICH_REG_LVI_MASK;
  662. iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
  663. for (i = 0; i < step; i++) {
  664. ichdev->lvi_frag++;
  665. ichdev->lvi_frag %= ichdev->frags;
  666. ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
  667. #if 0
  668. dev_dbg(chip->card->dev,
  669. "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
  670. ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
  671. ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
  672. inl(port + 4), inb(port + ICH_REG_OFF_CR));
  673. #endif
  674. if (--ichdev->ack == 0) {
  675. ichdev->ack = ichdev->ack_reload;
  676. ack = 1;
  677. }
  678. }
  679. spin_unlock_irqrestore(&chip->reg_lock, flags);
  680. if (ack && ichdev->substream) {
  681. snd_pcm_period_elapsed(ichdev->substream);
  682. }
  683. iputbyte(chip, port + ichdev->roff_sr,
  684. status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
  685. }
  686. static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
  687. {
  688. struct intel8x0 *chip = dev_id;
  689. struct ichdev *ichdev;
  690. unsigned int status;
  691. unsigned int i;
  692. status = igetdword(chip, chip->int_sta_reg);
  693. if (status == 0xffffffff) /* we are not yet resumed */
  694. return IRQ_NONE;
  695. if ((status & chip->int_sta_mask) == 0) {
  696. if (status) {
  697. /* ack */
  698. iputdword(chip, chip->int_sta_reg, status);
  699. if (! chip->buggy_irq)
  700. status = 0;
  701. }
  702. return IRQ_RETVAL(status);
  703. }
  704. for (i = 0; i < chip->bdbars_count; i++) {
  705. ichdev = &chip->ichd[i];
  706. if (status & ichdev->int_sta_mask)
  707. snd_intel8x0_update(chip, ichdev);
  708. }
  709. /* ack them */
  710. iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
  711. return IRQ_HANDLED;
  712. }
  713. /*
  714. * PCM part
  715. */
  716. static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  717. {
  718. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  719. struct ichdev *ichdev = get_ichdev(substream);
  720. unsigned char val = 0;
  721. unsigned long port = ichdev->reg_offset;
  722. switch (cmd) {
  723. case SNDRV_PCM_TRIGGER_RESUME:
  724. ichdev->suspended = 0;
  725. fallthrough;
  726. case SNDRV_PCM_TRIGGER_START:
  727. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  728. val = ICH_IOCE | ICH_STARTBM;
  729. ichdev->last_pos = ichdev->position;
  730. break;
  731. case SNDRV_PCM_TRIGGER_SUSPEND:
  732. ichdev->suspended = 1;
  733. fallthrough;
  734. case SNDRV_PCM_TRIGGER_STOP:
  735. val = 0;
  736. break;
  737. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  738. val = ICH_IOCE;
  739. break;
  740. default:
  741. return -EINVAL;
  742. }
  743. iputbyte(chip, port + ICH_REG_OFF_CR, val);
  744. if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  745. /* wait until DMA stopped */
  746. while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
  747. /* reset whole DMA things */
  748. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
  749. }
  750. return 0;
  751. }
  752. static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
  753. {
  754. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  755. struct ichdev *ichdev = get_ichdev(substream);
  756. unsigned long port = ichdev->reg_offset;
  757. static const int fiforeg[] = {
  758. ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
  759. };
  760. unsigned int val, fifo;
  761. val = igetdword(chip, ICHREG(ALI_DMACR));
  762. switch (cmd) {
  763. case SNDRV_PCM_TRIGGER_RESUME:
  764. ichdev->suspended = 0;
  765. fallthrough;
  766. case SNDRV_PCM_TRIGGER_START:
  767. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  768. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  769. /* clear FIFO for synchronization of channels */
  770. fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
  771. fifo &= ~(0xff << (ichdev->ali_slot % 4));
  772. fifo |= 0x83 << (ichdev->ali_slot % 4);
  773. iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
  774. }
  775. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
  776. val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
  777. /* start DMA */
  778. iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
  779. break;
  780. case SNDRV_PCM_TRIGGER_SUSPEND:
  781. ichdev->suspended = 1;
  782. fallthrough;
  783. case SNDRV_PCM_TRIGGER_STOP:
  784. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  785. /* pause */
  786. iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
  787. iputbyte(chip, port + ICH_REG_OFF_CR, 0);
  788. while (igetbyte(chip, port + ICH_REG_OFF_CR))
  789. ;
  790. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  791. break;
  792. /* reset whole DMA things */
  793. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
  794. /* clear interrupts */
  795. iputbyte(chip, port + ICH_REG_OFF_SR,
  796. igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
  797. iputdword(chip, ICHREG(ALI_INTERRUPTSR),
  798. igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
  799. break;
  800. default:
  801. return -EINVAL;
  802. }
  803. return 0;
  804. }
  805. static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
  806. struct snd_pcm_hw_params *hw_params)
  807. {
  808. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  809. struct ichdev *ichdev = get_ichdev(substream);
  810. int dbl = params_rate(hw_params) > 48000;
  811. int err;
  812. if (ichdev->pcm_open_flag) {
  813. snd_ac97_pcm_close(ichdev->pcm);
  814. ichdev->pcm_open_flag = 0;
  815. ichdev->prepared = 0;
  816. }
  817. err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
  818. params_channels(hw_params),
  819. ichdev->pcm->r[dbl].slots);
  820. if (err >= 0) {
  821. ichdev->pcm_open_flag = 1;
  822. /* Force SPDIF setting */
  823. if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
  824. snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
  825. params_rate(hw_params));
  826. }
  827. return err;
  828. }
  829. static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
  830. {
  831. struct ichdev *ichdev = get_ichdev(substream);
  832. if (ichdev->pcm_open_flag) {
  833. snd_ac97_pcm_close(ichdev->pcm);
  834. ichdev->pcm_open_flag = 0;
  835. ichdev->prepared = 0;
  836. }
  837. return 0;
  838. }
  839. static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
  840. struct snd_pcm_runtime *runtime)
  841. {
  842. unsigned int cnt;
  843. int dbl = runtime->rate > 48000;
  844. spin_lock_irq(&chip->reg_lock);
  845. switch (chip->device_type) {
  846. case DEVICE_ALI:
  847. cnt = igetdword(chip, ICHREG(ALI_SCR));
  848. cnt &= ~ICH_ALI_SC_PCM_246_MASK;
  849. if (runtime->channels == 4 || dbl)
  850. cnt |= ICH_ALI_SC_PCM_4;
  851. else if (runtime->channels == 6)
  852. cnt |= ICH_ALI_SC_PCM_6;
  853. iputdword(chip, ICHREG(ALI_SCR), cnt);
  854. break;
  855. case DEVICE_SIS:
  856. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  857. cnt &= ~ICH_SIS_PCM_246_MASK;
  858. if (runtime->channels == 4 || dbl)
  859. cnt |= ICH_SIS_PCM_4;
  860. else if (runtime->channels == 6)
  861. cnt |= ICH_SIS_PCM_6;
  862. iputdword(chip, ICHREG(GLOB_CNT), cnt);
  863. break;
  864. default:
  865. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  866. cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
  867. if (runtime->channels == 4 || dbl)
  868. cnt |= ICH_PCM_4;
  869. else if (runtime->channels == 6)
  870. cnt |= ICH_PCM_6;
  871. else if (runtime->channels == 8)
  872. cnt |= ICH_PCM_8;
  873. if (chip->device_type == DEVICE_NFORCE) {
  874. /* reset to 2ch once to keep the 6 channel data in alignment,
  875. * to start from Front Left always
  876. */
  877. if (cnt & ICH_PCM_246_MASK) {
  878. iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
  879. spin_unlock_irq(&chip->reg_lock);
  880. msleep(50); /* grrr... */
  881. spin_lock_irq(&chip->reg_lock);
  882. }
  883. } else if (chip->device_type == DEVICE_INTEL_ICH4) {
  884. if (runtime->sample_bits > 16)
  885. cnt |= ICH_PCM_20BIT;
  886. }
  887. iputdword(chip, ICHREG(GLOB_CNT), cnt);
  888. break;
  889. }
  890. spin_unlock_irq(&chip->reg_lock);
  891. }
  892. static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
  893. {
  894. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  895. struct snd_pcm_runtime *runtime = substream->runtime;
  896. struct ichdev *ichdev = get_ichdev(substream);
  897. ichdev->physbuf = runtime->dma_addr;
  898. ichdev->size = snd_pcm_lib_buffer_bytes(substream);
  899. ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
  900. if (ichdev->ichd == ICHD_PCMOUT) {
  901. snd_intel8x0_setup_pcm_out(chip, runtime);
  902. if (chip->device_type == DEVICE_INTEL_ICH4)
  903. ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
  904. }
  905. snd_intel8x0_setup_periods(chip, ichdev);
  906. ichdev->prepared = 1;
  907. return 0;
  908. }
  909. static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
  910. {
  911. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  912. struct ichdev *ichdev = get_ichdev(substream);
  913. size_t ptr1, ptr;
  914. int civ, timeout = 10;
  915. unsigned int position;
  916. spin_lock(&chip->reg_lock);
  917. do {
  918. civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
  919. ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
  920. position = ichdev->position;
  921. if (ptr1 == 0) {
  922. udelay(10);
  923. continue;
  924. }
  925. if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
  926. continue;
  927. /* IO read operation is very expensive inside virtual machine
  928. * as it is emulated. The probability that subsequent PICB read
  929. * will return different result is high enough to loop till
  930. * timeout here.
  931. * Same CIV is strict enough condition to be sure that PICB
  932. * is valid inside VM on emulated card. */
  933. if (chip->inside_vm)
  934. break;
  935. if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
  936. break;
  937. } while (timeout--);
  938. ptr = ichdev->last_pos;
  939. if (ptr1 != 0) {
  940. ptr1 <<= ichdev->pos_shift;
  941. ptr = ichdev->fragsize1 - ptr1;
  942. ptr += position;
  943. if (ptr < ichdev->last_pos) {
  944. unsigned int pos_base, last_base;
  945. pos_base = position / ichdev->fragsize1;
  946. last_base = ichdev->last_pos / ichdev->fragsize1;
  947. /* another sanity check; ptr1 can go back to full
  948. * before the base position is updated
  949. */
  950. if (pos_base == last_base)
  951. ptr = ichdev->last_pos;
  952. }
  953. }
  954. ichdev->last_pos = ptr;
  955. spin_unlock(&chip->reg_lock);
  956. if (ptr >= ichdev->size)
  957. return 0;
  958. return bytes_to_frames(substream->runtime, ptr);
  959. }
  960. static const struct snd_pcm_hardware snd_intel8x0_stream =
  961. {
  962. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  963. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  964. SNDRV_PCM_INFO_MMAP_VALID |
  965. SNDRV_PCM_INFO_PAUSE |
  966. SNDRV_PCM_INFO_RESUME),
  967. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  968. .rates = SNDRV_PCM_RATE_48000,
  969. .rate_min = 48000,
  970. .rate_max = 48000,
  971. .channels_min = 2,
  972. .channels_max = 2,
  973. .buffer_bytes_max = 128 * 1024,
  974. .period_bytes_min = 32,
  975. .period_bytes_max = 128 * 1024,
  976. .periods_min = 1,
  977. .periods_max = 1024,
  978. .fifo_size = 0,
  979. };
  980. static const unsigned int channels4[] = {
  981. 2, 4,
  982. };
  983. static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
  984. .count = ARRAY_SIZE(channels4),
  985. .list = channels4,
  986. .mask = 0,
  987. };
  988. static const unsigned int channels6[] = {
  989. 2, 4, 6,
  990. };
  991. static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
  992. .count = ARRAY_SIZE(channels6),
  993. .list = channels6,
  994. .mask = 0,
  995. };
  996. static const unsigned int channels8[] = {
  997. 2, 4, 6, 8,
  998. };
  999. static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
  1000. .count = ARRAY_SIZE(channels8),
  1001. .list = channels8,
  1002. .mask = 0,
  1003. };
  1004. static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
  1005. {
  1006. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1007. struct snd_pcm_runtime *runtime = substream->runtime;
  1008. int err;
  1009. ichdev->substream = substream;
  1010. runtime->hw = snd_intel8x0_stream;
  1011. runtime->hw.rates = ichdev->pcm->rates;
  1012. snd_pcm_limit_hw_rates(runtime);
  1013. if (chip->device_type == DEVICE_SIS) {
  1014. runtime->hw.buffer_bytes_max = 64*1024;
  1015. runtime->hw.period_bytes_max = 64*1024;
  1016. }
  1017. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  1018. return err;
  1019. runtime->private_data = ichdev;
  1020. return 0;
  1021. }
  1022. static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
  1023. {
  1024. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1025. struct snd_pcm_runtime *runtime = substream->runtime;
  1026. int err;
  1027. err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
  1028. if (err < 0)
  1029. return err;
  1030. if (chip->multi8) {
  1031. runtime->hw.channels_max = 8;
  1032. snd_pcm_hw_constraint_list(runtime, 0,
  1033. SNDRV_PCM_HW_PARAM_CHANNELS,
  1034. &hw_constraints_channels8);
  1035. } else if (chip->multi6) {
  1036. runtime->hw.channels_max = 6;
  1037. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
  1038. &hw_constraints_channels6);
  1039. } else if (chip->multi4) {
  1040. runtime->hw.channels_max = 4;
  1041. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
  1042. &hw_constraints_channels4);
  1043. }
  1044. if (chip->dra) {
  1045. snd_ac97_pcm_double_rate_rules(runtime);
  1046. }
  1047. if (chip->smp20bit) {
  1048. runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
  1049. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
  1050. }
  1051. return 0;
  1052. }
  1053. static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
  1054. {
  1055. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1056. chip->ichd[ICHD_PCMOUT].substream = NULL;
  1057. return 0;
  1058. }
  1059. static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
  1060. {
  1061. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1062. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
  1063. }
  1064. static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
  1065. {
  1066. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1067. chip->ichd[ICHD_PCMIN].substream = NULL;
  1068. return 0;
  1069. }
  1070. static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
  1071. {
  1072. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1073. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
  1074. }
  1075. static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
  1076. {
  1077. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1078. chip->ichd[ICHD_MIC].substream = NULL;
  1079. return 0;
  1080. }
  1081. static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
  1082. {
  1083. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1084. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
  1085. }
  1086. static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
  1087. {
  1088. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1089. chip->ichd[ICHD_MIC2].substream = NULL;
  1090. return 0;
  1091. }
  1092. static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
  1093. {
  1094. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1095. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
  1096. }
  1097. static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
  1098. {
  1099. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1100. chip->ichd[ICHD_PCM2IN].substream = NULL;
  1101. return 0;
  1102. }
  1103. static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
  1104. {
  1105. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1106. int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
  1107. return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
  1108. }
  1109. static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
  1110. {
  1111. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1112. int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
  1113. chip->ichd[idx].substream = NULL;
  1114. return 0;
  1115. }
  1116. static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
  1117. {
  1118. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1119. unsigned int val;
  1120. spin_lock_irq(&chip->reg_lock);
  1121. val = igetdword(chip, ICHREG(ALI_INTERFACECR));
  1122. val |= ICH_ALI_IF_AC97SP;
  1123. iputdword(chip, ICHREG(ALI_INTERFACECR), val);
  1124. /* also needs to set ALI_SC_CODEC_SPDF correctly */
  1125. spin_unlock_irq(&chip->reg_lock);
  1126. return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
  1127. }
  1128. static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
  1129. {
  1130. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1131. unsigned int val;
  1132. chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
  1133. spin_lock_irq(&chip->reg_lock);
  1134. val = igetdword(chip, ICHREG(ALI_INTERFACECR));
  1135. val &= ~ICH_ALI_IF_AC97SP;
  1136. iputdword(chip, ICHREG(ALI_INTERFACECR), val);
  1137. spin_unlock_irq(&chip->reg_lock);
  1138. return 0;
  1139. }
  1140. #if 0 // NYI
  1141. static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
  1142. {
  1143. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1144. return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
  1145. }
  1146. static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
  1147. {
  1148. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1149. chip->ichd[ALID_SPDIFIN].substream = NULL;
  1150. return 0;
  1151. }
  1152. static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
  1153. {
  1154. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1155. return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
  1156. }
  1157. static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
  1158. {
  1159. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1160. chip->ichd[ALID_SPDIFOUT].substream = NULL;
  1161. return 0;
  1162. }
  1163. #endif
  1164. static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
  1165. .open = snd_intel8x0_playback_open,
  1166. .close = snd_intel8x0_playback_close,
  1167. .hw_params = snd_intel8x0_hw_params,
  1168. .hw_free = snd_intel8x0_hw_free,
  1169. .prepare = snd_intel8x0_pcm_prepare,
  1170. .trigger = snd_intel8x0_pcm_trigger,
  1171. .pointer = snd_intel8x0_pcm_pointer,
  1172. };
  1173. static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
  1174. .open = snd_intel8x0_capture_open,
  1175. .close = snd_intel8x0_capture_close,
  1176. .hw_params = snd_intel8x0_hw_params,
  1177. .hw_free = snd_intel8x0_hw_free,
  1178. .prepare = snd_intel8x0_pcm_prepare,
  1179. .trigger = snd_intel8x0_pcm_trigger,
  1180. .pointer = snd_intel8x0_pcm_pointer,
  1181. };
  1182. static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
  1183. .open = snd_intel8x0_mic_open,
  1184. .close = snd_intel8x0_mic_close,
  1185. .hw_params = snd_intel8x0_hw_params,
  1186. .hw_free = snd_intel8x0_hw_free,
  1187. .prepare = snd_intel8x0_pcm_prepare,
  1188. .trigger = snd_intel8x0_pcm_trigger,
  1189. .pointer = snd_intel8x0_pcm_pointer,
  1190. };
  1191. static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
  1192. .open = snd_intel8x0_mic2_open,
  1193. .close = snd_intel8x0_mic2_close,
  1194. .hw_params = snd_intel8x0_hw_params,
  1195. .hw_free = snd_intel8x0_hw_free,
  1196. .prepare = snd_intel8x0_pcm_prepare,
  1197. .trigger = snd_intel8x0_pcm_trigger,
  1198. .pointer = snd_intel8x0_pcm_pointer,
  1199. };
  1200. static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
  1201. .open = snd_intel8x0_capture2_open,
  1202. .close = snd_intel8x0_capture2_close,
  1203. .hw_params = snd_intel8x0_hw_params,
  1204. .hw_free = snd_intel8x0_hw_free,
  1205. .prepare = snd_intel8x0_pcm_prepare,
  1206. .trigger = snd_intel8x0_pcm_trigger,
  1207. .pointer = snd_intel8x0_pcm_pointer,
  1208. };
  1209. static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
  1210. .open = snd_intel8x0_spdif_open,
  1211. .close = snd_intel8x0_spdif_close,
  1212. .hw_params = snd_intel8x0_hw_params,
  1213. .hw_free = snd_intel8x0_hw_free,
  1214. .prepare = snd_intel8x0_pcm_prepare,
  1215. .trigger = snd_intel8x0_pcm_trigger,
  1216. .pointer = snd_intel8x0_pcm_pointer,
  1217. };
  1218. static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
  1219. .open = snd_intel8x0_playback_open,
  1220. .close = snd_intel8x0_playback_close,
  1221. .hw_params = snd_intel8x0_hw_params,
  1222. .hw_free = snd_intel8x0_hw_free,
  1223. .prepare = snd_intel8x0_pcm_prepare,
  1224. .trigger = snd_intel8x0_ali_trigger,
  1225. .pointer = snd_intel8x0_pcm_pointer,
  1226. };
  1227. static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
  1228. .open = snd_intel8x0_capture_open,
  1229. .close = snd_intel8x0_capture_close,
  1230. .hw_params = snd_intel8x0_hw_params,
  1231. .hw_free = snd_intel8x0_hw_free,
  1232. .prepare = snd_intel8x0_pcm_prepare,
  1233. .trigger = snd_intel8x0_ali_trigger,
  1234. .pointer = snd_intel8x0_pcm_pointer,
  1235. };
  1236. static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
  1237. .open = snd_intel8x0_mic_open,
  1238. .close = snd_intel8x0_mic_close,
  1239. .hw_params = snd_intel8x0_hw_params,
  1240. .hw_free = snd_intel8x0_hw_free,
  1241. .prepare = snd_intel8x0_pcm_prepare,
  1242. .trigger = snd_intel8x0_ali_trigger,
  1243. .pointer = snd_intel8x0_pcm_pointer,
  1244. };
  1245. static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
  1246. .open = snd_intel8x0_ali_ac97spdifout_open,
  1247. .close = snd_intel8x0_ali_ac97spdifout_close,
  1248. .hw_params = snd_intel8x0_hw_params,
  1249. .hw_free = snd_intel8x0_hw_free,
  1250. .prepare = snd_intel8x0_pcm_prepare,
  1251. .trigger = snd_intel8x0_ali_trigger,
  1252. .pointer = snd_intel8x0_pcm_pointer,
  1253. };
  1254. #if 0 // NYI
  1255. static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
  1256. .open = snd_intel8x0_ali_spdifin_open,
  1257. .close = snd_intel8x0_ali_spdifin_close,
  1258. .hw_params = snd_intel8x0_hw_params,
  1259. .hw_free = snd_intel8x0_hw_free,
  1260. .prepare = snd_intel8x0_pcm_prepare,
  1261. .trigger = snd_intel8x0_pcm_trigger,
  1262. .pointer = snd_intel8x0_pcm_pointer,
  1263. };
  1264. static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
  1265. .open = snd_intel8x0_ali_spdifout_open,
  1266. .close = snd_intel8x0_ali_spdifout_close,
  1267. .hw_params = snd_intel8x0_hw_params,
  1268. .hw_free = snd_intel8x0_hw_free,
  1269. .prepare = snd_intel8x0_pcm_prepare,
  1270. .trigger = snd_intel8x0_pcm_trigger,
  1271. .pointer = snd_intel8x0_pcm_pointer,
  1272. };
  1273. #endif // NYI
  1274. struct ich_pcm_table {
  1275. char *suffix;
  1276. const struct snd_pcm_ops *playback_ops;
  1277. const struct snd_pcm_ops *capture_ops;
  1278. size_t prealloc_size;
  1279. size_t prealloc_max_size;
  1280. int ac97_idx;
  1281. };
  1282. #define intel8x0_dma_type(chip) \
  1283. ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_UC : SNDRV_DMA_TYPE_DEV)
  1284. static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
  1285. const struct ich_pcm_table *rec)
  1286. {
  1287. struct snd_pcm *pcm;
  1288. int err;
  1289. char name[32];
  1290. if (rec->suffix)
  1291. sprintf(name, "Intel ICH - %s", rec->suffix);
  1292. else
  1293. strcpy(name, "Intel ICH");
  1294. err = snd_pcm_new(chip->card, name, device,
  1295. rec->playback_ops ? 1 : 0,
  1296. rec->capture_ops ? 1 : 0, &pcm);
  1297. if (err < 0)
  1298. return err;
  1299. if (rec->playback_ops)
  1300. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
  1301. if (rec->capture_ops)
  1302. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
  1303. pcm->private_data = chip;
  1304. pcm->info_flags = 0;
  1305. if (rec->suffix)
  1306. sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
  1307. else
  1308. strcpy(pcm->name, chip->card->shortname);
  1309. chip->pcm[device] = pcm;
  1310. snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip),
  1311. &chip->pci->dev,
  1312. rec->prealloc_size, rec->prealloc_max_size);
  1313. if (rec->playback_ops &&
  1314. rec->playback_ops->open == snd_intel8x0_playback_open) {
  1315. struct snd_pcm_chmap *chmap;
  1316. int chs = 2;
  1317. if (chip->multi8)
  1318. chs = 8;
  1319. else if (chip->multi6)
  1320. chs = 6;
  1321. else if (chip->multi4)
  1322. chs = 4;
  1323. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1324. snd_pcm_alt_chmaps, chs, 0,
  1325. &chmap);
  1326. if (err < 0)
  1327. return err;
  1328. chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
  1329. chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
  1330. }
  1331. return 0;
  1332. }
  1333. static const struct ich_pcm_table intel_pcms[] = {
  1334. {
  1335. .playback_ops = &snd_intel8x0_playback_ops,
  1336. .capture_ops = &snd_intel8x0_capture_ops,
  1337. .prealloc_size = 64 * 1024,
  1338. .prealloc_max_size = 128 * 1024,
  1339. },
  1340. {
  1341. .suffix = "MIC ADC",
  1342. .capture_ops = &snd_intel8x0_capture_mic_ops,
  1343. .prealloc_size = 0,
  1344. .prealloc_max_size = 128 * 1024,
  1345. .ac97_idx = ICHD_MIC,
  1346. },
  1347. {
  1348. .suffix = "MIC2 ADC",
  1349. .capture_ops = &snd_intel8x0_capture_mic2_ops,
  1350. .prealloc_size = 0,
  1351. .prealloc_max_size = 128 * 1024,
  1352. .ac97_idx = ICHD_MIC2,
  1353. },
  1354. {
  1355. .suffix = "ADC2",
  1356. .capture_ops = &snd_intel8x0_capture2_ops,
  1357. .prealloc_size = 0,
  1358. .prealloc_max_size = 128 * 1024,
  1359. .ac97_idx = ICHD_PCM2IN,
  1360. },
  1361. {
  1362. .suffix = "IEC958",
  1363. .playback_ops = &snd_intel8x0_spdif_ops,
  1364. .prealloc_size = 64 * 1024,
  1365. .prealloc_max_size = 128 * 1024,
  1366. .ac97_idx = ICHD_SPBAR,
  1367. },
  1368. };
  1369. static const struct ich_pcm_table nforce_pcms[] = {
  1370. {
  1371. .playback_ops = &snd_intel8x0_playback_ops,
  1372. .capture_ops = &snd_intel8x0_capture_ops,
  1373. .prealloc_size = 64 * 1024,
  1374. .prealloc_max_size = 128 * 1024,
  1375. },
  1376. {
  1377. .suffix = "MIC ADC",
  1378. .capture_ops = &snd_intel8x0_capture_mic_ops,
  1379. .prealloc_size = 0,
  1380. .prealloc_max_size = 128 * 1024,
  1381. .ac97_idx = NVD_MIC,
  1382. },
  1383. {
  1384. .suffix = "IEC958",
  1385. .playback_ops = &snd_intel8x0_spdif_ops,
  1386. .prealloc_size = 64 * 1024,
  1387. .prealloc_max_size = 128 * 1024,
  1388. .ac97_idx = NVD_SPBAR,
  1389. },
  1390. };
  1391. static const struct ich_pcm_table ali_pcms[] = {
  1392. {
  1393. .playback_ops = &snd_intel8x0_ali_playback_ops,
  1394. .capture_ops = &snd_intel8x0_ali_capture_ops,
  1395. .prealloc_size = 64 * 1024,
  1396. .prealloc_max_size = 128 * 1024,
  1397. },
  1398. {
  1399. .suffix = "MIC ADC",
  1400. .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
  1401. .prealloc_size = 0,
  1402. .prealloc_max_size = 128 * 1024,
  1403. .ac97_idx = ALID_MIC,
  1404. },
  1405. {
  1406. .suffix = "IEC958",
  1407. .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
  1408. /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
  1409. .prealloc_size = 64 * 1024,
  1410. .prealloc_max_size = 128 * 1024,
  1411. .ac97_idx = ALID_AC97SPDIFOUT,
  1412. },
  1413. #if 0 // NYI
  1414. {
  1415. .suffix = "HW IEC958",
  1416. .playback_ops = &snd_intel8x0_ali_spdifout_ops,
  1417. .prealloc_size = 64 * 1024,
  1418. .prealloc_max_size = 128 * 1024,
  1419. },
  1420. #endif
  1421. };
  1422. static int snd_intel8x0_pcm(struct intel8x0 *chip)
  1423. {
  1424. int i, tblsize, device, err;
  1425. const struct ich_pcm_table *tbl, *rec;
  1426. switch (chip->device_type) {
  1427. case DEVICE_INTEL_ICH4:
  1428. tbl = intel_pcms;
  1429. tblsize = ARRAY_SIZE(intel_pcms);
  1430. if (spdif_aclink)
  1431. tblsize--;
  1432. break;
  1433. case DEVICE_NFORCE:
  1434. tbl = nforce_pcms;
  1435. tblsize = ARRAY_SIZE(nforce_pcms);
  1436. if (spdif_aclink)
  1437. tblsize--;
  1438. break;
  1439. case DEVICE_ALI:
  1440. tbl = ali_pcms;
  1441. tblsize = ARRAY_SIZE(ali_pcms);
  1442. break;
  1443. default:
  1444. tbl = intel_pcms;
  1445. tblsize = 2;
  1446. break;
  1447. }
  1448. device = 0;
  1449. for (i = 0; i < tblsize; i++) {
  1450. rec = tbl + i;
  1451. if (i > 0 && rec->ac97_idx) {
  1452. /* activate PCM only when associated AC'97 codec */
  1453. if (! chip->ichd[rec->ac97_idx].pcm)
  1454. continue;
  1455. }
  1456. err = snd_intel8x0_pcm1(chip, device, rec);
  1457. if (err < 0)
  1458. return err;
  1459. device++;
  1460. }
  1461. chip->pcm_devs = device;
  1462. return 0;
  1463. }
  1464. /*
  1465. * Mixer part
  1466. */
  1467. static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1468. {
  1469. struct intel8x0 *chip = bus->private_data;
  1470. chip->ac97_bus = NULL;
  1471. }
  1472. static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
  1473. {
  1474. struct intel8x0 *chip = ac97->private_data;
  1475. chip->ac97[ac97->num] = NULL;
  1476. }
  1477. static const struct ac97_pcm ac97_pcm_defs[] = {
  1478. /* front PCM */
  1479. {
  1480. .exclusive = 1,
  1481. .r = { {
  1482. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1483. (1 << AC97_SLOT_PCM_RIGHT) |
  1484. (1 << AC97_SLOT_PCM_CENTER) |
  1485. (1 << AC97_SLOT_PCM_SLEFT) |
  1486. (1 << AC97_SLOT_PCM_SRIGHT) |
  1487. (1 << AC97_SLOT_LFE)
  1488. },
  1489. {
  1490. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1491. (1 << AC97_SLOT_PCM_RIGHT) |
  1492. (1 << AC97_SLOT_PCM_LEFT_0) |
  1493. (1 << AC97_SLOT_PCM_RIGHT_0)
  1494. }
  1495. }
  1496. },
  1497. /* PCM IN #1 */
  1498. {
  1499. .stream = 1,
  1500. .exclusive = 1,
  1501. .r = { {
  1502. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1503. (1 << AC97_SLOT_PCM_RIGHT)
  1504. }
  1505. }
  1506. },
  1507. /* MIC IN #1 */
  1508. {
  1509. .stream = 1,
  1510. .exclusive = 1,
  1511. .r = { {
  1512. .slots = (1 << AC97_SLOT_MIC)
  1513. }
  1514. }
  1515. },
  1516. /* S/PDIF PCM */
  1517. {
  1518. .exclusive = 1,
  1519. .spdif = 1,
  1520. .r = { {
  1521. .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
  1522. (1 << AC97_SLOT_SPDIF_RIGHT2)
  1523. }
  1524. }
  1525. },
  1526. /* PCM IN #2 */
  1527. {
  1528. .stream = 1,
  1529. .exclusive = 1,
  1530. .r = { {
  1531. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1532. (1 << AC97_SLOT_PCM_RIGHT)
  1533. }
  1534. }
  1535. },
  1536. /* MIC IN #2 */
  1537. {
  1538. .stream = 1,
  1539. .exclusive = 1,
  1540. .r = { {
  1541. .slots = (1 << AC97_SLOT_MIC)
  1542. }
  1543. }
  1544. },
  1545. };
  1546. static const struct ac97_quirk ac97_quirks[] = {
  1547. {
  1548. .subvendor = 0x0e11,
  1549. .subdevice = 0x000e,
  1550. .name = "Compaq Deskpro EN", /* AD1885 */
  1551. .type = AC97_TUNE_HP_ONLY
  1552. },
  1553. {
  1554. .subvendor = 0x0e11,
  1555. .subdevice = 0x008a,
  1556. .name = "Compaq Evo W4000", /* AD1885 */
  1557. .type = AC97_TUNE_HP_ONLY
  1558. },
  1559. {
  1560. .subvendor = 0x0e11,
  1561. .subdevice = 0x00b8,
  1562. .name = "Compaq Evo D510C",
  1563. .type = AC97_TUNE_HP_ONLY
  1564. },
  1565. {
  1566. .subvendor = 0x0e11,
  1567. .subdevice = 0x0860,
  1568. .name = "HP/Compaq nx7010",
  1569. .type = AC97_TUNE_MUTE_LED
  1570. },
  1571. {
  1572. .subvendor = 0x1014,
  1573. .subdevice = 0x0534,
  1574. .name = "ThinkPad X31",
  1575. .type = AC97_TUNE_INV_EAPD
  1576. },
  1577. {
  1578. .subvendor = 0x1014,
  1579. .subdevice = 0x1f00,
  1580. .name = "MS-9128",
  1581. .type = AC97_TUNE_ALC_JACK
  1582. },
  1583. {
  1584. .subvendor = 0x1014,
  1585. .subdevice = 0x0267,
  1586. .name = "IBM NetVista A30p", /* AD1981B */
  1587. .type = AC97_TUNE_HP_ONLY
  1588. },
  1589. {
  1590. .subvendor = 0x1025,
  1591. .subdevice = 0x0082,
  1592. .name = "Acer Travelmate 2310",
  1593. .type = AC97_TUNE_HP_ONLY
  1594. },
  1595. {
  1596. .subvendor = 0x1025,
  1597. .subdevice = 0x0083,
  1598. .name = "Acer Aspire 3003LCi",
  1599. .type = AC97_TUNE_HP_ONLY
  1600. },
  1601. {
  1602. .subvendor = 0x1028,
  1603. .subdevice = 0x00d8,
  1604. .name = "Dell Precision 530", /* AD1885 */
  1605. .type = AC97_TUNE_HP_ONLY
  1606. },
  1607. {
  1608. .subvendor = 0x1028,
  1609. .subdevice = 0x010d,
  1610. .name = "Dell", /* which model? AD1885 */
  1611. .type = AC97_TUNE_HP_ONLY
  1612. },
  1613. {
  1614. .subvendor = 0x1028,
  1615. .subdevice = 0x0126,
  1616. .name = "Dell Optiplex GX260", /* AD1981A */
  1617. .type = AC97_TUNE_HP_ONLY
  1618. },
  1619. {
  1620. .subvendor = 0x1028,
  1621. .subdevice = 0x012c,
  1622. .name = "Dell Precision 650", /* AD1981A */
  1623. .type = AC97_TUNE_HP_ONLY
  1624. },
  1625. {
  1626. .subvendor = 0x1028,
  1627. .subdevice = 0x012d,
  1628. .name = "Dell Precision 450", /* AD1981B*/
  1629. .type = AC97_TUNE_HP_ONLY
  1630. },
  1631. {
  1632. .subvendor = 0x1028,
  1633. .subdevice = 0x0147,
  1634. .name = "Dell", /* which model? AD1981B*/
  1635. .type = AC97_TUNE_HP_ONLY
  1636. },
  1637. {
  1638. .subvendor = 0x1028,
  1639. .subdevice = 0x0151,
  1640. .name = "Dell Optiplex GX270", /* AD1981B */
  1641. .type = AC97_TUNE_HP_ONLY
  1642. },
  1643. {
  1644. .subvendor = 0x1028,
  1645. .subdevice = 0x014e,
  1646. .name = "Dell D800", /* STAC9750/51 */
  1647. .type = AC97_TUNE_HP_ONLY
  1648. },
  1649. {
  1650. .subvendor = 0x1028,
  1651. .subdevice = 0x0163,
  1652. .name = "Dell Unknown", /* STAC9750/51 */
  1653. .type = AC97_TUNE_HP_ONLY
  1654. },
  1655. {
  1656. .subvendor = 0x1028,
  1657. .subdevice = 0x016a,
  1658. .name = "Dell Inspiron 8600", /* STAC9750/51 */
  1659. .type = AC97_TUNE_HP_ONLY
  1660. },
  1661. {
  1662. .subvendor = 0x1028,
  1663. .subdevice = 0x0182,
  1664. .name = "Dell Latitude D610", /* STAC9750/51 */
  1665. .type = AC97_TUNE_HP_ONLY
  1666. },
  1667. {
  1668. .subvendor = 0x1028,
  1669. .subdevice = 0x0186,
  1670. .name = "Dell Latitude D810", /* cf. Malone #41015 */
  1671. .type = AC97_TUNE_HP_MUTE_LED
  1672. },
  1673. {
  1674. .subvendor = 0x1028,
  1675. .subdevice = 0x0188,
  1676. .name = "Dell Inspiron 6000",
  1677. .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
  1678. },
  1679. {
  1680. .subvendor = 0x1028,
  1681. .subdevice = 0x0189,
  1682. .name = "Dell Inspiron 9300",
  1683. .type = AC97_TUNE_HP_MUTE_LED
  1684. },
  1685. {
  1686. .subvendor = 0x1028,
  1687. .subdevice = 0x0191,
  1688. .name = "Dell Inspiron 8600",
  1689. .type = AC97_TUNE_HP_ONLY
  1690. },
  1691. {
  1692. .subvendor = 0x103c,
  1693. .subdevice = 0x006d,
  1694. .name = "HP zv5000",
  1695. .type = AC97_TUNE_MUTE_LED /*AD1981B*/
  1696. },
  1697. { /* FIXME: which codec? */
  1698. .subvendor = 0x103c,
  1699. .subdevice = 0x00c3,
  1700. .name = "HP xw6000",
  1701. .type = AC97_TUNE_HP_ONLY
  1702. },
  1703. {
  1704. .subvendor = 0x103c,
  1705. .subdevice = 0x088c,
  1706. .name = "HP nc8000",
  1707. .type = AC97_TUNE_HP_MUTE_LED
  1708. },
  1709. {
  1710. .subvendor = 0x103c,
  1711. .subdevice = 0x0890,
  1712. .name = "HP nc6000",
  1713. .type = AC97_TUNE_MUTE_LED
  1714. },
  1715. {
  1716. .subvendor = 0x103c,
  1717. .subdevice = 0x129d,
  1718. .name = "HP xw8000",
  1719. .type = AC97_TUNE_HP_ONLY
  1720. },
  1721. {
  1722. .subvendor = 0x103c,
  1723. .subdevice = 0x0938,
  1724. .name = "HP nc4200",
  1725. .type = AC97_TUNE_HP_MUTE_LED
  1726. },
  1727. {
  1728. .subvendor = 0x103c,
  1729. .subdevice = 0x099c,
  1730. .name = "HP nx6110/nc6120",
  1731. .type = AC97_TUNE_HP_MUTE_LED
  1732. },
  1733. {
  1734. .subvendor = 0x103c,
  1735. .subdevice = 0x0944,
  1736. .name = "HP nc6220",
  1737. .type = AC97_TUNE_HP_MUTE_LED
  1738. },
  1739. {
  1740. .subvendor = 0x103c,
  1741. .subdevice = 0x0934,
  1742. .name = "HP nc8220",
  1743. .type = AC97_TUNE_HP_MUTE_LED
  1744. },
  1745. {
  1746. .subvendor = 0x103c,
  1747. .subdevice = 0x12f1,
  1748. .name = "HP xw8200", /* AD1981B*/
  1749. .type = AC97_TUNE_HP_ONLY
  1750. },
  1751. {
  1752. .subvendor = 0x103c,
  1753. .subdevice = 0x12f2,
  1754. .name = "HP xw6200",
  1755. .type = AC97_TUNE_HP_ONLY
  1756. },
  1757. {
  1758. .subvendor = 0x103c,
  1759. .subdevice = 0x3008,
  1760. .name = "HP xw4200", /* AD1981B*/
  1761. .type = AC97_TUNE_HP_ONLY
  1762. },
  1763. {
  1764. .subvendor = 0x104d,
  1765. .subdevice = 0x8144,
  1766. .name = "Sony",
  1767. .type = AC97_TUNE_INV_EAPD
  1768. },
  1769. {
  1770. .subvendor = 0x104d,
  1771. .subdevice = 0x8197,
  1772. .name = "Sony S1XP",
  1773. .type = AC97_TUNE_INV_EAPD
  1774. },
  1775. {
  1776. .subvendor = 0x104d,
  1777. .subdevice = 0x81c0,
  1778. .name = "Sony VAIO VGN-T350P", /*AD1981B*/
  1779. .type = AC97_TUNE_INV_EAPD
  1780. },
  1781. {
  1782. .subvendor = 0x104d,
  1783. .subdevice = 0x81c5,
  1784. .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
  1785. .type = AC97_TUNE_INV_EAPD
  1786. },
  1787. {
  1788. .subvendor = 0x1043,
  1789. .subdevice = 0x80f3,
  1790. .name = "ASUS ICH5/AD1985",
  1791. .type = AC97_TUNE_AD_SHARING
  1792. },
  1793. {
  1794. .subvendor = 0x10cf,
  1795. .subdevice = 0x11c3,
  1796. .name = "Fujitsu-Siemens E4010",
  1797. .type = AC97_TUNE_HP_ONLY
  1798. },
  1799. {
  1800. .subvendor = 0x10cf,
  1801. .subdevice = 0x1225,
  1802. .name = "Fujitsu-Siemens T3010",
  1803. .type = AC97_TUNE_HP_ONLY
  1804. },
  1805. {
  1806. .subvendor = 0x10cf,
  1807. .subdevice = 0x1253,
  1808. .name = "Fujitsu S6210", /* STAC9750/51 */
  1809. .type = AC97_TUNE_HP_ONLY
  1810. },
  1811. {
  1812. .subvendor = 0x10cf,
  1813. .subdevice = 0x127d,
  1814. .name = "Fujitsu Lifebook P7010",
  1815. .type = AC97_TUNE_HP_ONLY
  1816. },
  1817. {
  1818. .subvendor = 0x10cf,
  1819. .subdevice = 0x127e,
  1820. .name = "Fujitsu Lifebook C1211D",
  1821. .type = AC97_TUNE_HP_ONLY
  1822. },
  1823. {
  1824. .subvendor = 0x10cf,
  1825. .subdevice = 0x12ec,
  1826. .name = "Fujitsu-Siemens 4010",
  1827. .type = AC97_TUNE_HP_ONLY
  1828. },
  1829. {
  1830. .subvendor = 0x10cf,
  1831. .subdevice = 0x12f2,
  1832. .name = "Fujitsu-Siemens Celsius H320",
  1833. .type = AC97_TUNE_SWAP_HP
  1834. },
  1835. {
  1836. .subvendor = 0x10f1,
  1837. .subdevice = 0x2665,
  1838. .name = "Fujitsu-Siemens Celsius", /* AD1981? */
  1839. .type = AC97_TUNE_HP_ONLY
  1840. },
  1841. {
  1842. .subvendor = 0x10f1,
  1843. .subdevice = 0x2885,
  1844. .name = "AMD64 Mobo", /* ALC650 */
  1845. .type = AC97_TUNE_HP_ONLY
  1846. },
  1847. {
  1848. .subvendor = 0x10f1,
  1849. .subdevice = 0x2895,
  1850. .name = "Tyan Thunder K8WE",
  1851. .type = AC97_TUNE_HP_ONLY
  1852. },
  1853. {
  1854. .subvendor = 0x10f7,
  1855. .subdevice = 0x834c,
  1856. .name = "Panasonic CF-R4",
  1857. .type = AC97_TUNE_HP_ONLY,
  1858. },
  1859. {
  1860. .subvendor = 0x110a,
  1861. .subdevice = 0x0056,
  1862. .name = "Fujitsu-Siemens Scenic", /* AD1981? */
  1863. .type = AC97_TUNE_HP_ONLY
  1864. },
  1865. {
  1866. .subvendor = 0x11d4,
  1867. .subdevice = 0x5375,
  1868. .name = "ADI AD1985 (discrete)",
  1869. .type = AC97_TUNE_HP_ONLY
  1870. },
  1871. {
  1872. .subvendor = 0x1462,
  1873. .subdevice = 0x5470,
  1874. .name = "MSI P4 ATX 645 Ultra",
  1875. .type = AC97_TUNE_HP_ONLY
  1876. },
  1877. {
  1878. .subvendor = 0x161f,
  1879. .subdevice = 0x202f,
  1880. .name = "Gateway M520",
  1881. .type = AC97_TUNE_INV_EAPD
  1882. },
  1883. {
  1884. .subvendor = 0x161f,
  1885. .subdevice = 0x203a,
  1886. .name = "Gateway 4525GZ", /* AD1981B */
  1887. .type = AC97_TUNE_INV_EAPD
  1888. },
  1889. {
  1890. .subvendor = 0x1734,
  1891. .subdevice = 0x0088,
  1892. .name = "Fujitsu-Siemens D1522", /* AD1981 */
  1893. .type = AC97_TUNE_HP_ONLY
  1894. },
  1895. {
  1896. .subvendor = 0x8086,
  1897. .subdevice = 0x2000,
  1898. .mask = 0xfff0,
  1899. .name = "Intel ICH5/AD1985",
  1900. .type = AC97_TUNE_AD_SHARING
  1901. },
  1902. {
  1903. .subvendor = 0x8086,
  1904. .subdevice = 0x4000,
  1905. .mask = 0xfff0,
  1906. .name = "Intel ICH5/AD1985",
  1907. .type = AC97_TUNE_AD_SHARING
  1908. },
  1909. {
  1910. .subvendor = 0x8086,
  1911. .subdevice = 0x4856,
  1912. .name = "Intel D845WN (82801BA)",
  1913. .type = AC97_TUNE_SWAP_HP
  1914. },
  1915. {
  1916. .subvendor = 0x8086,
  1917. .subdevice = 0x4d44,
  1918. .name = "Intel D850EMV2", /* AD1885 */
  1919. .type = AC97_TUNE_HP_ONLY
  1920. },
  1921. {
  1922. .subvendor = 0x8086,
  1923. .subdevice = 0x4d56,
  1924. .name = "Intel ICH/AD1885",
  1925. .type = AC97_TUNE_HP_ONLY
  1926. },
  1927. {
  1928. .subvendor = 0x8086,
  1929. .subdevice = 0x6000,
  1930. .mask = 0xfff0,
  1931. .name = "Intel ICH5/AD1985",
  1932. .type = AC97_TUNE_AD_SHARING
  1933. },
  1934. {
  1935. .subvendor = 0x8086,
  1936. .subdevice = 0xe000,
  1937. .mask = 0xfff0,
  1938. .name = "Intel ICH5/AD1985",
  1939. .type = AC97_TUNE_AD_SHARING
  1940. },
  1941. #if 0 /* FIXME: this seems wrong on most boards */
  1942. {
  1943. .subvendor = 0x8086,
  1944. .subdevice = 0xa000,
  1945. .mask = 0xfff0,
  1946. .name = "Intel ICH5/AD1985",
  1947. .type = AC97_TUNE_HP_ONLY
  1948. },
  1949. #endif
  1950. { } /* terminator */
  1951. };
  1952. static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
  1953. const char *quirk_override)
  1954. {
  1955. struct snd_ac97_bus *pbus;
  1956. struct snd_ac97_template ac97;
  1957. int err;
  1958. unsigned int i, codecs;
  1959. unsigned int glob_sta = 0;
  1960. const struct snd_ac97_bus_ops *ops;
  1961. static const struct snd_ac97_bus_ops standard_bus_ops = {
  1962. .write = snd_intel8x0_codec_write,
  1963. .read = snd_intel8x0_codec_read,
  1964. };
  1965. static const struct snd_ac97_bus_ops ali_bus_ops = {
  1966. .write = snd_intel8x0_ali_codec_write,
  1967. .read = snd_intel8x0_ali_codec_read,
  1968. };
  1969. chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
  1970. if (!spdif_aclink) {
  1971. switch (chip->device_type) {
  1972. case DEVICE_NFORCE:
  1973. chip->spdif_idx = NVD_SPBAR;
  1974. break;
  1975. case DEVICE_ALI:
  1976. chip->spdif_idx = ALID_AC97SPDIFOUT;
  1977. break;
  1978. case DEVICE_INTEL_ICH4:
  1979. chip->spdif_idx = ICHD_SPBAR;
  1980. break;
  1981. }
  1982. }
  1983. chip->in_ac97_init = 1;
  1984. memset(&ac97, 0, sizeof(ac97));
  1985. ac97.private_data = chip;
  1986. ac97.private_free = snd_intel8x0_mixer_free_ac97;
  1987. ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
  1988. if (chip->xbox)
  1989. ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
  1990. if (chip->device_type != DEVICE_ALI) {
  1991. glob_sta = igetdword(chip, ICHREG(GLOB_STA));
  1992. ops = &standard_bus_ops;
  1993. chip->in_sdin_init = 1;
  1994. codecs = 0;
  1995. for (i = 0; i < chip->max_codecs; i++) {
  1996. if (! (glob_sta & chip->codec_bit[i]))
  1997. continue;
  1998. if (chip->device_type == DEVICE_INTEL_ICH4) {
  1999. snd_intel8x0_codec_read_test(chip, codecs);
  2000. chip->ac97_sdin[codecs] =
  2001. igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
  2002. if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
  2003. chip->ac97_sdin[codecs] = 0;
  2004. } else
  2005. chip->ac97_sdin[codecs] = i;
  2006. codecs++;
  2007. }
  2008. chip->in_sdin_init = 0;
  2009. if (! codecs)
  2010. codecs = 1;
  2011. } else {
  2012. ops = &ali_bus_ops;
  2013. codecs = 1;
  2014. /* detect the secondary codec */
  2015. for (i = 0; i < 100; i++) {
  2016. unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
  2017. if (reg & 0x40) {
  2018. codecs = 2;
  2019. break;
  2020. }
  2021. iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
  2022. udelay(1);
  2023. }
  2024. }
  2025. if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
  2026. goto __err;
  2027. pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
  2028. if (ac97_clock >= 8000 && ac97_clock <= 48000)
  2029. pbus->clock = ac97_clock;
  2030. /* FIXME: my test board doesn't work well with VRA... */
  2031. if (chip->device_type == DEVICE_ALI)
  2032. pbus->no_vra = 1;
  2033. else
  2034. pbus->dra = 1;
  2035. chip->ac97_bus = pbus;
  2036. chip->ncodecs = codecs;
  2037. ac97.pci = chip->pci;
  2038. for (i = 0; i < codecs; i++) {
  2039. ac97.num = i;
  2040. if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
  2041. if (err != -EACCES)
  2042. dev_err(chip->card->dev,
  2043. "Unable to initialize codec #%d\n", i);
  2044. if (i == 0)
  2045. goto __err;
  2046. }
  2047. }
  2048. /* tune up the primary codec */
  2049. snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
  2050. /* enable separate SDINs for ICH4 */
  2051. if (chip->device_type == DEVICE_INTEL_ICH4)
  2052. pbus->isdin = 1;
  2053. /* find the available PCM streams */
  2054. i = ARRAY_SIZE(ac97_pcm_defs);
  2055. if (chip->device_type != DEVICE_INTEL_ICH4)
  2056. i -= 2; /* do not allocate PCM2IN and MIC2 */
  2057. if (chip->spdif_idx < 0)
  2058. i--; /* do not allocate S/PDIF */
  2059. err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
  2060. if (err < 0)
  2061. goto __err;
  2062. chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
  2063. chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
  2064. chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
  2065. if (chip->spdif_idx >= 0)
  2066. chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
  2067. if (chip->device_type == DEVICE_INTEL_ICH4) {
  2068. chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
  2069. chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
  2070. }
  2071. /* enable separate SDINs for ICH4 */
  2072. if (chip->device_type == DEVICE_INTEL_ICH4) {
  2073. struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
  2074. u8 tmp = igetbyte(chip, ICHREG(SDM));
  2075. tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
  2076. if (pcm) {
  2077. tmp |= ICH_SE; /* steer enable for multiple SDINs */
  2078. tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
  2079. for (i = 1; i < 4; i++) {
  2080. if (pcm->r[0].codec[i]) {
  2081. tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
  2082. break;
  2083. }
  2084. }
  2085. } else {
  2086. tmp &= ~ICH_SE; /* steer disable */
  2087. }
  2088. iputbyte(chip, ICHREG(SDM), tmp);
  2089. }
  2090. if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  2091. chip->multi4 = 1;
  2092. if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
  2093. chip->multi6 = 1;
  2094. if (chip->ac97[0]->flags & AC97_HAS_8CH)
  2095. chip->multi8 = 1;
  2096. }
  2097. }
  2098. if (pbus->pcms[0].r[1].rslots[0]) {
  2099. chip->dra = 1;
  2100. }
  2101. if (chip->device_type == DEVICE_INTEL_ICH4) {
  2102. if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
  2103. chip->smp20bit = 1;
  2104. }
  2105. if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
  2106. /* 48kHz only */
  2107. chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
  2108. }
  2109. if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
  2110. /* use slot 10/11 for SPDIF */
  2111. u32 val;
  2112. val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
  2113. val |= ICH_PCM_SPDIF_1011;
  2114. iputdword(chip, ICHREG(GLOB_CNT), val);
  2115. snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
  2116. }
  2117. chip->in_ac97_init = 0;
  2118. return 0;
  2119. __err:
  2120. /* clear the cold-reset bit for the next chance */
  2121. if (chip->device_type != DEVICE_ALI)
  2122. iputdword(chip, ICHREG(GLOB_CNT),
  2123. igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
  2124. return err;
  2125. }
  2126. /*
  2127. *
  2128. */
  2129. static void do_ali_reset(struct intel8x0 *chip)
  2130. {
  2131. iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
  2132. iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
  2133. iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
  2134. iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
  2135. iputdword(chip, ICHREG(ALI_INTERFACECR),
  2136. ICH_ALI_IF_PI|ICH_ALI_IF_PO);
  2137. iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
  2138. iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
  2139. }
  2140. #ifdef CONFIG_SND_AC97_POWER_SAVE
  2141. static const struct snd_pci_quirk ich_chip_reset_mode[] = {
  2142. SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
  2143. { } /* end */
  2144. };
  2145. static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
  2146. {
  2147. unsigned int cnt;
  2148. /* ACLink on, 2 channels */
  2149. if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
  2150. return -EIO;
  2151. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  2152. cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
  2153. /* do cold reset - the full ac97 powerdown may leave the controller
  2154. * in a warm state but actually it cannot communicate with the codec.
  2155. */
  2156. iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
  2157. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  2158. udelay(10);
  2159. iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
  2160. msleep(1);
  2161. return 0;
  2162. }
  2163. #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
  2164. (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
  2165. #else
  2166. #define snd_intel8x0_ich_chip_cold_reset(chip) 0
  2167. #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
  2168. #endif
  2169. static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
  2170. {
  2171. unsigned long end_time;
  2172. unsigned int cnt;
  2173. /* ACLink on, 2 channels */
  2174. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  2175. cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
  2176. /* finish cold or do warm reset */
  2177. cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
  2178. iputdword(chip, ICHREG(GLOB_CNT), cnt);
  2179. end_time = (jiffies + (HZ / 4)) + 1;
  2180. do {
  2181. if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
  2182. return 0;
  2183. schedule_timeout_uninterruptible(1);
  2184. } while (time_after_eq(end_time, jiffies));
  2185. dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
  2186. igetdword(chip, ICHREG(GLOB_CNT)));
  2187. return -EIO;
  2188. }
  2189. static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
  2190. {
  2191. unsigned long end_time;
  2192. unsigned int status, nstatus;
  2193. unsigned int cnt;
  2194. int err;
  2195. /* put logic to right state */
  2196. /* first clear status bits */
  2197. status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
  2198. if (chip->device_type == DEVICE_NFORCE)
  2199. status |= ICH_NVSPINT;
  2200. cnt = igetdword(chip, ICHREG(GLOB_STA));
  2201. iputdword(chip, ICHREG(GLOB_STA), cnt & status);
  2202. if (snd_intel8x0_ich_chip_can_cold_reset(chip))
  2203. err = snd_intel8x0_ich_chip_cold_reset(chip);
  2204. else
  2205. err = snd_intel8x0_ich_chip_reset(chip);
  2206. if (err < 0)
  2207. return err;
  2208. if (probing) {
  2209. /* wait for any codec ready status.
  2210. * Once it becomes ready it should remain ready
  2211. * as long as we do not disable the ac97 link.
  2212. */
  2213. end_time = jiffies + HZ;
  2214. do {
  2215. status = igetdword(chip, ICHREG(GLOB_STA)) &
  2216. chip->codec_isr_bits;
  2217. if (status)
  2218. break;
  2219. schedule_timeout_uninterruptible(1);
  2220. } while (time_after_eq(end_time, jiffies));
  2221. if (! status) {
  2222. /* no codec is found */
  2223. dev_err(chip->card->dev,
  2224. "codec_ready: codec is not ready [0x%x]\n",
  2225. igetdword(chip, ICHREG(GLOB_STA)));
  2226. return -EIO;
  2227. }
  2228. /* wait for other codecs ready status. */
  2229. end_time = jiffies + HZ / 4;
  2230. while (status != chip->codec_isr_bits &&
  2231. time_after_eq(end_time, jiffies)) {
  2232. schedule_timeout_uninterruptible(1);
  2233. status |= igetdword(chip, ICHREG(GLOB_STA)) &
  2234. chip->codec_isr_bits;
  2235. }
  2236. } else {
  2237. /* resume phase */
  2238. int i;
  2239. status = 0;
  2240. for (i = 0; i < chip->ncodecs; i++)
  2241. if (chip->ac97[i])
  2242. status |= chip->codec_bit[chip->ac97_sdin[i]];
  2243. /* wait until all the probed codecs are ready */
  2244. end_time = jiffies + HZ;
  2245. do {
  2246. nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
  2247. chip->codec_isr_bits;
  2248. if (status == nstatus)
  2249. break;
  2250. schedule_timeout_uninterruptible(1);
  2251. } while (time_after_eq(end_time, jiffies));
  2252. }
  2253. if (chip->device_type == DEVICE_SIS) {
  2254. /* unmute the output on SIS7012 */
  2255. iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
  2256. }
  2257. if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
  2258. /* enable SPDIF interrupt */
  2259. unsigned int val;
  2260. pci_read_config_dword(chip->pci, 0x4c, &val);
  2261. val |= 0x1000000;
  2262. pci_write_config_dword(chip->pci, 0x4c, val);
  2263. }
  2264. return 0;
  2265. }
  2266. static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
  2267. {
  2268. u32 reg;
  2269. int i = 0;
  2270. reg = igetdword(chip, ICHREG(ALI_SCR));
  2271. if ((reg & 2) == 0) /* Cold required */
  2272. reg |= 2;
  2273. else
  2274. reg |= 1; /* Warm */
  2275. reg &= ~0x80000000; /* ACLink on */
  2276. iputdword(chip, ICHREG(ALI_SCR), reg);
  2277. for (i = 0; i < HZ / 2; i++) {
  2278. if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
  2279. goto __ok;
  2280. schedule_timeout_uninterruptible(1);
  2281. }
  2282. dev_err(chip->card->dev, "AC'97 reset failed.\n");
  2283. if (probing)
  2284. return -EIO;
  2285. __ok:
  2286. for (i = 0; i < HZ / 2; i++) {
  2287. reg = igetdword(chip, ICHREG(ALI_RTSR));
  2288. if (reg & 0x80) /* primary codec */
  2289. break;
  2290. iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
  2291. schedule_timeout_uninterruptible(1);
  2292. }
  2293. do_ali_reset(chip);
  2294. return 0;
  2295. }
  2296. static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
  2297. {
  2298. unsigned int i, timeout;
  2299. int err;
  2300. if (chip->device_type != DEVICE_ALI) {
  2301. if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
  2302. return err;
  2303. iagetword(chip, 0); /* clear semaphore flag */
  2304. } else {
  2305. if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
  2306. return err;
  2307. }
  2308. /* disable interrupts */
  2309. for (i = 0; i < chip->bdbars_count; i++)
  2310. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
  2311. /* reset channels */
  2312. for (i = 0; i < chip->bdbars_count; i++)
  2313. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
  2314. for (i = 0; i < chip->bdbars_count; i++) {
  2315. timeout = 100000;
  2316. while (--timeout != 0) {
  2317. if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
  2318. break;
  2319. }
  2320. if (timeout == 0)
  2321. dev_err(chip->card->dev, "reset of registers failed?\n");
  2322. }
  2323. /* initialize Buffer Descriptor Lists */
  2324. for (i = 0; i < chip->bdbars_count; i++)
  2325. iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
  2326. chip->ichd[i].bdbar_addr);
  2327. return 0;
  2328. }
  2329. static int snd_intel8x0_free(struct intel8x0 *chip)
  2330. {
  2331. unsigned int i;
  2332. if (chip->irq < 0)
  2333. goto __hw_end;
  2334. /* disable interrupts */
  2335. for (i = 0; i < chip->bdbars_count; i++)
  2336. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
  2337. /* reset channels */
  2338. for (i = 0; i < chip->bdbars_count; i++)
  2339. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
  2340. if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
  2341. /* stop the spdif interrupt */
  2342. unsigned int val;
  2343. pci_read_config_dword(chip->pci, 0x4c, &val);
  2344. val &= ~0x1000000;
  2345. pci_write_config_dword(chip->pci, 0x4c, val);
  2346. }
  2347. /* --- */
  2348. __hw_end:
  2349. if (chip->irq >= 0)
  2350. free_irq(chip->irq, chip);
  2351. if (chip->bdbars.area)
  2352. snd_dma_free_pages(&chip->bdbars);
  2353. if (chip->addr)
  2354. pci_iounmap(chip->pci, chip->addr);
  2355. if (chip->bmaddr)
  2356. pci_iounmap(chip->pci, chip->bmaddr);
  2357. pci_release_regions(chip->pci);
  2358. pci_disable_device(chip->pci);
  2359. kfree(chip);
  2360. return 0;
  2361. }
  2362. #ifdef CONFIG_PM_SLEEP
  2363. /*
  2364. * power management
  2365. */
  2366. static int intel8x0_suspend(struct device *dev)
  2367. {
  2368. struct snd_card *card = dev_get_drvdata(dev);
  2369. struct intel8x0 *chip = card->private_data;
  2370. int i;
  2371. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2372. for (i = 0; i < chip->ncodecs; i++)
  2373. snd_ac97_suspend(chip->ac97[i]);
  2374. if (chip->device_type == DEVICE_INTEL_ICH4)
  2375. chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
  2376. if (chip->irq >= 0) {
  2377. free_irq(chip->irq, chip);
  2378. chip->irq = -1;
  2379. card->sync_irq = -1;
  2380. }
  2381. return 0;
  2382. }
  2383. static int intel8x0_resume(struct device *dev)
  2384. {
  2385. struct pci_dev *pci = to_pci_dev(dev);
  2386. struct snd_card *card = dev_get_drvdata(dev);
  2387. struct intel8x0 *chip = card->private_data;
  2388. int i;
  2389. snd_intel8x0_chip_init(chip, 0);
  2390. if (request_irq(pci->irq, snd_intel8x0_interrupt,
  2391. IRQF_SHARED, KBUILD_MODNAME, chip)) {
  2392. dev_err(dev, "unable to grab IRQ %d, disabling device\n",
  2393. pci->irq);
  2394. snd_card_disconnect(card);
  2395. return -EIO;
  2396. }
  2397. chip->irq = pci->irq;
  2398. card->sync_irq = chip->irq;
  2399. /* re-initialize mixer stuff */
  2400. if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
  2401. /* enable separate SDINs for ICH4 */
  2402. iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
  2403. /* use slot 10/11 for SPDIF */
  2404. iputdword(chip, ICHREG(GLOB_CNT),
  2405. (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
  2406. ICH_PCM_SPDIF_1011);
  2407. }
  2408. for (i = 0; i < chip->ncodecs; i++)
  2409. snd_ac97_resume(chip->ac97[i]);
  2410. /* resume status */
  2411. for (i = 0; i < chip->bdbars_count; i++) {
  2412. struct ichdev *ichdev = &chip->ichd[i];
  2413. unsigned long port = ichdev->reg_offset;
  2414. if (! ichdev->substream || ! ichdev->suspended)
  2415. continue;
  2416. if (ichdev->ichd == ICHD_PCMOUT)
  2417. snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
  2418. iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
  2419. iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
  2420. iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
  2421. iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
  2422. }
  2423. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2424. return 0;
  2425. }
  2426. static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
  2427. #define INTEL8X0_PM_OPS &intel8x0_pm
  2428. #else
  2429. #define INTEL8X0_PM_OPS NULL
  2430. #endif /* CONFIG_PM_SLEEP */
  2431. #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
  2432. static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
  2433. {
  2434. struct snd_pcm_substream *subs;
  2435. struct ichdev *ichdev;
  2436. unsigned long port;
  2437. unsigned long pos, pos1, t;
  2438. int civ, timeout = 1000, attempt = 1;
  2439. ktime_t start_time, stop_time;
  2440. if (chip->ac97_bus->clock != 48000)
  2441. return; /* specified in module option */
  2442. __again:
  2443. subs = chip->pcm[0]->streams[0].substream;
  2444. if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
  2445. dev_warn(chip->card->dev,
  2446. "no playback buffer allocated - aborting measure ac97 clock\n");
  2447. return;
  2448. }
  2449. ichdev = &chip->ichd[ICHD_PCMOUT];
  2450. ichdev->physbuf = subs->dma_buffer.addr;
  2451. ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
  2452. ichdev->substream = NULL; /* don't process interrupts */
  2453. /* set rate */
  2454. if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
  2455. dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
  2456. chip->ac97_bus->clock);
  2457. return;
  2458. }
  2459. snd_intel8x0_setup_periods(chip, ichdev);
  2460. port = ichdev->reg_offset;
  2461. spin_lock_irq(&chip->reg_lock);
  2462. chip->in_measurement = 1;
  2463. /* trigger */
  2464. if (chip->device_type != DEVICE_ALI)
  2465. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
  2466. else {
  2467. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
  2468. iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
  2469. }
  2470. start_time = ktime_get();
  2471. spin_unlock_irq(&chip->reg_lock);
  2472. msleep(50);
  2473. spin_lock_irq(&chip->reg_lock);
  2474. /* check the position */
  2475. do {
  2476. civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
  2477. pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
  2478. if (pos1 == 0) {
  2479. udelay(10);
  2480. continue;
  2481. }
  2482. if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
  2483. pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
  2484. break;
  2485. } while (timeout--);
  2486. if (pos1 == 0) { /* oops, this value is not reliable */
  2487. pos = 0;
  2488. } else {
  2489. pos = ichdev->fragsize1;
  2490. pos -= pos1 << ichdev->pos_shift;
  2491. pos += ichdev->position;
  2492. }
  2493. chip->in_measurement = 0;
  2494. stop_time = ktime_get();
  2495. /* stop */
  2496. if (chip->device_type == DEVICE_ALI) {
  2497. iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
  2498. iputbyte(chip, port + ICH_REG_OFF_CR, 0);
  2499. while (igetbyte(chip, port + ICH_REG_OFF_CR))
  2500. ;
  2501. } else {
  2502. iputbyte(chip, port + ICH_REG_OFF_CR, 0);
  2503. while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
  2504. ;
  2505. }
  2506. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
  2507. spin_unlock_irq(&chip->reg_lock);
  2508. if (pos == 0) {
  2509. dev_err(chip->card->dev,
  2510. "measure - unreliable DMA position..\n");
  2511. __retry:
  2512. if (attempt < 3) {
  2513. msleep(300);
  2514. attempt++;
  2515. goto __again;
  2516. }
  2517. goto __end;
  2518. }
  2519. pos /= 4;
  2520. t = ktime_us_delta(stop_time, start_time);
  2521. dev_info(chip->card->dev,
  2522. "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
  2523. if (t == 0) {
  2524. dev_err(chip->card->dev, "?? calculation error..\n");
  2525. goto __retry;
  2526. }
  2527. pos *= 1000;
  2528. pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
  2529. if (pos < 40000 || pos >= 60000) {
  2530. /* abnormal value. hw problem? */
  2531. dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
  2532. goto __retry;
  2533. } else if (pos > 40500 && pos < 41500)
  2534. /* first exception - 41000Hz reference clock */
  2535. chip->ac97_bus->clock = 41000;
  2536. else if (pos > 43600 && pos < 44600)
  2537. /* second exception - 44100HZ reference clock */
  2538. chip->ac97_bus->clock = 44100;
  2539. else if (pos < 47500 || pos > 48500)
  2540. /* not 48000Hz, tuning the clock.. */
  2541. chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
  2542. __end:
  2543. dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
  2544. snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
  2545. }
  2546. static const struct snd_pci_quirk intel8x0_clock_list[] = {
  2547. SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
  2548. SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
  2549. SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
  2550. SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
  2551. SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
  2552. SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
  2553. { } /* terminator */
  2554. };
  2555. static int intel8x0_in_clock_list(struct intel8x0 *chip)
  2556. {
  2557. struct pci_dev *pci = chip->pci;
  2558. const struct snd_pci_quirk *wl;
  2559. wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
  2560. if (!wl)
  2561. return 0;
  2562. dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n",
  2563. pci->subsystem_vendor, pci->subsystem_device, wl->value);
  2564. chip->ac97_bus->clock = wl->value;
  2565. return 1;
  2566. }
  2567. static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
  2568. struct snd_info_buffer *buffer)
  2569. {
  2570. struct intel8x0 *chip = entry->private_data;
  2571. unsigned int tmp;
  2572. snd_iprintf(buffer, "Intel8x0\n\n");
  2573. if (chip->device_type == DEVICE_ALI)
  2574. return;
  2575. tmp = igetdword(chip, ICHREG(GLOB_STA));
  2576. snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
  2577. snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
  2578. if (chip->device_type == DEVICE_INTEL_ICH4)
  2579. snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
  2580. snd_iprintf(buffer, "AC'97 codecs ready :");
  2581. if (tmp & chip->codec_isr_bits) {
  2582. int i;
  2583. static const char *codecs[3] = {
  2584. "primary", "secondary", "tertiary"
  2585. };
  2586. for (i = 0; i < chip->max_codecs; i++)
  2587. if (tmp & chip->codec_bit[i])
  2588. snd_iprintf(buffer, " %s", codecs[i]);
  2589. } else
  2590. snd_iprintf(buffer, " none");
  2591. snd_iprintf(buffer, "\n");
  2592. if (chip->device_type == DEVICE_INTEL_ICH4 ||
  2593. chip->device_type == DEVICE_SIS)
  2594. snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
  2595. chip->ac97_sdin[0],
  2596. chip->ac97_sdin[1],
  2597. chip->ac97_sdin[2]);
  2598. }
  2599. static void snd_intel8x0_proc_init(struct intel8x0 *chip)
  2600. {
  2601. snd_card_ro_proc_new(chip->card, "intel8x0", chip,
  2602. snd_intel8x0_proc_read);
  2603. }
  2604. static int snd_intel8x0_dev_free(struct snd_device *device)
  2605. {
  2606. struct intel8x0 *chip = device->device_data;
  2607. return snd_intel8x0_free(chip);
  2608. }
  2609. struct ich_reg_info {
  2610. unsigned int int_sta_mask;
  2611. unsigned int offset;
  2612. };
  2613. static const unsigned int ich_codec_bits[3] = {
  2614. ICH_PCR, ICH_SCR, ICH_TCR
  2615. };
  2616. static const unsigned int sis_codec_bits[3] = {
  2617. ICH_PCR, ICH_SCR, ICH_SIS_TCR
  2618. };
  2619. static int snd_intel8x0_inside_vm(struct pci_dev *pci)
  2620. {
  2621. int result = inside_vm;
  2622. char *msg = NULL;
  2623. /* check module parameter first (override detection) */
  2624. if (result >= 0) {
  2625. msg = result ? "enable (forced) VM" : "disable (forced) VM";
  2626. goto fini;
  2627. }
  2628. /* check for known (emulated) devices */
  2629. result = 0;
  2630. if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
  2631. pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
  2632. /* KVM emulated sound, PCI SSID: 1af4:1100 */
  2633. msg = "enable KVM";
  2634. result = 1;
  2635. } else if (pci->subsystem_vendor == 0x1ab8) {
  2636. /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
  2637. msg = "enable Parallels VM";
  2638. result = 1;
  2639. }
  2640. fini:
  2641. if (msg != NULL)
  2642. dev_info(&pci->dev, "%s optimization\n", msg);
  2643. return result;
  2644. }
  2645. static int snd_intel8x0_create(struct snd_card *card,
  2646. struct pci_dev *pci,
  2647. unsigned long device_type,
  2648. struct intel8x0 **r_intel8x0)
  2649. {
  2650. struct intel8x0 *chip;
  2651. int err;
  2652. unsigned int i;
  2653. unsigned int int_sta_masks;
  2654. struct ichdev *ichdev;
  2655. static const struct snd_device_ops ops = {
  2656. .dev_free = snd_intel8x0_dev_free,
  2657. };
  2658. static const unsigned int bdbars[] = {
  2659. 3, /* DEVICE_INTEL */
  2660. 6, /* DEVICE_INTEL_ICH4 */
  2661. 3, /* DEVICE_SIS */
  2662. 6, /* DEVICE_ALI */
  2663. 4, /* DEVICE_NFORCE */
  2664. };
  2665. static const struct ich_reg_info intel_regs[6] = {
  2666. { ICH_PIINT, 0 },
  2667. { ICH_POINT, 0x10 },
  2668. { ICH_MCINT, 0x20 },
  2669. { ICH_M2INT, 0x40 },
  2670. { ICH_P2INT, 0x50 },
  2671. { ICH_SPINT, 0x60 },
  2672. };
  2673. static const struct ich_reg_info nforce_regs[4] = {
  2674. { ICH_PIINT, 0 },
  2675. { ICH_POINT, 0x10 },
  2676. { ICH_MCINT, 0x20 },
  2677. { ICH_NVSPINT, 0x70 },
  2678. };
  2679. static const struct ich_reg_info ali_regs[6] = {
  2680. { ALI_INT_PCMIN, 0x40 },
  2681. { ALI_INT_PCMOUT, 0x50 },
  2682. { ALI_INT_MICIN, 0x60 },
  2683. { ALI_INT_CODECSPDIFOUT, 0x70 },
  2684. { ALI_INT_SPDIFIN, 0xa0 },
  2685. { ALI_INT_SPDIFOUT, 0xb0 },
  2686. };
  2687. const struct ich_reg_info *tbl;
  2688. *r_intel8x0 = NULL;
  2689. if ((err = pci_enable_device(pci)) < 0)
  2690. return err;
  2691. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2692. if (chip == NULL) {
  2693. pci_disable_device(pci);
  2694. return -ENOMEM;
  2695. }
  2696. spin_lock_init(&chip->reg_lock);
  2697. chip->device_type = device_type;
  2698. chip->card = card;
  2699. chip->pci = pci;
  2700. chip->irq = -1;
  2701. /* module parameters */
  2702. chip->buggy_irq = buggy_irq;
  2703. chip->buggy_semaphore = buggy_semaphore;
  2704. if (xbox)
  2705. chip->xbox = 1;
  2706. chip->inside_vm = snd_intel8x0_inside_vm(pci);
  2707. /*
  2708. * Intel 82443MX running a 100MHz processor system bus has a hardware
  2709. * bug, which aborts PCI busmaster for audio transfer. A workaround
  2710. * is to set the pages as non-cached. For details, see the errata in
  2711. * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
  2712. */
  2713. if (pci->vendor == PCI_VENDOR_ID_INTEL &&
  2714. pci->device == PCI_DEVICE_ID_INTEL_440MX)
  2715. chip->fix_nocache = 1; /* enable workaround */
  2716. if ((err = pci_request_regions(pci, card->shortname)) < 0) {
  2717. kfree(chip);
  2718. pci_disable_device(pci);
  2719. return err;
  2720. }
  2721. if (device_type == DEVICE_ALI) {
  2722. /* ALI5455 has no ac97 region */
  2723. chip->bmaddr = pci_iomap(pci, 0, 0);
  2724. goto port_inited;
  2725. }
  2726. if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
  2727. chip->addr = pci_iomap(pci, 2, 0);
  2728. else
  2729. chip->addr = pci_iomap(pci, 0, 0);
  2730. if (!chip->addr) {
  2731. dev_err(card->dev, "AC'97 space ioremap problem\n");
  2732. snd_intel8x0_free(chip);
  2733. return -EIO;
  2734. }
  2735. if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
  2736. chip->bmaddr = pci_iomap(pci, 3, 0);
  2737. else
  2738. chip->bmaddr = pci_iomap(pci, 1, 0);
  2739. port_inited:
  2740. if (!chip->bmaddr) {
  2741. dev_err(card->dev, "Controller space ioremap problem\n");
  2742. snd_intel8x0_free(chip);
  2743. return -EIO;
  2744. }
  2745. chip->bdbars_count = bdbars[device_type];
  2746. /* initialize offsets */
  2747. switch (device_type) {
  2748. case DEVICE_NFORCE:
  2749. tbl = nforce_regs;
  2750. break;
  2751. case DEVICE_ALI:
  2752. tbl = ali_regs;
  2753. break;
  2754. default:
  2755. tbl = intel_regs;
  2756. break;
  2757. }
  2758. for (i = 0; i < chip->bdbars_count; i++) {
  2759. ichdev = &chip->ichd[i];
  2760. ichdev->ichd = i;
  2761. ichdev->reg_offset = tbl[i].offset;
  2762. ichdev->int_sta_mask = tbl[i].int_sta_mask;
  2763. if (device_type == DEVICE_SIS) {
  2764. /* SiS 7012 swaps the registers */
  2765. ichdev->roff_sr = ICH_REG_OFF_PICB;
  2766. ichdev->roff_picb = ICH_REG_OFF_SR;
  2767. } else {
  2768. ichdev->roff_sr = ICH_REG_OFF_SR;
  2769. ichdev->roff_picb = ICH_REG_OFF_PICB;
  2770. }
  2771. if (device_type == DEVICE_ALI)
  2772. ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
  2773. /* SIS7012 handles the pcm data in bytes, others are in samples */
  2774. ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
  2775. }
  2776. /* allocate buffer descriptor lists */
  2777. /* the start of each lists must be aligned to 8 bytes */
  2778. if (snd_dma_alloc_pages(intel8x0_dma_type(chip), &pci->dev,
  2779. chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
  2780. &chip->bdbars) < 0) {
  2781. snd_intel8x0_free(chip);
  2782. dev_err(card->dev, "cannot allocate buffer descriptors\n");
  2783. return -ENOMEM;
  2784. }
  2785. /* tables must be aligned to 8 bytes here, but the kernel pages
  2786. are much bigger, so we don't care (on i386) */
  2787. int_sta_masks = 0;
  2788. for (i = 0; i < chip->bdbars_count; i++) {
  2789. ichdev = &chip->ichd[i];
  2790. ichdev->bdbar = ((__le32 *)chip->bdbars.area) +
  2791. (i * ICH_MAX_FRAGS * 2);
  2792. ichdev->bdbar_addr = chip->bdbars.addr +
  2793. (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
  2794. int_sta_masks |= ichdev->int_sta_mask;
  2795. }
  2796. chip->int_sta_reg = device_type == DEVICE_ALI ?
  2797. ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
  2798. chip->int_sta_mask = int_sta_masks;
  2799. pci_set_master(pci);
  2800. switch(chip->device_type) {
  2801. case DEVICE_INTEL_ICH4:
  2802. /* ICH4 can have three codecs */
  2803. chip->max_codecs = 3;
  2804. chip->codec_bit = ich_codec_bits;
  2805. chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
  2806. break;
  2807. case DEVICE_SIS:
  2808. /* recent SIS7012 can have three codecs */
  2809. chip->max_codecs = 3;
  2810. chip->codec_bit = sis_codec_bits;
  2811. chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
  2812. break;
  2813. default:
  2814. /* others up to two codecs */
  2815. chip->max_codecs = 2;
  2816. chip->codec_bit = ich_codec_bits;
  2817. chip->codec_ready_bits = ICH_PRI | ICH_SRI;
  2818. break;
  2819. }
  2820. for (i = 0; i < chip->max_codecs; i++)
  2821. chip->codec_isr_bits |= chip->codec_bit[i];
  2822. if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
  2823. snd_intel8x0_free(chip);
  2824. return err;
  2825. }
  2826. /* request irq after initializaing int_sta_mask, etc */
  2827. if (request_irq(pci->irq, snd_intel8x0_interrupt,
  2828. IRQF_SHARED, KBUILD_MODNAME, chip)) {
  2829. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2830. snd_intel8x0_free(chip);
  2831. return -EBUSY;
  2832. }
  2833. chip->irq = pci->irq;
  2834. card->sync_irq = chip->irq;
  2835. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2836. snd_intel8x0_free(chip);
  2837. return err;
  2838. }
  2839. *r_intel8x0 = chip;
  2840. return 0;
  2841. }
  2842. static struct shortname_table {
  2843. unsigned int id;
  2844. const char *s;
  2845. } shortnames[] = {
  2846. { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
  2847. { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
  2848. { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
  2849. { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
  2850. { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
  2851. { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
  2852. { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
  2853. { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
  2854. { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
  2855. { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
  2856. { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
  2857. { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
  2858. { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
  2859. { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
  2860. { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
  2861. { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
  2862. { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
  2863. { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
  2864. { 0x003a, "NVidia MCP04" },
  2865. { 0x746d, "AMD AMD8111" },
  2866. { 0x7445, "AMD AMD768" },
  2867. { 0x5455, "ALi M5455" },
  2868. { 0, NULL },
  2869. };
  2870. static const struct snd_pci_quirk spdif_aclink_defaults[] = {
  2871. SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
  2872. { } /* end */
  2873. };
  2874. /* look up allow/deny list for SPDIF over ac-link */
  2875. static int check_default_spdif_aclink(struct pci_dev *pci)
  2876. {
  2877. const struct snd_pci_quirk *w;
  2878. w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
  2879. if (w) {
  2880. if (w->value)
  2881. dev_dbg(&pci->dev,
  2882. "Using SPDIF over AC-Link for %s\n",
  2883. snd_pci_quirk_name(w));
  2884. else
  2885. dev_dbg(&pci->dev,
  2886. "Using integrated SPDIF DMA for %s\n",
  2887. snd_pci_quirk_name(w));
  2888. return w->value;
  2889. }
  2890. return 0;
  2891. }
  2892. static int snd_intel8x0_probe(struct pci_dev *pci,
  2893. const struct pci_device_id *pci_id)
  2894. {
  2895. struct snd_card *card;
  2896. struct intel8x0 *chip;
  2897. int err;
  2898. struct shortname_table *name;
  2899. err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
  2900. if (err < 0)
  2901. return err;
  2902. if (spdif_aclink < 0)
  2903. spdif_aclink = check_default_spdif_aclink(pci);
  2904. strcpy(card->driver, "ICH");
  2905. if (!spdif_aclink) {
  2906. switch (pci_id->driver_data) {
  2907. case DEVICE_NFORCE:
  2908. strcpy(card->driver, "NFORCE");
  2909. break;
  2910. case DEVICE_INTEL_ICH4:
  2911. strcpy(card->driver, "ICH4");
  2912. }
  2913. }
  2914. strcpy(card->shortname, "Intel ICH");
  2915. for (name = shortnames; name->id; name++) {
  2916. if (pci->device == name->id) {
  2917. strcpy(card->shortname, name->s);
  2918. break;
  2919. }
  2920. }
  2921. if (buggy_irq < 0) {
  2922. /* some Nforce[2] and ICH boards have problems with IRQ handling.
  2923. * Needs to return IRQ_HANDLED for unknown irqs.
  2924. */
  2925. if (pci_id->driver_data == DEVICE_NFORCE)
  2926. buggy_irq = 1;
  2927. else
  2928. buggy_irq = 0;
  2929. }
  2930. if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
  2931. &chip)) < 0) {
  2932. snd_card_free(card);
  2933. return err;
  2934. }
  2935. card->private_data = chip;
  2936. if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
  2937. snd_card_free(card);
  2938. return err;
  2939. }
  2940. if ((err = snd_intel8x0_pcm(chip)) < 0) {
  2941. snd_card_free(card);
  2942. return err;
  2943. }
  2944. snd_intel8x0_proc_init(chip);
  2945. snprintf(card->longname, sizeof(card->longname),
  2946. "%s with %s at irq %i", card->shortname,
  2947. snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
  2948. if (ac97_clock == 0 || ac97_clock == 1) {
  2949. if (ac97_clock == 0) {
  2950. if (intel8x0_in_clock_list(chip) == 0)
  2951. intel8x0_measure_ac97_clock(chip);
  2952. } else {
  2953. intel8x0_measure_ac97_clock(chip);
  2954. }
  2955. }
  2956. if ((err = snd_card_register(card)) < 0) {
  2957. snd_card_free(card);
  2958. return err;
  2959. }
  2960. pci_set_drvdata(pci, card);
  2961. return 0;
  2962. }
  2963. static void snd_intel8x0_remove(struct pci_dev *pci)
  2964. {
  2965. snd_card_free(pci_get_drvdata(pci));
  2966. }
  2967. static struct pci_driver intel8x0_driver = {
  2968. .name = KBUILD_MODNAME,
  2969. .id_table = snd_intel8x0_ids,
  2970. .probe = snd_intel8x0_probe,
  2971. .remove = snd_intel8x0_remove,
  2972. .driver = {
  2973. .pm = INTEL8X0_PM_OPS,
  2974. },
  2975. };
  2976. module_pci_driver(intel8x0_driver);