es1938.c 54 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for ESS Solo-1 (ES1938, ES1946, ES1969) soundcard
  4. * Copyright (c) by Jaromir Koutek <miri@punknet.cz>,
  5. * Jaroslav Kysela <perex@perex.cz>,
  6. * Thomas Sailer <sailer@ife.ee.ethz.ch>,
  7. * Abramo Bagnara <abramo@alsa-project.org>,
  8. * Markus Gruber <gruber@eikon.tum.de>
  9. *
  10. * Rewritten from sonicvibes.c source.
  11. *
  12. * TODO:
  13. * Rewrite better spinlocks
  14. */
  15. /*
  16. NOTES:
  17. - Capture data is written unaligned starting from dma_base + 1 so I need to
  18. disable mmap and to add a copy callback.
  19. - After several cycle of the following:
  20. while : ; do arecord -d1 -f cd -t raw | aplay -f cd ; done
  21. a "playback write error (DMA or IRQ trouble?)" may happen.
  22. This is due to playback interrupts not generated.
  23. I suspect a timing issue.
  24. - Sometimes the interrupt handler is invoked wrongly during playback.
  25. This generates some harmless "Unexpected hw_pointer: wrong interrupt
  26. acknowledge".
  27. I've seen that using small period sizes.
  28. Reproducible with:
  29. mpg123 test.mp3 &
  30. hdparm -t -T /dev/hda
  31. */
  32. #include <linux/init.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/pci.h>
  35. #include <linux/slab.h>
  36. #include <linux/gameport.h>
  37. #include <linux/module.h>
  38. #include <linux/delay.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/io.h>
  41. #include <sound/core.h>
  42. #include <sound/control.h>
  43. #include <sound/pcm.h>
  44. #include <sound/opl3.h>
  45. #include <sound/mpu401.h>
  46. #include <sound/initval.h>
  47. #include <sound/tlv.h>
  48. MODULE_AUTHOR("Jaromir Koutek <miri@punknet.cz>");
  49. MODULE_DESCRIPTION("ESS Solo-1");
  50. MODULE_LICENSE("GPL");
  51. MODULE_SUPPORTED_DEVICE("{{ESS,ES1938},"
  52. "{ESS,ES1946},"
  53. "{ESS,ES1969},"
  54. "{TerraTec,128i PCI}}");
  55. #if IS_REACHABLE(CONFIG_GAMEPORT)
  56. #define SUPPORT_JOYSTICK 1
  57. #endif
  58. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  59. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  60. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  61. module_param_array(index, int, NULL, 0444);
  62. MODULE_PARM_DESC(index, "Index value for ESS Solo-1 soundcard.");
  63. module_param_array(id, charp, NULL, 0444);
  64. MODULE_PARM_DESC(id, "ID string for ESS Solo-1 soundcard.");
  65. module_param_array(enable, bool, NULL, 0444);
  66. MODULE_PARM_DESC(enable, "Enable ESS Solo-1 soundcard.");
  67. #define SLIO_REG(chip, x) ((chip)->io_port + ESSIO_REG_##x)
  68. #define SLDM_REG(chip, x) ((chip)->ddma_port + ESSDM_REG_##x)
  69. #define SLSB_REG(chip, x) ((chip)->sb_port + ESSSB_REG_##x)
  70. #define SL_PCI_LEGACYCONTROL 0x40
  71. #define SL_PCI_CONFIG 0x50
  72. #define SL_PCI_DDMACONTROL 0x60
  73. #define ESSIO_REG_AUDIO2DMAADDR 0
  74. #define ESSIO_REG_AUDIO2DMACOUNT 4
  75. #define ESSIO_REG_AUDIO2MODE 6
  76. #define ESSIO_REG_IRQCONTROL 7
  77. #define ESSDM_REG_DMAADDR 0x00
  78. #define ESSDM_REG_DMACOUNT 0x04
  79. #define ESSDM_REG_DMACOMMAND 0x08
  80. #define ESSDM_REG_DMASTATUS 0x08
  81. #define ESSDM_REG_DMAMODE 0x0b
  82. #define ESSDM_REG_DMACLEAR 0x0d
  83. #define ESSDM_REG_DMAMASK 0x0f
  84. #define ESSSB_REG_FMLOWADDR 0x00
  85. #define ESSSB_REG_FMHIGHADDR 0x02
  86. #define ESSSB_REG_MIXERADDR 0x04
  87. #define ESSSB_REG_MIXERDATA 0x05
  88. #define ESSSB_IREG_AUDIO1 0x14
  89. #define ESSSB_IREG_MICMIX 0x1a
  90. #define ESSSB_IREG_RECSRC 0x1c
  91. #define ESSSB_IREG_MASTER 0x32
  92. #define ESSSB_IREG_FM 0x36
  93. #define ESSSB_IREG_AUXACD 0x38
  94. #define ESSSB_IREG_AUXB 0x3a
  95. #define ESSSB_IREG_PCSPEAKER 0x3c
  96. #define ESSSB_IREG_LINE 0x3e
  97. #define ESSSB_IREG_SPATCONTROL 0x50
  98. #define ESSSB_IREG_SPATLEVEL 0x52
  99. #define ESSSB_IREG_MASTER_LEFT 0x60
  100. #define ESSSB_IREG_MASTER_RIGHT 0x62
  101. #define ESSSB_IREG_MPU401CONTROL 0x64
  102. #define ESSSB_IREG_MICMIXRECORD 0x68
  103. #define ESSSB_IREG_AUDIO2RECORD 0x69
  104. #define ESSSB_IREG_AUXACDRECORD 0x6a
  105. #define ESSSB_IREG_FMRECORD 0x6b
  106. #define ESSSB_IREG_AUXBRECORD 0x6c
  107. #define ESSSB_IREG_MONO 0x6d
  108. #define ESSSB_IREG_LINERECORD 0x6e
  109. #define ESSSB_IREG_MONORECORD 0x6f
  110. #define ESSSB_IREG_AUDIO2SAMPLE 0x70
  111. #define ESSSB_IREG_AUDIO2MODE 0x71
  112. #define ESSSB_IREG_AUDIO2FILTER 0x72
  113. #define ESSSB_IREG_AUDIO2TCOUNTL 0x74
  114. #define ESSSB_IREG_AUDIO2TCOUNTH 0x76
  115. #define ESSSB_IREG_AUDIO2CONTROL1 0x78
  116. #define ESSSB_IREG_AUDIO2CONTROL2 0x7a
  117. #define ESSSB_IREG_AUDIO2 0x7c
  118. #define ESSSB_REG_RESET 0x06
  119. #define ESSSB_REG_READDATA 0x0a
  120. #define ESSSB_REG_WRITEDATA 0x0c
  121. #define ESSSB_REG_READSTATUS 0x0c
  122. #define ESSSB_REG_STATUS 0x0e
  123. #define ESS_CMD_EXTSAMPLERATE 0xa1
  124. #define ESS_CMD_FILTERDIV 0xa2
  125. #define ESS_CMD_DMACNTRELOADL 0xa4
  126. #define ESS_CMD_DMACNTRELOADH 0xa5
  127. #define ESS_CMD_ANALOGCONTROL 0xa8
  128. #define ESS_CMD_IRQCONTROL 0xb1
  129. #define ESS_CMD_DRQCONTROL 0xb2
  130. #define ESS_CMD_RECLEVEL 0xb4
  131. #define ESS_CMD_SETFORMAT 0xb6
  132. #define ESS_CMD_SETFORMAT2 0xb7
  133. #define ESS_CMD_DMACONTROL 0xb8
  134. #define ESS_CMD_DMATYPE 0xb9
  135. #define ESS_CMD_OFFSETLEFT 0xba
  136. #define ESS_CMD_OFFSETRIGHT 0xbb
  137. #define ESS_CMD_READREG 0xc0
  138. #define ESS_CMD_ENABLEEXT 0xc6
  139. #define ESS_CMD_PAUSEDMA 0xd0
  140. #define ESS_CMD_ENABLEAUDIO1 0xd1
  141. #define ESS_CMD_STOPAUDIO1 0xd3
  142. #define ESS_CMD_AUDIO1STATUS 0xd8
  143. #define ESS_CMD_CONTDMA 0xd4
  144. #define ESS_CMD_TESTIRQ 0xf2
  145. #define ESS_RECSRC_MIC 0
  146. #define ESS_RECSRC_AUXACD 2
  147. #define ESS_RECSRC_AUXB 5
  148. #define ESS_RECSRC_LINE 6
  149. #define ESS_RECSRC_NONE 7
  150. #define DAC1 0x01
  151. #define ADC1 0x02
  152. #define DAC2 0x04
  153. /*
  154. */
  155. #define SAVED_REG_SIZE 32 /* max. number of registers to save */
  156. struct es1938 {
  157. int irq;
  158. unsigned long io_port;
  159. unsigned long sb_port;
  160. unsigned long vc_port;
  161. unsigned long mpu_port;
  162. unsigned long game_port;
  163. unsigned long ddma_port;
  164. unsigned char irqmask;
  165. unsigned char revision;
  166. struct snd_kcontrol *hw_volume;
  167. struct snd_kcontrol *hw_switch;
  168. struct snd_kcontrol *master_volume;
  169. struct snd_kcontrol *master_switch;
  170. struct pci_dev *pci;
  171. struct snd_card *card;
  172. struct snd_pcm *pcm;
  173. struct snd_pcm_substream *capture_substream;
  174. struct snd_pcm_substream *playback1_substream;
  175. struct snd_pcm_substream *playback2_substream;
  176. struct snd_rawmidi *rmidi;
  177. unsigned int dma1_size;
  178. unsigned int dma2_size;
  179. unsigned int dma1_start;
  180. unsigned int dma2_start;
  181. unsigned int dma1_shift;
  182. unsigned int dma2_shift;
  183. unsigned int last_capture_dmaaddr;
  184. unsigned int active;
  185. spinlock_t reg_lock;
  186. spinlock_t mixer_lock;
  187. struct snd_info_entry *proc_entry;
  188. #ifdef SUPPORT_JOYSTICK
  189. struct gameport *gameport;
  190. #endif
  191. #ifdef CONFIG_PM_SLEEP
  192. unsigned char saved_regs[SAVED_REG_SIZE];
  193. #endif
  194. };
  195. static irqreturn_t snd_es1938_interrupt(int irq, void *dev_id);
  196. static const struct pci_device_id snd_es1938_ids[] = {
  197. { PCI_VDEVICE(ESS, 0x1969), 0, }, /* Solo-1 */
  198. { 0, }
  199. };
  200. MODULE_DEVICE_TABLE(pci, snd_es1938_ids);
  201. #define RESET_LOOP_TIMEOUT 0x10000
  202. #define WRITE_LOOP_TIMEOUT 0x10000
  203. #define GET_LOOP_TIMEOUT 0x01000
  204. /* -----------------------------------------------------------------
  205. * Write to a mixer register
  206. * -----------------------------------------------------------------*/
  207. static void snd_es1938_mixer_write(struct es1938 *chip, unsigned char reg, unsigned char val)
  208. {
  209. unsigned long flags;
  210. spin_lock_irqsave(&chip->mixer_lock, flags);
  211. outb(reg, SLSB_REG(chip, MIXERADDR));
  212. outb(val, SLSB_REG(chip, MIXERDATA));
  213. spin_unlock_irqrestore(&chip->mixer_lock, flags);
  214. dev_dbg(chip->card->dev, "Mixer reg %02x set to %02x\n", reg, val);
  215. }
  216. /* -----------------------------------------------------------------
  217. * Read from a mixer register
  218. * -----------------------------------------------------------------*/
  219. static int snd_es1938_mixer_read(struct es1938 *chip, unsigned char reg)
  220. {
  221. int data;
  222. unsigned long flags;
  223. spin_lock_irqsave(&chip->mixer_lock, flags);
  224. outb(reg, SLSB_REG(chip, MIXERADDR));
  225. data = inb(SLSB_REG(chip, MIXERDATA));
  226. spin_unlock_irqrestore(&chip->mixer_lock, flags);
  227. dev_dbg(chip->card->dev, "Mixer reg %02x now is %02x\n", reg, data);
  228. return data;
  229. }
  230. /* -----------------------------------------------------------------
  231. * Write to some bits of a mixer register (return old value)
  232. * -----------------------------------------------------------------*/
  233. static int snd_es1938_mixer_bits(struct es1938 *chip, unsigned char reg,
  234. unsigned char mask, unsigned char val)
  235. {
  236. unsigned long flags;
  237. unsigned char old, new, oval;
  238. spin_lock_irqsave(&chip->mixer_lock, flags);
  239. outb(reg, SLSB_REG(chip, MIXERADDR));
  240. old = inb(SLSB_REG(chip, MIXERDATA));
  241. oval = old & mask;
  242. if (val != oval) {
  243. new = (old & ~mask) | (val & mask);
  244. outb(new, SLSB_REG(chip, MIXERDATA));
  245. dev_dbg(chip->card->dev,
  246. "Mixer reg %02x was %02x, set to %02x\n",
  247. reg, old, new);
  248. }
  249. spin_unlock_irqrestore(&chip->mixer_lock, flags);
  250. return oval;
  251. }
  252. /* -----------------------------------------------------------------
  253. * Write command to Controller Registers
  254. * -----------------------------------------------------------------*/
  255. static void snd_es1938_write_cmd(struct es1938 *chip, unsigned char cmd)
  256. {
  257. int i;
  258. unsigned char v;
  259. for (i = 0; i < WRITE_LOOP_TIMEOUT; i++) {
  260. if (!(v = inb(SLSB_REG(chip, READSTATUS)) & 0x80)) {
  261. outb(cmd, SLSB_REG(chip, WRITEDATA));
  262. return;
  263. }
  264. }
  265. dev_err(chip->card->dev,
  266. "snd_es1938_write_cmd timeout (0x02%x/0x02%x)\n", cmd, v);
  267. }
  268. /* -----------------------------------------------------------------
  269. * Read the Read Data Buffer
  270. * -----------------------------------------------------------------*/
  271. static int snd_es1938_get_byte(struct es1938 *chip)
  272. {
  273. int i;
  274. unsigned char v;
  275. for (i = GET_LOOP_TIMEOUT; i; i--)
  276. if ((v = inb(SLSB_REG(chip, STATUS))) & 0x80)
  277. return inb(SLSB_REG(chip, READDATA));
  278. dev_err(chip->card->dev, "get_byte timeout: status 0x02%x\n", v);
  279. return -ENODEV;
  280. }
  281. /* -----------------------------------------------------------------
  282. * Write value cmd register
  283. * -----------------------------------------------------------------*/
  284. static void snd_es1938_write(struct es1938 *chip, unsigned char reg, unsigned char val)
  285. {
  286. unsigned long flags;
  287. spin_lock_irqsave(&chip->reg_lock, flags);
  288. snd_es1938_write_cmd(chip, reg);
  289. snd_es1938_write_cmd(chip, val);
  290. spin_unlock_irqrestore(&chip->reg_lock, flags);
  291. dev_dbg(chip->card->dev, "Reg %02x set to %02x\n", reg, val);
  292. }
  293. /* -----------------------------------------------------------------
  294. * Read data from cmd register and return it
  295. * -----------------------------------------------------------------*/
  296. static unsigned char snd_es1938_read(struct es1938 *chip, unsigned char reg)
  297. {
  298. unsigned char val;
  299. unsigned long flags;
  300. spin_lock_irqsave(&chip->reg_lock, flags);
  301. snd_es1938_write_cmd(chip, ESS_CMD_READREG);
  302. snd_es1938_write_cmd(chip, reg);
  303. val = snd_es1938_get_byte(chip);
  304. spin_unlock_irqrestore(&chip->reg_lock, flags);
  305. dev_dbg(chip->card->dev, "Reg %02x now is %02x\n", reg, val);
  306. return val;
  307. }
  308. /* -----------------------------------------------------------------
  309. * Write data to cmd register and return old value
  310. * -----------------------------------------------------------------*/
  311. static int snd_es1938_bits(struct es1938 *chip, unsigned char reg, unsigned char mask,
  312. unsigned char val)
  313. {
  314. unsigned long flags;
  315. unsigned char old, new, oval;
  316. spin_lock_irqsave(&chip->reg_lock, flags);
  317. snd_es1938_write_cmd(chip, ESS_CMD_READREG);
  318. snd_es1938_write_cmd(chip, reg);
  319. old = snd_es1938_get_byte(chip);
  320. oval = old & mask;
  321. if (val != oval) {
  322. snd_es1938_write_cmd(chip, reg);
  323. new = (old & ~mask) | (val & mask);
  324. snd_es1938_write_cmd(chip, new);
  325. dev_dbg(chip->card->dev, "Reg %02x was %02x, set to %02x\n",
  326. reg, old, new);
  327. }
  328. spin_unlock_irqrestore(&chip->reg_lock, flags);
  329. return oval;
  330. }
  331. /* --------------------------------------------------------------------
  332. * Reset the chip
  333. * --------------------------------------------------------------------*/
  334. static void snd_es1938_reset(struct es1938 *chip)
  335. {
  336. int i;
  337. outb(3, SLSB_REG(chip, RESET));
  338. inb(SLSB_REG(chip, RESET));
  339. outb(0, SLSB_REG(chip, RESET));
  340. for (i = 0; i < RESET_LOOP_TIMEOUT; i++) {
  341. if (inb(SLSB_REG(chip, STATUS)) & 0x80) {
  342. if (inb(SLSB_REG(chip, READDATA)) == 0xaa)
  343. goto __next;
  344. }
  345. }
  346. dev_err(chip->card->dev, "ESS Solo-1 reset failed\n");
  347. __next:
  348. snd_es1938_write_cmd(chip, ESS_CMD_ENABLEEXT);
  349. /* Demand transfer DMA: 4 bytes per DMA request */
  350. snd_es1938_write(chip, ESS_CMD_DMATYPE, 2);
  351. /* Change behaviour of register A1
  352. 4x oversampling
  353. 2nd channel DAC asynchronous */
  354. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2MODE, 0x32);
  355. /* enable/select DMA channel and IRQ channel */
  356. snd_es1938_bits(chip, ESS_CMD_IRQCONTROL, 0xf0, 0x50);
  357. snd_es1938_bits(chip, ESS_CMD_DRQCONTROL, 0xf0, 0x50);
  358. snd_es1938_write_cmd(chip, ESS_CMD_ENABLEAUDIO1);
  359. /* Set spatializer parameters to recommended values */
  360. snd_es1938_mixer_write(chip, 0x54, 0x8f);
  361. snd_es1938_mixer_write(chip, 0x56, 0x95);
  362. snd_es1938_mixer_write(chip, 0x58, 0x94);
  363. snd_es1938_mixer_write(chip, 0x5a, 0x80);
  364. }
  365. /* --------------------------------------------------------------------
  366. * Reset the FIFOs
  367. * --------------------------------------------------------------------*/
  368. static void snd_es1938_reset_fifo(struct es1938 *chip)
  369. {
  370. outb(2, SLSB_REG(chip, RESET));
  371. outb(0, SLSB_REG(chip, RESET));
  372. }
  373. static const struct snd_ratnum clocks[2] = {
  374. {
  375. .num = 793800,
  376. .den_min = 1,
  377. .den_max = 128,
  378. .den_step = 1,
  379. },
  380. {
  381. .num = 768000,
  382. .den_min = 1,
  383. .den_max = 128,
  384. .den_step = 1,
  385. }
  386. };
  387. static const struct snd_pcm_hw_constraint_ratnums hw_constraints_clocks = {
  388. .nrats = 2,
  389. .rats = clocks,
  390. };
  391. static void snd_es1938_rate_set(struct es1938 *chip,
  392. struct snd_pcm_substream *substream,
  393. int mode)
  394. {
  395. unsigned int bits, div0;
  396. struct snd_pcm_runtime *runtime = substream->runtime;
  397. if (runtime->rate_num == clocks[0].num)
  398. bits = 128 - runtime->rate_den;
  399. else
  400. bits = 256 - runtime->rate_den;
  401. /* set filter register */
  402. div0 = 256 - 7160000*20/(8*82*runtime->rate);
  403. if (mode == DAC2) {
  404. snd_es1938_mixer_write(chip, 0x70, bits);
  405. snd_es1938_mixer_write(chip, 0x72, div0);
  406. } else {
  407. snd_es1938_write(chip, 0xA1, bits);
  408. snd_es1938_write(chip, 0xA2, div0);
  409. }
  410. }
  411. /* --------------------------------------------------------------------
  412. * Configure Solo1 builtin DMA Controller
  413. * --------------------------------------------------------------------*/
  414. static void snd_es1938_playback1_setdma(struct es1938 *chip)
  415. {
  416. outb(0x00, SLIO_REG(chip, AUDIO2MODE));
  417. outl(chip->dma2_start, SLIO_REG(chip, AUDIO2DMAADDR));
  418. outw(0, SLIO_REG(chip, AUDIO2DMACOUNT));
  419. outw(chip->dma2_size, SLIO_REG(chip, AUDIO2DMACOUNT));
  420. }
  421. static void snd_es1938_playback2_setdma(struct es1938 *chip)
  422. {
  423. /* Enable DMA controller */
  424. outb(0xc4, SLDM_REG(chip, DMACOMMAND));
  425. /* 1. Master reset */
  426. outb(0, SLDM_REG(chip, DMACLEAR));
  427. /* 2. Mask DMA */
  428. outb(1, SLDM_REG(chip, DMAMASK));
  429. outb(0x18, SLDM_REG(chip, DMAMODE));
  430. outl(chip->dma1_start, SLDM_REG(chip, DMAADDR));
  431. outw(chip->dma1_size - 1, SLDM_REG(chip, DMACOUNT));
  432. /* 3. Unmask DMA */
  433. outb(0, SLDM_REG(chip, DMAMASK));
  434. }
  435. static void snd_es1938_capture_setdma(struct es1938 *chip)
  436. {
  437. /* Enable DMA controller */
  438. outb(0xc4, SLDM_REG(chip, DMACOMMAND));
  439. /* 1. Master reset */
  440. outb(0, SLDM_REG(chip, DMACLEAR));
  441. /* 2. Mask DMA */
  442. outb(1, SLDM_REG(chip, DMAMASK));
  443. outb(0x14, SLDM_REG(chip, DMAMODE));
  444. outl(chip->dma1_start, SLDM_REG(chip, DMAADDR));
  445. chip->last_capture_dmaaddr = chip->dma1_start;
  446. outw(chip->dma1_size - 1, SLDM_REG(chip, DMACOUNT));
  447. /* 3. Unmask DMA */
  448. outb(0, SLDM_REG(chip, DMAMASK));
  449. }
  450. /* ----------------------------------------------------------------------
  451. *
  452. * *** PCM part ***
  453. */
  454. static int snd_es1938_capture_trigger(struct snd_pcm_substream *substream,
  455. int cmd)
  456. {
  457. struct es1938 *chip = snd_pcm_substream_chip(substream);
  458. int val;
  459. switch (cmd) {
  460. case SNDRV_PCM_TRIGGER_START:
  461. case SNDRV_PCM_TRIGGER_RESUME:
  462. val = 0x0f;
  463. chip->active |= ADC1;
  464. break;
  465. case SNDRV_PCM_TRIGGER_STOP:
  466. case SNDRV_PCM_TRIGGER_SUSPEND:
  467. val = 0x00;
  468. chip->active &= ~ADC1;
  469. break;
  470. default:
  471. return -EINVAL;
  472. }
  473. snd_es1938_write(chip, ESS_CMD_DMACONTROL, val);
  474. return 0;
  475. }
  476. static int snd_es1938_playback1_trigger(struct snd_pcm_substream *substream,
  477. int cmd)
  478. {
  479. struct es1938 *chip = snd_pcm_substream_chip(substream);
  480. switch (cmd) {
  481. case SNDRV_PCM_TRIGGER_START:
  482. case SNDRV_PCM_TRIGGER_RESUME:
  483. /* According to the documentation this should be:
  484. 0x13 but that value may randomly swap stereo channels */
  485. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0x92);
  486. udelay(10);
  487. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0x93);
  488. /* This two stage init gives the FIFO -> DAC connection time to
  489. * settle before first data from DMA flows in. This should ensure
  490. * no swapping of stereo channels. Report a bug if otherwise :-) */
  491. outb(0x0a, SLIO_REG(chip, AUDIO2MODE));
  492. chip->active |= DAC2;
  493. break;
  494. case SNDRV_PCM_TRIGGER_STOP:
  495. case SNDRV_PCM_TRIGGER_SUSPEND:
  496. outb(0, SLIO_REG(chip, AUDIO2MODE));
  497. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL1, 0);
  498. chip->active &= ~DAC2;
  499. break;
  500. default:
  501. return -EINVAL;
  502. }
  503. return 0;
  504. }
  505. static int snd_es1938_playback2_trigger(struct snd_pcm_substream *substream,
  506. int cmd)
  507. {
  508. struct es1938 *chip = snd_pcm_substream_chip(substream);
  509. int val;
  510. switch (cmd) {
  511. case SNDRV_PCM_TRIGGER_START:
  512. case SNDRV_PCM_TRIGGER_RESUME:
  513. val = 5;
  514. chip->active |= DAC1;
  515. break;
  516. case SNDRV_PCM_TRIGGER_STOP:
  517. case SNDRV_PCM_TRIGGER_SUSPEND:
  518. val = 0;
  519. chip->active &= ~DAC1;
  520. break;
  521. default:
  522. return -EINVAL;
  523. }
  524. snd_es1938_write(chip, ESS_CMD_DMACONTROL, val);
  525. return 0;
  526. }
  527. static int snd_es1938_playback_trigger(struct snd_pcm_substream *substream,
  528. int cmd)
  529. {
  530. switch (substream->number) {
  531. case 0:
  532. return snd_es1938_playback1_trigger(substream, cmd);
  533. case 1:
  534. return snd_es1938_playback2_trigger(substream, cmd);
  535. }
  536. snd_BUG();
  537. return -EINVAL;
  538. }
  539. /* --------------------------------------------------------------------
  540. * First channel for Extended Mode Audio 1 ADC Operation
  541. * --------------------------------------------------------------------*/
  542. static int snd_es1938_capture_prepare(struct snd_pcm_substream *substream)
  543. {
  544. struct es1938 *chip = snd_pcm_substream_chip(substream);
  545. struct snd_pcm_runtime *runtime = substream->runtime;
  546. int u, is8, mono;
  547. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  548. unsigned int count = snd_pcm_lib_period_bytes(substream);
  549. chip->dma1_size = size;
  550. chip->dma1_start = runtime->dma_addr;
  551. mono = (runtime->channels > 1) ? 0 : 1;
  552. is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1;
  553. u = snd_pcm_format_unsigned(runtime->format);
  554. chip->dma1_shift = 2 - mono - is8;
  555. snd_es1938_reset_fifo(chip);
  556. /* program type */
  557. snd_es1938_bits(chip, ESS_CMD_ANALOGCONTROL, 0x03, (mono ? 2 : 1));
  558. /* set clock and counters */
  559. snd_es1938_rate_set(chip, substream, ADC1);
  560. count = 0x10000 - count;
  561. snd_es1938_write(chip, ESS_CMD_DMACNTRELOADL, count & 0xff);
  562. snd_es1938_write(chip, ESS_CMD_DMACNTRELOADH, count >> 8);
  563. /* initialize and configure ADC */
  564. snd_es1938_write(chip, ESS_CMD_SETFORMAT2, u ? 0x51 : 0x71);
  565. snd_es1938_write(chip, ESS_CMD_SETFORMAT2, 0x90 |
  566. (u ? 0x00 : 0x20) |
  567. (is8 ? 0x00 : 0x04) |
  568. (mono ? 0x40 : 0x08));
  569. // snd_es1938_reset_fifo(chip);
  570. /* 11. configure system interrupt controller and DMA controller */
  571. snd_es1938_capture_setdma(chip);
  572. return 0;
  573. }
  574. /* ------------------------------------------------------------------------------
  575. * Second Audio channel DAC Operation
  576. * ------------------------------------------------------------------------------*/
  577. static int snd_es1938_playback1_prepare(struct snd_pcm_substream *substream)
  578. {
  579. struct es1938 *chip = snd_pcm_substream_chip(substream);
  580. struct snd_pcm_runtime *runtime = substream->runtime;
  581. int u, is8, mono;
  582. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  583. unsigned int count = snd_pcm_lib_period_bytes(substream);
  584. chip->dma2_size = size;
  585. chip->dma2_start = runtime->dma_addr;
  586. mono = (runtime->channels > 1) ? 0 : 1;
  587. is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1;
  588. u = snd_pcm_format_unsigned(runtime->format);
  589. chip->dma2_shift = 2 - mono - is8;
  590. snd_es1938_reset_fifo(chip);
  591. /* set clock and counters */
  592. snd_es1938_rate_set(chip, substream, DAC2);
  593. count >>= 1;
  594. count = 0x10000 - count;
  595. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2TCOUNTL, count & 0xff);
  596. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2TCOUNTH, count >> 8);
  597. /* initialize and configure Audio 2 DAC */
  598. snd_es1938_mixer_write(chip, ESSSB_IREG_AUDIO2CONTROL2, 0x40 | (u ? 0 : 4) |
  599. (mono ? 0 : 2) | (is8 ? 0 : 1));
  600. /* program DMA */
  601. snd_es1938_playback1_setdma(chip);
  602. return 0;
  603. }
  604. static int snd_es1938_playback2_prepare(struct snd_pcm_substream *substream)
  605. {
  606. struct es1938 *chip = snd_pcm_substream_chip(substream);
  607. struct snd_pcm_runtime *runtime = substream->runtime;
  608. int u, is8, mono;
  609. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  610. unsigned int count = snd_pcm_lib_period_bytes(substream);
  611. chip->dma1_size = size;
  612. chip->dma1_start = runtime->dma_addr;
  613. mono = (runtime->channels > 1) ? 0 : 1;
  614. is8 = snd_pcm_format_width(runtime->format) == 16 ? 0 : 1;
  615. u = snd_pcm_format_unsigned(runtime->format);
  616. chip->dma1_shift = 2 - mono - is8;
  617. count = 0x10000 - count;
  618. /* reset */
  619. snd_es1938_reset_fifo(chip);
  620. snd_es1938_bits(chip, ESS_CMD_ANALOGCONTROL, 0x03, (mono ? 2 : 1));
  621. /* set clock and counters */
  622. snd_es1938_rate_set(chip, substream, DAC1);
  623. snd_es1938_write(chip, ESS_CMD_DMACNTRELOADL, count & 0xff);
  624. snd_es1938_write(chip, ESS_CMD_DMACNTRELOADH, count >> 8);
  625. /* initialized and configure DAC */
  626. snd_es1938_write(chip, ESS_CMD_SETFORMAT, u ? 0x80 : 0x00);
  627. snd_es1938_write(chip, ESS_CMD_SETFORMAT, u ? 0x51 : 0x71);
  628. snd_es1938_write(chip, ESS_CMD_SETFORMAT2,
  629. 0x90 | (mono ? 0x40 : 0x08) |
  630. (is8 ? 0x00 : 0x04) | (u ? 0x00 : 0x20));
  631. /* program DMA */
  632. snd_es1938_playback2_setdma(chip);
  633. return 0;
  634. }
  635. static int snd_es1938_playback_prepare(struct snd_pcm_substream *substream)
  636. {
  637. switch (substream->number) {
  638. case 0:
  639. return snd_es1938_playback1_prepare(substream);
  640. case 1:
  641. return snd_es1938_playback2_prepare(substream);
  642. }
  643. snd_BUG();
  644. return -EINVAL;
  645. }
  646. /* during the incrementing of dma counters the DMA register reads sometimes
  647. returns garbage. To ensure a valid hw pointer, the following checks which
  648. should be very unlikely to fail are used:
  649. - is the current DMA address in the valid DMA range ?
  650. - is the sum of DMA address and DMA counter pointing to the last DMA byte ?
  651. One can argue this could differ by one byte depending on which register is
  652. updated first, so the implementation below allows for that.
  653. */
  654. static snd_pcm_uframes_t snd_es1938_capture_pointer(struct snd_pcm_substream *substream)
  655. {
  656. struct es1938 *chip = snd_pcm_substream_chip(substream);
  657. size_t ptr;
  658. #if 0
  659. size_t old, new;
  660. /* This stuff is *needed*, don't ask why - AB */
  661. old = inw(SLDM_REG(chip, DMACOUNT));
  662. while ((new = inw(SLDM_REG(chip, DMACOUNT))) != old)
  663. old = new;
  664. ptr = chip->dma1_size - 1 - new;
  665. #else
  666. size_t count;
  667. unsigned int diff;
  668. ptr = inl(SLDM_REG(chip, DMAADDR));
  669. count = inw(SLDM_REG(chip, DMACOUNT));
  670. diff = chip->dma1_start + chip->dma1_size - ptr - count;
  671. if (diff > 3 || ptr < chip->dma1_start
  672. || ptr >= chip->dma1_start+chip->dma1_size)
  673. ptr = chip->last_capture_dmaaddr; /* bad, use last saved */
  674. else
  675. chip->last_capture_dmaaddr = ptr; /* good, remember it */
  676. ptr -= chip->dma1_start;
  677. #endif
  678. return ptr >> chip->dma1_shift;
  679. }
  680. static snd_pcm_uframes_t snd_es1938_playback1_pointer(struct snd_pcm_substream *substream)
  681. {
  682. struct es1938 *chip = snd_pcm_substream_chip(substream);
  683. size_t ptr;
  684. #if 1
  685. ptr = chip->dma2_size - inw(SLIO_REG(chip, AUDIO2DMACOUNT));
  686. #else
  687. ptr = inl(SLIO_REG(chip, AUDIO2DMAADDR)) - chip->dma2_start;
  688. #endif
  689. return ptr >> chip->dma2_shift;
  690. }
  691. static snd_pcm_uframes_t snd_es1938_playback2_pointer(struct snd_pcm_substream *substream)
  692. {
  693. struct es1938 *chip = snd_pcm_substream_chip(substream);
  694. size_t ptr;
  695. size_t old, new;
  696. #if 1
  697. /* This stuff is *needed*, don't ask why - AB */
  698. old = inw(SLDM_REG(chip, DMACOUNT));
  699. while ((new = inw(SLDM_REG(chip, DMACOUNT))) != old)
  700. old = new;
  701. ptr = chip->dma1_size - 1 - new;
  702. #else
  703. ptr = inl(SLDM_REG(chip, DMAADDR)) - chip->dma1_start;
  704. #endif
  705. return ptr >> chip->dma1_shift;
  706. }
  707. static snd_pcm_uframes_t snd_es1938_playback_pointer(struct snd_pcm_substream *substream)
  708. {
  709. switch (substream->number) {
  710. case 0:
  711. return snd_es1938_playback1_pointer(substream);
  712. case 1:
  713. return snd_es1938_playback2_pointer(substream);
  714. }
  715. snd_BUG();
  716. return -EINVAL;
  717. }
  718. static int snd_es1938_capture_copy(struct snd_pcm_substream *substream,
  719. int channel, unsigned long pos,
  720. void __user *dst, unsigned long count)
  721. {
  722. struct snd_pcm_runtime *runtime = substream->runtime;
  723. struct es1938 *chip = snd_pcm_substream_chip(substream);
  724. if (snd_BUG_ON(pos + count > chip->dma1_size))
  725. return -EINVAL;
  726. if (pos + count < chip->dma1_size) {
  727. if (copy_to_user(dst, runtime->dma_area + pos + 1, count))
  728. return -EFAULT;
  729. } else {
  730. if (copy_to_user(dst, runtime->dma_area + pos + 1, count - 1))
  731. return -EFAULT;
  732. if (put_user(runtime->dma_area[0],
  733. ((unsigned char __user *)dst) + count - 1))
  734. return -EFAULT;
  735. }
  736. return 0;
  737. }
  738. static int snd_es1938_capture_copy_kernel(struct snd_pcm_substream *substream,
  739. int channel, unsigned long pos,
  740. void *dst, unsigned long count)
  741. {
  742. struct snd_pcm_runtime *runtime = substream->runtime;
  743. struct es1938 *chip = snd_pcm_substream_chip(substream);
  744. if (snd_BUG_ON(pos + count > chip->dma1_size))
  745. return -EINVAL;
  746. if (pos + count < chip->dma1_size) {
  747. memcpy(dst, runtime->dma_area + pos + 1, count);
  748. } else {
  749. memcpy(dst, runtime->dma_area + pos + 1, count - 1);
  750. runtime->dma_area[0] = *((unsigned char *)dst + count - 1);
  751. }
  752. return 0;
  753. }
  754. /* ----------------------------------------------------------------------
  755. * Audio1 Capture (ADC)
  756. * ----------------------------------------------------------------------*/
  757. static const struct snd_pcm_hardware snd_es1938_capture =
  758. {
  759. .info = (SNDRV_PCM_INFO_INTERLEAVED |
  760. SNDRV_PCM_INFO_BLOCK_TRANSFER),
  761. .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
  762. SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE),
  763. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  764. .rate_min = 6000,
  765. .rate_max = 48000,
  766. .channels_min = 1,
  767. .channels_max = 2,
  768. .buffer_bytes_max = 0x8000, /* DMA controller screws on higher values */
  769. .period_bytes_min = 64,
  770. .period_bytes_max = 0x8000,
  771. .periods_min = 1,
  772. .periods_max = 1024,
  773. .fifo_size = 256,
  774. };
  775. /* -----------------------------------------------------------------------
  776. * Audio2 Playback (DAC)
  777. * -----------------------------------------------------------------------*/
  778. static const struct snd_pcm_hardware snd_es1938_playback =
  779. {
  780. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  781. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  782. SNDRV_PCM_INFO_MMAP_VALID),
  783. .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
  784. SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U16_LE),
  785. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  786. .rate_min = 6000,
  787. .rate_max = 48000,
  788. .channels_min = 1,
  789. .channels_max = 2,
  790. .buffer_bytes_max = 0x8000, /* DMA controller screws on higher values */
  791. .period_bytes_min = 64,
  792. .period_bytes_max = 0x8000,
  793. .periods_min = 1,
  794. .periods_max = 1024,
  795. .fifo_size = 256,
  796. };
  797. static int snd_es1938_capture_open(struct snd_pcm_substream *substream)
  798. {
  799. struct es1938 *chip = snd_pcm_substream_chip(substream);
  800. struct snd_pcm_runtime *runtime = substream->runtime;
  801. if (chip->playback2_substream)
  802. return -EAGAIN;
  803. chip->capture_substream = substream;
  804. runtime->hw = snd_es1938_capture;
  805. snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  806. &hw_constraints_clocks);
  807. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 0, 0xff00);
  808. return 0;
  809. }
  810. static int snd_es1938_playback_open(struct snd_pcm_substream *substream)
  811. {
  812. struct es1938 *chip = snd_pcm_substream_chip(substream);
  813. struct snd_pcm_runtime *runtime = substream->runtime;
  814. switch (substream->number) {
  815. case 0:
  816. chip->playback1_substream = substream;
  817. break;
  818. case 1:
  819. if (chip->capture_substream)
  820. return -EAGAIN;
  821. chip->playback2_substream = substream;
  822. break;
  823. default:
  824. snd_BUG();
  825. return -EINVAL;
  826. }
  827. runtime->hw = snd_es1938_playback;
  828. snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  829. &hw_constraints_clocks);
  830. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 0, 0xff00);
  831. return 0;
  832. }
  833. static int snd_es1938_capture_close(struct snd_pcm_substream *substream)
  834. {
  835. struct es1938 *chip = snd_pcm_substream_chip(substream);
  836. chip->capture_substream = NULL;
  837. return 0;
  838. }
  839. static int snd_es1938_playback_close(struct snd_pcm_substream *substream)
  840. {
  841. struct es1938 *chip = snd_pcm_substream_chip(substream);
  842. switch (substream->number) {
  843. case 0:
  844. chip->playback1_substream = NULL;
  845. break;
  846. case 1:
  847. chip->playback2_substream = NULL;
  848. break;
  849. default:
  850. snd_BUG();
  851. return -EINVAL;
  852. }
  853. return 0;
  854. }
  855. static const struct snd_pcm_ops snd_es1938_playback_ops = {
  856. .open = snd_es1938_playback_open,
  857. .close = snd_es1938_playback_close,
  858. .prepare = snd_es1938_playback_prepare,
  859. .trigger = snd_es1938_playback_trigger,
  860. .pointer = snd_es1938_playback_pointer,
  861. };
  862. static const struct snd_pcm_ops snd_es1938_capture_ops = {
  863. .open = snd_es1938_capture_open,
  864. .close = snd_es1938_capture_close,
  865. .prepare = snd_es1938_capture_prepare,
  866. .trigger = snd_es1938_capture_trigger,
  867. .pointer = snd_es1938_capture_pointer,
  868. .copy_user = snd_es1938_capture_copy,
  869. .copy_kernel = snd_es1938_capture_copy_kernel,
  870. };
  871. static int snd_es1938_new_pcm(struct es1938 *chip, int device)
  872. {
  873. struct snd_pcm *pcm;
  874. int err;
  875. if ((err = snd_pcm_new(chip->card, "es-1938-1946", device, 2, 1, &pcm)) < 0)
  876. return err;
  877. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1938_playback_ops);
  878. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1938_capture_ops);
  879. pcm->private_data = chip;
  880. pcm->info_flags = 0;
  881. strcpy(pcm->name, "ESS Solo-1");
  882. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  883. &chip->pci->dev, 64*1024, 64*1024);
  884. chip->pcm = pcm;
  885. return 0;
  886. }
  887. /* -------------------------------------------------------------------
  888. *
  889. * *** Mixer part ***
  890. */
  891. static int snd_es1938_info_mux(struct snd_kcontrol *kcontrol,
  892. struct snd_ctl_elem_info *uinfo)
  893. {
  894. static const char * const texts[8] = {
  895. "Mic", "Mic Master", "CD", "AOUT",
  896. "Mic1", "Mix", "Line", "Master"
  897. };
  898. return snd_ctl_enum_info(uinfo, 1, 8, texts);
  899. }
  900. static int snd_es1938_get_mux(struct snd_kcontrol *kcontrol,
  901. struct snd_ctl_elem_value *ucontrol)
  902. {
  903. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  904. ucontrol->value.enumerated.item[0] = snd_es1938_mixer_read(chip, 0x1c) & 0x07;
  905. return 0;
  906. }
  907. static int snd_es1938_put_mux(struct snd_kcontrol *kcontrol,
  908. struct snd_ctl_elem_value *ucontrol)
  909. {
  910. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  911. unsigned char val = ucontrol->value.enumerated.item[0];
  912. if (val > 7)
  913. return -EINVAL;
  914. return snd_es1938_mixer_bits(chip, 0x1c, 0x07, val) != val;
  915. }
  916. #define snd_es1938_info_spatializer_enable snd_ctl_boolean_mono_info
  917. static int snd_es1938_get_spatializer_enable(struct snd_kcontrol *kcontrol,
  918. struct snd_ctl_elem_value *ucontrol)
  919. {
  920. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  921. unsigned char val = snd_es1938_mixer_read(chip, 0x50);
  922. ucontrol->value.integer.value[0] = !!(val & 8);
  923. return 0;
  924. }
  925. static int snd_es1938_put_spatializer_enable(struct snd_kcontrol *kcontrol,
  926. struct snd_ctl_elem_value *ucontrol)
  927. {
  928. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  929. unsigned char oval, nval;
  930. int change;
  931. nval = ucontrol->value.integer.value[0] ? 0x0c : 0x04;
  932. oval = snd_es1938_mixer_read(chip, 0x50) & 0x0c;
  933. change = nval != oval;
  934. if (change) {
  935. snd_es1938_mixer_write(chip, 0x50, nval & ~0x04);
  936. snd_es1938_mixer_write(chip, 0x50, nval);
  937. }
  938. return change;
  939. }
  940. static int snd_es1938_info_hw_volume(struct snd_kcontrol *kcontrol,
  941. struct snd_ctl_elem_info *uinfo)
  942. {
  943. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  944. uinfo->count = 2;
  945. uinfo->value.integer.min = 0;
  946. uinfo->value.integer.max = 63;
  947. return 0;
  948. }
  949. static int snd_es1938_get_hw_volume(struct snd_kcontrol *kcontrol,
  950. struct snd_ctl_elem_value *ucontrol)
  951. {
  952. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  953. ucontrol->value.integer.value[0] = snd_es1938_mixer_read(chip, 0x61) & 0x3f;
  954. ucontrol->value.integer.value[1] = snd_es1938_mixer_read(chip, 0x63) & 0x3f;
  955. return 0;
  956. }
  957. #define snd_es1938_info_hw_switch snd_ctl_boolean_stereo_info
  958. static int snd_es1938_get_hw_switch(struct snd_kcontrol *kcontrol,
  959. struct snd_ctl_elem_value *ucontrol)
  960. {
  961. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  962. ucontrol->value.integer.value[0] = !(snd_es1938_mixer_read(chip, 0x61) & 0x40);
  963. ucontrol->value.integer.value[1] = !(snd_es1938_mixer_read(chip, 0x63) & 0x40);
  964. return 0;
  965. }
  966. static void snd_es1938_hwv_free(struct snd_kcontrol *kcontrol)
  967. {
  968. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  969. chip->master_volume = NULL;
  970. chip->master_switch = NULL;
  971. chip->hw_volume = NULL;
  972. chip->hw_switch = NULL;
  973. }
  974. static int snd_es1938_reg_bits(struct es1938 *chip, unsigned char reg,
  975. unsigned char mask, unsigned char val)
  976. {
  977. if (reg < 0xa0)
  978. return snd_es1938_mixer_bits(chip, reg, mask, val);
  979. else
  980. return snd_es1938_bits(chip, reg, mask, val);
  981. }
  982. static int snd_es1938_reg_read(struct es1938 *chip, unsigned char reg)
  983. {
  984. if (reg < 0xa0)
  985. return snd_es1938_mixer_read(chip, reg);
  986. else
  987. return snd_es1938_read(chip, reg);
  988. }
  989. #define ES1938_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \
  990. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  991. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ,\
  992. .name = xname, .index = xindex, \
  993. .info = snd_es1938_info_single, \
  994. .get = snd_es1938_get_single, .put = snd_es1938_put_single, \
  995. .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \
  996. .tlv = { .p = xtlv } }
  997. #define ES1938_SINGLE(xname, xindex, reg, shift, mask, invert) \
  998. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  999. .info = snd_es1938_info_single, \
  1000. .get = snd_es1938_get_single, .put = snd_es1938_put_single, \
  1001. .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
  1002. static int snd_es1938_info_single(struct snd_kcontrol *kcontrol,
  1003. struct snd_ctl_elem_info *uinfo)
  1004. {
  1005. int mask = (kcontrol->private_value >> 16) & 0xff;
  1006. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1007. uinfo->count = 1;
  1008. uinfo->value.integer.min = 0;
  1009. uinfo->value.integer.max = mask;
  1010. return 0;
  1011. }
  1012. static int snd_es1938_get_single(struct snd_kcontrol *kcontrol,
  1013. struct snd_ctl_elem_value *ucontrol)
  1014. {
  1015. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  1016. int reg = kcontrol->private_value & 0xff;
  1017. int shift = (kcontrol->private_value >> 8) & 0xff;
  1018. int mask = (kcontrol->private_value >> 16) & 0xff;
  1019. int invert = (kcontrol->private_value >> 24) & 0xff;
  1020. int val;
  1021. val = snd_es1938_reg_read(chip, reg);
  1022. ucontrol->value.integer.value[0] = (val >> shift) & mask;
  1023. if (invert)
  1024. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1025. return 0;
  1026. }
  1027. static int snd_es1938_put_single(struct snd_kcontrol *kcontrol,
  1028. struct snd_ctl_elem_value *ucontrol)
  1029. {
  1030. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  1031. int reg = kcontrol->private_value & 0xff;
  1032. int shift = (kcontrol->private_value >> 8) & 0xff;
  1033. int mask = (kcontrol->private_value >> 16) & 0xff;
  1034. int invert = (kcontrol->private_value >> 24) & 0xff;
  1035. unsigned char val;
  1036. val = (ucontrol->value.integer.value[0] & mask);
  1037. if (invert)
  1038. val = mask - val;
  1039. mask <<= shift;
  1040. val <<= shift;
  1041. return snd_es1938_reg_bits(chip, reg, mask, val) != val;
  1042. }
  1043. #define ES1938_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert, xtlv) \
  1044. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  1045. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ,\
  1046. .name = xname, .index = xindex, \
  1047. .info = snd_es1938_info_double, \
  1048. .get = snd_es1938_get_double, .put = snd_es1938_put_double, \
  1049. .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22), \
  1050. .tlv = { .p = xtlv } }
  1051. #define ES1938_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
  1052. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1053. .info = snd_es1938_info_double, \
  1054. .get = snd_es1938_get_double, .put = snd_es1938_put_double, \
  1055. .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
  1056. static int snd_es1938_info_double(struct snd_kcontrol *kcontrol,
  1057. struct snd_ctl_elem_info *uinfo)
  1058. {
  1059. int mask = (kcontrol->private_value >> 24) & 0xff;
  1060. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1061. uinfo->count = 2;
  1062. uinfo->value.integer.min = 0;
  1063. uinfo->value.integer.max = mask;
  1064. return 0;
  1065. }
  1066. static int snd_es1938_get_double(struct snd_kcontrol *kcontrol,
  1067. struct snd_ctl_elem_value *ucontrol)
  1068. {
  1069. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  1070. int left_reg = kcontrol->private_value & 0xff;
  1071. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1072. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1073. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1074. int mask = (kcontrol->private_value >> 24) & 0xff;
  1075. int invert = (kcontrol->private_value >> 22) & 1;
  1076. unsigned char left, right;
  1077. left = snd_es1938_reg_read(chip, left_reg);
  1078. if (left_reg != right_reg)
  1079. right = snd_es1938_reg_read(chip, right_reg);
  1080. else
  1081. right = left;
  1082. ucontrol->value.integer.value[0] = (left >> shift_left) & mask;
  1083. ucontrol->value.integer.value[1] = (right >> shift_right) & mask;
  1084. if (invert) {
  1085. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1086. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  1087. }
  1088. return 0;
  1089. }
  1090. static int snd_es1938_put_double(struct snd_kcontrol *kcontrol,
  1091. struct snd_ctl_elem_value *ucontrol)
  1092. {
  1093. struct es1938 *chip = snd_kcontrol_chip(kcontrol);
  1094. int left_reg = kcontrol->private_value & 0xff;
  1095. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1096. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1097. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1098. int mask = (kcontrol->private_value >> 24) & 0xff;
  1099. int invert = (kcontrol->private_value >> 22) & 1;
  1100. int change;
  1101. unsigned char val1, val2, mask1, mask2;
  1102. val1 = ucontrol->value.integer.value[0] & mask;
  1103. val2 = ucontrol->value.integer.value[1] & mask;
  1104. if (invert) {
  1105. val1 = mask - val1;
  1106. val2 = mask - val2;
  1107. }
  1108. val1 <<= shift_left;
  1109. val2 <<= shift_right;
  1110. mask1 = mask << shift_left;
  1111. mask2 = mask << shift_right;
  1112. if (left_reg != right_reg) {
  1113. change = 0;
  1114. if (snd_es1938_reg_bits(chip, left_reg, mask1, val1) != val1)
  1115. change = 1;
  1116. if (snd_es1938_reg_bits(chip, right_reg, mask2, val2) != val2)
  1117. change = 1;
  1118. } else {
  1119. change = (snd_es1938_reg_bits(chip, left_reg, mask1 | mask2,
  1120. val1 | val2) != (val1 | val2));
  1121. }
  1122. return change;
  1123. }
  1124. static const DECLARE_TLV_DB_RANGE(db_scale_master,
  1125. 0, 54, TLV_DB_SCALE_ITEM(-3600, 50, 1),
  1126. 54, 63, TLV_DB_SCALE_ITEM(-900, 100, 0),
  1127. );
  1128. static const DECLARE_TLV_DB_RANGE(db_scale_audio1,
  1129. 0, 8, TLV_DB_SCALE_ITEM(-3300, 300, 1),
  1130. 8, 15, TLV_DB_SCALE_ITEM(-900, 150, 0),
  1131. );
  1132. static const DECLARE_TLV_DB_RANGE(db_scale_audio2,
  1133. 0, 8, TLV_DB_SCALE_ITEM(-3450, 300, 1),
  1134. 8, 15, TLV_DB_SCALE_ITEM(-1050, 150, 0),
  1135. );
  1136. static const DECLARE_TLV_DB_RANGE(db_scale_mic,
  1137. 0, 8, TLV_DB_SCALE_ITEM(-2400, 300, 1),
  1138. 8, 15, TLV_DB_SCALE_ITEM(0, 150, 0),
  1139. );
  1140. static const DECLARE_TLV_DB_RANGE(db_scale_line,
  1141. 0, 8, TLV_DB_SCALE_ITEM(-3150, 300, 1),
  1142. 8, 15, TLV_DB_SCALE_ITEM(-750, 150, 0),
  1143. );
  1144. static const DECLARE_TLV_DB_SCALE(db_scale_capture, 0, 150, 0);
  1145. static const struct snd_kcontrol_new snd_es1938_controls[] = {
  1146. ES1938_DOUBLE_TLV("Master Playback Volume", 0, 0x60, 0x62, 0, 0, 63, 0,
  1147. db_scale_master),
  1148. ES1938_DOUBLE("Master Playback Switch", 0, 0x60, 0x62, 6, 6, 1, 1),
  1149. {
  1150. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1151. .name = "Hardware Master Playback Volume",
  1152. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1153. .info = snd_es1938_info_hw_volume,
  1154. .get = snd_es1938_get_hw_volume,
  1155. },
  1156. {
  1157. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1158. .access = (SNDRV_CTL_ELEM_ACCESS_READ |
  1159. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1160. .name = "Hardware Master Playback Switch",
  1161. .info = snd_es1938_info_hw_switch,
  1162. .get = snd_es1938_get_hw_switch,
  1163. .tlv = { .p = db_scale_master },
  1164. },
  1165. ES1938_SINGLE("Hardware Volume Split", 0, 0x64, 7, 1, 0),
  1166. ES1938_DOUBLE_TLV("Line Playback Volume", 0, 0x3e, 0x3e, 4, 0, 15, 0,
  1167. db_scale_line),
  1168. ES1938_DOUBLE("CD Playback Volume", 0, 0x38, 0x38, 4, 0, 15, 0),
  1169. ES1938_DOUBLE_TLV("FM Playback Volume", 0, 0x36, 0x36, 4, 0, 15, 0,
  1170. db_scale_mic),
  1171. ES1938_DOUBLE_TLV("Mono Playback Volume", 0, 0x6d, 0x6d, 4, 0, 15, 0,
  1172. db_scale_line),
  1173. ES1938_DOUBLE_TLV("Mic Playback Volume", 0, 0x1a, 0x1a, 4, 0, 15, 0,
  1174. db_scale_mic),
  1175. ES1938_DOUBLE_TLV("Aux Playback Volume", 0, 0x3a, 0x3a, 4, 0, 15, 0,
  1176. db_scale_line),
  1177. ES1938_DOUBLE_TLV("Capture Volume", 0, 0xb4, 0xb4, 4, 0, 15, 0,
  1178. db_scale_capture),
  1179. ES1938_SINGLE("Beep Volume", 0, 0x3c, 0, 7, 0),
  1180. ES1938_SINGLE("Record Monitor", 0, 0xa8, 3, 1, 0),
  1181. ES1938_SINGLE("Capture Switch", 0, 0x1c, 4, 1, 1),
  1182. {
  1183. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1184. .name = "Capture Source",
  1185. .info = snd_es1938_info_mux,
  1186. .get = snd_es1938_get_mux,
  1187. .put = snd_es1938_put_mux,
  1188. },
  1189. ES1938_DOUBLE_TLV("Mono Input Playback Volume", 0, 0x6d, 0x6d, 4, 0, 15, 0,
  1190. db_scale_line),
  1191. ES1938_DOUBLE_TLV("PCM Capture Volume", 0, 0x69, 0x69, 4, 0, 15, 0,
  1192. db_scale_audio2),
  1193. ES1938_DOUBLE_TLV("Mic Capture Volume", 0, 0x68, 0x68, 4, 0, 15, 0,
  1194. db_scale_mic),
  1195. ES1938_DOUBLE_TLV("Line Capture Volume", 0, 0x6e, 0x6e, 4, 0, 15, 0,
  1196. db_scale_line),
  1197. ES1938_DOUBLE_TLV("FM Capture Volume", 0, 0x6b, 0x6b, 4, 0, 15, 0,
  1198. db_scale_mic),
  1199. ES1938_DOUBLE_TLV("Mono Capture Volume", 0, 0x6f, 0x6f, 4, 0, 15, 0,
  1200. db_scale_line),
  1201. ES1938_DOUBLE_TLV("CD Capture Volume", 0, 0x6a, 0x6a, 4, 0, 15, 0,
  1202. db_scale_line),
  1203. ES1938_DOUBLE_TLV("Aux Capture Volume", 0, 0x6c, 0x6c, 4, 0, 15, 0,
  1204. db_scale_line),
  1205. ES1938_DOUBLE_TLV("PCM Playback Volume", 0, 0x7c, 0x7c, 4, 0, 15, 0,
  1206. db_scale_audio2),
  1207. ES1938_DOUBLE_TLV("PCM Playback Volume", 1, 0x14, 0x14, 4, 0, 15, 0,
  1208. db_scale_audio1),
  1209. ES1938_SINGLE("3D Control - Level", 0, 0x52, 0, 63, 0),
  1210. {
  1211. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1212. .name = "3D Control - Switch",
  1213. .info = snd_es1938_info_spatializer_enable,
  1214. .get = snd_es1938_get_spatializer_enable,
  1215. .put = snd_es1938_put_spatializer_enable,
  1216. },
  1217. ES1938_SINGLE("Mic Boost (+26dB)", 0, 0x7d, 3, 1, 0)
  1218. };
  1219. /* ---------------------------------------------------------------------------- */
  1220. /* ---------------------------------------------------------------------------- */
  1221. /*
  1222. * initialize the chip - used by resume callback, too
  1223. */
  1224. static void snd_es1938_chip_init(struct es1938 *chip)
  1225. {
  1226. /* reset chip */
  1227. snd_es1938_reset(chip);
  1228. /* configure native mode */
  1229. /* enable bus master */
  1230. pci_set_master(chip->pci);
  1231. /* disable legacy audio */
  1232. pci_write_config_word(chip->pci, SL_PCI_LEGACYCONTROL, 0x805f);
  1233. /* set DDMA base */
  1234. pci_write_config_word(chip->pci, SL_PCI_DDMACONTROL, chip->ddma_port | 1);
  1235. /* set DMA/IRQ policy */
  1236. pci_write_config_dword(chip->pci, SL_PCI_CONFIG, 0);
  1237. /* enable Audio 1, Audio 2, MPU401 IRQ and HW volume IRQ*/
  1238. outb(0xf0, SLIO_REG(chip, IRQCONTROL));
  1239. /* reset DMA */
  1240. outb(0, SLDM_REG(chip, DMACLEAR));
  1241. }
  1242. #ifdef CONFIG_PM_SLEEP
  1243. /*
  1244. * PM support
  1245. */
  1246. static const unsigned char saved_regs[SAVED_REG_SIZE+1] = {
  1247. 0x14, 0x1a, 0x1c, 0x3a, 0x3c, 0x3e, 0x36, 0x38,
  1248. 0x50, 0x52, 0x60, 0x61, 0x62, 0x63, 0x64, 0x68,
  1249. 0x69, 0x6a, 0x6b, 0x6d, 0x6e, 0x6f, 0x7c, 0x7d,
  1250. 0xa8, 0xb4,
  1251. };
  1252. static int es1938_suspend(struct device *dev)
  1253. {
  1254. struct snd_card *card = dev_get_drvdata(dev);
  1255. struct es1938 *chip = card->private_data;
  1256. const unsigned char *s;
  1257. unsigned char *d;
  1258. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1259. /* save mixer-related registers */
  1260. for (s = saved_regs, d = chip->saved_regs; *s; s++, d++)
  1261. *d = snd_es1938_reg_read(chip, *s);
  1262. outb(0x00, SLIO_REG(chip, IRQCONTROL)); /* disable irqs */
  1263. if (chip->irq >= 0) {
  1264. free_irq(chip->irq, chip);
  1265. chip->irq = -1;
  1266. card->sync_irq = -1;
  1267. }
  1268. return 0;
  1269. }
  1270. static int es1938_resume(struct device *dev)
  1271. {
  1272. struct pci_dev *pci = to_pci_dev(dev);
  1273. struct snd_card *card = dev_get_drvdata(dev);
  1274. struct es1938 *chip = card->private_data;
  1275. const unsigned char *s;
  1276. unsigned char *d;
  1277. if (request_irq(pci->irq, snd_es1938_interrupt,
  1278. IRQF_SHARED, KBUILD_MODNAME, chip)) {
  1279. dev_err(dev, "unable to grab IRQ %d, disabling device\n",
  1280. pci->irq);
  1281. snd_card_disconnect(card);
  1282. return -EIO;
  1283. }
  1284. chip->irq = pci->irq;
  1285. card->sync_irq = chip->irq;
  1286. snd_es1938_chip_init(chip);
  1287. /* restore mixer-related registers */
  1288. for (s = saved_regs, d = chip->saved_regs; *s; s++, d++) {
  1289. if (*s < 0xa0)
  1290. snd_es1938_mixer_write(chip, *s, *d);
  1291. else
  1292. snd_es1938_write(chip, *s, *d);
  1293. }
  1294. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1295. return 0;
  1296. }
  1297. static SIMPLE_DEV_PM_OPS(es1938_pm, es1938_suspend, es1938_resume);
  1298. #define ES1938_PM_OPS &es1938_pm
  1299. #else
  1300. #define ES1938_PM_OPS NULL
  1301. #endif /* CONFIG_PM_SLEEP */
  1302. #ifdef SUPPORT_JOYSTICK
  1303. static int snd_es1938_create_gameport(struct es1938 *chip)
  1304. {
  1305. struct gameport *gp;
  1306. chip->gameport = gp = gameport_allocate_port();
  1307. if (!gp) {
  1308. dev_err(chip->card->dev,
  1309. "cannot allocate memory for gameport\n");
  1310. return -ENOMEM;
  1311. }
  1312. gameport_set_name(gp, "ES1938");
  1313. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  1314. gameport_set_dev_parent(gp, &chip->pci->dev);
  1315. gp->io = chip->game_port;
  1316. gameport_register_port(gp);
  1317. return 0;
  1318. }
  1319. static void snd_es1938_free_gameport(struct es1938 *chip)
  1320. {
  1321. if (chip->gameport) {
  1322. gameport_unregister_port(chip->gameport);
  1323. chip->gameport = NULL;
  1324. }
  1325. }
  1326. #else
  1327. static inline int snd_es1938_create_gameport(struct es1938 *chip) { return -ENOSYS; }
  1328. static inline void snd_es1938_free_gameport(struct es1938 *chip) { }
  1329. #endif /* SUPPORT_JOYSTICK */
  1330. static int snd_es1938_free(struct es1938 *chip)
  1331. {
  1332. /* disable irqs */
  1333. outb(0x00, SLIO_REG(chip, IRQCONTROL));
  1334. if (chip->rmidi)
  1335. snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0);
  1336. snd_es1938_free_gameport(chip);
  1337. if (chip->irq >= 0)
  1338. free_irq(chip->irq, chip);
  1339. pci_release_regions(chip->pci);
  1340. pci_disable_device(chip->pci);
  1341. kfree(chip);
  1342. return 0;
  1343. }
  1344. static int snd_es1938_dev_free(struct snd_device *device)
  1345. {
  1346. struct es1938 *chip = device->device_data;
  1347. return snd_es1938_free(chip);
  1348. }
  1349. static int snd_es1938_create(struct snd_card *card,
  1350. struct pci_dev *pci,
  1351. struct es1938 **rchip)
  1352. {
  1353. struct es1938 *chip;
  1354. int err;
  1355. static const struct snd_device_ops ops = {
  1356. .dev_free = snd_es1938_dev_free,
  1357. };
  1358. *rchip = NULL;
  1359. /* enable PCI device */
  1360. if ((err = pci_enable_device(pci)) < 0)
  1361. return err;
  1362. /* check, if we can restrict PCI DMA transfers to 24 bits */
  1363. if (dma_set_mask(&pci->dev, DMA_BIT_MASK(24)) < 0 ||
  1364. dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(24)) < 0) {
  1365. dev_err(card->dev,
  1366. "architecture does not support 24bit PCI busmaster DMA\n");
  1367. pci_disable_device(pci);
  1368. return -ENXIO;
  1369. }
  1370. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1371. if (chip == NULL) {
  1372. pci_disable_device(pci);
  1373. return -ENOMEM;
  1374. }
  1375. spin_lock_init(&chip->reg_lock);
  1376. spin_lock_init(&chip->mixer_lock);
  1377. chip->card = card;
  1378. chip->pci = pci;
  1379. chip->irq = -1;
  1380. if ((err = pci_request_regions(pci, "ESS Solo-1")) < 0) {
  1381. kfree(chip);
  1382. pci_disable_device(pci);
  1383. return err;
  1384. }
  1385. chip->io_port = pci_resource_start(pci, 0);
  1386. chip->sb_port = pci_resource_start(pci, 1);
  1387. chip->vc_port = pci_resource_start(pci, 2);
  1388. chip->mpu_port = pci_resource_start(pci, 3);
  1389. chip->game_port = pci_resource_start(pci, 4);
  1390. if (request_irq(pci->irq, snd_es1938_interrupt, IRQF_SHARED,
  1391. KBUILD_MODNAME, chip)) {
  1392. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  1393. snd_es1938_free(chip);
  1394. return -EBUSY;
  1395. }
  1396. chip->irq = pci->irq;
  1397. card->sync_irq = chip->irq;
  1398. dev_dbg(card->dev,
  1399. "create: io: 0x%lx, sb: 0x%lx, vc: 0x%lx, mpu: 0x%lx, game: 0x%lx\n",
  1400. chip->io_port, chip->sb_port, chip->vc_port, chip->mpu_port, chip->game_port);
  1401. chip->ddma_port = chip->vc_port + 0x00; /* fix from Thomas Sailer */
  1402. snd_es1938_chip_init(chip);
  1403. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1404. snd_es1938_free(chip);
  1405. return err;
  1406. }
  1407. *rchip = chip;
  1408. return 0;
  1409. }
  1410. /* --------------------------------------------------------------------
  1411. * Interrupt handler
  1412. * -------------------------------------------------------------------- */
  1413. static irqreturn_t snd_es1938_interrupt(int irq, void *dev_id)
  1414. {
  1415. struct es1938 *chip = dev_id;
  1416. unsigned char status;
  1417. __always_unused unsigned char audiostatus;
  1418. int handled = 0;
  1419. status = inb(SLIO_REG(chip, IRQCONTROL));
  1420. #if 0
  1421. dev_dbg(chip->card->dev,
  1422. "Es1938debug - interrupt status: =0x%x\n", status);
  1423. #endif
  1424. /* AUDIO 1 */
  1425. if (status & 0x10) {
  1426. #if 0
  1427. dev_dbg(chip->card->dev,
  1428. "Es1938debug - AUDIO channel 1 interrupt\n");
  1429. dev_dbg(chip->card->dev,
  1430. "Es1938debug - AUDIO channel 1 DMAC DMA count: %u\n",
  1431. inw(SLDM_REG(chip, DMACOUNT)));
  1432. dev_dbg(chip->card->dev,
  1433. "Es1938debug - AUDIO channel 1 DMAC DMA base: %u\n",
  1434. inl(SLDM_REG(chip, DMAADDR)));
  1435. dev_dbg(chip->card->dev,
  1436. "Es1938debug - AUDIO channel 1 DMAC DMA status: 0x%x\n",
  1437. inl(SLDM_REG(chip, DMASTATUS)));
  1438. #endif
  1439. /* clear irq */
  1440. handled = 1;
  1441. audiostatus = inb(SLSB_REG(chip, STATUS));
  1442. if (chip->active & ADC1)
  1443. snd_pcm_period_elapsed(chip->capture_substream);
  1444. else if (chip->active & DAC1)
  1445. snd_pcm_period_elapsed(chip->playback2_substream);
  1446. }
  1447. /* AUDIO 2 */
  1448. if (status & 0x20) {
  1449. #if 0
  1450. dev_dbg(chip->card->dev,
  1451. "Es1938debug - AUDIO channel 2 interrupt\n");
  1452. dev_dbg(chip->card->dev,
  1453. "Es1938debug - AUDIO channel 2 DMAC DMA count: %u\n",
  1454. inw(SLIO_REG(chip, AUDIO2DMACOUNT)));
  1455. dev_dbg(chip->card->dev,
  1456. "Es1938debug - AUDIO channel 2 DMAC DMA base: %u\n",
  1457. inl(SLIO_REG(chip, AUDIO2DMAADDR)));
  1458. #endif
  1459. /* clear irq */
  1460. handled = 1;
  1461. snd_es1938_mixer_bits(chip, ESSSB_IREG_AUDIO2CONTROL2, 0x80, 0);
  1462. if (chip->active & DAC2)
  1463. snd_pcm_period_elapsed(chip->playback1_substream);
  1464. }
  1465. /* Hardware volume */
  1466. if (status & 0x40) {
  1467. int split = snd_es1938_mixer_read(chip, 0x64) & 0x80;
  1468. handled = 1;
  1469. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->hw_switch->id);
  1470. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, &chip->hw_volume->id);
  1471. if (!split) {
  1472. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
  1473. &chip->master_switch->id);
  1474. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
  1475. &chip->master_volume->id);
  1476. }
  1477. /* ack interrupt */
  1478. snd_es1938_mixer_write(chip, 0x66, 0x00);
  1479. }
  1480. /* MPU401 */
  1481. if (status & 0x80) {
  1482. // the following line is evil! It switches off MIDI interrupt handling after the first interrupt received.
  1483. // replacing the last 0 by 0x40 works for ESS-Solo1, but just doing nothing works as well!
  1484. // andreas@flying-snail.de
  1485. // snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0); /* ack? */
  1486. if (chip->rmidi) {
  1487. handled = 1;
  1488. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  1489. }
  1490. }
  1491. return IRQ_RETVAL(handled);
  1492. }
  1493. #define ES1938_DMA_SIZE 64
  1494. static int snd_es1938_mixer(struct es1938 *chip)
  1495. {
  1496. struct snd_card *card;
  1497. unsigned int idx;
  1498. int err;
  1499. card = chip->card;
  1500. strcpy(card->mixername, "ESS Solo-1");
  1501. for (idx = 0; idx < ARRAY_SIZE(snd_es1938_controls); idx++) {
  1502. struct snd_kcontrol *kctl;
  1503. kctl = snd_ctl_new1(&snd_es1938_controls[idx], chip);
  1504. switch (idx) {
  1505. case 0:
  1506. chip->master_volume = kctl;
  1507. kctl->private_free = snd_es1938_hwv_free;
  1508. break;
  1509. case 1:
  1510. chip->master_switch = kctl;
  1511. kctl->private_free = snd_es1938_hwv_free;
  1512. break;
  1513. case 2:
  1514. chip->hw_volume = kctl;
  1515. kctl->private_free = snd_es1938_hwv_free;
  1516. break;
  1517. case 3:
  1518. chip->hw_switch = kctl;
  1519. kctl->private_free = snd_es1938_hwv_free;
  1520. break;
  1521. }
  1522. if ((err = snd_ctl_add(card, kctl)) < 0)
  1523. return err;
  1524. }
  1525. return 0;
  1526. }
  1527. static int snd_es1938_probe(struct pci_dev *pci,
  1528. const struct pci_device_id *pci_id)
  1529. {
  1530. static int dev;
  1531. struct snd_card *card;
  1532. struct es1938 *chip;
  1533. struct snd_opl3 *opl3;
  1534. int idx, err;
  1535. if (dev >= SNDRV_CARDS)
  1536. return -ENODEV;
  1537. if (!enable[dev]) {
  1538. dev++;
  1539. return -ENOENT;
  1540. }
  1541. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  1542. 0, &card);
  1543. if (err < 0)
  1544. return err;
  1545. for (idx = 0; idx < 5; idx++) {
  1546. if (pci_resource_start(pci, idx) == 0 ||
  1547. !(pci_resource_flags(pci, idx) & IORESOURCE_IO)) {
  1548. snd_card_free(card);
  1549. return -ENODEV;
  1550. }
  1551. }
  1552. if ((err = snd_es1938_create(card, pci, &chip)) < 0) {
  1553. snd_card_free(card);
  1554. return err;
  1555. }
  1556. card->private_data = chip;
  1557. strcpy(card->driver, "ES1938");
  1558. strcpy(card->shortname, "ESS ES1938 (Solo-1)");
  1559. sprintf(card->longname, "%s rev %i, irq %i",
  1560. card->shortname,
  1561. chip->revision,
  1562. chip->irq);
  1563. if ((err = snd_es1938_new_pcm(chip, 0)) < 0) {
  1564. snd_card_free(card);
  1565. return err;
  1566. }
  1567. if ((err = snd_es1938_mixer(chip)) < 0) {
  1568. snd_card_free(card);
  1569. return err;
  1570. }
  1571. if (snd_opl3_create(card,
  1572. SLSB_REG(chip, FMLOWADDR),
  1573. SLSB_REG(chip, FMHIGHADDR),
  1574. OPL3_HW_OPL3, 1, &opl3) < 0) {
  1575. dev_err(card->dev, "OPL3 not detected at 0x%lx\n",
  1576. SLSB_REG(chip, FMLOWADDR));
  1577. } else {
  1578. if ((err = snd_opl3_timer_new(opl3, 0, 1)) < 0) {
  1579. snd_card_free(card);
  1580. return err;
  1581. }
  1582. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1583. snd_card_free(card);
  1584. return err;
  1585. }
  1586. }
  1587. if (snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
  1588. chip->mpu_port,
  1589. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  1590. -1, &chip->rmidi) < 0) {
  1591. dev_err(card->dev, "unable to initialize MPU-401\n");
  1592. } else {
  1593. // this line is vital for MIDI interrupt handling on ess-solo1
  1594. // andreas@flying-snail.de
  1595. snd_es1938_mixer_bits(chip, ESSSB_IREG_MPU401CONTROL, 0x40, 0x40);
  1596. }
  1597. snd_es1938_create_gameport(chip);
  1598. if ((err = snd_card_register(card)) < 0) {
  1599. snd_card_free(card);
  1600. return err;
  1601. }
  1602. pci_set_drvdata(pci, card);
  1603. dev++;
  1604. return 0;
  1605. }
  1606. static void snd_es1938_remove(struct pci_dev *pci)
  1607. {
  1608. snd_card_free(pci_get_drvdata(pci));
  1609. }
  1610. static struct pci_driver es1938_driver = {
  1611. .name = KBUILD_MODNAME,
  1612. .id_table = snd_es1938_ids,
  1613. .probe = snd_es1938_probe,
  1614. .remove = snd_es1938_remove,
  1615. .driver = {
  1616. .pm = ES1938_PM_OPS,
  1617. },
  1618. };
  1619. module_pci_driver(es1938_driver);