ens1370.c 77 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
  4. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
  5. * Thomas Sailer <sailer@ife.ee.ethz.ch>
  6. */
  7. /* Power-Management-Code ( CONFIG_PM )
  8. * for ens1371 only ( FIXME )
  9. * derived from cs4281.c, atiixp.c and via82xx.c
  10. * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/
  11. * by Kurt J. Bosch
  12. */
  13. #include <linux/io.h>
  14. #include <linux/delay.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/init.h>
  17. #include <linux/pci.h>
  18. #include <linux/slab.h>
  19. #include <linux/gameport.h>
  20. #include <linux/module.h>
  21. #include <linux/mutex.h>
  22. #include <sound/core.h>
  23. #include <sound/control.h>
  24. #include <sound/pcm.h>
  25. #include <sound/rawmidi.h>
  26. #ifdef CHIP1371
  27. #include <sound/ac97_codec.h>
  28. #else
  29. #include <sound/ak4531_codec.h>
  30. #endif
  31. #include <sound/initval.h>
  32. #include <sound/asoundef.h>
  33. #ifndef CHIP1371
  34. #undef CHIP1370
  35. #define CHIP1370
  36. #endif
  37. #ifdef CHIP1370
  38. #define DRIVER_NAME "ENS1370"
  39. #define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */
  40. #else
  41. #define DRIVER_NAME "ENS1371"
  42. #define CHIP_NAME "ES1371"
  43. #endif
  44. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
  45. MODULE_LICENSE("GPL");
  46. #ifdef CHIP1370
  47. MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  48. MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
  49. "{Creative Labs,SB PCI64/128 (ES1370)}}");
  50. #endif
  51. #ifdef CHIP1371
  52. MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  53. MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
  54. "{Ensoniq,AudioPCI ES1373},"
  55. "{Creative Labs,Ectiva EV1938},"
  56. "{Creative Labs,SB PCI64/128 (ES1371/73)},"
  57. "{Creative Labs,Vibra PCI128},"
  58. "{Ectiva,EV1938}}");
  59. #endif
  60. #if IS_REACHABLE(CONFIG_GAMEPORT)
  61. #define SUPPORT_JOYSTICK
  62. #endif
  63. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  64. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  65. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
  66. #ifdef SUPPORT_JOYSTICK
  67. #ifdef CHIP1371
  68. static int joystick_port[SNDRV_CARDS];
  69. #else
  70. static bool joystick[SNDRV_CARDS];
  71. #endif
  72. #endif
  73. #ifdef CHIP1371
  74. static int spdif[SNDRV_CARDS];
  75. static int lineio[SNDRV_CARDS];
  76. #endif
  77. module_param_array(index, int, NULL, 0444);
  78. MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
  79. module_param_array(id, charp, NULL, 0444);
  80. MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
  81. module_param_array(enable, bool, NULL, 0444);
  82. MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
  83. #ifdef SUPPORT_JOYSTICK
  84. #ifdef CHIP1371
  85. module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
  86. MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  87. #else
  88. module_param_array(joystick, bool, NULL, 0444);
  89. MODULE_PARM_DESC(joystick, "Enable joystick.");
  90. #endif
  91. #endif /* SUPPORT_JOYSTICK */
  92. #ifdef CHIP1371
  93. module_param_array(spdif, int, NULL, 0444);
  94. MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
  95. module_param_array(lineio, int, NULL, 0444);
  96. MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
  97. #endif
  98. /* ES1371 chip ID */
  99. /* This is a little confusing because all ES1371 compatible chips have the
  100. same DEVICE_ID, the only thing differentiating them is the REV_ID field.
  101. This is only significant if you want to enable features on the later parts.
  102. Yes, I know it's stupid and why didn't we use the sub IDs?
  103. */
  104. #define ES1371REV_ES1373_A 0x04
  105. #define ES1371REV_ES1373_B 0x06
  106. #define ES1371REV_CT5880_A 0x07
  107. #define CT5880REV_CT5880_C 0x02
  108. #define CT5880REV_CT5880_D 0x03 /* ??? -jk */
  109. #define CT5880REV_CT5880_E 0x04 /* mw */
  110. #define ES1371REV_ES1371_B 0x09
  111. #define EV1938REV_EV1938_A 0x00
  112. #define ES1371REV_ES1373_8 0x08
  113. /*
  114. * Direct registers
  115. */
  116. #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
  117. #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
  118. #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
  119. #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
  120. #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
  121. #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
  122. #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
  123. #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
  124. #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
  125. #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
  126. #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
  127. #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
  128. #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
  129. #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
  130. #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
  131. #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
  132. #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
  133. #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
  134. #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
  135. #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
  136. #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
  137. #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
  138. #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
  139. #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
  140. #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
  141. #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
  142. #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
  143. #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
  144. #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
  145. #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
  146. #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
  147. #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
  148. #define ES_1371_PDLEVM (0x03<<8) /* mask for above */
  149. #define ES_BREQ (1<<7) /* memory bus request enable */
  150. #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
  151. #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
  152. #define ES_ADC_EN (1<<4) /* ADC capture channel enable */
  153. #define ES_UART_EN (1<<3) /* UART enable */
  154. #define ES_JYSTK_EN (1<<2) /* Joystick module enable */
  155. #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
  156. #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
  157. #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
  158. #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
  159. #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
  160. #define ES_INTR (1<<31) /* Interrupt is pending */
  161. #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
  162. #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
  163. #define ES_1373_REAR_BIT26 (1<<26)
  164. #define ES_1373_REAR_BIT24 (1<<24)
  165. #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
  166. #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
  167. #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
  168. #define ES_1371_TEST (1<<16) /* test ASIC */
  169. #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
  170. #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
  171. #define ES_1370_CBUSY (1<<9) /* CODEC is busy */
  172. #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
  173. #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
  174. #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
  175. #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
  176. #define ES_1371_MPWR (1<<5) /* power level interrupt pending */
  177. #define ES_MCCB (1<<4) /* CCB interrupt pending */
  178. #define ES_UART (1<<3) /* UART interrupt pending */
  179. #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
  180. #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
  181. #define ES_ADC (1<<0) /* ADC channel interrupt pending */
  182. #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
  183. #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
  184. #define ES_RXINT (1<<7) /* RX interrupt occurred */
  185. #define ES_TXINT (1<<2) /* TX interrupt occurred */
  186. #define ES_TXRDY (1<<1) /* transmitter ready */
  187. #define ES_RXRDY (1<<0) /* receiver ready */
  188. #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
  189. #define ES_RXINTEN (1<<7) /* RX interrupt enable */
  190. #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
  191. #define ES_TXINTENM (0x03<<5) /* mask for above */
  192. #define ES_TXINTENI(i) (((i)>>5)&0x03)
  193. #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
  194. #define ES_CNTRLM (0x03<<0) /* mask for above */
  195. #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
  196. #define ES_TEST_MODE (1<<0) /* test mode enabled */
  197. #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
  198. #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
  199. #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
  200. #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
  201. #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
  202. #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
  203. #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
  204. #define ES_1371_CODEC_RDY (1<<31) /* codec ready */
  205. #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
  206. #define EV_1938_CODEC_MAGIC (1<<26)
  207. #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
  208. #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
  209. #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
  210. #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
  211. #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
  212. #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
  213. #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
  214. #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
  215. #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
  216. #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
  217. #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
  218. #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
  219. #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
  220. #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
  221. #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
  222. #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
  223. #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
  224. #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
  225. #define ES_1371_JFAST (1<<31) /* fast joystick timing */
  226. #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
  227. #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
  228. #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
  229. #define ES_1371_VMPUM (0x03<<27) /* mask for above */
  230. #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
  231. #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
  232. #define ES_1371_VCDCM (0x03<<25) /* mask for above */
  233. #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
  234. #define ES_1371_FIRQ (1<<24) /* force an interrupt */
  235. #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
  236. #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
  237. #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
  238. #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
  239. #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
  240. #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
  241. #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
  242. #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
  243. #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
  244. #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
  245. #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
  246. #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
  247. #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
  248. #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
  249. #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
  250. #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
  251. #define ES_P2_END_INCM (0x07<<19) /* mask for above */
  252. #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
  253. #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
  254. #define ES_P2_ST_INCM (0x07<<16) /* mask for above */
  255. #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
  256. #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
  257. #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
  258. #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
  259. #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
  260. #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
  261. #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
  262. #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
  263. #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
  264. #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
  265. #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
  266. #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
  267. #define ES_R1_MODEM (0x03<<4) /* mask for above */
  268. #define ES_R1_MODEI(i) (((i)>>4)&0x03)
  269. #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
  270. #define ES_P2_MODEM (0x03<<2) /* mask for above */
  271. #define ES_P2_MODEI(i) (((i)>>2)&0x03)
  272. #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
  273. #define ES_P1_MODEM (0x03<<0) /* mask for above */
  274. #define ES_P1_MODEI(i) (((i)>>0)&0x03)
  275. #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
  276. #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
  277. #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
  278. #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
  279. #define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
  280. #define ES_REG_COUNTM (0xffff<<0)
  281. #define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
  282. #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
  283. #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
  284. #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
  285. #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
  286. #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
  287. #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
  288. #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
  289. #define ES_REG_FCURR_COUNTM (0xffff<<16)
  290. #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
  291. #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
  292. #define ES_REG_FSIZEM (0xffff<<0)
  293. #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
  294. #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
  295. #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
  296. #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
  297. #define ES_REG_UF_VALID (1<<8)
  298. #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
  299. #define ES_REG_UF_BYTEM (0xff<<0)
  300. #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
  301. /*
  302. * Pages
  303. */
  304. #define ES_PAGE_DAC 0x0c
  305. #define ES_PAGE_ADC 0x0d
  306. #define ES_PAGE_UART 0x0e
  307. #define ES_PAGE_UART1 0x0f
  308. /*
  309. * Sample rate converter addresses
  310. */
  311. #define ES_SMPREG_DAC1 0x70
  312. #define ES_SMPREG_DAC2 0x74
  313. #define ES_SMPREG_ADC 0x78
  314. #define ES_SMPREG_VOL_ADC 0x6c
  315. #define ES_SMPREG_VOL_DAC1 0x7c
  316. #define ES_SMPREG_VOL_DAC2 0x7e
  317. #define ES_SMPREG_TRUNC_N 0x00
  318. #define ES_SMPREG_INT_REGS 0x01
  319. #define ES_SMPREG_ACCUM_FRAC 0x02
  320. #define ES_SMPREG_VFREQ_FRAC 0x03
  321. /*
  322. * Some contants
  323. */
  324. #define ES_1370_SRCLOCK 1411200
  325. #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
  326. /*
  327. * Open modes
  328. */
  329. #define ES_MODE_PLAY1 0x0001
  330. #define ES_MODE_PLAY2 0x0002
  331. #define ES_MODE_CAPTURE 0x0004
  332. #define ES_MODE_OUTPUT 0x0001 /* for MIDI */
  333. #define ES_MODE_INPUT 0x0002 /* for MIDI */
  334. /*
  335. */
  336. struct ensoniq {
  337. spinlock_t reg_lock;
  338. struct mutex src_mutex;
  339. int irq;
  340. unsigned long playback1size;
  341. unsigned long playback2size;
  342. unsigned long capture3size;
  343. unsigned long port;
  344. unsigned int mode;
  345. unsigned int uartm; /* UART mode */
  346. unsigned int ctrl; /* control register */
  347. unsigned int sctrl; /* serial control register */
  348. unsigned int cssr; /* control status register */
  349. unsigned int uartc; /* uart control register */
  350. unsigned int rev; /* chip revision */
  351. union {
  352. #ifdef CHIP1371
  353. struct {
  354. struct snd_ac97 *ac97;
  355. } es1371;
  356. #else
  357. struct {
  358. int pclkdiv_lock;
  359. struct snd_ak4531 *ak4531;
  360. } es1370;
  361. #endif
  362. } u;
  363. struct pci_dev *pci;
  364. struct snd_card *card;
  365. struct snd_pcm *pcm1; /* DAC1/ADC PCM */
  366. struct snd_pcm *pcm2; /* DAC2 PCM */
  367. struct snd_pcm_substream *playback1_substream;
  368. struct snd_pcm_substream *playback2_substream;
  369. struct snd_pcm_substream *capture_substream;
  370. unsigned int p1_dma_size;
  371. unsigned int p2_dma_size;
  372. unsigned int c_dma_size;
  373. unsigned int p1_period_size;
  374. unsigned int p2_period_size;
  375. unsigned int c_period_size;
  376. struct snd_rawmidi *rmidi;
  377. struct snd_rawmidi_substream *midi_input;
  378. struct snd_rawmidi_substream *midi_output;
  379. unsigned int spdif;
  380. unsigned int spdif_default;
  381. unsigned int spdif_stream;
  382. #ifdef CHIP1370
  383. struct snd_dma_buffer dma_bug;
  384. #endif
  385. #ifdef SUPPORT_JOYSTICK
  386. struct gameport *gameport;
  387. #endif
  388. };
  389. static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
  390. static const struct pci_device_id snd_audiopci_ids[] = {
  391. #ifdef CHIP1370
  392. { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */
  393. #endif
  394. #ifdef CHIP1371
  395. { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */
  396. { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */
  397. { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */
  398. #endif
  399. { 0, }
  400. };
  401. MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
  402. /*
  403. * constants
  404. */
  405. #define POLL_COUNT 0xa000
  406. #ifdef CHIP1370
  407. static const unsigned int snd_es1370_fixed_rates[] =
  408. {5512, 11025, 22050, 44100};
  409. static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
  410. .count = 4,
  411. .list = snd_es1370_fixed_rates,
  412. .mask = 0,
  413. };
  414. static const struct snd_ratnum es1370_clock = {
  415. .num = ES_1370_SRCLOCK,
  416. .den_min = 29,
  417. .den_max = 353,
  418. .den_step = 1,
  419. };
  420. static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
  421. .nrats = 1,
  422. .rats = &es1370_clock,
  423. };
  424. #else
  425. static const struct snd_ratden es1371_dac_clock = {
  426. .num_min = 3000 * (1 << 15),
  427. .num_max = 48000 * (1 << 15),
  428. .num_step = 3000,
  429. .den = 1 << 15,
  430. };
  431. static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
  432. .nrats = 1,
  433. .rats = &es1371_dac_clock,
  434. };
  435. static const struct snd_ratnum es1371_adc_clock = {
  436. .num = 48000 << 15,
  437. .den_min = 32768,
  438. .den_max = 393216,
  439. .den_step = 1,
  440. };
  441. static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
  442. .nrats = 1,
  443. .rats = &es1371_adc_clock,
  444. };
  445. #endif
  446. static const unsigned int snd_ensoniq_sample_shift[] =
  447. {0, 1, 1, 2};
  448. /*
  449. * common I/O routines
  450. */
  451. #ifdef CHIP1371
  452. static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
  453. {
  454. unsigned int t, r = 0;
  455. for (t = 0; t < POLL_COUNT; t++) {
  456. r = inl(ES_REG(ensoniq, 1371_SMPRATE));
  457. if ((r & ES_1371_SRC_RAM_BUSY) == 0)
  458. return r;
  459. cond_resched();
  460. }
  461. dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n",
  462. ES_REG(ensoniq, 1371_SMPRATE), r);
  463. return 0;
  464. }
  465. static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
  466. {
  467. unsigned int temp, i, orig, r;
  468. /* wait for ready */
  469. temp = orig = snd_es1371_wait_src_ready(ensoniq);
  470. /* expose the SRC state bits */
  471. r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
  472. ES_1371_DIS_P2 | ES_1371_DIS_R1);
  473. r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
  474. outl(r, ES_REG(ensoniq, 1371_SMPRATE));
  475. /* now, wait for busy and the correct time to read */
  476. temp = snd_es1371_wait_src_ready(ensoniq);
  477. if ((temp & 0x00870000) != 0x00010000) {
  478. /* wait for the right state */
  479. for (i = 0; i < POLL_COUNT; i++) {
  480. temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
  481. if ((temp & 0x00870000) == 0x00010000)
  482. break;
  483. }
  484. }
  485. /* hide the state bits */
  486. r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
  487. ES_1371_DIS_P2 | ES_1371_DIS_R1);
  488. r |= ES_1371_SRC_RAM_ADDRO(reg);
  489. outl(r, ES_REG(ensoniq, 1371_SMPRATE));
  490. return temp;
  491. }
  492. static void snd_es1371_src_write(struct ensoniq * ensoniq,
  493. unsigned short reg, unsigned short data)
  494. {
  495. unsigned int r;
  496. r = snd_es1371_wait_src_ready(ensoniq) &
  497. (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
  498. ES_1371_DIS_P2 | ES_1371_DIS_R1);
  499. r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
  500. outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
  501. }
  502. #endif /* CHIP1371 */
  503. #ifdef CHIP1370
  504. static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
  505. unsigned short reg, unsigned short val)
  506. {
  507. struct ensoniq *ensoniq = ak4531->private_data;
  508. unsigned long end_time = jiffies + HZ / 10;
  509. #if 0
  510. dev_dbg(ensoniq->card->dev,
  511. "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
  512. reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
  513. #endif
  514. do {
  515. if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
  516. outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
  517. return;
  518. }
  519. schedule_timeout_uninterruptible(1);
  520. } while (time_after(end_time, jiffies));
  521. dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n",
  522. inl(ES_REG(ensoniq, STATUS)));
  523. }
  524. #endif /* CHIP1370 */
  525. #ifdef CHIP1371
  526. static inline bool is_ev1938(struct ensoniq *ensoniq)
  527. {
  528. return ensoniq->pci->device == 0x8938;
  529. }
  530. static void snd_es1371_codec_write(struct snd_ac97 *ac97,
  531. unsigned short reg, unsigned short val)
  532. {
  533. struct ensoniq *ensoniq = ac97->private_data;
  534. unsigned int t, x, flag;
  535. flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
  536. mutex_lock(&ensoniq->src_mutex);
  537. for (t = 0; t < POLL_COUNT; t++) {
  538. if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
  539. /* save the current state for latter */
  540. x = snd_es1371_wait_src_ready(ensoniq);
  541. outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
  542. ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
  543. ES_REG(ensoniq, 1371_SMPRATE));
  544. /* wait for not busy (state 0) first to avoid
  545. transition states */
  546. for (t = 0; t < POLL_COUNT; t++) {
  547. if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
  548. 0x00000000)
  549. break;
  550. }
  551. /* wait for a SAFE time to write addr/data and then do it, dammit */
  552. for (t = 0; t < POLL_COUNT; t++) {
  553. if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
  554. 0x00010000)
  555. break;
  556. }
  557. outl(ES_1371_CODEC_WRITE(reg, val) | flag,
  558. ES_REG(ensoniq, 1371_CODEC));
  559. /* restore SRC reg */
  560. snd_es1371_wait_src_ready(ensoniq);
  561. outl(x, ES_REG(ensoniq, 1371_SMPRATE));
  562. mutex_unlock(&ensoniq->src_mutex);
  563. return;
  564. }
  565. }
  566. mutex_unlock(&ensoniq->src_mutex);
  567. dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n",
  568. ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
  569. }
  570. static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
  571. unsigned short reg)
  572. {
  573. struct ensoniq *ensoniq = ac97->private_data;
  574. unsigned int t, x, flag, fail = 0;
  575. flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
  576. __again:
  577. mutex_lock(&ensoniq->src_mutex);
  578. for (t = 0; t < POLL_COUNT; t++) {
  579. if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
  580. /* save the current state for latter */
  581. x = snd_es1371_wait_src_ready(ensoniq);
  582. outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
  583. ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
  584. ES_REG(ensoniq, 1371_SMPRATE));
  585. /* wait for not busy (state 0) first to avoid
  586. transition states */
  587. for (t = 0; t < POLL_COUNT; t++) {
  588. if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
  589. 0x00000000)
  590. break;
  591. }
  592. /* wait for a SAFE time to write addr/data and then do it, dammit */
  593. for (t = 0; t < POLL_COUNT; t++) {
  594. if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
  595. 0x00010000)
  596. break;
  597. }
  598. outl(ES_1371_CODEC_READS(reg) | flag,
  599. ES_REG(ensoniq, 1371_CODEC));
  600. /* restore SRC reg */
  601. snd_es1371_wait_src_ready(ensoniq);
  602. outl(x, ES_REG(ensoniq, 1371_SMPRATE));
  603. /* wait for WIP again */
  604. for (t = 0; t < POLL_COUNT; t++) {
  605. if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
  606. break;
  607. }
  608. /* now wait for the stinkin' data (RDY) */
  609. for (t = 0; t < POLL_COUNT; t++) {
  610. if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
  611. if (is_ev1938(ensoniq)) {
  612. for (t = 0; t < 100; t++)
  613. inl(ES_REG(ensoniq, CONTROL));
  614. x = inl(ES_REG(ensoniq, 1371_CODEC));
  615. }
  616. mutex_unlock(&ensoniq->src_mutex);
  617. return ES_1371_CODEC_READ(x);
  618. }
  619. }
  620. mutex_unlock(&ensoniq->src_mutex);
  621. if (++fail > 10) {
  622. dev_err(ensoniq->card->dev,
  623. "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n",
  624. ES_REG(ensoniq, 1371_CODEC), reg,
  625. inl(ES_REG(ensoniq, 1371_CODEC)));
  626. return 0;
  627. }
  628. goto __again;
  629. }
  630. }
  631. mutex_unlock(&ensoniq->src_mutex);
  632. dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n",
  633. ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
  634. return 0;
  635. }
  636. static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
  637. {
  638. msleep(750);
  639. snd_es1371_codec_read(ac97, AC97_RESET);
  640. snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
  641. snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
  642. msleep(50);
  643. }
  644. static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
  645. {
  646. unsigned int n, truncm, freq;
  647. mutex_lock(&ensoniq->src_mutex);
  648. n = rate / 3000;
  649. if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
  650. n--;
  651. truncm = (21 * n - 1) | 1;
  652. freq = ((48000UL << 15) / rate) * n;
  653. if (rate >= 24000) {
  654. if (truncm > 239)
  655. truncm = 239;
  656. snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
  657. (((239 - truncm) >> 1) << 9) | (n << 4));
  658. } else {
  659. if (truncm > 119)
  660. truncm = 119;
  661. snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
  662. 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
  663. }
  664. snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
  665. (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
  666. ES_SMPREG_INT_REGS) & 0x00ff) |
  667. ((freq >> 5) & 0xfc00));
  668. snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
  669. snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
  670. snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
  671. mutex_unlock(&ensoniq->src_mutex);
  672. }
  673. static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
  674. {
  675. unsigned int freq, r;
  676. mutex_lock(&ensoniq->src_mutex);
  677. freq = ((rate << 15) + 1500) / 3000;
  678. r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
  679. ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
  680. ES_1371_DIS_P1;
  681. outl(r, ES_REG(ensoniq, 1371_SMPRATE));
  682. snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
  683. (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
  684. ES_SMPREG_INT_REGS) & 0x00ff) |
  685. ((freq >> 5) & 0xfc00));
  686. snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
  687. r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
  688. ES_1371_DIS_P2 | ES_1371_DIS_R1));
  689. outl(r, ES_REG(ensoniq, 1371_SMPRATE));
  690. mutex_unlock(&ensoniq->src_mutex);
  691. }
  692. static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
  693. {
  694. unsigned int freq, r;
  695. mutex_lock(&ensoniq->src_mutex);
  696. freq = ((rate << 15) + 1500) / 3000;
  697. r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
  698. ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
  699. ES_1371_DIS_P2;
  700. outl(r, ES_REG(ensoniq, 1371_SMPRATE));
  701. snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
  702. (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
  703. ES_SMPREG_INT_REGS) & 0x00ff) |
  704. ((freq >> 5) & 0xfc00));
  705. snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
  706. freq & 0x7fff);
  707. r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
  708. ES_1371_DIS_P1 | ES_1371_DIS_R1));
  709. outl(r, ES_REG(ensoniq, 1371_SMPRATE));
  710. mutex_unlock(&ensoniq->src_mutex);
  711. }
  712. #endif /* CHIP1371 */
  713. static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
  714. {
  715. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  716. switch (cmd) {
  717. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  718. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  719. {
  720. unsigned int what = 0;
  721. struct snd_pcm_substream *s;
  722. snd_pcm_group_for_each_entry(s, substream) {
  723. if (s == ensoniq->playback1_substream) {
  724. what |= ES_P1_PAUSE;
  725. snd_pcm_trigger_done(s, substream);
  726. } else if (s == ensoniq->playback2_substream) {
  727. what |= ES_P2_PAUSE;
  728. snd_pcm_trigger_done(s, substream);
  729. } else if (s == ensoniq->capture_substream)
  730. return -EINVAL;
  731. }
  732. spin_lock(&ensoniq->reg_lock);
  733. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  734. ensoniq->sctrl |= what;
  735. else
  736. ensoniq->sctrl &= ~what;
  737. outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
  738. spin_unlock(&ensoniq->reg_lock);
  739. break;
  740. }
  741. case SNDRV_PCM_TRIGGER_START:
  742. case SNDRV_PCM_TRIGGER_STOP:
  743. {
  744. unsigned int what = 0;
  745. struct snd_pcm_substream *s;
  746. snd_pcm_group_for_each_entry(s, substream) {
  747. if (s == ensoniq->playback1_substream) {
  748. what |= ES_DAC1_EN;
  749. snd_pcm_trigger_done(s, substream);
  750. } else if (s == ensoniq->playback2_substream) {
  751. what |= ES_DAC2_EN;
  752. snd_pcm_trigger_done(s, substream);
  753. } else if (s == ensoniq->capture_substream) {
  754. what |= ES_ADC_EN;
  755. snd_pcm_trigger_done(s, substream);
  756. }
  757. }
  758. spin_lock(&ensoniq->reg_lock);
  759. if (cmd == SNDRV_PCM_TRIGGER_START)
  760. ensoniq->ctrl |= what;
  761. else
  762. ensoniq->ctrl &= ~what;
  763. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  764. spin_unlock(&ensoniq->reg_lock);
  765. break;
  766. }
  767. default:
  768. return -EINVAL;
  769. }
  770. return 0;
  771. }
  772. /*
  773. * PCM part
  774. */
  775. static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
  776. {
  777. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  778. struct snd_pcm_runtime *runtime = substream->runtime;
  779. unsigned int mode = 0;
  780. ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
  781. ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
  782. if (snd_pcm_format_width(runtime->format) == 16)
  783. mode |= 0x02;
  784. if (runtime->channels > 1)
  785. mode |= 0x01;
  786. spin_lock_irq(&ensoniq->reg_lock);
  787. ensoniq->ctrl &= ~ES_DAC1_EN;
  788. #ifdef CHIP1371
  789. /* 48k doesn't need SRC (it breaks AC3-passthru) */
  790. if (runtime->rate == 48000)
  791. ensoniq->ctrl |= ES_1373_BYPASS_P1;
  792. else
  793. ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
  794. #endif
  795. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  796. outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
  797. outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
  798. outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
  799. ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
  800. ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
  801. outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
  802. outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
  803. ES_REG(ensoniq, DAC1_COUNT));
  804. #ifdef CHIP1370
  805. ensoniq->ctrl &= ~ES_1370_WTSRSELM;
  806. switch (runtime->rate) {
  807. case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
  808. case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
  809. case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
  810. case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
  811. default: snd_BUG();
  812. }
  813. #endif
  814. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  815. spin_unlock_irq(&ensoniq->reg_lock);
  816. #ifndef CHIP1370
  817. snd_es1371_dac1_rate(ensoniq, runtime->rate);
  818. #endif
  819. return 0;
  820. }
  821. static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
  822. {
  823. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  824. struct snd_pcm_runtime *runtime = substream->runtime;
  825. unsigned int mode = 0;
  826. ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
  827. ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
  828. if (snd_pcm_format_width(runtime->format) == 16)
  829. mode |= 0x02;
  830. if (runtime->channels > 1)
  831. mode |= 0x01;
  832. spin_lock_irq(&ensoniq->reg_lock);
  833. ensoniq->ctrl &= ~ES_DAC2_EN;
  834. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  835. outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
  836. outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
  837. outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
  838. ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
  839. ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
  840. ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
  841. ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
  842. outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
  843. outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
  844. ES_REG(ensoniq, DAC2_COUNT));
  845. #ifdef CHIP1370
  846. if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
  847. ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
  848. ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
  849. ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
  850. }
  851. #endif
  852. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  853. spin_unlock_irq(&ensoniq->reg_lock);
  854. #ifndef CHIP1370
  855. snd_es1371_dac2_rate(ensoniq, runtime->rate);
  856. #endif
  857. return 0;
  858. }
  859. static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
  860. {
  861. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  862. struct snd_pcm_runtime *runtime = substream->runtime;
  863. unsigned int mode = 0;
  864. ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
  865. ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
  866. if (snd_pcm_format_width(runtime->format) == 16)
  867. mode |= 0x02;
  868. if (runtime->channels > 1)
  869. mode |= 0x01;
  870. spin_lock_irq(&ensoniq->reg_lock);
  871. ensoniq->ctrl &= ~ES_ADC_EN;
  872. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  873. outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
  874. outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
  875. outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
  876. ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
  877. ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
  878. outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
  879. outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
  880. ES_REG(ensoniq, ADC_COUNT));
  881. #ifdef CHIP1370
  882. if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
  883. ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
  884. ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
  885. ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
  886. }
  887. #endif
  888. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  889. spin_unlock_irq(&ensoniq->reg_lock);
  890. #ifndef CHIP1370
  891. snd_es1371_adc_rate(ensoniq, runtime->rate);
  892. #endif
  893. return 0;
  894. }
  895. static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
  896. {
  897. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  898. size_t ptr;
  899. spin_lock(&ensoniq->reg_lock);
  900. if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
  901. outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
  902. ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
  903. ptr = bytes_to_frames(substream->runtime, ptr);
  904. } else {
  905. ptr = 0;
  906. }
  907. spin_unlock(&ensoniq->reg_lock);
  908. return ptr;
  909. }
  910. static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
  911. {
  912. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  913. size_t ptr;
  914. spin_lock(&ensoniq->reg_lock);
  915. if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
  916. outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
  917. ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
  918. ptr = bytes_to_frames(substream->runtime, ptr);
  919. } else {
  920. ptr = 0;
  921. }
  922. spin_unlock(&ensoniq->reg_lock);
  923. return ptr;
  924. }
  925. static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
  926. {
  927. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  928. size_t ptr;
  929. spin_lock(&ensoniq->reg_lock);
  930. if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
  931. outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
  932. ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
  933. ptr = bytes_to_frames(substream->runtime, ptr);
  934. } else {
  935. ptr = 0;
  936. }
  937. spin_unlock(&ensoniq->reg_lock);
  938. return ptr;
  939. }
  940. static const struct snd_pcm_hardware snd_ensoniq_playback1 =
  941. {
  942. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  943. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  944. SNDRV_PCM_INFO_MMAP_VALID |
  945. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  946. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  947. .rates =
  948. #ifndef CHIP1370
  949. SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  950. #else
  951. (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
  952. SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
  953. SNDRV_PCM_RATE_44100),
  954. #endif
  955. .rate_min = 4000,
  956. .rate_max = 48000,
  957. .channels_min = 1,
  958. .channels_max = 2,
  959. .buffer_bytes_max = (128*1024),
  960. .period_bytes_min = 64,
  961. .period_bytes_max = (128*1024),
  962. .periods_min = 1,
  963. .periods_max = 1024,
  964. .fifo_size = 0,
  965. };
  966. static const struct snd_pcm_hardware snd_ensoniq_playback2 =
  967. {
  968. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  969. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  970. SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
  971. SNDRV_PCM_INFO_SYNC_START),
  972. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  973. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  974. .rate_min = 4000,
  975. .rate_max = 48000,
  976. .channels_min = 1,
  977. .channels_max = 2,
  978. .buffer_bytes_max = (128*1024),
  979. .period_bytes_min = 64,
  980. .period_bytes_max = (128*1024),
  981. .periods_min = 1,
  982. .periods_max = 1024,
  983. .fifo_size = 0,
  984. };
  985. static const struct snd_pcm_hardware snd_ensoniq_capture =
  986. {
  987. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  988. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  989. SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
  990. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  991. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  992. .rate_min = 4000,
  993. .rate_max = 48000,
  994. .channels_min = 1,
  995. .channels_max = 2,
  996. .buffer_bytes_max = (128*1024),
  997. .period_bytes_min = 64,
  998. .period_bytes_max = (128*1024),
  999. .periods_min = 1,
  1000. .periods_max = 1024,
  1001. .fifo_size = 0,
  1002. };
  1003. static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
  1004. {
  1005. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  1006. struct snd_pcm_runtime *runtime = substream->runtime;
  1007. ensoniq->mode |= ES_MODE_PLAY1;
  1008. ensoniq->playback1_substream = substream;
  1009. runtime->hw = snd_ensoniq_playback1;
  1010. snd_pcm_set_sync(substream);
  1011. spin_lock_irq(&ensoniq->reg_lock);
  1012. if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
  1013. ensoniq->spdif_stream = ensoniq->spdif_default;
  1014. spin_unlock_irq(&ensoniq->reg_lock);
  1015. #ifdef CHIP1370
  1016. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1017. &snd_es1370_hw_constraints_rates);
  1018. #else
  1019. snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1020. &snd_es1371_hw_constraints_dac_clock);
  1021. #endif
  1022. return 0;
  1023. }
  1024. static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
  1025. {
  1026. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  1027. struct snd_pcm_runtime *runtime = substream->runtime;
  1028. ensoniq->mode |= ES_MODE_PLAY2;
  1029. ensoniq->playback2_substream = substream;
  1030. runtime->hw = snd_ensoniq_playback2;
  1031. snd_pcm_set_sync(substream);
  1032. spin_lock_irq(&ensoniq->reg_lock);
  1033. if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
  1034. ensoniq->spdif_stream = ensoniq->spdif_default;
  1035. spin_unlock_irq(&ensoniq->reg_lock);
  1036. #ifdef CHIP1370
  1037. snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1038. &snd_es1370_hw_constraints_clock);
  1039. #else
  1040. snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1041. &snd_es1371_hw_constraints_dac_clock);
  1042. #endif
  1043. return 0;
  1044. }
  1045. static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
  1046. {
  1047. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  1048. struct snd_pcm_runtime *runtime = substream->runtime;
  1049. ensoniq->mode |= ES_MODE_CAPTURE;
  1050. ensoniq->capture_substream = substream;
  1051. runtime->hw = snd_ensoniq_capture;
  1052. snd_pcm_set_sync(substream);
  1053. #ifdef CHIP1370
  1054. snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1055. &snd_es1370_hw_constraints_clock);
  1056. #else
  1057. snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1058. &snd_es1371_hw_constraints_adc_clock);
  1059. #endif
  1060. return 0;
  1061. }
  1062. static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
  1063. {
  1064. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  1065. ensoniq->playback1_substream = NULL;
  1066. ensoniq->mode &= ~ES_MODE_PLAY1;
  1067. return 0;
  1068. }
  1069. static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
  1070. {
  1071. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  1072. ensoniq->playback2_substream = NULL;
  1073. spin_lock_irq(&ensoniq->reg_lock);
  1074. #ifdef CHIP1370
  1075. ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
  1076. #endif
  1077. ensoniq->mode &= ~ES_MODE_PLAY2;
  1078. spin_unlock_irq(&ensoniq->reg_lock);
  1079. return 0;
  1080. }
  1081. static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
  1082. {
  1083. struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
  1084. ensoniq->capture_substream = NULL;
  1085. spin_lock_irq(&ensoniq->reg_lock);
  1086. #ifdef CHIP1370
  1087. ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
  1088. #endif
  1089. ensoniq->mode &= ~ES_MODE_CAPTURE;
  1090. spin_unlock_irq(&ensoniq->reg_lock);
  1091. return 0;
  1092. }
  1093. static const struct snd_pcm_ops snd_ensoniq_playback1_ops = {
  1094. .open = snd_ensoniq_playback1_open,
  1095. .close = snd_ensoniq_playback1_close,
  1096. .prepare = snd_ensoniq_playback1_prepare,
  1097. .trigger = snd_ensoniq_trigger,
  1098. .pointer = snd_ensoniq_playback1_pointer,
  1099. };
  1100. static const struct snd_pcm_ops snd_ensoniq_playback2_ops = {
  1101. .open = snd_ensoniq_playback2_open,
  1102. .close = snd_ensoniq_playback2_close,
  1103. .prepare = snd_ensoniq_playback2_prepare,
  1104. .trigger = snd_ensoniq_trigger,
  1105. .pointer = snd_ensoniq_playback2_pointer,
  1106. };
  1107. static const struct snd_pcm_ops snd_ensoniq_capture_ops = {
  1108. .open = snd_ensoniq_capture_open,
  1109. .close = snd_ensoniq_capture_close,
  1110. .prepare = snd_ensoniq_capture_prepare,
  1111. .trigger = snd_ensoniq_trigger,
  1112. .pointer = snd_ensoniq_capture_pointer,
  1113. };
  1114. static const struct snd_pcm_chmap_elem surround_map[] = {
  1115. { .channels = 1,
  1116. .map = { SNDRV_CHMAP_MONO } },
  1117. { .channels = 2,
  1118. .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
  1119. { }
  1120. };
  1121. static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device)
  1122. {
  1123. struct snd_pcm *pcm;
  1124. int err;
  1125. err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm);
  1126. if (err < 0)
  1127. return err;
  1128. #ifdef CHIP1370
  1129. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
  1130. #else
  1131. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
  1132. #endif
  1133. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
  1134. pcm->private_data = ensoniq;
  1135. pcm->info_flags = 0;
  1136. strcpy(pcm->name, CHIP_NAME " DAC2/ADC");
  1137. ensoniq->pcm1 = pcm;
  1138. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1139. &ensoniq->pci->dev, 64*1024, 128*1024);
  1140. #ifdef CHIP1370
  1141. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1142. surround_map, 2, 0, NULL);
  1143. #else
  1144. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1145. snd_pcm_std_chmaps, 2, 0, NULL);
  1146. #endif
  1147. return err;
  1148. }
  1149. static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device)
  1150. {
  1151. struct snd_pcm *pcm;
  1152. int err;
  1153. err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm);
  1154. if (err < 0)
  1155. return err;
  1156. #ifdef CHIP1370
  1157. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
  1158. #else
  1159. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
  1160. #endif
  1161. pcm->private_data = ensoniq;
  1162. pcm->info_flags = 0;
  1163. strcpy(pcm->name, CHIP_NAME " DAC1");
  1164. ensoniq->pcm2 = pcm;
  1165. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1166. &ensoniq->pci->dev, 64*1024, 128*1024);
  1167. #ifdef CHIP1370
  1168. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1169. snd_pcm_std_chmaps, 2, 0, NULL);
  1170. #else
  1171. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1172. surround_map, 2, 0, NULL);
  1173. #endif
  1174. return err;
  1175. }
  1176. /*
  1177. * Mixer section
  1178. */
  1179. /*
  1180. * ENS1371 mixer (including SPDIF interface)
  1181. */
  1182. #ifdef CHIP1371
  1183. static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
  1184. struct snd_ctl_elem_info *uinfo)
  1185. {
  1186. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1187. uinfo->count = 1;
  1188. return 0;
  1189. }
  1190. static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
  1191. struct snd_ctl_elem_value *ucontrol)
  1192. {
  1193. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1194. spin_lock_irq(&ensoniq->reg_lock);
  1195. ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
  1196. ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
  1197. ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
  1198. ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
  1199. spin_unlock_irq(&ensoniq->reg_lock);
  1200. return 0;
  1201. }
  1202. static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
  1203. struct snd_ctl_elem_value *ucontrol)
  1204. {
  1205. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1206. unsigned int val;
  1207. int change;
  1208. val = ((u32)ucontrol->value.iec958.status[0] << 0) |
  1209. ((u32)ucontrol->value.iec958.status[1] << 8) |
  1210. ((u32)ucontrol->value.iec958.status[2] << 16) |
  1211. ((u32)ucontrol->value.iec958.status[3] << 24);
  1212. spin_lock_irq(&ensoniq->reg_lock);
  1213. change = ensoniq->spdif_default != val;
  1214. ensoniq->spdif_default = val;
  1215. if (change && ensoniq->playback1_substream == NULL &&
  1216. ensoniq->playback2_substream == NULL)
  1217. outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
  1218. spin_unlock_irq(&ensoniq->reg_lock);
  1219. return change;
  1220. }
  1221. static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1222. struct snd_ctl_elem_value *ucontrol)
  1223. {
  1224. ucontrol->value.iec958.status[0] = 0xff;
  1225. ucontrol->value.iec958.status[1] = 0xff;
  1226. ucontrol->value.iec958.status[2] = 0xff;
  1227. ucontrol->value.iec958.status[3] = 0xff;
  1228. return 0;
  1229. }
  1230. static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1231. struct snd_ctl_elem_value *ucontrol)
  1232. {
  1233. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1234. spin_lock_irq(&ensoniq->reg_lock);
  1235. ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
  1236. ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
  1237. ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
  1238. ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
  1239. spin_unlock_irq(&ensoniq->reg_lock);
  1240. return 0;
  1241. }
  1242. static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1243. struct snd_ctl_elem_value *ucontrol)
  1244. {
  1245. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1246. unsigned int val;
  1247. int change;
  1248. val = ((u32)ucontrol->value.iec958.status[0] << 0) |
  1249. ((u32)ucontrol->value.iec958.status[1] << 8) |
  1250. ((u32)ucontrol->value.iec958.status[2] << 16) |
  1251. ((u32)ucontrol->value.iec958.status[3] << 24);
  1252. spin_lock_irq(&ensoniq->reg_lock);
  1253. change = ensoniq->spdif_stream != val;
  1254. ensoniq->spdif_stream = val;
  1255. if (change && (ensoniq->playback1_substream != NULL ||
  1256. ensoniq->playback2_substream != NULL))
  1257. outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
  1258. spin_unlock_irq(&ensoniq->reg_lock);
  1259. return change;
  1260. }
  1261. #define ES1371_SPDIF(xname) \
  1262. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
  1263. .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
  1264. #define snd_es1371_spdif_info snd_ctl_boolean_mono_info
  1265. static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
  1266. struct snd_ctl_elem_value *ucontrol)
  1267. {
  1268. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1269. spin_lock_irq(&ensoniq->reg_lock);
  1270. ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
  1271. spin_unlock_irq(&ensoniq->reg_lock);
  1272. return 0;
  1273. }
  1274. static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
  1275. struct snd_ctl_elem_value *ucontrol)
  1276. {
  1277. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1278. unsigned int nval1, nval2;
  1279. int change;
  1280. nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
  1281. nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
  1282. spin_lock_irq(&ensoniq->reg_lock);
  1283. change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
  1284. ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
  1285. ensoniq->ctrl |= nval1;
  1286. ensoniq->cssr &= ~ES_1373_SPDIF_EN;
  1287. ensoniq->cssr |= nval2;
  1288. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  1289. outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
  1290. spin_unlock_irq(&ensoniq->reg_lock);
  1291. return change;
  1292. }
  1293. /* spdif controls */
  1294. static const struct snd_kcontrol_new snd_es1371_mixer_spdif[] = {
  1295. ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
  1296. {
  1297. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1298. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1299. .info = snd_ens1373_spdif_info,
  1300. .get = snd_ens1373_spdif_default_get,
  1301. .put = snd_ens1373_spdif_default_put,
  1302. },
  1303. {
  1304. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1305. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1306. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
  1307. .info = snd_ens1373_spdif_info,
  1308. .get = snd_ens1373_spdif_mask_get
  1309. },
  1310. {
  1311. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1312. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1313. .info = snd_ens1373_spdif_info,
  1314. .get = snd_ens1373_spdif_stream_get,
  1315. .put = snd_ens1373_spdif_stream_put
  1316. },
  1317. };
  1318. #define snd_es1373_rear_info snd_ctl_boolean_mono_info
  1319. static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
  1320. struct snd_ctl_elem_value *ucontrol)
  1321. {
  1322. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1323. int val = 0;
  1324. spin_lock_irq(&ensoniq->reg_lock);
  1325. if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
  1326. ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
  1327. val = 1;
  1328. ucontrol->value.integer.value[0] = val;
  1329. spin_unlock_irq(&ensoniq->reg_lock);
  1330. return 0;
  1331. }
  1332. static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
  1333. struct snd_ctl_elem_value *ucontrol)
  1334. {
  1335. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1336. unsigned int nval1;
  1337. int change;
  1338. nval1 = ucontrol->value.integer.value[0] ?
  1339. ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
  1340. spin_lock_irq(&ensoniq->reg_lock);
  1341. change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
  1342. ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
  1343. ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
  1344. ensoniq->cssr |= nval1;
  1345. outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
  1346. spin_unlock_irq(&ensoniq->reg_lock);
  1347. return change;
  1348. }
  1349. static const struct snd_kcontrol_new snd_ens1373_rear =
  1350. {
  1351. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1352. .name = "AC97 2ch->4ch Copy Switch",
  1353. .info = snd_es1373_rear_info,
  1354. .get = snd_es1373_rear_get,
  1355. .put = snd_es1373_rear_put,
  1356. };
  1357. #define snd_es1373_line_info snd_ctl_boolean_mono_info
  1358. static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
  1359. struct snd_ctl_elem_value *ucontrol)
  1360. {
  1361. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1362. int val = 0;
  1363. spin_lock_irq(&ensoniq->reg_lock);
  1364. if (ensoniq->ctrl & ES_1371_GPIO_OUT(4))
  1365. val = 1;
  1366. ucontrol->value.integer.value[0] = val;
  1367. spin_unlock_irq(&ensoniq->reg_lock);
  1368. return 0;
  1369. }
  1370. static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
  1371. struct snd_ctl_elem_value *ucontrol)
  1372. {
  1373. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1374. int changed;
  1375. unsigned int ctrl;
  1376. spin_lock_irq(&ensoniq->reg_lock);
  1377. ctrl = ensoniq->ctrl;
  1378. if (ucontrol->value.integer.value[0])
  1379. ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
  1380. else
  1381. ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
  1382. changed = (ctrl != ensoniq->ctrl);
  1383. if (changed)
  1384. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  1385. spin_unlock_irq(&ensoniq->reg_lock);
  1386. return changed;
  1387. }
  1388. static const struct snd_kcontrol_new snd_ens1373_line =
  1389. {
  1390. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1391. .name = "Line In->Rear Out Switch",
  1392. .info = snd_es1373_line_info,
  1393. .get = snd_es1373_line_get,
  1394. .put = snd_es1373_line_put,
  1395. };
  1396. static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
  1397. {
  1398. struct ensoniq *ensoniq = ac97->private_data;
  1399. ensoniq->u.es1371.ac97 = NULL;
  1400. }
  1401. struct es1371_quirk {
  1402. unsigned short vid; /* vendor ID */
  1403. unsigned short did; /* device ID */
  1404. unsigned char rev; /* revision */
  1405. };
  1406. static int es1371_quirk_lookup(struct ensoniq *ensoniq,
  1407. const struct es1371_quirk *list)
  1408. {
  1409. while (list->vid != (unsigned short)PCI_ANY_ID) {
  1410. if (ensoniq->pci->vendor == list->vid &&
  1411. ensoniq->pci->device == list->did &&
  1412. ensoniq->rev == list->rev)
  1413. return 1;
  1414. list++;
  1415. }
  1416. return 0;
  1417. }
  1418. static const struct es1371_quirk es1371_spdif_present[] = {
  1419. { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
  1420. { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
  1421. { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
  1422. { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
  1423. { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
  1424. { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
  1425. };
  1426. static const struct snd_pci_quirk ens1373_line_quirk[] = {
  1427. SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
  1428. SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
  1429. { } /* end */
  1430. };
  1431. static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
  1432. int has_spdif, int has_line)
  1433. {
  1434. struct snd_card *card = ensoniq->card;
  1435. struct snd_ac97_bus *pbus;
  1436. struct snd_ac97_template ac97;
  1437. int err;
  1438. static const struct snd_ac97_bus_ops ops = {
  1439. .write = snd_es1371_codec_write,
  1440. .read = snd_es1371_codec_read,
  1441. .wait = snd_es1371_codec_wait,
  1442. };
  1443. if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
  1444. return err;
  1445. memset(&ac97, 0, sizeof(ac97));
  1446. ac97.private_data = ensoniq;
  1447. ac97.private_free = snd_ensoniq_mixer_free_ac97;
  1448. ac97.pci = ensoniq->pci;
  1449. ac97.scaps = AC97_SCAP_AUDIO;
  1450. if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
  1451. return err;
  1452. if (has_spdif > 0 ||
  1453. (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
  1454. struct snd_kcontrol *kctl;
  1455. int i, is_spdif = 0;
  1456. ensoniq->spdif_default = ensoniq->spdif_stream =
  1457. SNDRV_PCM_DEFAULT_CON_SPDIF;
  1458. outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
  1459. if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
  1460. is_spdif++;
  1461. for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
  1462. kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
  1463. if (!kctl)
  1464. return -ENOMEM;
  1465. kctl->id.index = is_spdif;
  1466. err = snd_ctl_add(card, kctl);
  1467. if (err < 0)
  1468. return err;
  1469. }
  1470. }
  1471. if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
  1472. /* mirror rear to front speakers */
  1473. ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
  1474. ensoniq->cssr |= ES_1373_REAR_BIT26;
  1475. err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
  1476. if (err < 0)
  1477. return err;
  1478. }
  1479. if (has_line > 0 ||
  1480. snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
  1481. err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
  1482. ensoniq));
  1483. if (err < 0)
  1484. return err;
  1485. }
  1486. return 0;
  1487. }
  1488. #endif /* CHIP1371 */
  1489. /* generic control callbacks for ens1370 */
  1490. #ifdef CHIP1370
  1491. #define ENSONIQ_CONTROL(xname, mask) \
  1492. { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
  1493. .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
  1494. .private_value = mask }
  1495. #define snd_ensoniq_control_info snd_ctl_boolean_mono_info
  1496. static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
  1497. struct snd_ctl_elem_value *ucontrol)
  1498. {
  1499. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1500. int mask = kcontrol->private_value;
  1501. spin_lock_irq(&ensoniq->reg_lock);
  1502. ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
  1503. spin_unlock_irq(&ensoniq->reg_lock);
  1504. return 0;
  1505. }
  1506. static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
  1507. struct snd_ctl_elem_value *ucontrol)
  1508. {
  1509. struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
  1510. int mask = kcontrol->private_value;
  1511. unsigned int nval;
  1512. int change;
  1513. nval = ucontrol->value.integer.value[0] ? mask : 0;
  1514. spin_lock_irq(&ensoniq->reg_lock);
  1515. change = (ensoniq->ctrl & mask) != nval;
  1516. ensoniq->ctrl &= ~mask;
  1517. ensoniq->ctrl |= nval;
  1518. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  1519. spin_unlock_irq(&ensoniq->reg_lock);
  1520. return change;
  1521. }
  1522. /*
  1523. * ENS1370 mixer
  1524. */
  1525. static const struct snd_kcontrol_new snd_es1370_controls[2] = {
  1526. ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
  1527. ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
  1528. };
  1529. #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
  1530. static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
  1531. {
  1532. struct ensoniq *ensoniq = ak4531->private_data;
  1533. ensoniq->u.es1370.ak4531 = NULL;
  1534. }
  1535. static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq)
  1536. {
  1537. struct snd_card *card = ensoniq->card;
  1538. struct snd_ak4531 ak4531;
  1539. unsigned int idx;
  1540. int err;
  1541. /* try reset AK4531 */
  1542. outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
  1543. inw(ES_REG(ensoniq, 1370_CODEC));
  1544. udelay(100);
  1545. outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
  1546. inw(ES_REG(ensoniq, 1370_CODEC));
  1547. udelay(100);
  1548. memset(&ak4531, 0, sizeof(ak4531));
  1549. ak4531.write = snd_es1370_codec_write;
  1550. ak4531.private_data = ensoniq;
  1551. ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
  1552. if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
  1553. return err;
  1554. for (idx = 0; idx < ES1370_CONTROLS; idx++) {
  1555. err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
  1556. if (err < 0)
  1557. return err;
  1558. }
  1559. return 0;
  1560. }
  1561. #endif /* CHIP1370 */
  1562. #ifdef SUPPORT_JOYSTICK
  1563. #ifdef CHIP1371
  1564. static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
  1565. {
  1566. switch (joystick_port[dev]) {
  1567. case 0: /* disabled */
  1568. case 1: /* auto-detect */
  1569. case 0x200:
  1570. case 0x208:
  1571. case 0x210:
  1572. case 0x218:
  1573. return joystick_port[dev];
  1574. default:
  1575. dev_err(ensoniq->card->dev,
  1576. "invalid joystick port %#x", joystick_port[dev]);
  1577. return 0;
  1578. }
  1579. }
  1580. #else
  1581. static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
  1582. {
  1583. return joystick[dev] ? 0x200 : 0;
  1584. }
  1585. #endif
  1586. static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
  1587. {
  1588. struct gameport *gp;
  1589. int io_port;
  1590. io_port = snd_ensoniq_get_joystick_port(ensoniq, dev);
  1591. switch (io_port) {
  1592. case 0:
  1593. return -ENOSYS;
  1594. case 1: /* auto_detect */
  1595. for (io_port = 0x200; io_port <= 0x218; io_port += 8)
  1596. if (request_region(io_port, 8, "ens137x: gameport"))
  1597. break;
  1598. if (io_port > 0x218) {
  1599. dev_warn(ensoniq->card->dev,
  1600. "no gameport ports available\n");
  1601. return -EBUSY;
  1602. }
  1603. break;
  1604. default:
  1605. if (!request_region(io_port, 8, "ens137x: gameport")) {
  1606. dev_warn(ensoniq->card->dev,
  1607. "gameport io port %#x in use\n",
  1608. io_port);
  1609. return -EBUSY;
  1610. }
  1611. break;
  1612. }
  1613. ensoniq->gameport = gp = gameport_allocate_port();
  1614. if (!gp) {
  1615. dev_err(ensoniq->card->dev,
  1616. "cannot allocate memory for gameport\n");
  1617. release_region(io_port, 8);
  1618. return -ENOMEM;
  1619. }
  1620. gameport_set_name(gp, "ES137x");
  1621. gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
  1622. gameport_set_dev_parent(gp, &ensoniq->pci->dev);
  1623. gp->io = io_port;
  1624. ensoniq->ctrl |= ES_JYSTK_EN;
  1625. #ifdef CHIP1371
  1626. ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
  1627. ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
  1628. #endif
  1629. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  1630. gameport_register_port(ensoniq->gameport);
  1631. return 0;
  1632. }
  1633. static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
  1634. {
  1635. if (ensoniq->gameport) {
  1636. int port = ensoniq->gameport->io;
  1637. gameport_unregister_port(ensoniq->gameport);
  1638. ensoniq->gameport = NULL;
  1639. ensoniq->ctrl &= ~ES_JYSTK_EN;
  1640. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  1641. release_region(port, 8);
  1642. }
  1643. }
  1644. #else
  1645. static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
  1646. static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
  1647. #endif /* SUPPORT_JOYSTICK */
  1648. /*
  1649. */
  1650. static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
  1651. struct snd_info_buffer *buffer)
  1652. {
  1653. struct ensoniq *ensoniq = entry->private_data;
  1654. snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n");
  1655. snd_iprintf(buffer, "Joystick enable : %s\n",
  1656. ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
  1657. #ifdef CHIP1370
  1658. snd_iprintf(buffer, "MIC +5V bias : %s\n",
  1659. ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
  1660. snd_iprintf(buffer, "Line In to AOUT : %s\n",
  1661. ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
  1662. #else
  1663. snd_iprintf(buffer, "Joystick port : 0x%x\n",
  1664. (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
  1665. #endif
  1666. }
  1667. static void snd_ensoniq_proc_init(struct ensoniq *ensoniq)
  1668. {
  1669. snd_card_ro_proc_new(ensoniq->card, "audiopci", ensoniq,
  1670. snd_ensoniq_proc_read);
  1671. }
  1672. /*
  1673. */
  1674. static int snd_ensoniq_free(struct ensoniq *ensoniq)
  1675. {
  1676. snd_ensoniq_free_gameport(ensoniq);
  1677. if (ensoniq->irq < 0)
  1678. goto __hw_end;
  1679. #ifdef CHIP1370
  1680. outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
  1681. outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
  1682. #else
  1683. outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
  1684. outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
  1685. #endif
  1686. pci_set_power_state(ensoniq->pci, PCI_D3hot);
  1687. __hw_end:
  1688. #ifdef CHIP1370
  1689. if (ensoniq->dma_bug.area)
  1690. snd_dma_free_pages(&ensoniq->dma_bug);
  1691. #endif
  1692. if (ensoniq->irq >= 0)
  1693. free_irq(ensoniq->irq, ensoniq);
  1694. pci_release_regions(ensoniq->pci);
  1695. pci_disable_device(ensoniq->pci);
  1696. kfree(ensoniq);
  1697. return 0;
  1698. }
  1699. static int snd_ensoniq_dev_free(struct snd_device *device)
  1700. {
  1701. struct ensoniq *ensoniq = device->device_data;
  1702. return snd_ensoniq_free(ensoniq);
  1703. }
  1704. #ifdef CHIP1371
  1705. static const struct snd_pci_quirk es1371_amplifier_hack[] = {
  1706. SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */
  1707. SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */
  1708. SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */
  1709. SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */
  1710. { } /* end */
  1711. };
  1712. static const struct es1371_quirk es1371_ac97_reset_hack[] = {
  1713. { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
  1714. { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
  1715. { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
  1716. { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
  1717. { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
  1718. { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
  1719. };
  1720. #endif
  1721. static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
  1722. {
  1723. #ifdef CHIP1371
  1724. int idx;
  1725. #endif
  1726. /* this code was part of snd_ensoniq_create before intruduction
  1727. * of suspend/resume
  1728. */
  1729. #ifdef CHIP1370
  1730. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  1731. outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
  1732. outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
  1733. outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
  1734. outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
  1735. #else
  1736. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  1737. outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
  1738. outl(0, ES_REG(ensoniq, 1371_LEGACY));
  1739. if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
  1740. outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
  1741. /* need to delay around 20ms(bleech) to give
  1742. some CODECs enough time to wakeup */
  1743. msleep(20);
  1744. }
  1745. /* AC'97 warm reset to start the bitclk */
  1746. outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
  1747. inl(ES_REG(ensoniq, CONTROL));
  1748. udelay(20);
  1749. outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
  1750. /* Init the sample rate converter */
  1751. snd_es1371_wait_src_ready(ensoniq);
  1752. outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
  1753. for (idx = 0; idx < 0x80; idx++)
  1754. snd_es1371_src_write(ensoniq, idx, 0);
  1755. snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
  1756. snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
  1757. snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
  1758. snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
  1759. snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
  1760. snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
  1761. snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
  1762. snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
  1763. snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
  1764. snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
  1765. snd_es1371_adc_rate(ensoniq, 22050);
  1766. snd_es1371_dac1_rate(ensoniq, 22050);
  1767. snd_es1371_dac2_rate(ensoniq, 22050);
  1768. /* WARNING:
  1769. * enabling the sample rate converter without properly programming
  1770. * its parameters causes the chip to lock up (the SRC busy bit will
  1771. * be stuck high, and I've found no way to rectify this other than
  1772. * power cycle) - Thomas Sailer
  1773. */
  1774. snd_es1371_wait_src_ready(ensoniq);
  1775. outl(0, ES_REG(ensoniq, 1371_SMPRATE));
  1776. /* try reset codec directly */
  1777. outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
  1778. #endif
  1779. outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
  1780. outb(0x00, ES_REG(ensoniq, UART_RES));
  1781. outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
  1782. }
  1783. #ifdef CONFIG_PM_SLEEP
  1784. static int snd_ensoniq_suspend(struct device *dev)
  1785. {
  1786. struct snd_card *card = dev_get_drvdata(dev);
  1787. struct ensoniq *ensoniq = card->private_data;
  1788. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1789. #ifdef CHIP1371
  1790. snd_ac97_suspend(ensoniq->u.es1371.ac97);
  1791. #else
  1792. /* try to reset AK4531 */
  1793. outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
  1794. inw(ES_REG(ensoniq, 1370_CODEC));
  1795. udelay(100);
  1796. outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
  1797. inw(ES_REG(ensoniq, 1370_CODEC));
  1798. udelay(100);
  1799. snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
  1800. #endif
  1801. return 0;
  1802. }
  1803. static int snd_ensoniq_resume(struct device *dev)
  1804. {
  1805. struct snd_card *card = dev_get_drvdata(dev);
  1806. struct ensoniq *ensoniq = card->private_data;
  1807. snd_ensoniq_chip_init(ensoniq);
  1808. #ifdef CHIP1371
  1809. snd_ac97_resume(ensoniq->u.es1371.ac97);
  1810. #else
  1811. snd_ak4531_resume(ensoniq->u.es1370.ak4531);
  1812. #endif
  1813. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1814. return 0;
  1815. }
  1816. static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
  1817. #define SND_ENSONIQ_PM_OPS &snd_ensoniq_pm
  1818. #else
  1819. #define SND_ENSONIQ_PM_OPS NULL
  1820. #endif /* CONFIG_PM_SLEEP */
  1821. static int snd_ensoniq_create(struct snd_card *card,
  1822. struct pci_dev *pci,
  1823. struct ensoniq **rensoniq)
  1824. {
  1825. struct ensoniq *ensoniq;
  1826. int err;
  1827. static const struct snd_device_ops ops = {
  1828. .dev_free = snd_ensoniq_dev_free,
  1829. };
  1830. *rensoniq = NULL;
  1831. if ((err = pci_enable_device(pci)) < 0)
  1832. return err;
  1833. ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
  1834. if (ensoniq == NULL) {
  1835. pci_disable_device(pci);
  1836. return -ENOMEM;
  1837. }
  1838. spin_lock_init(&ensoniq->reg_lock);
  1839. mutex_init(&ensoniq->src_mutex);
  1840. ensoniq->card = card;
  1841. ensoniq->pci = pci;
  1842. ensoniq->irq = -1;
  1843. if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
  1844. kfree(ensoniq);
  1845. pci_disable_device(pci);
  1846. return err;
  1847. }
  1848. ensoniq->port = pci_resource_start(pci, 0);
  1849. if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
  1850. KBUILD_MODNAME, ensoniq)) {
  1851. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  1852. snd_ensoniq_free(ensoniq);
  1853. return -EBUSY;
  1854. }
  1855. ensoniq->irq = pci->irq;
  1856. card->sync_irq = ensoniq->irq;
  1857. #ifdef CHIP1370
  1858. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
  1859. 16, &ensoniq->dma_bug) < 0) {
  1860. dev_err(card->dev, "unable to allocate space for phantom area - dma_bug\n");
  1861. snd_ensoniq_free(ensoniq);
  1862. return -EBUSY;
  1863. }
  1864. #endif
  1865. pci_set_master(pci);
  1866. ensoniq->rev = pci->revision;
  1867. #ifdef CHIP1370
  1868. #if 0
  1869. ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
  1870. ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
  1871. #else /* get microphone working */
  1872. ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
  1873. #endif
  1874. ensoniq->sctrl = 0;
  1875. #else
  1876. ensoniq->ctrl = 0;
  1877. ensoniq->sctrl = 0;
  1878. ensoniq->cssr = 0;
  1879. if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
  1880. ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
  1881. if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
  1882. ensoniq->cssr |= ES_1371_ST_AC97_RST;
  1883. #endif
  1884. snd_ensoniq_chip_init(ensoniq);
  1885. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
  1886. snd_ensoniq_free(ensoniq);
  1887. return err;
  1888. }
  1889. snd_ensoniq_proc_init(ensoniq);
  1890. *rensoniq = ensoniq;
  1891. return 0;
  1892. }
  1893. /*
  1894. * MIDI section
  1895. */
  1896. static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
  1897. {
  1898. struct snd_rawmidi *rmidi = ensoniq->rmidi;
  1899. unsigned char status, mask, byte;
  1900. if (rmidi == NULL)
  1901. return;
  1902. /* do Rx at first */
  1903. spin_lock(&ensoniq->reg_lock);
  1904. mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
  1905. while (mask) {
  1906. status = inb(ES_REG(ensoniq, UART_STATUS));
  1907. if ((status & mask) == 0)
  1908. break;
  1909. byte = inb(ES_REG(ensoniq, UART_DATA));
  1910. snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
  1911. }
  1912. spin_unlock(&ensoniq->reg_lock);
  1913. /* do Tx at second */
  1914. spin_lock(&ensoniq->reg_lock);
  1915. mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
  1916. while (mask) {
  1917. status = inb(ES_REG(ensoniq, UART_STATUS));
  1918. if ((status & mask) == 0)
  1919. break;
  1920. if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
  1921. ensoniq->uartc &= ~ES_TXINTENM;
  1922. outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
  1923. mask &= ~ES_TXRDY;
  1924. } else {
  1925. outb(byte, ES_REG(ensoniq, UART_DATA));
  1926. }
  1927. }
  1928. spin_unlock(&ensoniq->reg_lock);
  1929. }
  1930. static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
  1931. {
  1932. struct ensoniq *ensoniq = substream->rmidi->private_data;
  1933. spin_lock_irq(&ensoniq->reg_lock);
  1934. ensoniq->uartm |= ES_MODE_INPUT;
  1935. ensoniq->midi_input = substream;
  1936. if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
  1937. outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
  1938. outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
  1939. outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
  1940. }
  1941. spin_unlock_irq(&ensoniq->reg_lock);
  1942. return 0;
  1943. }
  1944. static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
  1945. {
  1946. struct ensoniq *ensoniq = substream->rmidi->private_data;
  1947. spin_lock_irq(&ensoniq->reg_lock);
  1948. if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
  1949. outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
  1950. outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
  1951. } else {
  1952. outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
  1953. }
  1954. ensoniq->midi_input = NULL;
  1955. ensoniq->uartm &= ~ES_MODE_INPUT;
  1956. spin_unlock_irq(&ensoniq->reg_lock);
  1957. return 0;
  1958. }
  1959. static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
  1960. {
  1961. struct ensoniq *ensoniq = substream->rmidi->private_data;
  1962. spin_lock_irq(&ensoniq->reg_lock);
  1963. ensoniq->uartm |= ES_MODE_OUTPUT;
  1964. ensoniq->midi_output = substream;
  1965. if (!(ensoniq->uartm & ES_MODE_INPUT)) {
  1966. outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
  1967. outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
  1968. outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
  1969. }
  1970. spin_unlock_irq(&ensoniq->reg_lock);
  1971. return 0;
  1972. }
  1973. static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
  1974. {
  1975. struct ensoniq *ensoniq = substream->rmidi->private_data;
  1976. spin_lock_irq(&ensoniq->reg_lock);
  1977. if (!(ensoniq->uartm & ES_MODE_INPUT)) {
  1978. outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
  1979. outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
  1980. } else {
  1981. outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
  1982. }
  1983. ensoniq->midi_output = NULL;
  1984. ensoniq->uartm &= ~ES_MODE_OUTPUT;
  1985. spin_unlock_irq(&ensoniq->reg_lock);
  1986. return 0;
  1987. }
  1988. static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
  1989. {
  1990. unsigned long flags;
  1991. struct ensoniq *ensoniq = substream->rmidi->private_data;
  1992. int idx;
  1993. spin_lock_irqsave(&ensoniq->reg_lock, flags);
  1994. if (up) {
  1995. if ((ensoniq->uartc & ES_RXINTEN) == 0) {
  1996. /* empty input FIFO */
  1997. for (idx = 0; idx < 32; idx++)
  1998. inb(ES_REG(ensoniq, UART_DATA));
  1999. ensoniq->uartc |= ES_RXINTEN;
  2000. outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
  2001. }
  2002. } else {
  2003. if (ensoniq->uartc & ES_RXINTEN) {
  2004. ensoniq->uartc &= ~ES_RXINTEN;
  2005. outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
  2006. }
  2007. }
  2008. spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
  2009. }
  2010. static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
  2011. {
  2012. unsigned long flags;
  2013. struct ensoniq *ensoniq = substream->rmidi->private_data;
  2014. unsigned char byte;
  2015. spin_lock_irqsave(&ensoniq->reg_lock, flags);
  2016. if (up) {
  2017. if (ES_TXINTENI(ensoniq->uartc) == 0) {
  2018. ensoniq->uartc |= ES_TXINTENO(1);
  2019. /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
  2020. while (ES_TXINTENI(ensoniq->uartc) == 1 &&
  2021. (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
  2022. if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
  2023. ensoniq->uartc &= ~ES_TXINTENM;
  2024. } else {
  2025. outb(byte, ES_REG(ensoniq, UART_DATA));
  2026. }
  2027. }
  2028. outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
  2029. }
  2030. } else {
  2031. if (ES_TXINTENI(ensoniq->uartc) == 1) {
  2032. ensoniq->uartc &= ~ES_TXINTENM;
  2033. outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
  2034. }
  2035. }
  2036. spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
  2037. }
  2038. static const struct snd_rawmidi_ops snd_ensoniq_midi_output =
  2039. {
  2040. .open = snd_ensoniq_midi_output_open,
  2041. .close = snd_ensoniq_midi_output_close,
  2042. .trigger = snd_ensoniq_midi_output_trigger,
  2043. };
  2044. static const struct snd_rawmidi_ops snd_ensoniq_midi_input =
  2045. {
  2046. .open = snd_ensoniq_midi_input_open,
  2047. .close = snd_ensoniq_midi_input_close,
  2048. .trigger = snd_ensoniq_midi_input_trigger,
  2049. };
  2050. static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device)
  2051. {
  2052. struct snd_rawmidi *rmidi;
  2053. int err;
  2054. if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
  2055. return err;
  2056. strcpy(rmidi->name, CHIP_NAME);
  2057. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
  2058. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
  2059. rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
  2060. SNDRV_RAWMIDI_INFO_DUPLEX;
  2061. rmidi->private_data = ensoniq;
  2062. ensoniq->rmidi = rmidi;
  2063. return 0;
  2064. }
  2065. /*
  2066. * Interrupt handler
  2067. */
  2068. static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
  2069. {
  2070. struct ensoniq *ensoniq = dev_id;
  2071. unsigned int status, sctrl;
  2072. if (ensoniq == NULL)
  2073. return IRQ_NONE;
  2074. status = inl(ES_REG(ensoniq, STATUS));
  2075. if (!(status & ES_INTR))
  2076. return IRQ_NONE;
  2077. spin_lock(&ensoniq->reg_lock);
  2078. sctrl = ensoniq->sctrl;
  2079. if (status & ES_DAC1)
  2080. sctrl &= ~ES_P1_INT_EN;
  2081. if (status & ES_DAC2)
  2082. sctrl &= ~ES_P2_INT_EN;
  2083. if (status & ES_ADC)
  2084. sctrl &= ~ES_R1_INT_EN;
  2085. outl(sctrl, ES_REG(ensoniq, SERIAL));
  2086. outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
  2087. spin_unlock(&ensoniq->reg_lock);
  2088. if (status & ES_UART)
  2089. snd_ensoniq_midi_interrupt(ensoniq);
  2090. if ((status & ES_DAC2) && ensoniq->playback2_substream)
  2091. snd_pcm_period_elapsed(ensoniq->playback2_substream);
  2092. if ((status & ES_ADC) && ensoniq->capture_substream)
  2093. snd_pcm_period_elapsed(ensoniq->capture_substream);
  2094. if ((status & ES_DAC1) && ensoniq->playback1_substream)
  2095. snd_pcm_period_elapsed(ensoniq->playback1_substream);
  2096. return IRQ_HANDLED;
  2097. }
  2098. static int snd_audiopci_probe(struct pci_dev *pci,
  2099. const struct pci_device_id *pci_id)
  2100. {
  2101. static int dev;
  2102. struct snd_card *card;
  2103. struct ensoniq *ensoniq;
  2104. int err;
  2105. if (dev >= SNDRV_CARDS)
  2106. return -ENODEV;
  2107. if (!enable[dev]) {
  2108. dev++;
  2109. return -ENOENT;
  2110. }
  2111. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  2112. 0, &card);
  2113. if (err < 0)
  2114. return err;
  2115. if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
  2116. snd_card_free(card);
  2117. return err;
  2118. }
  2119. card->private_data = ensoniq;
  2120. #ifdef CHIP1370
  2121. if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
  2122. snd_card_free(card);
  2123. return err;
  2124. }
  2125. #endif
  2126. #ifdef CHIP1371
  2127. if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
  2128. snd_card_free(card);
  2129. return err;
  2130. }
  2131. #endif
  2132. if ((err = snd_ensoniq_pcm(ensoniq, 0)) < 0) {
  2133. snd_card_free(card);
  2134. return err;
  2135. }
  2136. if ((err = snd_ensoniq_pcm2(ensoniq, 1)) < 0) {
  2137. snd_card_free(card);
  2138. return err;
  2139. }
  2140. if ((err = snd_ensoniq_midi(ensoniq, 0)) < 0) {
  2141. snd_card_free(card);
  2142. return err;
  2143. }
  2144. snd_ensoniq_create_gameport(ensoniq, dev);
  2145. strcpy(card->driver, DRIVER_NAME);
  2146. strcpy(card->shortname, "Ensoniq AudioPCI");
  2147. sprintf(card->longname, "%s %s at 0x%lx, irq %i",
  2148. card->shortname,
  2149. card->driver,
  2150. ensoniq->port,
  2151. ensoniq->irq);
  2152. if ((err = snd_card_register(card)) < 0) {
  2153. snd_card_free(card);
  2154. return err;
  2155. }
  2156. pci_set_drvdata(pci, card);
  2157. dev++;
  2158. return 0;
  2159. }
  2160. static void snd_audiopci_remove(struct pci_dev *pci)
  2161. {
  2162. snd_card_free(pci_get_drvdata(pci));
  2163. }
  2164. static struct pci_driver ens137x_driver = {
  2165. .name = KBUILD_MODNAME,
  2166. .id_table = snd_audiopci_ids,
  2167. .probe = snd_audiopci_probe,
  2168. .remove = snd_audiopci_remove,
  2169. .driver = {
  2170. .pm = SND_ENSONIQ_PM_OPS,
  2171. },
  2172. };
  2173. module_pci_driver(ens137x_driver);