cs4281.c 63 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Cirrus Logic CS4281 based PCI soundcard
  4. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
  5. */
  6. #include <linux/io.h>
  7. #include <linux/delay.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/init.h>
  10. #include <linux/pci.h>
  11. #include <linux/slab.h>
  12. #include <linux/gameport.h>
  13. #include <linux/module.h>
  14. #include <sound/core.h>
  15. #include <sound/control.h>
  16. #include <sound/pcm.h>
  17. #include <sound/rawmidi.h>
  18. #include <sound/ac97_codec.h>
  19. #include <sound/tlv.h>
  20. #include <sound/opl3.h>
  21. #include <sound/initval.h>
  22. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  23. MODULE_DESCRIPTION("Cirrus Logic CS4281");
  24. MODULE_LICENSE("GPL");
  25. MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
  26. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  27. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  28. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
  29. static bool dual_codec[SNDRV_CARDS]; /* dual codec */
  30. module_param_array(index, int, NULL, 0444);
  31. MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
  32. module_param_array(id, charp, NULL, 0444);
  33. MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
  34. module_param_array(enable, bool, NULL, 0444);
  35. MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
  36. module_param_array(dual_codec, bool, NULL, 0444);
  37. MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
  38. /*
  39. * Direct registers
  40. */
  41. #define CS4281_BA0_SIZE 0x1000
  42. #define CS4281_BA1_SIZE 0x10000
  43. /*
  44. * BA0 registers
  45. */
  46. #define BA0_HISR 0x0000 /* Host Interrupt Status Register */
  47. #define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
  48. #define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
  49. #define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
  50. #define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
  51. #define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
  52. #define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
  53. #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
  54. #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
  55. #define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
  56. #define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
  57. #define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
  58. #define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
  59. #define BA0_HICR 0x0008 /* Host Interrupt Control Register */
  60. #define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
  61. #define BA0_HICR_IEV (1<<0) /* INTENA Value */
  62. #define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
  63. #define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
  64. /* Use same contants as for BA0_HISR */
  65. #define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
  66. #define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
  67. #define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
  68. #define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
  69. #define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
  70. #define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
  71. #define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
  72. #define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
  73. #define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
  74. #define BA0_HDSR_DRUN (1<<15) /* DMA Running */
  75. #define BA0_HDSR_RQ (1<<7) /* Pending Request */
  76. #define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
  77. #define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
  78. #define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
  79. #define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
  80. #define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
  81. #define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
  82. #define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
  83. #define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
  84. #define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
  85. #define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
  86. #define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
  87. #define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
  88. #define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
  89. #define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
  90. #define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
  91. #define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
  92. #define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
  93. #define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
  94. #define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
  95. #define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
  96. #define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
  97. #define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
  98. #define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
  99. #define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
  100. #define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
  101. #define BA0_DMR_POLL (1<<28) /* Enable poll mode */
  102. #define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
  103. #define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
  104. #define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
  105. #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
  106. #define BA0_DMR_USIGN (1<<19) /* Unsigned */
  107. #define BA0_DMR_BEND (1<<18) /* Big Endian */
  108. #define BA0_DMR_MONO (1<<17) /* Mono */
  109. #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
  110. #define BA0_DMR_TYPE_DEMAND (0<<6)
  111. #define BA0_DMR_TYPE_SINGLE (1<<6)
  112. #define BA0_DMR_TYPE_BLOCK (2<<6)
  113. #define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
  114. #define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
  115. #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
  116. #define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
  117. #define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
  118. #define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
  119. #define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
  120. #define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
  121. #define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
  122. #define BA0_FCR0 0x0180 /* FIFO Control 0 */
  123. #define BA0_FCR1 0x0184 /* FIFO Control 1 */
  124. #define BA0_FCR2 0x0188 /* FIFO Control 2 */
  125. #define BA0_FCR3 0x018c /* FIFO Control 3 */
  126. #define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
  127. #define BA0_FCR_DACZ (1<<30) /* DAC Zero */
  128. #define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
  129. #define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
  130. #define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
  131. #define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
  132. #define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
  133. #define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
  134. #define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
  135. #define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
  136. #define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
  137. #define BA0_FCHS 0x020c /* FIFO Channel Status */
  138. #define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
  139. #define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
  140. #define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
  141. #define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
  142. #define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
  143. #define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
  144. #define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
  145. #define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
  146. #define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
  147. #define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
  148. #define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
  149. #define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
  150. #define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
  151. #define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
  152. #define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
  153. #define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
  154. #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
  155. #define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
  156. #define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
  157. #define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
  158. #define BA0_PMCS 0x0344 /* Power Management Control/Status */
  159. #define BA0_CWPR 0x03e0 /* Configuration Write Protect */
  160. #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
  161. #define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
  162. #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
  163. #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
  164. #define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
  165. #define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
  166. #define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
  167. #define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
  168. #define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
  169. #define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
  170. #define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
  171. #define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
  172. #define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
  173. #define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
  174. #define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
  175. #define BA0_IISR 0x03f4 /* ISA Interrupt Select */
  176. #define BA0_TMS 0x03f8 /* Test Register */
  177. #define BA0_SSVID 0x03fc /* Subsystem ID register */
  178. #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
  179. #define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
  180. #define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
  181. #define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
  182. #define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
  183. #define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
  184. #define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
  185. #define BA0_FRR 0x0410 /* Feature Reporting Register */
  186. #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
  187. #define BA0_SERMC 0x0420 /* Serial Port Master Control */
  188. #define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
  189. #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
  190. #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
  191. #define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
  192. #define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
  193. #define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
  194. #define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
  195. #define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
  196. #define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
  197. #define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
  198. #define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
  199. #define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
  200. #define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
  201. #define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
  202. #define BA0_SERC1_AC97 (1<<1)
  203. #define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
  204. #define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
  205. #define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
  206. #define BA0_SERC2_AC97 (1<<1)
  207. #define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
  208. #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
  209. #define BA0_ACCTL 0x0460 /* AC'97 Control */
  210. #define BA0_ACCTL_TC (1<<6) /* Target Codec */
  211. #define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
  212. #define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
  213. #define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
  214. #define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
  215. #define BA0_ACSTS 0x0464 /* AC'97 Status */
  216. #define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
  217. #define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
  218. #define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
  219. #define BA0_ACOSV_SLV(x) (1<<((x)-3))
  220. #define BA0_ACCAD 0x046c /* AC'97 Command Address */
  221. #define BA0_ACCDA 0x0470 /* AC'97 Command Data */
  222. #define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
  223. #define BA0_ACISV_SLV(x) (1<<((x)-3))
  224. #define BA0_ACSAD 0x0478 /* AC'97 Status Address */
  225. #define BA0_ACSDA 0x047c /* AC'97 Status Data */
  226. #define BA0_JSPT 0x0480 /* Joystick poll/trigger */
  227. #define BA0_JSCTL 0x0484 /* Joystick control */
  228. #define BA0_JSC1 0x0488 /* Joystick control */
  229. #define BA0_JSC2 0x048c /* Joystick control */
  230. #define BA0_JSIO 0x04a0
  231. #define BA0_MIDCR 0x0490 /* MIDI Control */
  232. #define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
  233. #define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
  234. #define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
  235. #define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
  236. #define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
  237. #define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
  238. #define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
  239. #define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
  240. #define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
  241. #define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
  242. #define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
  243. #define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
  244. #define BA0_MIDWP 0x0498 /* MIDI Write */
  245. #define BA0_MIDRP 0x049c /* MIDI Read (ro) */
  246. #define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
  247. #define BA0_AODSD1_NDS(x) (1<<((x)-3))
  248. #define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
  249. #define BA0_AODSD2_NDS(x) (1<<((x)-3))
  250. #define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
  251. #define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
  252. #define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
  253. #define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
  254. #define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
  255. #define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
  256. #define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
  257. #define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
  258. #define BA0_FMDP 0x0734 /* FM Data Port */
  259. #define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
  260. #define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
  261. #define BA0_SSPM 0x0740 /* Sound System Power Management */
  262. #define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
  263. #define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
  264. #define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
  265. #define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
  266. #define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
  267. #define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
  268. #define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
  269. #define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
  270. #define BA0_SSCR 0x074c /* Sound System Control Register */
  271. #define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
  272. #define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
  273. #define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
  274. #define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
  275. #define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
  276. #define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
  277. #define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
  278. #define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
  279. #define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
  280. #define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
  281. #define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
  282. #define BA0_SRCSA 0x075c /* SRC Slot Assignments */
  283. #define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
  284. #define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
  285. #define BA0_PASR 0x0768 /* playback sample rate */
  286. #define BA0_CASR 0x076C /* capture sample rate */
  287. /* Source Slot Numbers - Playback */
  288. #define SRCSLOT_LEFT_PCM_PLAYBACK 0
  289. #define SRCSLOT_RIGHT_PCM_PLAYBACK 1
  290. #define SRCSLOT_PHONE_LINE_1_DAC 2
  291. #define SRCSLOT_CENTER_PCM_PLAYBACK 3
  292. #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
  293. #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
  294. #define SRCSLOT_LFE_PCM_PLAYBACK 6
  295. #define SRCSLOT_PHONE_LINE_2_DAC 7
  296. #define SRCSLOT_HEADSET_DAC 8
  297. #define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
  298. #define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
  299. /* Source Slot Numbers - Capture */
  300. #define SRCSLOT_LEFT_PCM_RECORD 10
  301. #define SRCSLOT_RIGHT_PCM_RECORD 11
  302. #define SRCSLOT_PHONE_LINE_1_ADC 12
  303. #define SRCSLOT_MIC_ADC 13
  304. #define SRCSLOT_PHONE_LINE_2_ADC 17
  305. #define SRCSLOT_HEADSET_ADC 18
  306. #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
  307. #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
  308. #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
  309. #define SRCSLOT_SECONDARY_MIC_ADC 23
  310. #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
  311. #define SRCSLOT_SECONDARY_HEADSET_ADC 28
  312. /* Source Slot Numbers - Others */
  313. #define SRCSLOT_POWER_DOWN 31
  314. /* MIDI modes */
  315. #define CS4281_MODE_OUTPUT (1<<0)
  316. #define CS4281_MODE_INPUT (1<<1)
  317. /* joystick bits */
  318. /* Bits for JSPT */
  319. #define JSPT_CAX 0x00000001
  320. #define JSPT_CAY 0x00000002
  321. #define JSPT_CBX 0x00000004
  322. #define JSPT_CBY 0x00000008
  323. #define JSPT_BA1 0x00000010
  324. #define JSPT_BA2 0x00000020
  325. #define JSPT_BB1 0x00000040
  326. #define JSPT_BB2 0x00000080
  327. /* Bits for JSCTL */
  328. #define JSCTL_SP_MASK 0x00000003
  329. #define JSCTL_SP_SLOW 0x00000000
  330. #define JSCTL_SP_MEDIUM_SLOW 0x00000001
  331. #define JSCTL_SP_MEDIUM_FAST 0x00000002
  332. #define JSCTL_SP_FAST 0x00000003
  333. #define JSCTL_ARE 0x00000004
  334. /* Data register pairs masks */
  335. #define JSC1_Y1V_MASK 0x0000FFFF
  336. #define JSC1_X1V_MASK 0xFFFF0000
  337. #define JSC1_Y1V_SHIFT 0
  338. #define JSC1_X1V_SHIFT 16
  339. #define JSC2_Y2V_MASK 0x0000FFFF
  340. #define JSC2_X2V_MASK 0xFFFF0000
  341. #define JSC2_Y2V_SHIFT 0
  342. #define JSC2_X2V_SHIFT 16
  343. /* JS GPIO */
  344. #define JSIO_DAX 0x00000001
  345. #define JSIO_DAY 0x00000002
  346. #define JSIO_DBX 0x00000004
  347. #define JSIO_DBY 0x00000008
  348. #define JSIO_AXOE 0x00000010
  349. #define JSIO_AYOE 0x00000020
  350. #define JSIO_BXOE 0x00000040
  351. #define JSIO_BYOE 0x00000080
  352. /*
  353. *
  354. */
  355. struct cs4281_dma {
  356. struct snd_pcm_substream *substream;
  357. unsigned int regDBA; /* offset to DBA register */
  358. unsigned int regDCA; /* offset to DCA register */
  359. unsigned int regDBC; /* offset to DBC register */
  360. unsigned int regDCC; /* offset to DCC register */
  361. unsigned int regDMR; /* offset to DMR register */
  362. unsigned int regDCR; /* offset to DCR register */
  363. unsigned int regHDSR; /* offset to HDSR register */
  364. unsigned int regFCR; /* offset to FCR register */
  365. unsigned int regFSIC; /* offset to FSIC register */
  366. unsigned int valDMR; /* DMA mode */
  367. unsigned int valDCR; /* DMA command */
  368. unsigned int valFCR; /* FIFO control */
  369. unsigned int fifo_offset; /* FIFO offset within BA1 */
  370. unsigned char left_slot; /* FIFO left slot */
  371. unsigned char right_slot; /* FIFO right slot */
  372. int frag; /* period number */
  373. };
  374. #define SUSPEND_REGISTERS 20
  375. struct cs4281 {
  376. int irq;
  377. void __iomem *ba0; /* virtual (accessible) address */
  378. void __iomem *ba1; /* virtual (accessible) address */
  379. unsigned long ba0_addr;
  380. unsigned long ba1_addr;
  381. int dual_codec;
  382. struct snd_ac97_bus *ac97_bus;
  383. struct snd_ac97 *ac97;
  384. struct snd_ac97 *ac97_secondary;
  385. struct pci_dev *pci;
  386. struct snd_card *card;
  387. struct snd_pcm *pcm;
  388. struct snd_rawmidi *rmidi;
  389. struct snd_rawmidi_substream *midi_input;
  390. struct snd_rawmidi_substream *midi_output;
  391. struct cs4281_dma dma[4];
  392. unsigned char src_left_play_slot;
  393. unsigned char src_right_play_slot;
  394. unsigned char src_left_rec_slot;
  395. unsigned char src_right_rec_slot;
  396. unsigned int spurious_dhtc_irq;
  397. unsigned int spurious_dtc_irq;
  398. spinlock_t reg_lock;
  399. unsigned int midcr;
  400. unsigned int uartm;
  401. struct gameport *gameport;
  402. #ifdef CONFIG_PM_SLEEP
  403. u32 suspend_regs[SUSPEND_REGISTERS];
  404. #endif
  405. };
  406. static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
  407. static const struct pci_device_id snd_cs4281_ids[] = {
  408. { PCI_VDEVICE(CIRRUS, 0x6005), 0, }, /* CS4281 */
  409. { 0, }
  410. };
  411. MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
  412. /*
  413. * constants
  414. */
  415. #define CS4281_FIFO_SIZE 32
  416. /*
  417. * common I/O routines
  418. */
  419. static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
  420. unsigned int val)
  421. {
  422. writel(val, chip->ba0 + offset);
  423. }
  424. static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
  425. {
  426. return readl(chip->ba0 + offset);
  427. }
  428. static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
  429. unsigned short reg, unsigned short val)
  430. {
  431. /*
  432. * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
  433. * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
  434. * 3. Write ACCTL = Control Register = 460h for initiating the write
  435. * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
  436. * 5. if DCV not cleared, break and return error
  437. */
  438. struct cs4281 *chip = ac97->private_data;
  439. int count;
  440. /*
  441. * Setup the AC97 control registers on the CS461x to send the
  442. * appropriate command to the AC97 to perform the read.
  443. * ACCAD = Command Address Register = 46Ch
  444. * ACCDA = Command Data Register = 470h
  445. * ACCTL = Control Register = 460h
  446. * set DCV - will clear when process completed
  447. * reset CRW - Write command
  448. * set VFRM - valid frame enabled
  449. * set ESYN - ASYNC generation enabled
  450. * set RSTN - ARST# inactive, AC97 codec not reset
  451. */
  452. snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
  453. snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
  454. snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
  455. BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
  456. for (count = 0; count < 2000; count++) {
  457. /*
  458. * First, we want to wait for a short time.
  459. */
  460. udelay(10);
  461. /*
  462. * Now, check to see if the write has completed.
  463. * ACCTL = 460h, DCV should be reset by now and 460h = 07h
  464. */
  465. if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
  466. return;
  467. }
  468. }
  469. dev_err(chip->card->dev,
  470. "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
  471. }
  472. static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
  473. unsigned short reg)
  474. {
  475. struct cs4281 *chip = ac97->private_data;
  476. int count;
  477. unsigned short result;
  478. // FIXME: volatile is necessary in the following due to a bug of
  479. // some gcc versions
  480. volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
  481. /*
  482. * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
  483. * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
  484. * 3. Write ACCTL = Control Register = 460h for initiating the write
  485. * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
  486. * 5. if DCV not cleared, break and return error
  487. * 6. Read ACSTS = Status Register = 464h, check VSTS bit
  488. */
  489. snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
  490. /*
  491. * Setup the AC97 control registers on the CS461x to send the
  492. * appropriate command to the AC97 to perform the read.
  493. * ACCAD = Command Address Register = 46Ch
  494. * ACCDA = Command Data Register = 470h
  495. * ACCTL = Control Register = 460h
  496. * set DCV - will clear when process completed
  497. * set CRW - Read command
  498. * set VFRM - valid frame enabled
  499. * set ESYN - ASYNC generation enabled
  500. * set RSTN - ARST# inactive, AC97 codec not reset
  501. */
  502. snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
  503. snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
  504. snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
  505. BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
  506. (ac97_num ? BA0_ACCTL_TC : 0));
  507. /*
  508. * Wait for the read to occur.
  509. */
  510. for (count = 0; count < 500; count++) {
  511. /*
  512. * First, we want to wait for a short time.
  513. */
  514. udelay(10);
  515. /*
  516. * Now, check to see if the read has completed.
  517. * ACCTL = 460h, DCV should be reset by now and 460h = 17h
  518. */
  519. if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
  520. goto __ok1;
  521. }
  522. dev_err(chip->card->dev,
  523. "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
  524. result = 0xffff;
  525. goto __end;
  526. __ok1:
  527. /*
  528. * Wait for the valid status bit to go active.
  529. */
  530. for (count = 0; count < 100; count++) {
  531. /*
  532. * Read the AC97 status register.
  533. * ACSTS = Status Register = 464h
  534. * VSTS - Valid Status
  535. */
  536. if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
  537. goto __ok2;
  538. udelay(10);
  539. }
  540. dev_err(chip->card->dev,
  541. "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
  542. result = 0xffff;
  543. goto __end;
  544. __ok2:
  545. /*
  546. * Read the data returned from the AC97 register.
  547. * ACSDA = Status Data Register = 474h
  548. */
  549. result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
  550. __end:
  551. return result;
  552. }
  553. /*
  554. * PCM part
  555. */
  556. static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
  557. {
  558. struct cs4281_dma *dma = substream->runtime->private_data;
  559. struct cs4281 *chip = snd_pcm_substream_chip(substream);
  560. spin_lock(&chip->reg_lock);
  561. switch (cmd) {
  562. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  563. dma->valDCR |= BA0_DCR_MSK;
  564. dma->valFCR |= BA0_FCR_FEN;
  565. break;
  566. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  567. dma->valDCR &= ~BA0_DCR_MSK;
  568. dma->valFCR &= ~BA0_FCR_FEN;
  569. break;
  570. case SNDRV_PCM_TRIGGER_START:
  571. case SNDRV_PCM_TRIGGER_RESUME:
  572. snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
  573. dma->valDMR |= BA0_DMR_DMA;
  574. dma->valDCR &= ~BA0_DCR_MSK;
  575. dma->valFCR |= BA0_FCR_FEN;
  576. break;
  577. case SNDRV_PCM_TRIGGER_STOP:
  578. case SNDRV_PCM_TRIGGER_SUSPEND:
  579. dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
  580. dma->valDCR |= BA0_DCR_MSK;
  581. dma->valFCR &= ~BA0_FCR_FEN;
  582. /* Leave wave playback FIFO enabled for FM */
  583. if (dma->regFCR != BA0_FCR0)
  584. dma->valFCR &= ~BA0_FCR_FEN;
  585. break;
  586. default:
  587. spin_unlock(&chip->reg_lock);
  588. return -EINVAL;
  589. }
  590. snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
  591. snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
  592. snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
  593. spin_unlock(&chip->reg_lock);
  594. return 0;
  595. }
  596. static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
  597. {
  598. unsigned int val;
  599. if (real_rate)
  600. *real_rate = rate;
  601. /* special "hardcoded" rates */
  602. switch (rate) {
  603. case 8000: return 5;
  604. case 11025: return 4;
  605. case 16000: return 3;
  606. case 22050: return 2;
  607. case 44100: return 1;
  608. case 48000: return 0;
  609. default:
  610. break;
  611. }
  612. val = 1536000 / rate;
  613. if (real_rate)
  614. *real_rate = 1536000 / val;
  615. return val;
  616. }
  617. static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
  618. struct snd_pcm_runtime *runtime,
  619. int capture, int src)
  620. {
  621. int rec_mono;
  622. dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
  623. (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
  624. if (runtime->channels == 1)
  625. dma->valDMR |= BA0_DMR_MONO;
  626. if (snd_pcm_format_unsigned(runtime->format) > 0)
  627. dma->valDMR |= BA0_DMR_USIGN;
  628. if (snd_pcm_format_big_endian(runtime->format) > 0)
  629. dma->valDMR |= BA0_DMR_BEND;
  630. switch (snd_pcm_format_width(runtime->format)) {
  631. case 8: dma->valDMR |= BA0_DMR_SIZE8;
  632. if (runtime->channels == 1)
  633. dma->valDMR |= BA0_DMR_SWAPC;
  634. break;
  635. case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
  636. }
  637. dma->frag = 0; /* for workaround */
  638. dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
  639. if (runtime->buffer_size != runtime->period_size)
  640. dma->valDCR |= BA0_DCR_HTCIE;
  641. /* Initialize DMA */
  642. snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
  643. snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
  644. rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
  645. snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
  646. (chip->src_right_play_slot << 8) |
  647. (chip->src_left_rec_slot << 16) |
  648. ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
  649. if (!src)
  650. goto __skip_src;
  651. if (!capture) {
  652. if (dma->left_slot == chip->src_left_play_slot) {
  653. unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
  654. snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
  655. snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
  656. }
  657. } else {
  658. if (dma->left_slot == chip->src_left_rec_slot) {
  659. unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
  660. snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
  661. snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
  662. }
  663. }
  664. __skip_src:
  665. /* Deactivate wave playback FIFO before changing slot assignments */
  666. if (dma->regFCR == BA0_FCR0)
  667. snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
  668. /* Initialize FIFO */
  669. dma->valFCR = BA0_FCR_LS(dma->left_slot) |
  670. BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
  671. BA0_FCR_SZ(CS4281_FIFO_SIZE) |
  672. BA0_FCR_OF(dma->fifo_offset);
  673. snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
  674. /* Activate FIFO again for FM playback */
  675. if (dma->regFCR == BA0_FCR0)
  676. snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
  677. /* Clear FIFO Status and Interrupt Control Register */
  678. snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
  679. }
  680. static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
  681. {
  682. struct snd_pcm_runtime *runtime = substream->runtime;
  683. struct cs4281_dma *dma = runtime->private_data;
  684. struct cs4281 *chip = snd_pcm_substream_chip(substream);
  685. spin_lock_irq(&chip->reg_lock);
  686. snd_cs4281_mode(chip, dma, runtime, 0, 1);
  687. spin_unlock_irq(&chip->reg_lock);
  688. return 0;
  689. }
  690. static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
  691. {
  692. struct snd_pcm_runtime *runtime = substream->runtime;
  693. struct cs4281_dma *dma = runtime->private_data;
  694. struct cs4281 *chip = snd_pcm_substream_chip(substream);
  695. spin_lock_irq(&chip->reg_lock);
  696. snd_cs4281_mode(chip, dma, runtime, 1, 1);
  697. spin_unlock_irq(&chip->reg_lock);
  698. return 0;
  699. }
  700. static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
  701. {
  702. struct snd_pcm_runtime *runtime = substream->runtime;
  703. struct cs4281_dma *dma = runtime->private_data;
  704. struct cs4281 *chip = snd_pcm_substream_chip(substream);
  705. /*
  706. dev_dbg(chip->card->dev,
  707. "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
  708. snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
  709. jiffies);
  710. */
  711. return runtime->buffer_size -
  712. snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
  713. }
  714. static const struct snd_pcm_hardware snd_cs4281_playback =
  715. {
  716. .info = SNDRV_PCM_INFO_MMAP |
  717. SNDRV_PCM_INFO_INTERLEAVED |
  718. SNDRV_PCM_INFO_MMAP_VALID |
  719. SNDRV_PCM_INFO_PAUSE |
  720. SNDRV_PCM_INFO_RESUME,
  721. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
  722. SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
  723. SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
  724. SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
  725. SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
  726. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  727. .rate_min = 4000,
  728. .rate_max = 48000,
  729. .channels_min = 1,
  730. .channels_max = 2,
  731. .buffer_bytes_max = (512*1024),
  732. .period_bytes_min = 64,
  733. .period_bytes_max = (512*1024),
  734. .periods_min = 1,
  735. .periods_max = 2,
  736. .fifo_size = CS4281_FIFO_SIZE,
  737. };
  738. static const struct snd_pcm_hardware snd_cs4281_capture =
  739. {
  740. .info = SNDRV_PCM_INFO_MMAP |
  741. SNDRV_PCM_INFO_INTERLEAVED |
  742. SNDRV_PCM_INFO_MMAP_VALID |
  743. SNDRV_PCM_INFO_PAUSE |
  744. SNDRV_PCM_INFO_RESUME,
  745. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
  746. SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
  747. SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
  748. SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
  749. SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
  750. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  751. .rate_min = 4000,
  752. .rate_max = 48000,
  753. .channels_min = 1,
  754. .channels_max = 2,
  755. .buffer_bytes_max = (512*1024),
  756. .period_bytes_min = 64,
  757. .period_bytes_max = (512*1024),
  758. .periods_min = 1,
  759. .periods_max = 2,
  760. .fifo_size = CS4281_FIFO_SIZE,
  761. };
  762. static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
  763. {
  764. struct cs4281 *chip = snd_pcm_substream_chip(substream);
  765. struct snd_pcm_runtime *runtime = substream->runtime;
  766. struct cs4281_dma *dma;
  767. dma = &chip->dma[0];
  768. dma->substream = substream;
  769. dma->left_slot = 0;
  770. dma->right_slot = 1;
  771. runtime->private_data = dma;
  772. runtime->hw = snd_cs4281_playback;
  773. /* should be detected from the AC'97 layer, but it seems
  774. that although CS4297A rev B reports 18-bit ADC resolution,
  775. samples are 20-bit */
  776. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
  777. return 0;
  778. }
  779. static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
  780. {
  781. struct cs4281 *chip = snd_pcm_substream_chip(substream);
  782. struct snd_pcm_runtime *runtime = substream->runtime;
  783. struct cs4281_dma *dma;
  784. dma = &chip->dma[1];
  785. dma->substream = substream;
  786. dma->left_slot = 10;
  787. dma->right_slot = 11;
  788. runtime->private_data = dma;
  789. runtime->hw = snd_cs4281_capture;
  790. /* should be detected from the AC'97 layer, but it seems
  791. that although CS4297A rev B reports 18-bit ADC resolution,
  792. samples are 20-bit */
  793. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
  794. return 0;
  795. }
  796. static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
  797. {
  798. struct cs4281_dma *dma = substream->runtime->private_data;
  799. dma->substream = NULL;
  800. return 0;
  801. }
  802. static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
  803. {
  804. struct cs4281_dma *dma = substream->runtime->private_data;
  805. dma->substream = NULL;
  806. return 0;
  807. }
  808. static const struct snd_pcm_ops snd_cs4281_playback_ops = {
  809. .open = snd_cs4281_playback_open,
  810. .close = snd_cs4281_playback_close,
  811. .prepare = snd_cs4281_playback_prepare,
  812. .trigger = snd_cs4281_trigger,
  813. .pointer = snd_cs4281_pointer,
  814. };
  815. static const struct snd_pcm_ops snd_cs4281_capture_ops = {
  816. .open = snd_cs4281_capture_open,
  817. .close = snd_cs4281_capture_close,
  818. .prepare = snd_cs4281_capture_prepare,
  819. .trigger = snd_cs4281_trigger,
  820. .pointer = snd_cs4281_pointer,
  821. };
  822. static int snd_cs4281_pcm(struct cs4281 *chip, int device)
  823. {
  824. struct snd_pcm *pcm;
  825. int err;
  826. err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
  827. if (err < 0)
  828. return err;
  829. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
  830. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
  831. pcm->private_data = chip;
  832. pcm->info_flags = 0;
  833. strcpy(pcm->name, "CS4281");
  834. chip->pcm = pcm;
  835. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
  836. 64*1024, 512*1024);
  837. return 0;
  838. }
  839. /*
  840. * Mixer section
  841. */
  842. #define CS_VOL_MASK 0x1f
  843. static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
  844. struct snd_ctl_elem_info *uinfo)
  845. {
  846. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  847. uinfo->count = 2;
  848. uinfo->value.integer.min = 0;
  849. uinfo->value.integer.max = CS_VOL_MASK;
  850. return 0;
  851. }
  852. static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
  853. struct snd_ctl_elem_value *ucontrol)
  854. {
  855. struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
  856. int regL = (kcontrol->private_value >> 16) & 0xffff;
  857. int regR = kcontrol->private_value & 0xffff;
  858. int volL, volR;
  859. volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
  860. volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
  861. ucontrol->value.integer.value[0] = volL;
  862. ucontrol->value.integer.value[1] = volR;
  863. return 0;
  864. }
  865. static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
  866. struct snd_ctl_elem_value *ucontrol)
  867. {
  868. struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
  869. int change = 0;
  870. int regL = (kcontrol->private_value >> 16) & 0xffff;
  871. int regR = kcontrol->private_value & 0xffff;
  872. int volL, volR;
  873. volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
  874. volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
  875. if (ucontrol->value.integer.value[0] != volL) {
  876. volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
  877. snd_cs4281_pokeBA0(chip, regL, volL);
  878. change = 1;
  879. }
  880. if (ucontrol->value.integer.value[1] != volR) {
  881. volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
  882. snd_cs4281_pokeBA0(chip, regR, volR);
  883. change = 1;
  884. }
  885. return change;
  886. }
  887. static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
  888. static const struct snd_kcontrol_new snd_cs4281_fm_vol =
  889. {
  890. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  891. .name = "Synth Playback Volume",
  892. .info = snd_cs4281_info_volume,
  893. .get = snd_cs4281_get_volume,
  894. .put = snd_cs4281_put_volume,
  895. .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
  896. .tlv = { .p = db_scale_dsp },
  897. };
  898. static const struct snd_kcontrol_new snd_cs4281_pcm_vol =
  899. {
  900. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  901. .name = "PCM Stream Playback Volume",
  902. .info = snd_cs4281_info_volume,
  903. .get = snd_cs4281_get_volume,
  904. .put = snd_cs4281_put_volume,
  905. .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
  906. .tlv = { .p = db_scale_dsp },
  907. };
  908. static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  909. {
  910. struct cs4281 *chip = bus->private_data;
  911. chip->ac97_bus = NULL;
  912. }
  913. static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
  914. {
  915. struct cs4281 *chip = ac97->private_data;
  916. if (ac97->num)
  917. chip->ac97_secondary = NULL;
  918. else
  919. chip->ac97 = NULL;
  920. }
  921. static int snd_cs4281_mixer(struct cs4281 *chip)
  922. {
  923. struct snd_card *card = chip->card;
  924. struct snd_ac97_template ac97;
  925. int err;
  926. static const struct snd_ac97_bus_ops ops = {
  927. .write = snd_cs4281_ac97_write,
  928. .read = snd_cs4281_ac97_read,
  929. };
  930. if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  931. return err;
  932. chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
  933. memset(&ac97, 0, sizeof(ac97));
  934. ac97.private_data = chip;
  935. ac97.private_free = snd_cs4281_mixer_free_ac97;
  936. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  937. return err;
  938. if (chip->dual_codec) {
  939. ac97.num = 1;
  940. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
  941. return err;
  942. }
  943. if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
  944. return err;
  945. if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
  946. return err;
  947. return 0;
  948. }
  949. /*
  950. * proc interface
  951. */
  952. static void snd_cs4281_proc_read(struct snd_info_entry *entry,
  953. struct snd_info_buffer *buffer)
  954. {
  955. struct cs4281 *chip = entry->private_data;
  956. snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
  957. snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
  958. snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
  959. }
  960. static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
  961. void *file_private_data,
  962. struct file *file, char __user *buf,
  963. size_t count, loff_t pos)
  964. {
  965. struct cs4281 *chip = entry->private_data;
  966. if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
  967. return -EFAULT;
  968. return count;
  969. }
  970. static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
  971. void *file_private_data,
  972. struct file *file, char __user *buf,
  973. size_t count, loff_t pos)
  974. {
  975. struct cs4281 *chip = entry->private_data;
  976. if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
  977. return -EFAULT;
  978. return count;
  979. }
  980. static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
  981. .read = snd_cs4281_BA0_read,
  982. };
  983. static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
  984. .read = snd_cs4281_BA1_read,
  985. };
  986. static void snd_cs4281_proc_init(struct cs4281 *chip)
  987. {
  988. struct snd_info_entry *entry;
  989. snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);
  990. if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
  991. entry->content = SNDRV_INFO_CONTENT_DATA;
  992. entry->private_data = chip;
  993. entry->c.ops = &snd_cs4281_proc_ops_BA0;
  994. entry->size = CS4281_BA0_SIZE;
  995. }
  996. if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
  997. entry->content = SNDRV_INFO_CONTENT_DATA;
  998. entry->private_data = chip;
  999. entry->c.ops = &snd_cs4281_proc_ops_BA1;
  1000. entry->size = CS4281_BA1_SIZE;
  1001. }
  1002. }
  1003. /*
  1004. * joystick support
  1005. */
  1006. #if IS_REACHABLE(CONFIG_GAMEPORT)
  1007. static void snd_cs4281_gameport_trigger(struct gameport *gameport)
  1008. {
  1009. struct cs4281 *chip = gameport_get_port_data(gameport);
  1010. if (snd_BUG_ON(!chip))
  1011. return;
  1012. snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
  1013. }
  1014. static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
  1015. {
  1016. struct cs4281 *chip = gameport_get_port_data(gameport);
  1017. if (snd_BUG_ON(!chip))
  1018. return 0;
  1019. return snd_cs4281_peekBA0(chip, BA0_JSPT);
  1020. }
  1021. #ifdef COOKED_MODE
  1022. static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
  1023. int *axes, int *buttons)
  1024. {
  1025. struct cs4281 *chip = gameport_get_port_data(gameport);
  1026. unsigned js1, js2, jst;
  1027. if (snd_BUG_ON(!chip))
  1028. return 0;
  1029. js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
  1030. js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
  1031. jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
  1032. *buttons = (~jst >> 4) & 0x0F;
  1033. axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
  1034. axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
  1035. axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
  1036. axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
  1037. for (jst = 0; jst < 4; ++jst)
  1038. if (axes[jst] == 0xFFFF) axes[jst] = -1;
  1039. return 0;
  1040. }
  1041. #else
  1042. #define snd_cs4281_gameport_cooked_read NULL
  1043. #endif
  1044. static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
  1045. {
  1046. switch (mode) {
  1047. #ifdef COOKED_MODE
  1048. case GAMEPORT_MODE_COOKED:
  1049. return 0;
  1050. #endif
  1051. case GAMEPORT_MODE_RAW:
  1052. return 0;
  1053. default:
  1054. return -1;
  1055. }
  1056. return 0;
  1057. }
  1058. static int snd_cs4281_create_gameport(struct cs4281 *chip)
  1059. {
  1060. struct gameport *gp;
  1061. chip->gameport = gp = gameport_allocate_port();
  1062. if (!gp) {
  1063. dev_err(chip->card->dev,
  1064. "cannot allocate memory for gameport\n");
  1065. return -ENOMEM;
  1066. }
  1067. gameport_set_name(gp, "CS4281 Gameport");
  1068. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  1069. gameport_set_dev_parent(gp, &chip->pci->dev);
  1070. gp->open = snd_cs4281_gameport_open;
  1071. gp->read = snd_cs4281_gameport_read;
  1072. gp->trigger = snd_cs4281_gameport_trigger;
  1073. gp->cooked_read = snd_cs4281_gameport_cooked_read;
  1074. gameport_set_port_data(gp, chip);
  1075. snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
  1076. snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
  1077. gameport_register_port(gp);
  1078. return 0;
  1079. }
  1080. static void snd_cs4281_free_gameport(struct cs4281 *chip)
  1081. {
  1082. if (chip->gameport) {
  1083. gameport_unregister_port(chip->gameport);
  1084. chip->gameport = NULL;
  1085. }
  1086. }
  1087. #else
  1088. static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
  1089. static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
  1090. #endif /* IS_REACHABLE(CONFIG_GAMEPORT) */
  1091. static int snd_cs4281_free(struct cs4281 *chip)
  1092. {
  1093. snd_cs4281_free_gameport(chip);
  1094. /* Mask interrupts */
  1095. snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
  1096. /* Stop the DLL Clock logic. */
  1097. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
  1098. /* Sound System Power Management - Turn Everything OFF */
  1099. snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
  1100. /* PCI interface - D3 state */
  1101. pci_set_power_state(chip->pci, PCI_D3hot);
  1102. if (chip->irq >= 0)
  1103. free_irq(chip->irq, chip);
  1104. iounmap(chip->ba0);
  1105. iounmap(chip->ba1);
  1106. pci_release_regions(chip->pci);
  1107. pci_disable_device(chip->pci);
  1108. kfree(chip);
  1109. return 0;
  1110. }
  1111. static int snd_cs4281_dev_free(struct snd_device *device)
  1112. {
  1113. struct cs4281 *chip = device->device_data;
  1114. return snd_cs4281_free(chip);
  1115. }
  1116. static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
  1117. static int snd_cs4281_create(struct snd_card *card,
  1118. struct pci_dev *pci,
  1119. struct cs4281 **rchip,
  1120. int dual_codec)
  1121. {
  1122. struct cs4281 *chip;
  1123. unsigned int tmp;
  1124. int err;
  1125. static const struct snd_device_ops ops = {
  1126. .dev_free = snd_cs4281_dev_free,
  1127. };
  1128. *rchip = NULL;
  1129. if ((err = pci_enable_device(pci)) < 0)
  1130. return err;
  1131. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1132. if (chip == NULL) {
  1133. pci_disable_device(pci);
  1134. return -ENOMEM;
  1135. }
  1136. spin_lock_init(&chip->reg_lock);
  1137. chip->card = card;
  1138. chip->pci = pci;
  1139. chip->irq = -1;
  1140. pci_set_master(pci);
  1141. if (dual_codec < 0 || dual_codec > 3) {
  1142. dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);
  1143. dual_codec = 0;
  1144. }
  1145. chip->dual_codec = dual_codec;
  1146. if ((err = pci_request_regions(pci, "CS4281")) < 0) {
  1147. kfree(chip);
  1148. pci_disable_device(pci);
  1149. return err;
  1150. }
  1151. chip->ba0_addr = pci_resource_start(pci, 0);
  1152. chip->ba1_addr = pci_resource_start(pci, 1);
  1153. chip->ba0 = pci_ioremap_bar(pci, 0);
  1154. chip->ba1 = pci_ioremap_bar(pci, 1);
  1155. if (!chip->ba0 || !chip->ba1) {
  1156. snd_cs4281_free(chip);
  1157. return -ENOMEM;
  1158. }
  1159. if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
  1160. KBUILD_MODNAME, chip)) {
  1161. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  1162. snd_cs4281_free(chip);
  1163. return -ENOMEM;
  1164. }
  1165. chip->irq = pci->irq;
  1166. card->sync_irq = chip->irq;
  1167. tmp = snd_cs4281_chip_init(chip);
  1168. if (tmp) {
  1169. snd_cs4281_free(chip);
  1170. return tmp;
  1171. }
  1172. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1173. snd_cs4281_free(chip);
  1174. return err;
  1175. }
  1176. snd_cs4281_proc_init(chip);
  1177. *rchip = chip;
  1178. return 0;
  1179. }
  1180. static int snd_cs4281_chip_init(struct cs4281 *chip)
  1181. {
  1182. unsigned int tmp;
  1183. unsigned long end_time;
  1184. int retry_count = 2;
  1185. /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
  1186. tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
  1187. if (tmp & BA0_EPPMC_FPDN)
  1188. snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
  1189. __retry:
  1190. tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
  1191. if (tmp != BA0_CFLR_DEFAULT) {
  1192. snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
  1193. tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
  1194. if (tmp != BA0_CFLR_DEFAULT) {
  1195. dev_err(chip->card->dev,
  1196. "CFLR setup failed (0x%x)\n", tmp);
  1197. return -EIO;
  1198. }
  1199. }
  1200. /* Set the 'Configuration Write Protect' register
  1201. * to 4281h. Allows vendor-defined configuration
  1202. * space between 0e4h and 0ffh to be written. */
  1203. snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
  1204. if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
  1205. dev_err(chip->card->dev,
  1206. "SERC1 AC'97 check failed (0x%x)\n", tmp);
  1207. return -EIO;
  1208. }
  1209. if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
  1210. dev_err(chip->card->dev,
  1211. "SERC2 AC'97 check failed (0x%x)\n", tmp);
  1212. return -EIO;
  1213. }
  1214. /* Sound System Power Management */
  1215. snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
  1216. BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
  1217. BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
  1218. /* Serial Port Power Management */
  1219. /* Blast the clock control register to zero so that the
  1220. * PLL starts out in a known state, and blast the master serial
  1221. * port control register to zero so that the serial ports also
  1222. * start out in a known state. */
  1223. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
  1224. snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
  1225. /* Make ESYN go to zero to turn off
  1226. * the Sync pulse on the AC97 link. */
  1227. snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
  1228. udelay(50);
  1229. /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
  1230. * spec) and then drive it high. This is done for non AC97 modes since
  1231. * there might be logic external to the CS4281 that uses the ARST# line
  1232. * for a reset. */
  1233. snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
  1234. udelay(50);
  1235. snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
  1236. msleep(50);
  1237. if (chip->dual_codec)
  1238. snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
  1239. /*
  1240. * Set the serial port timing configuration.
  1241. */
  1242. snd_cs4281_pokeBA0(chip, BA0_SERMC,
  1243. (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
  1244. BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
  1245. /*
  1246. * Start the DLL Clock logic.
  1247. */
  1248. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
  1249. msleep(50);
  1250. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
  1251. /*
  1252. * Wait for the DLL ready signal from the clock logic.
  1253. */
  1254. end_time = jiffies + HZ;
  1255. do {
  1256. /*
  1257. * Read the AC97 status register to see if we've seen a CODEC
  1258. * signal from the AC97 codec.
  1259. */
  1260. if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
  1261. goto __ok0;
  1262. schedule_timeout_uninterruptible(1);
  1263. } while (time_after_eq(end_time, jiffies));
  1264. dev_err(chip->card->dev, "DLLRDY not seen\n");
  1265. return -EIO;
  1266. __ok0:
  1267. /*
  1268. * The first thing we do here is to enable sync generation. As soon
  1269. * as we start receiving bit clock, we'll start producing the SYNC
  1270. * signal.
  1271. */
  1272. snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
  1273. /*
  1274. * Wait for the codec ready signal from the AC97 codec.
  1275. */
  1276. end_time = jiffies + HZ;
  1277. do {
  1278. /*
  1279. * Read the AC97 status register to see if we've seen a CODEC
  1280. * signal from the AC97 codec.
  1281. */
  1282. if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
  1283. goto __ok1;
  1284. schedule_timeout_uninterruptible(1);
  1285. } while (time_after_eq(end_time, jiffies));
  1286. dev_err(chip->card->dev,
  1287. "never read codec ready from AC'97 (0x%x)\n",
  1288. snd_cs4281_peekBA0(chip, BA0_ACSTS));
  1289. return -EIO;
  1290. __ok1:
  1291. if (chip->dual_codec) {
  1292. end_time = jiffies + HZ;
  1293. do {
  1294. if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
  1295. goto __codec2_ok;
  1296. schedule_timeout_uninterruptible(1);
  1297. } while (time_after_eq(end_time, jiffies));
  1298. dev_info(chip->card->dev,
  1299. "secondary codec doesn't respond. disable it...\n");
  1300. chip->dual_codec = 0;
  1301. __codec2_ok: ;
  1302. }
  1303. /*
  1304. * Assert the valid frame signal so that we can start sending commands
  1305. * to the AC97 codec.
  1306. */
  1307. snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
  1308. /*
  1309. * Wait until we've sampled input slots 3 and 4 as valid, meaning that
  1310. * the codec is pumping ADC data across the AC-link.
  1311. */
  1312. end_time = jiffies + HZ;
  1313. do {
  1314. /*
  1315. * Read the input slot valid register and see if input slots 3
  1316. * 4 are valid yet.
  1317. */
  1318. if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
  1319. goto __ok2;
  1320. schedule_timeout_uninterruptible(1);
  1321. } while (time_after_eq(end_time, jiffies));
  1322. if (--retry_count > 0)
  1323. goto __retry;
  1324. dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
  1325. return -EIO;
  1326. __ok2:
  1327. /*
  1328. * Now, assert valid frame and the slot 3 and 4 valid bits. This will
  1329. * commense the transfer of digital audio data to the AC97 codec.
  1330. */
  1331. snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
  1332. /*
  1333. * Initialize DMA structures
  1334. */
  1335. for (tmp = 0; tmp < 4; tmp++) {
  1336. struct cs4281_dma *dma = &chip->dma[tmp];
  1337. dma->regDBA = BA0_DBA0 + (tmp * 0x10);
  1338. dma->regDCA = BA0_DCA0 + (tmp * 0x10);
  1339. dma->regDBC = BA0_DBC0 + (tmp * 0x10);
  1340. dma->regDCC = BA0_DCC0 + (tmp * 0x10);
  1341. dma->regDMR = BA0_DMR0 + (tmp * 8);
  1342. dma->regDCR = BA0_DCR0 + (tmp * 8);
  1343. dma->regHDSR = BA0_HDSR0 + (tmp * 4);
  1344. dma->regFCR = BA0_FCR0 + (tmp * 4);
  1345. dma->regFSIC = BA0_FSIC0 + (tmp * 4);
  1346. dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
  1347. snd_cs4281_pokeBA0(chip, dma->regFCR,
  1348. BA0_FCR_LS(31) |
  1349. BA0_FCR_RS(31) |
  1350. BA0_FCR_SZ(CS4281_FIFO_SIZE) |
  1351. BA0_FCR_OF(dma->fifo_offset));
  1352. }
  1353. chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
  1354. chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
  1355. chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
  1356. chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
  1357. /* Activate wave playback FIFO for FM playback */
  1358. chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
  1359. BA0_FCR_RS(1) |
  1360. BA0_FCR_SZ(CS4281_FIFO_SIZE) |
  1361. BA0_FCR_OF(chip->dma[0].fifo_offset);
  1362. snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
  1363. snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
  1364. (chip->src_right_play_slot << 8) |
  1365. (chip->src_left_rec_slot << 16) |
  1366. (chip->src_right_rec_slot << 24));
  1367. /* Initialize digital volume */
  1368. snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
  1369. snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
  1370. /* Enable IRQs */
  1371. snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
  1372. /* Unmask interrupts */
  1373. snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
  1374. BA0_HISR_MIDI |
  1375. BA0_HISR_DMAI |
  1376. BA0_HISR_DMA(0) |
  1377. BA0_HISR_DMA(1) |
  1378. BA0_HISR_DMA(2) |
  1379. BA0_HISR_DMA(3)));
  1380. return 0;
  1381. }
  1382. /*
  1383. * MIDI section
  1384. */
  1385. static void snd_cs4281_midi_reset(struct cs4281 *chip)
  1386. {
  1387. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
  1388. udelay(100);
  1389. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1390. }
  1391. static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
  1392. {
  1393. struct cs4281 *chip = substream->rmidi->private_data;
  1394. spin_lock_irq(&chip->reg_lock);
  1395. chip->midcr |= BA0_MIDCR_RXE;
  1396. chip->midi_input = substream;
  1397. if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
  1398. snd_cs4281_midi_reset(chip);
  1399. } else {
  1400. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1401. }
  1402. spin_unlock_irq(&chip->reg_lock);
  1403. return 0;
  1404. }
  1405. static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
  1406. {
  1407. struct cs4281 *chip = substream->rmidi->private_data;
  1408. spin_lock_irq(&chip->reg_lock);
  1409. chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
  1410. chip->midi_input = NULL;
  1411. if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
  1412. snd_cs4281_midi_reset(chip);
  1413. } else {
  1414. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1415. }
  1416. chip->uartm &= ~CS4281_MODE_INPUT;
  1417. spin_unlock_irq(&chip->reg_lock);
  1418. return 0;
  1419. }
  1420. static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
  1421. {
  1422. struct cs4281 *chip = substream->rmidi->private_data;
  1423. spin_lock_irq(&chip->reg_lock);
  1424. chip->uartm |= CS4281_MODE_OUTPUT;
  1425. chip->midcr |= BA0_MIDCR_TXE;
  1426. chip->midi_output = substream;
  1427. if (!(chip->uartm & CS4281_MODE_INPUT)) {
  1428. snd_cs4281_midi_reset(chip);
  1429. } else {
  1430. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1431. }
  1432. spin_unlock_irq(&chip->reg_lock);
  1433. return 0;
  1434. }
  1435. static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
  1436. {
  1437. struct cs4281 *chip = substream->rmidi->private_data;
  1438. spin_lock_irq(&chip->reg_lock);
  1439. chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
  1440. chip->midi_output = NULL;
  1441. if (!(chip->uartm & CS4281_MODE_INPUT)) {
  1442. snd_cs4281_midi_reset(chip);
  1443. } else {
  1444. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1445. }
  1446. chip->uartm &= ~CS4281_MODE_OUTPUT;
  1447. spin_unlock_irq(&chip->reg_lock);
  1448. return 0;
  1449. }
  1450. static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
  1451. {
  1452. unsigned long flags;
  1453. struct cs4281 *chip = substream->rmidi->private_data;
  1454. spin_lock_irqsave(&chip->reg_lock, flags);
  1455. if (up) {
  1456. if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
  1457. chip->midcr |= BA0_MIDCR_RIE;
  1458. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1459. }
  1460. } else {
  1461. if (chip->midcr & BA0_MIDCR_RIE) {
  1462. chip->midcr &= ~BA0_MIDCR_RIE;
  1463. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1464. }
  1465. }
  1466. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1467. }
  1468. static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
  1469. {
  1470. unsigned long flags;
  1471. struct cs4281 *chip = substream->rmidi->private_data;
  1472. unsigned char byte;
  1473. spin_lock_irqsave(&chip->reg_lock, flags);
  1474. if (up) {
  1475. if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
  1476. chip->midcr |= BA0_MIDCR_TIE;
  1477. /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
  1478. while ((chip->midcr & BA0_MIDCR_TIE) &&
  1479. (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
  1480. if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
  1481. chip->midcr &= ~BA0_MIDCR_TIE;
  1482. } else {
  1483. snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
  1484. }
  1485. }
  1486. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1487. }
  1488. } else {
  1489. if (chip->midcr & BA0_MIDCR_TIE) {
  1490. chip->midcr &= ~BA0_MIDCR_TIE;
  1491. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1492. }
  1493. }
  1494. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1495. }
  1496. static const struct snd_rawmidi_ops snd_cs4281_midi_output =
  1497. {
  1498. .open = snd_cs4281_midi_output_open,
  1499. .close = snd_cs4281_midi_output_close,
  1500. .trigger = snd_cs4281_midi_output_trigger,
  1501. };
  1502. static const struct snd_rawmidi_ops snd_cs4281_midi_input =
  1503. {
  1504. .open = snd_cs4281_midi_input_open,
  1505. .close = snd_cs4281_midi_input_close,
  1506. .trigger = snd_cs4281_midi_input_trigger,
  1507. };
  1508. static int snd_cs4281_midi(struct cs4281 *chip, int device)
  1509. {
  1510. struct snd_rawmidi *rmidi;
  1511. int err;
  1512. if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
  1513. return err;
  1514. strcpy(rmidi->name, "CS4281");
  1515. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
  1516. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
  1517. rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
  1518. rmidi->private_data = chip;
  1519. chip->rmidi = rmidi;
  1520. return 0;
  1521. }
  1522. /*
  1523. * Interrupt handler
  1524. */
  1525. static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
  1526. {
  1527. struct cs4281 *chip = dev_id;
  1528. unsigned int status, dma, val;
  1529. struct cs4281_dma *cdma;
  1530. if (chip == NULL)
  1531. return IRQ_NONE;
  1532. status = snd_cs4281_peekBA0(chip, BA0_HISR);
  1533. if ((status & 0x7fffffff) == 0) {
  1534. snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
  1535. return IRQ_NONE;
  1536. }
  1537. if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
  1538. for (dma = 0; dma < 4; dma++)
  1539. if (status & BA0_HISR_DMA(dma)) {
  1540. cdma = &chip->dma[dma];
  1541. spin_lock(&chip->reg_lock);
  1542. /* ack DMA IRQ */
  1543. val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
  1544. /* workaround, sometimes CS4281 acknowledges */
  1545. /* end or middle transfer position twice */
  1546. cdma->frag++;
  1547. if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
  1548. cdma->frag--;
  1549. chip->spurious_dhtc_irq++;
  1550. spin_unlock(&chip->reg_lock);
  1551. continue;
  1552. }
  1553. if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
  1554. cdma->frag--;
  1555. chip->spurious_dtc_irq++;
  1556. spin_unlock(&chip->reg_lock);
  1557. continue;
  1558. }
  1559. spin_unlock(&chip->reg_lock);
  1560. snd_pcm_period_elapsed(cdma->substream);
  1561. }
  1562. }
  1563. if ((status & BA0_HISR_MIDI) && chip->rmidi) {
  1564. unsigned char c;
  1565. spin_lock(&chip->reg_lock);
  1566. while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
  1567. c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
  1568. if ((chip->midcr & BA0_MIDCR_RIE) == 0)
  1569. continue;
  1570. snd_rawmidi_receive(chip->midi_input, &c, 1);
  1571. }
  1572. while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
  1573. if ((chip->midcr & BA0_MIDCR_TIE) == 0)
  1574. break;
  1575. if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
  1576. chip->midcr &= ~BA0_MIDCR_TIE;
  1577. snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1578. break;
  1579. }
  1580. snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
  1581. }
  1582. spin_unlock(&chip->reg_lock);
  1583. }
  1584. /* EOI to the PCI part... reenables interrupts */
  1585. snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
  1586. return IRQ_HANDLED;
  1587. }
  1588. /*
  1589. * OPL3 command
  1590. */
  1591. static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
  1592. unsigned char val)
  1593. {
  1594. unsigned long flags;
  1595. struct cs4281 *chip = opl3->private_data;
  1596. void __iomem *port;
  1597. if (cmd & OPL3_RIGHT)
  1598. port = chip->ba0 + BA0_B1AP; /* right port */
  1599. else
  1600. port = chip->ba0 + BA0_B0AP; /* left port */
  1601. spin_lock_irqsave(&opl3->reg_lock, flags);
  1602. writel((unsigned int)cmd, port);
  1603. udelay(10);
  1604. writel((unsigned int)val, port + 4);
  1605. udelay(30);
  1606. spin_unlock_irqrestore(&opl3->reg_lock, flags);
  1607. }
  1608. static int snd_cs4281_probe(struct pci_dev *pci,
  1609. const struct pci_device_id *pci_id)
  1610. {
  1611. static int dev;
  1612. struct snd_card *card;
  1613. struct cs4281 *chip;
  1614. struct snd_opl3 *opl3;
  1615. int err;
  1616. if (dev >= SNDRV_CARDS)
  1617. return -ENODEV;
  1618. if (!enable[dev]) {
  1619. dev++;
  1620. return -ENOENT;
  1621. }
  1622. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  1623. 0, &card);
  1624. if (err < 0)
  1625. return err;
  1626. if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
  1627. snd_card_free(card);
  1628. return err;
  1629. }
  1630. card->private_data = chip;
  1631. if ((err = snd_cs4281_mixer(chip)) < 0) {
  1632. snd_card_free(card);
  1633. return err;
  1634. }
  1635. if ((err = snd_cs4281_pcm(chip, 0)) < 0) {
  1636. snd_card_free(card);
  1637. return err;
  1638. }
  1639. if ((err = snd_cs4281_midi(chip, 0)) < 0) {
  1640. snd_card_free(card);
  1641. return err;
  1642. }
  1643. if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
  1644. snd_card_free(card);
  1645. return err;
  1646. }
  1647. opl3->private_data = chip;
  1648. opl3->command = snd_cs4281_opl3_command;
  1649. snd_opl3_init(opl3);
  1650. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1651. snd_card_free(card);
  1652. return err;
  1653. }
  1654. snd_cs4281_create_gameport(chip);
  1655. strcpy(card->driver, "CS4281");
  1656. strcpy(card->shortname, "Cirrus Logic CS4281");
  1657. sprintf(card->longname, "%s at 0x%lx, irq %d",
  1658. card->shortname,
  1659. chip->ba0_addr,
  1660. chip->irq);
  1661. if ((err = snd_card_register(card)) < 0) {
  1662. snd_card_free(card);
  1663. return err;
  1664. }
  1665. pci_set_drvdata(pci, card);
  1666. dev++;
  1667. return 0;
  1668. }
  1669. static void snd_cs4281_remove(struct pci_dev *pci)
  1670. {
  1671. snd_card_free(pci_get_drvdata(pci));
  1672. }
  1673. /*
  1674. * Power Management
  1675. */
  1676. #ifdef CONFIG_PM_SLEEP
  1677. static const int saved_regs[SUSPEND_REGISTERS] = {
  1678. BA0_JSCTL,
  1679. BA0_GPIOR,
  1680. BA0_SSCR,
  1681. BA0_MIDCR,
  1682. BA0_SRCSA,
  1683. BA0_PASR,
  1684. BA0_CASR,
  1685. BA0_DACSR,
  1686. BA0_ADCSR,
  1687. BA0_FMLVC,
  1688. BA0_FMRVC,
  1689. BA0_PPLVC,
  1690. BA0_PPRVC,
  1691. };
  1692. #define CLKCR1_CKRA 0x00010000L
  1693. static int cs4281_suspend(struct device *dev)
  1694. {
  1695. struct snd_card *card = dev_get_drvdata(dev);
  1696. struct cs4281 *chip = card->private_data;
  1697. u32 ulCLK;
  1698. unsigned int i;
  1699. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1700. snd_ac97_suspend(chip->ac97);
  1701. snd_ac97_suspend(chip->ac97_secondary);
  1702. ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
  1703. ulCLK |= CLKCR1_CKRA;
  1704. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
  1705. /* Disable interrupts. */
  1706. snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
  1707. /* remember the status registers */
  1708. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  1709. if (saved_regs[i])
  1710. chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
  1711. /* Turn off the serial ports. */
  1712. snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
  1713. /* Power off FM, Joystick, AC link, */
  1714. snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
  1715. /* DLL off. */
  1716. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
  1717. /* AC link off. */
  1718. snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
  1719. ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
  1720. ulCLK &= ~CLKCR1_CKRA;
  1721. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
  1722. return 0;
  1723. }
  1724. static int cs4281_resume(struct device *dev)
  1725. {
  1726. struct snd_card *card = dev_get_drvdata(dev);
  1727. struct cs4281 *chip = card->private_data;
  1728. unsigned int i;
  1729. u32 ulCLK;
  1730. ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
  1731. ulCLK |= CLKCR1_CKRA;
  1732. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
  1733. snd_cs4281_chip_init(chip);
  1734. /* restore the status registers */
  1735. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  1736. if (saved_regs[i])
  1737. snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
  1738. snd_ac97_resume(chip->ac97);
  1739. snd_ac97_resume(chip->ac97_secondary);
  1740. ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
  1741. ulCLK &= ~CLKCR1_CKRA;
  1742. snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
  1743. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1744. return 0;
  1745. }
  1746. static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
  1747. #define CS4281_PM_OPS &cs4281_pm
  1748. #else
  1749. #define CS4281_PM_OPS NULL
  1750. #endif /* CONFIG_PM_SLEEP */
  1751. static struct pci_driver cs4281_driver = {
  1752. .name = KBUILD_MODNAME,
  1753. .id_table = snd_cs4281_ids,
  1754. .probe = snd_cs4281_probe,
  1755. .remove = snd_cs4281_remove,
  1756. .driver = {
  1757. .pm = CS4281_PM_OPS,
  1758. },
  1759. };
  1760. module_pci_driver(cs4281_driver);