cmipci.c 100 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for C-Media CMI8338 and 8738 PCI soundcards.
  4. * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
  5. */
  6. /* Does not work. Warning may block system in capture mode */
  7. /* #define USE_VAR48KRATE */
  8. #include <linux/io.h>
  9. #include <linux/delay.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/init.h>
  12. #include <linux/pci.h>
  13. #include <linux/slab.h>
  14. #include <linux/gameport.h>
  15. #include <linux/module.h>
  16. #include <linux/mutex.h>
  17. #include <sound/core.h>
  18. #include <sound/info.h>
  19. #include <sound/control.h>
  20. #include <sound/pcm.h>
  21. #include <sound/rawmidi.h>
  22. #include <sound/mpu401.h>
  23. #include <sound/opl3.h>
  24. #include <sound/sb.h>
  25. #include <sound/asoundef.h>
  26. #include <sound/initval.h>
  27. MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  28. MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
  29. MODULE_LICENSE("GPL");
  30. MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
  31. "{C-Media,CMI8738B},"
  32. "{C-Media,CMI8338A},"
  33. "{C-Media,CMI8338B}}");
  34. #if IS_REACHABLE(CONFIG_GAMEPORT)
  35. #define SUPPORT_JOYSTICK 1
  36. #endif
  37. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  38. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  39. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
  40. static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
  41. static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  42. static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  43. #ifdef SUPPORT_JOYSTICK
  44. static int joystick_port[SNDRV_CARDS];
  45. #endif
  46. module_param_array(index, int, NULL, 0444);
  47. MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
  48. module_param_array(id, charp, NULL, 0444);
  49. MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
  50. module_param_array(enable, bool, NULL, 0444);
  51. MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
  52. module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
  53. MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
  54. module_param_hw_array(fm_port, long, ioport, NULL, 0444);
  55. MODULE_PARM_DESC(fm_port, "FM port.");
  56. module_param_array(soft_ac3, bool, NULL, 0444);
  57. MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
  58. #ifdef SUPPORT_JOYSTICK
  59. module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
  60. MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  61. #endif
  62. /*
  63. * CM8x38 registers definition
  64. */
  65. #define CM_REG_FUNCTRL0 0x00
  66. #define CM_RST_CH1 0x00080000
  67. #define CM_RST_CH0 0x00040000
  68. #define CM_CHEN1 0x00020000 /* ch1: enable */
  69. #define CM_CHEN0 0x00010000 /* ch0: enable */
  70. #define CM_PAUSE1 0x00000008 /* ch1: pause */
  71. #define CM_PAUSE0 0x00000004 /* ch0: pause */
  72. #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
  73. #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
  74. #define CM_REG_FUNCTRL1 0x04
  75. #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
  76. #define CM_DSFC_SHIFT 13
  77. #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
  78. #define CM_ASFC_SHIFT 10
  79. #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
  80. #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
  81. #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
  82. #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
  83. #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
  84. #define CM_BREQ 0x00000010 /* bus master enabled */
  85. #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
  86. #define CM_UART_EN 0x00000004 /* legacy UART */
  87. #define CM_JYSTK_EN 0x00000002 /* legacy joystick */
  88. #define CM_ZVPORT 0x00000001 /* ZVPORT */
  89. #define CM_REG_CHFORMAT 0x08
  90. #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
  91. #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
  92. #define CM_CHB3D 0x20000000 /* 4 channels */
  93. #define CM_CHIP_MASK1 0x1f000000
  94. #define CM_CHIP_037 0x01000000
  95. #define CM_SETLAT48 0x00800000 /* set latency timer 48h */
  96. #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
  97. #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
  98. #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
  99. #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
  100. #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
  101. /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
  102. #define CM_ADCBITLEN_MASK 0x0000C000
  103. #define CM_ADCBITLEN_16 0x00000000
  104. #define CM_ADCBITLEN_15 0x00004000
  105. #define CM_ADCBITLEN_14 0x00008000
  106. #define CM_ADCBITLEN_13 0x0000C000
  107. #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
  108. #define CM_ADCDACLEN_060 0x00000000
  109. #define CM_ADCDACLEN_066 0x00001000
  110. #define CM_ADCDACLEN_130 0x00002000
  111. #define CM_ADCDACLEN_280 0x00003000
  112. #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
  113. #define CM_ADCDLEN_ORIGINAL 0x00000000
  114. #define CM_ADCDLEN_EXTRA 0x00001000
  115. #define CM_ADCDLEN_24K 0x00002000
  116. #define CM_ADCDLEN_WEIGHT 0x00003000
  117. #define CM_CH1_SRATE_176K 0x00000800
  118. #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
  119. #define CM_CH1_SRATE_88K 0x00000400
  120. #define CM_CH0_SRATE_176K 0x00000200
  121. #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
  122. #define CM_CH0_SRATE_88K 0x00000100
  123. #define CM_CH0_SRATE_128K 0x00000300
  124. #define CM_CH0_SRATE_MASK 0x00000300
  125. #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
  126. #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
  127. #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
  128. #define CM_SPDLOCKED 0x00000010
  129. #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
  130. #define CM_CH1FMT_SHIFT 2
  131. #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
  132. #define CM_CH0FMT_SHIFT 0
  133. #define CM_REG_INT_HLDCLR 0x0C
  134. #define CM_CHIP_MASK2 0xff000000
  135. #define CM_CHIP_8768 0x20000000
  136. #define CM_CHIP_055 0x08000000
  137. #define CM_CHIP_039 0x04000000
  138. #define CM_CHIP_039_6CH 0x01000000
  139. #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
  140. #define CM_TDMA_INT_EN 0x00040000
  141. #define CM_CH1_INT_EN 0x00020000
  142. #define CM_CH0_INT_EN 0x00010000
  143. #define CM_REG_INT_STATUS 0x10
  144. #define CM_INTR 0x80000000
  145. #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
  146. #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
  147. #define CM_UARTINT 0x00010000
  148. #define CM_LTDMAINT 0x00008000
  149. #define CM_HTDMAINT 0x00004000
  150. #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
  151. #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
  152. #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
  153. #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
  154. #define CM_CH1BUSY 0x00000008
  155. #define CM_CH0BUSY 0x00000004
  156. #define CM_CHINT1 0x00000002
  157. #define CM_CHINT0 0x00000001
  158. #define CM_REG_LEGACY_CTRL 0x14
  159. #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
  160. #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
  161. #define CM_VMPU_330 0x00000000
  162. #define CM_VMPU_320 0x20000000
  163. #define CM_VMPU_310 0x40000000
  164. #define CM_VMPU_300 0x60000000
  165. #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
  166. #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
  167. #define CM_VSBSEL_220 0x00000000
  168. #define CM_VSBSEL_240 0x04000000
  169. #define CM_VSBSEL_260 0x08000000
  170. #define CM_VSBSEL_280 0x0C000000
  171. #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
  172. #define CM_FMSEL_388 0x00000000
  173. #define CM_FMSEL_3C8 0x01000000
  174. #define CM_FMSEL_3E0 0x02000000
  175. #define CM_FMSEL_3E8 0x03000000
  176. #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
  177. #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
  178. #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
  179. #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
  180. #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
  181. #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
  182. #define CM_C_EECS 0x00040000
  183. #define CM_C_EEDI46 0x00020000
  184. #define CM_C_EECK46 0x00010000
  185. #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
  186. #define CM_CENTR2LIN 0x00004000 /* line-in as center out */
  187. #define CM_BASE2LIN 0x00002000 /* line-in as bass out */
  188. #define CM_EXBASEN 0x00001000 /* external bass input enable */
  189. #define CM_REG_MISC_CTRL 0x18
  190. #define CM_PWD 0x80000000 /* power down */
  191. #define CM_RESET 0x40000000
  192. #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
  193. #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
  194. #define CM_TXVX 0x08000000 /* model 037? */
  195. #define CM_N4SPK3D 0x04000000 /* copy front to rear */
  196. #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
  197. #define CM_SPDIF48K 0x01000000 /* write */
  198. #define CM_SPATUS48K 0x01000000 /* read */
  199. #define CM_ENDBDAC 0x00800000 /* enable double dac */
  200. #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
  201. #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
  202. #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
  203. #define CM_FM_EN 0x00080000 /* enable legacy FM */
  204. #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
  205. #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
  206. #define CM_VIDWPDSB 0x00010000 /* model 037? */
  207. #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
  208. #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
  209. #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
  210. #define CM_VIDWPPRT 0x00002000 /* model 037? */
  211. #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
  212. #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
  213. #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
  214. #define CM_ENCENTER 0x00000080
  215. #define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
  216. #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
  217. #define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
  218. #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
  219. #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
  220. #define CM_UPDDMA_2048 0x00000000
  221. #define CM_UPDDMA_1024 0x00000004
  222. #define CM_UPDDMA_512 0x00000008
  223. #define CM_UPDDMA_256 0x0000000C
  224. #define CM_TWAIT_MASK 0x00000003 /* model 037 */
  225. #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
  226. #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
  227. #define CM_REG_TDMA_POSITION 0x1C
  228. #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
  229. #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
  230. /* byte */
  231. #define CM_REG_MIXER0 0x20
  232. #define CM_REG_SBVR 0x20 /* write: sb16 version */
  233. #define CM_REG_DEV 0x20 /* read: hardware device version */
  234. #define CM_REG_MIXER21 0x21
  235. #define CM_UNKNOWN_21_MASK 0x78 /* ? */
  236. #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
  237. #define CM_PROINV 0x02 /* SBPro left/right channel switching */
  238. #define CM_X_SB16 0x01 /* SB16 compatible */
  239. #define CM_REG_SB16_DATA 0x22
  240. #define CM_REG_SB16_ADDR 0x23
  241. #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
  242. #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
  243. #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
  244. #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
  245. #define CM_REG_MIXER1 0x24
  246. #define CM_FMMUTE 0x80 /* mute FM */
  247. #define CM_FMMUTE_SHIFT 7
  248. #define CM_WSMUTE 0x40 /* mute PCM */
  249. #define CM_WSMUTE_SHIFT 6
  250. #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
  251. #define CM_REAR2LIN_SHIFT 5
  252. #define CM_REAR2FRONT 0x10 /* exchange rear/front */
  253. #define CM_REAR2FRONT_SHIFT 4
  254. #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
  255. #define CM_WAVEINL_SHIFT 3
  256. #define CM_WAVEINR 0x04 /* digical wave rec. right */
  257. #define CM_WAVEINR_SHIFT 2
  258. #define CM_X3DEN 0x02 /* 3D surround enable */
  259. #define CM_X3DEN_SHIFT 1
  260. #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
  261. #define CM_CDPLAY_SHIFT 0
  262. #define CM_REG_MIXER2 0x25
  263. #define CM_RAUXREN 0x80 /* AUX right capture */
  264. #define CM_RAUXREN_SHIFT 7
  265. #define CM_RAUXLEN 0x40 /* AUX left capture */
  266. #define CM_RAUXLEN_SHIFT 6
  267. #define CM_VAUXRM 0x20 /* AUX right mute */
  268. #define CM_VAUXRM_SHIFT 5
  269. #define CM_VAUXLM 0x10 /* AUX left mute */
  270. #define CM_VAUXLM_SHIFT 4
  271. #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
  272. #define CM_VADMIC_SHIFT 1
  273. #define CM_MICGAINZ 0x01 /* mic boost */
  274. #define CM_MICGAINZ_SHIFT 0
  275. #define CM_REG_AUX_VOL 0x26
  276. #define CM_VAUXL_MASK 0xf0
  277. #define CM_VAUXR_MASK 0x0f
  278. #define CM_REG_MISC 0x27
  279. #define CM_UNKNOWN_27_MASK 0xd8 /* ? */
  280. #define CM_XGPO1 0x20
  281. // #define CM_XGPBIO 0x04
  282. #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
  283. #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
  284. #define CM_SPDVALID 0x02 /* spdif input valid check */
  285. #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
  286. #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
  287. /*
  288. * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
  289. * or identical with AC97 codec?
  290. */
  291. #define CM_REG_EXTERN_CODEC CM_REG_AC97
  292. /*
  293. * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
  294. */
  295. #define CM_REG_MPU_PCI 0x40
  296. /*
  297. * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
  298. */
  299. #define CM_REG_FM_PCI 0x50
  300. /*
  301. * access from SB-mixer port
  302. */
  303. #define CM_REG_EXTENT_IND 0xf0
  304. #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
  305. #define CM_VPHONE_SHIFT 5
  306. #define CM_VPHOM 0x10 /* Phone mute control */
  307. #define CM_VSPKM 0x08 /* Speaker mute control, default high */
  308. #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
  309. #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
  310. #define CM_VADMIC3 0x01 /* Mic record boost */
  311. /*
  312. * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
  313. * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
  314. * unit (readonly?).
  315. */
  316. #define CM_REG_PLL 0xf8
  317. /*
  318. * extended registers
  319. */
  320. #define CM_REG_CH0_FRAME1 0x80 /* write: base address */
  321. #define CM_REG_CH0_FRAME2 0x84 /* read: current address */
  322. #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
  323. #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
  324. #define CM_REG_EXT_MISC 0x90
  325. #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
  326. #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
  327. #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
  328. #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
  329. #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
  330. #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
  331. #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
  332. #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
  333. /*
  334. * size of i/o region
  335. */
  336. #define CM_EXTENT_CODEC 0x100
  337. #define CM_EXTENT_MIDI 0x2
  338. #define CM_EXTENT_SYNTH 0x4
  339. /*
  340. * channels for playback / capture
  341. */
  342. #define CM_CH_PLAY 0
  343. #define CM_CH_CAPT 1
  344. /*
  345. * flags to check device open/close
  346. */
  347. #define CM_OPEN_NONE 0
  348. #define CM_OPEN_CH_MASK 0x01
  349. #define CM_OPEN_DAC 0x10
  350. #define CM_OPEN_ADC 0x20
  351. #define CM_OPEN_SPDIF 0x40
  352. #define CM_OPEN_MCHAN 0x80
  353. #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
  354. #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
  355. #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
  356. #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
  357. #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
  358. #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
  359. #if CM_CH_PLAY == 1
  360. #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
  361. #define CM_PLAYBACK_SPDF CM_SPDF_1
  362. #define CM_CAPTURE_SPDF CM_SPDF_0
  363. #else
  364. #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
  365. #define CM_PLAYBACK_SPDF CM_SPDF_0
  366. #define CM_CAPTURE_SPDF CM_SPDF_1
  367. #endif
  368. /*
  369. * driver data
  370. */
  371. struct cmipci_pcm {
  372. struct snd_pcm_substream *substream;
  373. u8 running; /* dac/adc running? */
  374. u8 fmt; /* format bits */
  375. u8 is_dac;
  376. u8 needs_silencing;
  377. unsigned int dma_size; /* in frames */
  378. unsigned int shift;
  379. unsigned int ch; /* channel (0/1) */
  380. unsigned int offset; /* physical address of the buffer */
  381. };
  382. /* mixer elements toggled/resumed during ac3 playback */
  383. struct cmipci_mixer_auto_switches {
  384. const char *name; /* switch to toggle */
  385. int toggle_on; /* value to change when ac3 mode */
  386. };
  387. static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
  388. {"PCM Playback Switch", 0},
  389. {"IEC958 Output Switch", 1},
  390. {"IEC958 Mix Analog", 0},
  391. // {"IEC958 Out To DAC", 1}, // no longer used
  392. {"IEC958 Loop", 0},
  393. };
  394. #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
  395. struct cmipci {
  396. struct snd_card *card;
  397. struct pci_dev *pci;
  398. unsigned int device; /* device ID */
  399. int irq;
  400. unsigned long iobase;
  401. unsigned int ctrl; /* FUNCTRL0 current value */
  402. struct snd_pcm *pcm; /* DAC/ADC PCM */
  403. struct snd_pcm *pcm2; /* 2nd DAC */
  404. struct snd_pcm *pcm_spdif; /* SPDIF */
  405. int chip_version;
  406. int max_channels;
  407. unsigned int can_ac3_sw: 1;
  408. unsigned int can_ac3_hw: 1;
  409. unsigned int can_multi_ch: 1;
  410. unsigned int can_96k: 1; /* samplerate above 48k */
  411. unsigned int do_soft_ac3: 1;
  412. unsigned int spdif_playback_avail: 1; /* spdif ready? */
  413. unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
  414. int spdif_counter; /* for software AC3 */
  415. unsigned int dig_status;
  416. unsigned int dig_pcm_status;
  417. struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
  418. int opened[2]; /* open mode */
  419. struct mutex open_mutex;
  420. unsigned int mixer_insensitive: 1;
  421. struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
  422. int mixer_res_status[CM_SAVED_MIXERS];
  423. struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
  424. /* external MIDI */
  425. struct snd_rawmidi *rmidi;
  426. #ifdef SUPPORT_JOYSTICK
  427. struct gameport *gameport;
  428. #endif
  429. spinlock_t reg_lock;
  430. #ifdef CONFIG_PM_SLEEP
  431. unsigned int saved_regs[0x20];
  432. unsigned char saved_mixers[0x20];
  433. #endif
  434. };
  435. /* read/write operations for dword register */
  436. static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
  437. {
  438. outl(data, cm->iobase + cmd);
  439. }
  440. static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
  441. {
  442. return inl(cm->iobase + cmd);
  443. }
  444. /* read/write operations for word register */
  445. static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
  446. {
  447. outw(data, cm->iobase + cmd);
  448. }
  449. static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
  450. {
  451. return inw(cm->iobase + cmd);
  452. }
  453. /* read/write operations for byte register */
  454. static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
  455. {
  456. outb(data, cm->iobase + cmd);
  457. }
  458. static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
  459. {
  460. return inb(cm->iobase + cmd);
  461. }
  462. /* bit operations for dword register */
  463. static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
  464. {
  465. unsigned int val, oval;
  466. val = oval = inl(cm->iobase + cmd);
  467. val |= flag;
  468. if (val == oval)
  469. return 0;
  470. outl(val, cm->iobase + cmd);
  471. return 1;
  472. }
  473. static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
  474. {
  475. unsigned int val, oval;
  476. val = oval = inl(cm->iobase + cmd);
  477. val &= ~flag;
  478. if (val == oval)
  479. return 0;
  480. outl(val, cm->iobase + cmd);
  481. return 1;
  482. }
  483. /* bit operations for byte register */
  484. static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
  485. {
  486. unsigned char val, oval;
  487. val = oval = inb(cm->iobase + cmd);
  488. val |= flag;
  489. if (val == oval)
  490. return 0;
  491. outb(val, cm->iobase + cmd);
  492. return 1;
  493. }
  494. static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
  495. {
  496. unsigned char val, oval;
  497. val = oval = inb(cm->iobase + cmd);
  498. val &= ~flag;
  499. if (val == oval)
  500. return 0;
  501. outb(val, cm->iobase + cmd);
  502. return 1;
  503. }
  504. /*
  505. * PCM interface
  506. */
  507. /*
  508. * calculate frequency
  509. */
  510. static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
  511. static unsigned int snd_cmipci_rate_freq(unsigned int rate)
  512. {
  513. unsigned int i;
  514. for (i = 0; i < ARRAY_SIZE(rates); i++) {
  515. if (rates[i] == rate)
  516. return i;
  517. }
  518. snd_BUG();
  519. return 0;
  520. }
  521. #ifdef USE_VAR48KRATE
  522. /*
  523. * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
  524. * does it this way .. maybe not. Never get any information from C-Media about
  525. * that <werner@suse.de>.
  526. */
  527. static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
  528. {
  529. unsigned int delta, tolerance;
  530. int xm, xn, xr;
  531. for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
  532. rate <<= 1;
  533. *n = -1;
  534. if (*r > 0xff)
  535. goto out;
  536. tolerance = rate*CM_TOLERANCE_RATE;
  537. for (xn = (1+2); xn < (0x1f+2); xn++) {
  538. for (xm = (1+2); xm < (0xff+2); xm++) {
  539. xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
  540. if (xr < rate)
  541. delta = rate - xr;
  542. else
  543. delta = xr - rate;
  544. /*
  545. * If we found one, remember this,
  546. * and try to find a closer one
  547. */
  548. if (delta < tolerance) {
  549. tolerance = delta;
  550. *m = xm - 2;
  551. *n = xn - 2;
  552. }
  553. }
  554. }
  555. out:
  556. return (*n > -1);
  557. }
  558. /*
  559. * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
  560. * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
  561. * at the register CM_REG_FUNCTRL1 (0x04).
  562. * Problem: other ways are also possible (any information about that?)
  563. */
  564. static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
  565. {
  566. unsigned int reg = CM_REG_PLL + slot;
  567. /*
  568. * Guess that this programs at reg. 0x04 the pos 15:13/12:10
  569. * for DSFC/ASFC (000 up to 111).
  570. */
  571. /* FIXME: Init (Do we've to set an other register first before programming?) */
  572. /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
  573. snd_cmipci_write_b(cm, reg, rate>>8);
  574. snd_cmipci_write_b(cm, reg, rate&0xff);
  575. /* FIXME: Setup (Do we've to set an other register first to enable this?) */
  576. }
  577. #endif /* USE_VAR48KRATE */
  578. static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
  579. struct snd_pcm_hw_params *hw_params)
  580. {
  581. struct cmipci *cm = snd_pcm_substream_chip(substream);
  582. if (params_channels(hw_params) > 2) {
  583. mutex_lock(&cm->open_mutex);
  584. if (cm->opened[CM_CH_PLAY]) {
  585. mutex_unlock(&cm->open_mutex);
  586. return -EBUSY;
  587. }
  588. /* reserve the channel A */
  589. cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
  590. mutex_unlock(&cm->open_mutex);
  591. }
  592. return 0;
  593. }
  594. static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
  595. {
  596. int reset = CM_RST_CH0 << (cm->channel[ch].ch);
  597. snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
  598. snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
  599. udelay(10);
  600. }
  601. /*
  602. */
  603. static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
  604. static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
  605. .count = 3,
  606. .list = hw_channels,
  607. .mask = 0,
  608. };
  609. static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
  610. .count = 4,
  611. .list = hw_channels,
  612. .mask = 0,
  613. };
  614. static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
  615. .count = 5,
  616. .list = hw_channels,
  617. .mask = 0,
  618. };
  619. static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
  620. {
  621. if (channels > 2) {
  622. if (!cm->can_multi_ch || !rec->ch)
  623. return -EINVAL;
  624. if (rec->fmt != 0x03) /* stereo 16bit only */
  625. return -EINVAL;
  626. }
  627. if (cm->can_multi_ch) {
  628. spin_lock_irq(&cm->reg_lock);
  629. if (channels > 2) {
  630. snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
  631. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
  632. } else {
  633. snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
  634. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
  635. }
  636. if (channels == 8)
  637. snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
  638. else
  639. snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
  640. if (channels == 6) {
  641. snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
  642. snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
  643. } else {
  644. snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
  645. snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
  646. }
  647. if (channels == 4)
  648. snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
  649. else
  650. snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
  651. spin_unlock_irq(&cm->reg_lock);
  652. }
  653. return 0;
  654. }
  655. /*
  656. * prepare playback/capture channel
  657. * channel to be used must have been set in rec->ch.
  658. */
  659. static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
  660. struct snd_pcm_substream *substream)
  661. {
  662. unsigned int reg, freq, freq_ext, val;
  663. unsigned int period_size;
  664. struct snd_pcm_runtime *runtime = substream->runtime;
  665. rec->fmt = 0;
  666. rec->shift = 0;
  667. if (snd_pcm_format_width(runtime->format) >= 16) {
  668. rec->fmt |= 0x02;
  669. if (snd_pcm_format_width(runtime->format) > 16)
  670. rec->shift++; /* 24/32bit */
  671. }
  672. if (runtime->channels > 1)
  673. rec->fmt |= 0x01;
  674. if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
  675. dev_dbg(cm->card->dev, "cannot set dac channels\n");
  676. return -EINVAL;
  677. }
  678. rec->offset = runtime->dma_addr;
  679. /* buffer and period sizes in frame */
  680. rec->dma_size = runtime->buffer_size << rec->shift;
  681. period_size = runtime->period_size << rec->shift;
  682. if (runtime->channels > 2) {
  683. /* multi-channels */
  684. rec->dma_size = (rec->dma_size * runtime->channels) / 2;
  685. period_size = (period_size * runtime->channels) / 2;
  686. }
  687. spin_lock_irq(&cm->reg_lock);
  688. /* set buffer address */
  689. reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
  690. snd_cmipci_write(cm, reg, rec->offset);
  691. /* program sample counts */
  692. reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
  693. snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
  694. snd_cmipci_write_w(cm, reg + 2, period_size - 1);
  695. /* set adc/dac flag */
  696. val = rec->ch ? CM_CHADC1 : CM_CHADC0;
  697. if (rec->is_dac)
  698. cm->ctrl &= ~val;
  699. else
  700. cm->ctrl |= val;
  701. snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
  702. /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
  703. /* set sample rate */
  704. freq = 0;
  705. freq_ext = 0;
  706. if (runtime->rate > 48000)
  707. switch (runtime->rate) {
  708. case 88200: freq_ext = CM_CH0_SRATE_88K; break;
  709. case 96000: freq_ext = CM_CH0_SRATE_96K; break;
  710. case 128000: freq_ext = CM_CH0_SRATE_128K; break;
  711. default: snd_BUG(); break;
  712. }
  713. else
  714. freq = snd_cmipci_rate_freq(runtime->rate);
  715. val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
  716. if (rec->ch) {
  717. val &= ~CM_DSFC_MASK;
  718. val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
  719. } else {
  720. val &= ~CM_ASFC_MASK;
  721. val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
  722. }
  723. snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
  724. dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
  725. /* set format */
  726. val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
  727. if (rec->ch) {
  728. val &= ~CM_CH1FMT_MASK;
  729. val |= rec->fmt << CM_CH1FMT_SHIFT;
  730. } else {
  731. val &= ~CM_CH0FMT_MASK;
  732. val |= rec->fmt << CM_CH0FMT_SHIFT;
  733. }
  734. if (cm->can_96k) {
  735. val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
  736. val |= freq_ext << (rec->ch * 2);
  737. }
  738. snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
  739. dev_dbg(cm->card->dev, "chformat = %08x\n", val);
  740. if (!rec->is_dac && cm->chip_version) {
  741. if (runtime->rate > 44100)
  742. snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
  743. else
  744. snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
  745. }
  746. rec->running = 0;
  747. spin_unlock_irq(&cm->reg_lock);
  748. return 0;
  749. }
  750. /*
  751. * PCM trigger/stop
  752. */
  753. static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
  754. int cmd)
  755. {
  756. unsigned int inthld, chen, reset, pause;
  757. int result = 0;
  758. inthld = CM_CH0_INT_EN << rec->ch;
  759. chen = CM_CHEN0 << rec->ch;
  760. reset = CM_RST_CH0 << rec->ch;
  761. pause = CM_PAUSE0 << rec->ch;
  762. spin_lock(&cm->reg_lock);
  763. switch (cmd) {
  764. case SNDRV_PCM_TRIGGER_START:
  765. rec->running = 1;
  766. /* set interrupt */
  767. snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
  768. cm->ctrl |= chen;
  769. /* enable channel */
  770. snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
  771. dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
  772. break;
  773. case SNDRV_PCM_TRIGGER_STOP:
  774. rec->running = 0;
  775. /* disable interrupt */
  776. snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
  777. /* reset */
  778. cm->ctrl &= ~chen;
  779. snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
  780. snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
  781. rec->needs_silencing = rec->is_dac;
  782. break;
  783. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  784. case SNDRV_PCM_TRIGGER_SUSPEND:
  785. cm->ctrl |= pause;
  786. snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
  787. break;
  788. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  789. case SNDRV_PCM_TRIGGER_RESUME:
  790. cm->ctrl &= ~pause;
  791. snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
  792. break;
  793. default:
  794. result = -EINVAL;
  795. break;
  796. }
  797. spin_unlock(&cm->reg_lock);
  798. return result;
  799. }
  800. /*
  801. * return the current pointer
  802. */
  803. static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
  804. struct snd_pcm_substream *substream)
  805. {
  806. size_t ptr;
  807. unsigned int reg, rem, tries;
  808. if (!rec->running)
  809. return 0;
  810. #if 1 // this seems better..
  811. reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
  812. for (tries = 0; tries < 3; tries++) {
  813. rem = snd_cmipci_read_w(cm, reg);
  814. if (rem < rec->dma_size)
  815. goto ok;
  816. }
  817. dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
  818. return SNDRV_PCM_POS_XRUN;
  819. ok:
  820. ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
  821. #else
  822. reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
  823. ptr = snd_cmipci_read(cm, reg) - rec->offset;
  824. ptr = bytes_to_frames(substream->runtime, ptr);
  825. #endif
  826. if (substream->runtime->channels > 2)
  827. ptr = (ptr * 2) / substream->runtime->channels;
  828. return ptr;
  829. }
  830. /*
  831. * playback
  832. */
  833. static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
  834. int cmd)
  835. {
  836. struct cmipci *cm = snd_pcm_substream_chip(substream);
  837. return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
  838. }
  839. static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
  840. {
  841. struct cmipci *cm = snd_pcm_substream_chip(substream);
  842. return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
  843. }
  844. /*
  845. * capture
  846. */
  847. static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
  848. int cmd)
  849. {
  850. struct cmipci *cm = snd_pcm_substream_chip(substream);
  851. return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
  852. }
  853. static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
  854. {
  855. struct cmipci *cm = snd_pcm_substream_chip(substream);
  856. return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
  857. }
  858. /*
  859. * hw preparation for spdif
  860. */
  861. static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
  862. struct snd_ctl_elem_info *uinfo)
  863. {
  864. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  865. uinfo->count = 1;
  866. return 0;
  867. }
  868. static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
  869. struct snd_ctl_elem_value *ucontrol)
  870. {
  871. struct cmipci *chip = snd_kcontrol_chip(kcontrol);
  872. int i;
  873. spin_lock_irq(&chip->reg_lock);
  874. for (i = 0; i < 4; i++)
  875. ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
  876. spin_unlock_irq(&chip->reg_lock);
  877. return 0;
  878. }
  879. static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
  880. struct snd_ctl_elem_value *ucontrol)
  881. {
  882. struct cmipci *chip = snd_kcontrol_chip(kcontrol);
  883. int i, change;
  884. unsigned int val;
  885. val = 0;
  886. spin_lock_irq(&chip->reg_lock);
  887. for (i = 0; i < 4; i++)
  888. val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
  889. change = val != chip->dig_status;
  890. chip->dig_status = val;
  891. spin_unlock_irq(&chip->reg_lock);
  892. return change;
  893. }
  894. static const struct snd_kcontrol_new snd_cmipci_spdif_default =
  895. {
  896. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  897. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  898. .info = snd_cmipci_spdif_default_info,
  899. .get = snd_cmipci_spdif_default_get,
  900. .put = snd_cmipci_spdif_default_put
  901. };
  902. static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
  903. struct snd_ctl_elem_info *uinfo)
  904. {
  905. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  906. uinfo->count = 1;
  907. return 0;
  908. }
  909. static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
  910. struct snd_ctl_elem_value *ucontrol)
  911. {
  912. ucontrol->value.iec958.status[0] = 0xff;
  913. ucontrol->value.iec958.status[1] = 0xff;
  914. ucontrol->value.iec958.status[2] = 0xff;
  915. ucontrol->value.iec958.status[3] = 0xff;
  916. return 0;
  917. }
  918. static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
  919. {
  920. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  921. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  922. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  923. .info = snd_cmipci_spdif_mask_info,
  924. .get = snd_cmipci_spdif_mask_get,
  925. };
  926. static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
  927. struct snd_ctl_elem_info *uinfo)
  928. {
  929. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  930. uinfo->count = 1;
  931. return 0;
  932. }
  933. static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
  934. struct snd_ctl_elem_value *ucontrol)
  935. {
  936. struct cmipci *chip = snd_kcontrol_chip(kcontrol);
  937. int i;
  938. spin_lock_irq(&chip->reg_lock);
  939. for (i = 0; i < 4; i++)
  940. ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
  941. spin_unlock_irq(&chip->reg_lock);
  942. return 0;
  943. }
  944. static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
  945. struct snd_ctl_elem_value *ucontrol)
  946. {
  947. struct cmipci *chip = snd_kcontrol_chip(kcontrol);
  948. int i, change;
  949. unsigned int val;
  950. val = 0;
  951. spin_lock_irq(&chip->reg_lock);
  952. for (i = 0; i < 4; i++)
  953. val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
  954. change = val != chip->dig_pcm_status;
  955. chip->dig_pcm_status = val;
  956. spin_unlock_irq(&chip->reg_lock);
  957. return change;
  958. }
  959. static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
  960. {
  961. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  962. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  963. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  964. .info = snd_cmipci_spdif_stream_info,
  965. .get = snd_cmipci_spdif_stream_get,
  966. .put = snd_cmipci_spdif_stream_put
  967. };
  968. /*
  969. */
  970. /* save mixer setting and mute for AC3 playback */
  971. static int save_mixer_state(struct cmipci *cm)
  972. {
  973. if (! cm->mixer_insensitive) {
  974. struct snd_ctl_elem_value *val;
  975. unsigned int i;
  976. val = kmalloc(sizeof(*val), GFP_KERNEL);
  977. if (!val)
  978. return -ENOMEM;
  979. for (i = 0; i < CM_SAVED_MIXERS; i++) {
  980. struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
  981. if (ctl) {
  982. int event;
  983. memset(val, 0, sizeof(*val));
  984. ctl->get(ctl, val);
  985. cm->mixer_res_status[i] = val->value.integer.value[0];
  986. val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
  987. event = SNDRV_CTL_EVENT_MASK_INFO;
  988. if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
  989. ctl->put(ctl, val); /* toggle */
  990. event |= SNDRV_CTL_EVENT_MASK_VALUE;
  991. }
  992. ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  993. snd_ctl_notify(cm->card, event, &ctl->id);
  994. }
  995. }
  996. kfree(val);
  997. cm->mixer_insensitive = 1;
  998. }
  999. return 0;
  1000. }
  1001. /* restore the previously saved mixer status */
  1002. static void restore_mixer_state(struct cmipci *cm)
  1003. {
  1004. if (cm->mixer_insensitive) {
  1005. struct snd_ctl_elem_value *val;
  1006. unsigned int i;
  1007. val = kmalloc(sizeof(*val), GFP_KERNEL);
  1008. if (!val)
  1009. return;
  1010. cm->mixer_insensitive = 0; /* at first clear this;
  1011. otherwise the changes will be ignored */
  1012. for (i = 0; i < CM_SAVED_MIXERS; i++) {
  1013. struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
  1014. if (ctl) {
  1015. int event;
  1016. memset(val, 0, sizeof(*val));
  1017. ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  1018. ctl->get(ctl, val);
  1019. event = SNDRV_CTL_EVENT_MASK_INFO;
  1020. if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
  1021. val->value.integer.value[0] = cm->mixer_res_status[i];
  1022. ctl->put(ctl, val);
  1023. event |= SNDRV_CTL_EVENT_MASK_VALUE;
  1024. }
  1025. snd_ctl_notify(cm->card, event, &ctl->id);
  1026. }
  1027. }
  1028. kfree(val);
  1029. }
  1030. }
  1031. /* spinlock held! */
  1032. static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
  1033. {
  1034. if (do_ac3) {
  1035. /* AC3EN for 037 */
  1036. snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
  1037. /* AC3EN for 039 */
  1038. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
  1039. if (cm->can_ac3_hw) {
  1040. /* SPD24SEL for 037, 0x02 */
  1041. /* SPD24SEL for 039, 0x20, but cannot be set */
  1042. snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
  1043. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
  1044. } else { /* can_ac3_sw */
  1045. /* SPD32SEL for 037 & 039, 0x20 */
  1046. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
  1047. /* set 176K sample rate to fix 033 HW bug */
  1048. if (cm->chip_version == 33) {
  1049. if (rate >= 48000) {
  1050. snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
  1051. } else {
  1052. snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
  1053. }
  1054. }
  1055. }
  1056. } else {
  1057. snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
  1058. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
  1059. if (cm->can_ac3_hw) {
  1060. /* chip model >= 37 */
  1061. if (snd_pcm_format_width(subs->runtime->format) > 16) {
  1062. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
  1063. snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
  1064. } else {
  1065. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
  1066. snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
  1067. }
  1068. } else {
  1069. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
  1070. snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
  1071. snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
  1072. }
  1073. }
  1074. }
  1075. static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
  1076. {
  1077. int rate, err;
  1078. rate = subs->runtime->rate;
  1079. if (up && do_ac3)
  1080. if ((err = save_mixer_state(cm)) < 0)
  1081. return err;
  1082. spin_lock_irq(&cm->reg_lock);
  1083. cm->spdif_playback_avail = up;
  1084. if (up) {
  1085. /* they are controlled via "IEC958 Output Switch" */
  1086. /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
  1087. /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
  1088. if (cm->spdif_playback_enabled)
  1089. snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
  1090. setup_ac3(cm, subs, do_ac3, rate);
  1091. if (rate == 48000 || rate == 96000)
  1092. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
  1093. else
  1094. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
  1095. if (rate > 48000)
  1096. snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
  1097. else
  1098. snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
  1099. } else {
  1100. /* they are controlled via "IEC958 Output Switch" */
  1101. /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
  1102. /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
  1103. snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
  1104. snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
  1105. setup_ac3(cm, subs, 0, 0);
  1106. }
  1107. spin_unlock_irq(&cm->reg_lock);
  1108. return 0;
  1109. }
  1110. /*
  1111. * preparation
  1112. */
  1113. /* playback - enable spdif only on the certain condition */
  1114. static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
  1115. {
  1116. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1117. int rate = substream->runtime->rate;
  1118. int err, do_spdif, do_ac3 = 0;
  1119. do_spdif = (rate >= 44100 && rate <= 96000 &&
  1120. substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
  1121. substream->runtime->channels == 2);
  1122. if (do_spdif && cm->can_ac3_hw)
  1123. do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
  1124. if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
  1125. return err;
  1126. return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
  1127. }
  1128. /* playback (via device #2) - enable spdif always */
  1129. static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
  1130. {
  1131. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1132. int err, do_ac3;
  1133. if (cm->can_ac3_hw)
  1134. do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
  1135. else
  1136. do_ac3 = 1; /* doesn't matter */
  1137. if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
  1138. return err;
  1139. return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
  1140. }
  1141. /*
  1142. * Apparently, the samples last played on channel A stay in some buffer, even
  1143. * after the channel is reset, and get added to the data for the rear DACs when
  1144. * playing a multichannel stream on channel B. This is likely to generate
  1145. * wraparounds and thus distortions.
  1146. * To avoid this, we play at least one zero sample after the actual stream has
  1147. * stopped.
  1148. */
  1149. static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
  1150. {
  1151. struct snd_pcm_runtime *runtime = rec->substream->runtime;
  1152. unsigned int reg, val;
  1153. if (rec->needs_silencing && runtime && runtime->dma_area) {
  1154. /* set up a small silence buffer */
  1155. memset(runtime->dma_area, 0, PAGE_SIZE);
  1156. reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
  1157. val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
  1158. snd_cmipci_write(cm, reg, val);
  1159. /* configure for 16 bits, 2 channels, 8 kHz */
  1160. if (runtime->channels > 2)
  1161. set_dac_channels(cm, rec, 2);
  1162. spin_lock_irq(&cm->reg_lock);
  1163. val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
  1164. val &= ~(CM_ASFC_MASK << (rec->ch * 3));
  1165. val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
  1166. snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
  1167. val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
  1168. val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
  1169. val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
  1170. if (cm->can_96k)
  1171. val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
  1172. snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
  1173. /* start stream (we don't need interrupts) */
  1174. cm->ctrl |= CM_CHEN0 << rec->ch;
  1175. snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
  1176. spin_unlock_irq(&cm->reg_lock);
  1177. msleep(1);
  1178. /* stop and reset stream */
  1179. spin_lock_irq(&cm->reg_lock);
  1180. cm->ctrl &= ~(CM_CHEN0 << rec->ch);
  1181. val = CM_RST_CH0 << rec->ch;
  1182. snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
  1183. snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
  1184. spin_unlock_irq(&cm->reg_lock);
  1185. rec->needs_silencing = 0;
  1186. }
  1187. }
  1188. static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
  1189. {
  1190. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1191. setup_spdif_playback(cm, substream, 0, 0);
  1192. restore_mixer_state(cm);
  1193. snd_cmipci_silence_hack(cm, &cm->channel[0]);
  1194. return 0;
  1195. }
  1196. static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
  1197. {
  1198. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1199. snd_cmipci_silence_hack(cm, &cm->channel[1]);
  1200. return 0;
  1201. }
  1202. /* capture */
  1203. static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
  1204. {
  1205. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1206. return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
  1207. }
  1208. /* capture with spdif (via device #2) */
  1209. static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
  1210. {
  1211. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1212. spin_lock_irq(&cm->reg_lock);
  1213. snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
  1214. if (cm->can_96k) {
  1215. if (substream->runtime->rate > 48000)
  1216. snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
  1217. else
  1218. snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
  1219. }
  1220. if (snd_pcm_format_width(substream->runtime->format) > 16)
  1221. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
  1222. else
  1223. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
  1224. spin_unlock_irq(&cm->reg_lock);
  1225. return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
  1226. }
  1227. static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
  1228. {
  1229. struct cmipci *cm = snd_pcm_substream_chip(subs);
  1230. spin_lock_irq(&cm->reg_lock);
  1231. snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
  1232. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
  1233. spin_unlock_irq(&cm->reg_lock);
  1234. return 0;
  1235. }
  1236. /*
  1237. * interrupt handler
  1238. */
  1239. static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
  1240. {
  1241. struct cmipci *cm = dev_id;
  1242. unsigned int status, mask = 0;
  1243. /* fastpath out, to ease interrupt sharing */
  1244. status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
  1245. if (!(status & CM_INTR))
  1246. return IRQ_NONE;
  1247. /* acknowledge interrupt */
  1248. spin_lock(&cm->reg_lock);
  1249. if (status & CM_CHINT0)
  1250. mask |= CM_CH0_INT_EN;
  1251. if (status & CM_CHINT1)
  1252. mask |= CM_CH1_INT_EN;
  1253. snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
  1254. snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
  1255. spin_unlock(&cm->reg_lock);
  1256. if (cm->rmidi && (status & CM_UARTINT))
  1257. snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
  1258. if (cm->pcm) {
  1259. if ((status & CM_CHINT0) && cm->channel[0].running)
  1260. snd_pcm_period_elapsed(cm->channel[0].substream);
  1261. if ((status & CM_CHINT1) && cm->channel[1].running)
  1262. snd_pcm_period_elapsed(cm->channel[1].substream);
  1263. }
  1264. return IRQ_HANDLED;
  1265. }
  1266. /*
  1267. * h/w infos
  1268. */
  1269. /* playback on channel A */
  1270. static const struct snd_pcm_hardware snd_cmipci_playback =
  1271. {
  1272. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1273. SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
  1274. SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
  1275. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  1276. .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
  1277. .rate_min = 5512,
  1278. .rate_max = 48000,
  1279. .channels_min = 1,
  1280. .channels_max = 2,
  1281. .buffer_bytes_max = (128*1024),
  1282. .period_bytes_min = 64,
  1283. .period_bytes_max = (128*1024),
  1284. .periods_min = 2,
  1285. .periods_max = 1024,
  1286. .fifo_size = 0,
  1287. };
  1288. /* capture on channel B */
  1289. static const struct snd_pcm_hardware snd_cmipci_capture =
  1290. {
  1291. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1292. SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
  1293. SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
  1294. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  1295. .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
  1296. .rate_min = 5512,
  1297. .rate_max = 48000,
  1298. .channels_min = 1,
  1299. .channels_max = 2,
  1300. .buffer_bytes_max = (128*1024),
  1301. .period_bytes_min = 64,
  1302. .period_bytes_max = (128*1024),
  1303. .periods_min = 2,
  1304. .periods_max = 1024,
  1305. .fifo_size = 0,
  1306. };
  1307. /* playback on channel B - stereo 16bit only? */
  1308. static const struct snd_pcm_hardware snd_cmipci_playback2 =
  1309. {
  1310. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1311. SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
  1312. SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
  1313. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1314. .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
  1315. .rate_min = 5512,
  1316. .rate_max = 48000,
  1317. .channels_min = 2,
  1318. .channels_max = 2,
  1319. .buffer_bytes_max = (128*1024),
  1320. .period_bytes_min = 64,
  1321. .period_bytes_max = (128*1024),
  1322. .periods_min = 2,
  1323. .periods_max = 1024,
  1324. .fifo_size = 0,
  1325. };
  1326. /* spdif playback on channel A */
  1327. static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
  1328. {
  1329. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1330. SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
  1331. SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
  1332. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1333. .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
  1334. .rate_min = 44100,
  1335. .rate_max = 48000,
  1336. .channels_min = 2,
  1337. .channels_max = 2,
  1338. .buffer_bytes_max = (128*1024),
  1339. .period_bytes_min = 64,
  1340. .period_bytes_max = (128*1024),
  1341. .periods_min = 2,
  1342. .periods_max = 1024,
  1343. .fifo_size = 0,
  1344. };
  1345. /* spdif playback on channel A (32bit, IEC958 subframes) */
  1346. static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
  1347. {
  1348. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1349. SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
  1350. SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
  1351. .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
  1352. .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
  1353. .rate_min = 44100,
  1354. .rate_max = 48000,
  1355. .channels_min = 2,
  1356. .channels_max = 2,
  1357. .buffer_bytes_max = (128*1024),
  1358. .period_bytes_min = 64,
  1359. .period_bytes_max = (128*1024),
  1360. .periods_min = 2,
  1361. .periods_max = 1024,
  1362. .fifo_size = 0,
  1363. };
  1364. /* spdif capture on channel B */
  1365. static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
  1366. {
  1367. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1368. SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
  1369. SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
  1370. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  1371. SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
  1372. .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
  1373. .rate_min = 44100,
  1374. .rate_max = 48000,
  1375. .channels_min = 2,
  1376. .channels_max = 2,
  1377. .buffer_bytes_max = (128*1024),
  1378. .period_bytes_min = 64,
  1379. .period_bytes_max = (128*1024),
  1380. .periods_min = 2,
  1381. .periods_max = 1024,
  1382. .fifo_size = 0,
  1383. };
  1384. static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
  1385. 32000, 44100, 48000, 88200, 96000, 128000 };
  1386. static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  1387. .count = ARRAY_SIZE(rate_constraints),
  1388. .list = rate_constraints,
  1389. .mask = 0,
  1390. };
  1391. /*
  1392. * check device open/close
  1393. */
  1394. static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
  1395. {
  1396. int ch = mode & CM_OPEN_CH_MASK;
  1397. /* FIXME: a file should wait until the device becomes free
  1398. * when it's opened on blocking mode. however, since the current
  1399. * pcm framework doesn't pass file pointer before actually opened,
  1400. * we can't know whether blocking mode or not in open callback..
  1401. */
  1402. mutex_lock(&cm->open_mutex);
  1403. if (cm->opened[ch]) {
  1404. mutex_unlock(&cm->open_mutex);
  1405. return -EBUSY;
  1406. }
  1407. cm->opened[ch] = mode;
  1408. cm->channel[ch].substream = subs;
  1409. if (! (mode & CM_OPEN_DAC)) {
  1410. /* disable dual DAC mode */
  1411. cm->channel[ch].is_dac = 0;
  1412. spin_lock_irq(&cm->reg_lock);
  1413. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
  1414. spin_unlock_irq(&cm->reg_lock);
  1415. }
  1416. mutex_unlock(&cm->open_mutex);
  1417. return 0;
  1418. }
  1419. static void close_device_check(struct cmipci *cm, int mode)
  1420. {
  1421. int ch = mode & CM_OPEN_CH_MASK;
  1422. mutex_lock(&cm->open_mutex);
  1423. if (cm->opened[ch] == mode) {
  1424. if (cm->channel[ch].substream) {
  1425. snd_cmipci_ch_reset(cm, ch);
  1426. cm->channel[ch].running = 0;
  1427. cm->channel[ch].substream = NULL;
  1428. }
  1429. cm->opened[ch] = 0;
  1430. if (! cm->channel[ch].is_dac) {
  1431. /* enable dual DAC mode again */
  1432. cm->channel[ch].is_dac = 1;
  1433. spin_lock_irq(&cm->reg_lock);
  1434. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
  1435. spin_unlock_irq(&cm->reg_lock);
  1436. }
  1437. }
  1438. mutex_unlock(&cm->open_mutex);
  1439. }
  1440. /*
  1441. */
  1442. static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
  1443. {
  1444. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1445. struct snd_pcm_runtime *runtime = substream->runtime;
  1446. int err;
  1447. if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
  1448. return err;
  1449. runtime->hw = snd_cmipci_playback;
  1450. if (cm->chip_version == 68) {
  1451. runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
  1452. SNDRV_PCM_RATE_96000;
  1453. runtime->hw.rate_max = 96000;
  1454. } else if (cm->chip_version == 55) {
  1455. err = snd_pcm_hw_constraint_list(runtime, 0,
  1456. SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1457. if (err < 0)
  1458. return err;
  1459. runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
  1460. runtime->hw.rate_max = 128000;
  1461. }
  1462. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
  1463. cm->dig_pcm_status = cm->dig_status;
  1464. return 0;
  1465. }
  1466. static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
  1467. {
  1468. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1469. struct snd_pcm_runtime *runtime = substream->runtime;
  1470. int err;
  1471. if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
  1472. return err;
  1473. runtime->hw = snd_cmipci_capture;
  1474. if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
  1475. runtime->hw.rate_min = 41000;
  1476. runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
  1477. } else if (cm->chip_version == 55) {
  1478. err = snd_pcm_hw_constraint_list(runtime, 0,
  1479. SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1480. if (err < 0)
  1481. return err;
  1482. runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
  1483. runtime->hw.rate_max = 128000;
  1484. }
  1485. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
  1486. return 0;
  1487. }
  1488. static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
  1489. {
  1490. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1491. struct snd_pcm_runtime *runtime = substream->runtime;
  1492. int err;
  1493. if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
  1494. return err;
  1495. runtime->hw = snd_cmipci_playback2;
  1496. mutex_lock(&cm->open_mutex);
  1497. if (! cm->opened[CM_CH_PLAY]) {
  1498. if (cm->can_multi_ch) {
  1499. runtime->hw.channels_max = cm->max_channels;
  1500. if (cm->max_channels == 4)
  1501. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
  1502. else if (cm->max_channels == 6)
  1503. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
  1504. else if (cm->max_channels == 8)
  1505. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
  1506. }
  1507. }
  1508. mutex_unlock(&cm->open_mutex);
  1509. if (cm->chip_version == 68) {
  1510. runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
  1511. SNDRV_PCM_RATE_96000;
  1512. runtime->hw.rate_max = 96000;
  1513. } else if (cm->chip_version == 55) {
  1514. err = snd_pcm_hw_constraint_list(runtime, 0,
  1515. SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1516. if (err < 0)
  1517. return err;
  1518. runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
  1519. runtime->hw.rate_max = 128000;
  1520. }
  1521. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
  1522. return 0;
  1523. }
  1524. static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
  1525. {
  1526. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1527. struct snd_pcm_runtime *runtime = substream->runtime;
  1528. int err;
  1529. if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
  1530. return err;
  1531. if (cm->can_ac3_hw) {
  1532. runtime->hw = snd_cmipci_playback_spdif;
  1533. if (cm->chip_version >= 37) {
  1534. runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
  1535. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1536. }
  1537. if (cm->can_96k) {
  1538. runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
  1539. SNDRV_PCM_RATE_96000;
  1540. runtime->hw.rate_max = 96000;
  1541. }
  1542. } else {
  1543. runtime->hw = snd_cmipci_playback_iec958_subframe;
  1544. }
  1545. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
  1546. cm->dig_pcm_status = cm->dig_status;
  1547. return 0;
  1548. }
  1549. static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
  1550. {
  1551. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1552. struct snd_pcm_runtime *runtime = substream->runtime;
  1553. int err;
  1554. if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
  1555. return err;
  1556. runtime->hw = snd_cmipci_capture_spdif;
  1557. if (cm->can_96k && !(cm->chip_version == 68)) {
  1558. runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
  1559. SNDRV_PCM_RATE_96000;
  1560. runtime->hw.rate_max = 96000;
  1561. }
  1562. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
  1563. return 0;
  1564. }
  1565. /*
  1566. */
  1567. static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
  1568. {
  1569. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1570. close_device_check(cm, CM_OPEN_PLAYBACK);
  1571. return 0;
  1572. }
  1573. static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
  1574. {
  1575. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1576. close_device_check(cm, CM_OPEN_CAPTURE);
  1577. return 0;
  1578. }
  1579. static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
  1580. {
  1581. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1582. close_device_check(cm, CM_OPEN_PLAYBACK2);
  1583. close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
  1584. return 0;
  1585. }
  1586. static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
  1587. {
  1588. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1589. close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
  1590. return 0;
  1591. }
  1592. static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
  1593. {
  1594. struct cmipci *cm = snd_pcm_substream_chip(substream);
  1595. close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
  1596. return 0;
  1597. }
  1598. /*
  1599. */
  1600. static const struct snd_pcm_ops snd_cmipci_playback_ops = {
  1601. .open = snd_cmipci_playback_open,
  1602. .close = snd_cmipci_playback_close,
  1603. .hw_free = snd_cmipci_playback_hw_free,
  1604. .prepare = snd_cmipci_playback_prepare,
  1605. .trigger = snd_cmipci_playback_trigger,
  1606. .pointer = snd_cmipci_playback_pointer,
  1607. };
  1608. static const struct snd_pcm_ops snd_cmipci_capture_ops = {
  1609. .open = snd_cmipci_capture_open,
  1610. .close = snd_cmipci_capture_close,
  1611. .prepare = snd_cmipci_capture_prepare,
  1612. .trigger = snd_cmipci_capture_trigger,
  1613. .pointer = snd_cmipci_capture_pointer,
  1614. };
  1615. static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
  1616. .open = snd_cmipci_playback2_open,
  1617. .close = snd_cmipci_playback2_close,
  1618. .hw_params = snd_cmipci_playback2_hw_params,
  1619. .hw_free = snd_cmipci_playback2_hw_free,
  1620. .prepare = snd_cmipci_capture_prepare, /* channel B */
  1621. .trigger = snd_cmipci_capture_trigger, /* channel B */
  1622. .pointer = snd_cmipci_capture_pointer, /* channel B */
  1623. };
  1624. static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
  1625. .open = snd_cmipci_playback_spdif_open,
  1626. .close = snd_cmipci_playback_spdif_close,
  1627. .hw_free = snd_cmipci_playback_hw_free,
  1628. .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
  1629. .trigger = snd_cmipci_playback_trigger,
  1630. .pointer = snd_cmipci_playback_pointer,
  1631. };
  1632. static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
  1633. .open = snd_cmipci_capture_spdif_open,
  1634. .close = snd_cmipci_capture_spdif_close,
  1635. .hw_free = snd_cmipci_capture_spdif_hw_free,
  1636. .prepare = snd_cmipci_capture_spdif_prepare,
  1637. .trigger = snd_cmipci_capture_trigger,
  1638. .pointer = snd_cmipci_capture_pointer,
  1639. };
  1640. /*
  1641. */
  1642. static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
  1643. {
  1644. struct snd_pcm *pcm;
  1645. int err;
  1646. err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
  1647. if (err < 0)
  1648. return err;
  1649. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
  1650. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
  1651. pcm->private_data = cm;
  1652. pcm->info_flags = 0;
  1653. strcpy(pcm->name, "C-Media PCI DAC/ADC");
  1654. cm->pcm = pcm;
  1655. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1656. &cm->pci->dev, 64*1024, 128*1024);
  1657. return 0;
  1658. }
  1659. static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
  1660. {
  1661. struct snd_pcm *pcm;
  1662. int err;
  1663. err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
  1664. if (err < 0)
  1665. return err;
  1666. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
  1667. pcm->private_data = cm;
  1668. pcm->info_flags = 0;
  1669. strcpy(pcm->name, "C-Media PCI 2nd DAC");
  1670. cm->pcm2 = pcm;
  1671. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1672. &cm->pci->dev, 64*1024, 128*1024);
  1673. return 0;
  1674. }
  1675. static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
  1676. {
  1677. struct snd_pcm *pcm;
  1678. int err;
  1679. err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
  1680. if (err < 0)
  1681. return err;
  1682. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
  1683. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
  1684. pcm->private_data = cm;
  1685. pcm->info_flags = 0;
  1686. strcpy(pcm->name, "C-Media PCI IEC958");
  1687. cm->pcm_spdif = pcm;
  1688. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1689. &cm->pci->dev, 64*1024, 128*1024);
  1690. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1691. snd_pcm_alt_chmaps, cm->max_channels, 0,
  1692. NULL);
  1693. if (err < 0)
  1694. return err;
  1695. return 0;
  1696. }
  1697. /*
  1698. * mixer interface:
  1699. * - CM8338/8738 has a compatible mixer interface with SB16, but
  1700. * lack of some elements like tone control, i/o gain and AGC.
  1701. * - Access to native registers:
  1702. * - A 3D switch
  1703. * - Output mute switches
  1704. */
  1705. static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
  1706. {
  1707. outb(idx, s->iobase + CM_REG_SB16_ADDR);
  1708. outb(data, s->iobase + CM_REG_SB16_DATA);
  1709. }
  1710. static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
  1711. {
  1712. unsigned char v;
  1713. outb(idx, s->iobase + CM_REG_SB16_ADDR);
  1714. v = inb(s->iobase + CM_REG_SB16_DATA);
  1715. return v;
  1716. }
  1717. /*
  1718. * general mixer element
  1719. */
  1720. struct cmipci_sb_reg {
  1721. unsigned int left_reg, right_reg;
  1722. unsigned int left_shift, right_shift;
  1723. unsigned int mask;
  1724. unsigned int invert: 1;
  1725. unsigned int stereo: 1;
  1726. };
  1727. #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
  1728. ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
  1729. #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
  1730. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  1731. .info = snd_cmipci_info_volume, \
  1732. .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
  1733. .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
  1734. }
  1735. #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
  1736. #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
  1737. #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
  1738. #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
  1739. static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
  1740. {
  1741. r->left_reg = val & 0xff;
  1742. r->right_reg = (val >> 8) & 0xff;
  1743. r->left_shift = (val >> 16) & 0x07;
  1744. r->right_shift = (val >> 19) & 0x07;
  1745. r->invert = (val >> 22) & 1;
  1746. r->stereo = (val >> 23) & 1;
  1747. r->mask = (val >> 24) & 0xff;
  1748. }
  1749. static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
  1750. struct snd_ctl_elem_info *uinfo)
  1751. {
  1752. struct cmipci_sb_reg reg;
  1753. cmipci_sb_reg_decode(&reg, kcontrol->private_value);
  1754. uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1755. uinfo->count = reg.stereo + 1;
  1756. uinfo->value.integer.min = 0;
  1757. uinfo->value.integer.max = reg.mask;
  1758. return 0;
  1759. }
  1760. static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
  1761. struct snd_ctl_elem_value *ucontrol)
  1762. {
  1763. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  1764. struct cmipci_sb_reg reg;
  1765. int val;
  1766. cmipci_sb_reg_decode(&reg, kcontrol->private_value);
  1767. spin_lock_irq(&cm->reg_lock);
  1768. val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
  1769. if (reg.invert)
  1770. val = reg.mask - val;
  1771. ucontrol->value.integer.value[0] = val;
  1772. if (reg.stereo) {
  1773. val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
  1774. if (reg.invert)
  1775. val = reg.mask - val;
  1776. ucontrol->value.integer.value[1] = val;
  1777. }
  1778. spin_unlock_irq(&cm->reg_lock);
  1779. return 0;
  1780. }
  1781. static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
  1782. struct snd_ctl_elem_value *ucontrol)
  1783. {
  1784. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  1785. struct cmipci_sb_reg reg;
  1786. int change;
  1787. int left, right, oleft, oright;
  1788. cmipci_sb_reg_decode(&reg, kcontrol->private_value);
  1789. left = ucontrol->value.integer.value[0] & reg.mask;
  1790. if (reg.invert)
  1791. left = reg.mask - left;
  1792. left <<= reg.left_shift;
  1793. if (reg.stereo) {
  1794. right = ucontrol->value.integer.value[1] & reg.mask;
  1795. if (reg.invert)
  1796. right = reg.mask - right;
  1797. right <<= reg.right_shift;
  1798. } else
  1799. right = 0;
  1800. spin_lock_irq(&cm->reg_lock);
  1801. oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
  1802. left |= oleft & ~(reg.mask << reg.left_shift);
  1803. change = left != oleft;
  1804. if (reg.stereo) {
  1805. if (reg.left_reg != reg.right_reg) {
  1806. snd_cmipci_mixer_write(cm, reg.left_reg, left);
  1807. oright = snd_cmipci_mixer_read(cm, reg.right_reg);
  1808. } else
  1809. oright = left;
  1810. right |= oright & ~(reg.mask << reg.right_shift);
  1811. change |= right != oright;
  1812. snd_cmipci_mixer_write(cm, reg.right_reg, right);
  1813. } else
  1814. snd_cmipci_mixer_write(cm, reg.left_reg, left);
  1815. spin_unlock_irq(&cm->reg_lock);
  1816. return change;
  1817. }
  1818. /*
  1819. * input route (left,right) -> (left,right)
  1820. */
  1821. #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
  1822. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  1823. .info = snd_cmipci_info_input_sw, \
  1824. .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
  1825. .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
  1826. }
  1827. static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
  1828. struct snd_ctl_elem_info *uinfo)
  1829. {
  1830. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1831. uinfo->count = 4;
  1832. uinfo->value.integer.min = 0;
  1833. uinfo->value.integer.max = 1;
  1834. return 0;
  1835. }
  1836. static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
  1837. struct snd_ctl_elem_value *ucontrol)
  1838. {
  1839. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  1840. struct cmipci_sb_reg reg;
  1841. int val1, val2;
  1842. cmipci_sb_reg_decode(&reg, kcontrol->private_value);
  1843. spin_lock_irq(&cm->reg_lock);
  1844. val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
  1845. val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
  1846. spin_unlock_irq(&cm->reg_lock);
  1847. ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
  1848. ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
  1849. ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
  1850. ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
  1851. return 0;
  1852. }
  1853. static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
  1854. struct snd_ctl_elem_value *ucontrol)
  1855. {
  1856. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  1857. struct cmipci_sb_reg reg;
  1858. int change;
  1859. int val1, val2, oval1, oval2;
  1860. cmipci_sb_reg_decode(&reg, kcontrol->private_value);
  1861. spin_lock_irq(&cm->reg_lock);
  1862. oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
  1863. oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
  1864. val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
  1865. val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
  1866. val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
  1867. val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
  1868. val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
  1869. val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
  1870. change = val1 != oval1 || val2 != oval2;
  1871. snd_cmipci_mixer_write(cm, reg.left_reg, val1);
  1872. snd_cmipci_mixer_write(cm, reg.right_reg, val2);
  1873. spin_unlock_irq(&cm->reg_lock);
  1874. return change;
  1875. }
  1876. /*
  1877. * native mixer switches/volumes
  1878. */
  1879. #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
  1880. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  1881. .info = snd_cmipci_info_native_mixer, \
  1882. .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
  1883. .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
  1884. }
  1885. #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
  1886. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  1887. .info = snd_cmipci_info_native_mixer, \
  1888. .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
  1889. .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
  1890. }
  1891. #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
  1892. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  1893. .info = snd_cmipci_info_native_mixer, \
  1894. .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
  1895. .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
  1896. }
  1897. #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
  1898. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  1899. .info = snd_cmipci_info_native_mixer, \
  1900. .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
  1901. .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
  1902. }
  1903. static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
  1904. struct snd_ctl_elem_info *uinfo)
  1905. {
  1906. struct cmipci_sb_reg reg;
  1907. cmipci_sb_reg_decode(&reg, kcontrol->private_value);
  1908. uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1909. uinfo->count = reg.stereo + 1;
  1910. uinfo->value.integer.min = 0;
  1911. uinfo->value.integer.max = reg.mask;
  1912. return 0;
  1913. }
  1914. static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
  1915. struct snd_ctl_elem_value *ucontrol)
  1916. {
  1917. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  1918. struct cmipci_sb_reg reg;
  1919. unsigned char oreg, val;
  1920. cmipci_sb_reg_decode(&reg, kcontrol->private_value);
  1921. spin_lock_irq(&cm->reg_lock);
  1922. oreg = inb(cm->iobase + reg.left_reg);
  1923. val = (oreg >> reg.left_shift) & reg.mask;
  1924. if (reg.invert)
  1925. val = reg.mask - val;
  1926. ucontrol->value.integer.value[0] = val;
  1927. if (reg.stereo) {
  1928. val = (oreg >> reg.right_shift) & reg.mask;
  1929. if (reg.invert)
  1930. val = reg.mask - val;
  1931. ucontrol->value.integer.value[1] = val;
  1932. }
  1933. spin_unlock_irq(&cm->reg_lock);
  1934. return 0;
  1935. }
  1936. static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
  1937. struct snd_ctl_elem_value *ucontrol)
  1938. {
  1939. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  1940. struct cmipci_sb_reg reg;
  1941. unsigned char oreg, nreg, val;
  1942. cmipci_sb_reg_decode(&reg, kcontrol->private_value);
  1943. spin_lock_irq(&cm->reg_lock);
  1944. oreg = inb(cm->iobase + reg.left_reg);
  1945. val = ucontrol->value.integer.value[0] & reg.mask;
  1946. if (reg.invert)
  1947. val = reg.mask - val;
  1948. nreg = oreg & ~(reg.mask << reg.left_shift);
  1949. nreg |= (val << reg.left_shift);
  1950. if (reg.stereo) {
  1951. val = ucontrol->value.integer.value[1] & reg.mask;
  1952. if (reg.invert)
  1953. val = reg.mask - val;
  1954. nreg &= ~(reg.mask << reg.right_shift);
  1955. nreg |= (val << reg.right_shift);
  1956. }
  1957. outb(nreg, cm->iobase + reg.left_reg);
  1958. spin_unlock_irq(&cm->reg_lock);
  1959. return (nreg != oreg);
  1960. }
  1961. /*
  1962. * special case - check mixer sensitivity
  1963. */
  1964. static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
  1965. struct snd_ctl_elem_value *ucontrol)
  1966. {
  1967. //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  1968. return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
  1969. }
  1970. static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
  1971. struct snd_ctl_elem_value *ucontrol)
  1972. {
  1973. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  1974. if (cm->mixer_insensitive) {
  1975. /* ignored */
  1976. return 0;
  1977. }
  1978. return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
  1979. }
  1980. static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
  1981. CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
  1982. CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
  1983. CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
  1984. //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
  1985. { /* switch with sensitivity */
  1986. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1987. .name = "PCM Playback Switch",
  1988. .info = snd_cmipci_info_native_mixer,
  1989. .get = snd_cmipci_get_native_mixer_sensitive,
  1990. .put = snd_cmipci_put_native_mixer_sensitive,
  1991. .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
  1992. },
  1993. CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
  1994. CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
  1995. CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
  1996. CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
  1997. CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
  1998. CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
  1999. CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
  2000. CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
  2001. CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
  2002. CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
  2003. CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
  2004. CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
  2005. CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
  2006. CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
  2007. CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
  2008. CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
  2009. CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
  2010. CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
  2011. CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
  2012. CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
  2013. CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
  2014. CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
  2015. CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
  2016. };
  2017. /*
  2018. * other switches
  2019. */
  2020. struct cmipci_switch_args {
  2021. int reg; /* register index */
  2022. unsigned int mask; /* mask bits */
  2023. unsigned int mask_on; /* mask bits to turn on */
  2024. unsigned int is_byte: 1; /* byte access? */
  2025. unsigned int ac3_sensitive: 1; /* access forbidden during
  2026. * non-audio operation?
  2027. */
  2028. };
  2029. #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
  2030. static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
  2031. struct snd_ctl_elem_value *ucontrol,
  2032. struct cmipci_switch_args *args)
  2033. {
  2034. unsigned int val;
  2035. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  2036. spin_lock_irq(&cm->reg_lock);
  2037. if (args->ac3_sensitive && cm->mixer_insensitive) {
  2038. ucontrol->value.integer.value[0] = 0;
  2039. spin_unlock_irq(&cm->reg_lock);
  2040. return 0;
  2041. }
  2042. if (args->is_byte)
  2043. val = inb(cm->iobase + args->reg);
  2044. else
  2045. val = snd_cmipci_read(cm, args->reg);
  2046. ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
  2047. spin_unlock_irq(&cm->reg_lock);
  2048. return 0;
  2049. }
  2050. static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
  2051. struct snd_ctl_elem_value *ucontrol)
  2052. {
  2053. struct cmipci_switch_args *args;
  2054. args = (struct cmipci_switch_args *)kcontrol->private_value;
  2055. if (snd_BUG_ON(!args))
  2056. return -EINVAL;
  2057. return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
  2058. }
  2059. static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
  2060. struct snd_ctl_elem_value *ucontrol,
  2061. struct cmipci_switch_args *args)
  2062. {
  2063. unsigned int val;
  2064. int change;
  2065. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  2066. spin_lock_irq(&cm->reg_lock);
  2067. if (args->ac3_sensitive && cm->mixer_insensitive) {
  2068. /* ignored */
  2069. spin_unlock_irq(&cm->reg_lock);
  2070. return 0;
  2071. }
  2072. if (args->is_byte)
  2073. val = inb(cm->iobase + args->reg);
  2074. else
  2075. val = snd_cmipci_read(cm, args->reg);
  2076. change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
  2077. args->mask_on : (args->mask & ~args->mask_on));
  2078. if (change) {
  2079. val &= ~args->mask;
  2080. if (ucontrol->value.integer.value[0])
  2081. val |= args->mask_on;
  2082. else
  2083. val |= (args->mask & ~args->mask_on);
  2084. if (args->is_byte)
  2085. outb((unsigned char)val, cm->iobase + args->reg);
  2086. else
  2087. snd_cmipci_write(cm, args->reg, val);
  2088. }
  2089. spin_unlock_irq(&cm->reg_lock);
  2090. return change;
  2091. }
  2092. static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
  2093. struct snd_ctl_elem_value *ucontrol)
  2094. {
  2095. struct cmipci_switch_args *args;
  2096. args = (struct cmipci_switch_args *)kcontrol->private_value;
  2097. if (snd_BUG_ON(!args))
  2098. return -EINVAL;
  2099. return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
  2100. }
  2101. #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
  2102. static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
  2103. .reg = xreg, \
  2104. .mask = xmask, \
  2105. .mask_on = xmask_on, \
  2106. .is_byte = xis_byte, \
  2107. .ac3_sensitive = xac3, \
  2108. }
  2109. #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
  2110. DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
  2111. #if 0 /* these will be controlled in pcm device */
  2112. DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
  2113. DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
  2114. #endif
  2115. DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
  2116. DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
  2117. DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
  2118. DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
  2119. DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
  2120. DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
  2121. DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
  2122. DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
  2123. // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
  2124. DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
  2125. DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
  2126. /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
  2127. DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
  2128. DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
  2129. #if CM_CH_PLAY == 1
  2130. DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
  2131. #else
  2132. DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
  2133. #endif
  2134. DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
  2135. // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
  2136. // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
  2137. // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
  2138. DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
  2139. #define DEFINE_SWITCH(sname, stype, sarg) \
  2140. { .name = sname, \
  2141. .iface = stype, \
  2142. .info = snd_cmipci_uswitch_info, \
  2143. .get = snd_cmipci_uswitch_get, \
  2144. .put = snd_cmipci_uswitch_put, \
  2145. .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
  2146. }
  2147. #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
  2148. #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
  2149. /*
  2150. * callbacks for spdif output switch
  2151. * needs toggle two registers..
  2152. */
  2153. static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
  2154. struct snd_ctl_elem_value *ucontrol)
  2155. {
  2156. int changed;
  2157. changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
  2158. changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
  2159. return changed;
  2160. }
  2161. static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
  2162. struct snd_ctl_elem_value *ucontrol)
  2163. {
  2164. struct cmipci *chip = snd_kcontrol_chip(kcontrol);
  2165. int changed;
  2166. changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
  2167. changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
  2168. if (changed) {
  2169. if (ucontrol->value.integer.value[0]) {
  2170. if (chip->spdif_playback_avail)
  2171. snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
  2172. } else {
  2173. if (chip->spdif_playback_avail)
  2174. snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
  2175. }
  2176. }
  2177. chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
  2178. return changed;
  2179. }
  2180. static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
  2181. struct snd_ctl_elem_info *uinfo)
  2182. {
  2183. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  2184. static const char *const texts[3] = {
  2185. "Line-In", "Rear Output", "Bass Output"
  2186. };
  2187. return snd_ctl_enum_info(uinfo, 1,
  2188. cm->chip_version >= 39 ? 3 : 2, texts);
  2189. }
  2190. static inline unsigned int get_line_in_mode(struct cmipci *cm)
  2191. {
  2192. unsigned int val;
  2193. if (cm->chip_version >= 39) {
  2194. val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
  2195. if (val & (CM_CENTR2LIN | CM_BASE2LIN))
  2196. return 2;
  2197. }
  2198. val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
  2199. if (val & CM_REAR2LIN)
  2200. return 1;
  2201. return 0;
  2202. }
  2203. static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
  2204. struct snd_ctl_elem_value *ucontrol)
  2205. {
  2206. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  2207. spin_lock_irq(&cm->reg_lock);
  2208. ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
  2209. spin_unlock_irq(&cm->reg_lock);
  2210. return 0;
  2211. }
  2212. static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
  2213. struct snd_ctl_elem_value *ucontrol)
  2214. {
  2215. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  2216. int change;
  2217. spin_lock_irq(&cm->reg_lock);
  2218. if (ucontrol->value.enumerated.item[0] == 2)
  2219. change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
  2220. else
  2221. change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
  2222. if (ucontrol->value.enumerated.item[0] == 1)
  2223. change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
  2224. else
  2225. change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
  2226. spin_unlock_irq(&cm->reg_lock);
  2227. return change;
  2228. }
  2229. static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
  2230. struct snd_ctl_elem_info *uinfo)
  2231. {
  2232. static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
  2233. return snd_ctl_enum_info(uinfo, 1, 2, texts);
  2234. }
  2235. static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
  2236. struct snd_ctl_elem_value *ucontrol)
  2237. {
  2238. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  2239. /* same bit as spdi_phase */
  2240. spin_lock_irq(&cm->reg_lock);
  2241. ucontrol->value.enumerated.item[0] =
  2242. (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
  2243. spin_unlock_irq(&cm->reg_lock);
  2244. return 0;
  2245. }
  2246. static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
  2247. struct snd_ctl_elem_value *ucontrol)
  2248. {
  2249. struct cmipci *cm = snd_kcontrol_chip(kcontrol);
  2250. int change;
  2251. spin_lock_irq(&cm->reg_lock);
  2252. if (ucontrol->value.enumerated.item[0])
  2253. change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
  2254. else
  2255. change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
  2256. spin_unlock_irq(&cm->reg_lock);
  2257. return change;
  2258. }
  2259. /* both for CM8338/8738 */
  2260. static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
  2261. DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
  2262. {
  2263. .name = "Line-In Mode",
  2264. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2265. .info = snd_cmipci_line_in_mode_info,
  2266. .get = snd_cmipci_line_in_mode_get,
  2267. .put = snd_cmipci_line_in_mode_put,
  2268. },
  2269. };
  2270. /* for non-multichannel chips */
  2271. static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
  2272. DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
  2273. /* only for CM8738 */
  2274. static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
  2275. #if 0 /* controlled in pcm device */
  2276. DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
  2277. DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
  2278. DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
  2279. #endif
  2280. // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
  2281. { .name = "IEC958 Output Switch",
  2282. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2283. .info = snd_cmipci_uswitch_info,
  2284. .get = snd_cmipci_spdout_enable_get,
  2285. .put = snd_cmipci_spdout_enable_put,
  2286. },
  2287. DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
  2288. DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
  2289. DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
  2290. // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
  2291. DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
  2292. DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
  2293. };
  2294. /* only for model 033/037 */
  2295. static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
  2296. DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
  2297. DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
  2298. DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
  2299. };
  2300. /* only for model 039 or later */
  2301. static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
  2302. DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
  2303. DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
  2304. {
  2305. .name = "Mic-In Mode",
  2306. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2307. .info = snd_cmipci_mic_in_mode_info,
  2308. .get = snd_cmipci_mic_in_mode_get,
  2309. .put = snd_cmipci_mic_in_mode_put,
  2310. }
  2311. };
  2312. /* card control switches */
  2313. static const struct snd_kcontrol_new snd_cmipci_modem_switch =
  2314. DEFINE_CARD_SWITCH("Modem", modem);
  2315. static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
  2316. {
  2317. struct snd_card *card;
  2318. const struct snd_kcontrol_new *sw;
  2319. struct snd_kcontrol *kctl;
  2320. unsigned int idx;
  2321. int err;
  2322. if (snd_BUG_ON(!cm || !cm->card))
  2323. return -EINVAL;
  2324. card = cm->card;
  2325. strcpy(card->mixername, "CMedia PCI");
  2326. spin_lock_irq(&cm->reg_lock);
  2327. snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
  2328. spin_unlock_irq(&cm->reg_lock);
  2329. for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
  2330. if (cm->chip_version == 68) { // 8768 has no PCM volume
  2331. if (!strcmp(snd_cmipci_mixers[idx].name,
  2332. "PCM Playback Volume"))
  2333. continue;
  2334. }
  2335. if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
  2336. return err;
  2337. }
  2338. /* mixer switches */
  2339. sw = snd_cmipci_mixer_switches;
  2340. for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
  2341. err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
  2342. if (err < 0)
  2343. return err;
  2344. }
  2345. if (! cm->can_multi_ch) {
  2346. err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
  2347. if (err < 0)
  2348. return err;
  2349. }
  2350. if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
  2351. cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
  2352. sw = snd_cmipci_8738_mixer_switches;
  2353. for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
  2354. err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
  2355. if (err < 0)
  2356. return err;
  2357. }
  2358. if (cm->can_ac3_hw) {
  2359. if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
  2360. return err;
  2361. kctl->id.device = pcm_spdif_device;
  2362. if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
  2363. return err;
  2364. kctl->id.device = pcm_spdif_device;
  2365. if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
  2366. return err;
  2367. kctl->id.device = pcm_spdif_device;
  2368. }
  2369. if (cm->chip_version <= 37) {
  2370. sw = snd_cmipci_old_mixer_switches;
  2371. for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
  2372. err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
  2373. if (err < 0)
  2374. return err;
  2375. }
  2376. }
  2377. }
  2378. if (cm->chip_version >= 39) {
  2379. sw = snd_cmipci_extra_mixer_switches;
  2380. for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
  2381. err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
  2382. if (err < 0)
  2383. return err;
  2384. }
  2385. }
  2386. /* card switches */
  2387. /*
  2388. * newer chips don't have the register bits to force modem link
  2389. * detection; the bit that was FLINKON now mutes CH1
  2390. */
  2391. if (cm->chip_version < 39) {
  2392. err = snd_ctl_add(cm->card,
  2393. snd_ctl_new1(&snd_cmipci_modem_switch, cm));
  2394. if (err < 0)
  2395. return err;
  2396. }
  2397. for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
  2398. struct snd_ctl_elem_id elem_id;
  2399. struct snd_kcontrol *ctl;
  2400. memset(&elem_id, 0, sizeof(elem_id));
  2401. elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  2402. strcpy(elem_id.name, cm_saved_mixer[idx].name);
  2403. ctl = snd_ctl_find_id(cm->card, &elem_id);
  2404. if (ctl)
  2405. cm->mixer_res_ctl[idx] = ctl;
  2406. }
  2407. return 0;
  2408. }
  2409. /*
  2410. * proc interface
  2411. */
  2412. static void snd_cmipci_proc_read(struct snd_info_entry *entry,
  2413. struct snd_info_buffer *buffer)
  2414. {
  2415. struct cmipci *cm = entry->private_data;
  2416. int i, v;
  2417. snd_iprintf(buffer, "%s\n", cm->card->longname);
  2418. for (i = 0; i < 0x94; i++) {
  2419. if (i == 0x28)
  2420. i = 0x90;
  2421. v = inb(cm->iobase + i);
  2422. if (i % 4 == 0)
  2423. snd_iprintf(buffer, "\n%02x:", i);
  2424. snd_iprintf(buffer, " %02x", v);
  2425. }
  2426. snd_iprintf(buffer, "\n");
  2427. }
  2428. static void snd_cmipci_proc_init(struct cmipci *cm)
  2429. {
  2430. snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
  2431. }
  2432. static const struct pci_device_id snd_cmipci_ids[] = {
  2433. {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
  2434. {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
  2435. {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
  2436. {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
  2437. {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
  2438. {0,},
  2439. };
  2440. /*
  2441. * check chip version and capabilities
  2442. * driver name is modified according to the chip model
  2443. */
  2444. static void query_chip(struct cmipci *cm)
  2445. {
  2446. unsigned int detect;
  2447. /* check reg 0Ch, bit 24-31 */
  2448. detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
  2449. if (! detect) {
  2450. /* check reg 08h, bit 24-28 */
  2451. detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
  2452. switch (detect) {
  2453. case 0:
  2454. cm->chip_version = 33;
  2455. if (cm->do_soft_ac3)
  2456. cm->can_ac3_sw = 1;
  2457. else
  2458. cm->can_ac3_hw = 1;
  2459. break;
  2460. case CM_CHIP_037:
  2461. cm->chip_version = 37;
  2462. cm->can_ac3_hw = 1;
  2463. break;
  2464. default:
  2465. cm->chip_version = 39;
  2466. cm->can_ac3_hw = 1;
  2467. break;
  2468. }
  2469. cm->max_channels = 2;
  2470. } else {
  2471. if (detect & CM_CHIP_039) {
  2472. cm->chip_version = 39;
  2473. if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
  2474. cm->max_channels = 6;
  2475. else
  2476. cm->max_channels = 4;
  2477. } else if (detect & CM_CHIP_8768) {
  2478. cm->chip_version = 68;
  2479. cm->max_channels = 8;
  2480. cm->can_96k = 1;
  2481. } else {
  2482. cm->chip_version = 55;
  2483. cm->max_channels = 6;
  2484. cm->can_96k = 1;
  2485. }
  2486. cm->can_ac3_hw = 1;
  2487. cm->can_multi_ch = 1;
  2488. }
  2489. }
  2490. #ifdef SUPPORT_JOYSTICK
  2491. static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
  2492. {
  2493. static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
  2494. struct gameport *gp;
  2495. struct resource *r = NULL;
  2496. int i, io_port = 0;
  2497. if (joystick_port[dev] == 0)
  2498. return -ENODEV;
  2499. if (joystick_port[dev] == 1) { /* auto-detect */
  2500. for (i = 0; ports[i]; i++) {
  2501. io_port = ports[i];
  2502. r = request_region(io_port, 1, "CMIPCI gameport");
  2503. if (r)
  2504. break;
  2505. }
  2506. } else {
  2507. io_port = joystick_port[dev];
  2508. r = request_region(io_port, 1, "CMIPCI gameport");
  2509. }
  2510. if (!r) {
  2511. dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
  2512. return -EBUSY;
  2513. }
  2514. cm->gameport = gp = gameport_allocate_port();
  2515. if (!gp) {
  2516. dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
  2517. release_and_free_resource(r);
  2518. return -ENOMEM;
  2519. }
  2520. gameport_set_name(gp, "C-Media Gameport");
  2521. gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
  2522. gameport_set_dev_parent(gp, &cm->pci->dev);
  2523. gp->io = io_port;
  2524. gameport_set_port_data(gp, r);
  2525. snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
  2526. gameport_register_port(cm->gameport);
  2527. return 0;
  2528. }
  2529. static void snd_cmipci_free_gameport(struct cmipci *cm)
  2530. {
  2531. if (cm->gameport) {
  2532. struct resource *r = gameport_get_port_data(cm->gameport);
  2533. gameport_unregister_port(cm->gameport);
  2534. cm->gameport = NULL;
  2535. snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
  2536. release_and_free_resource(r);
  2537. }
  2538. }
  2539. #else
  2540. static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
  2541. static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
  2542. #endif
  2543. static int snd_cmipci_free(struct cmipci *cm)
  2544. {
  2545. if (cm->irq >= 0) {
  2546. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
  2547. snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
  2548. snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
  2549. snd_cmipci_ch_reset(cm, CM_CH_PLAY);
  2550. snd_cmipci_ch_reset(cm, CM_CH_CAPT);
  2551. snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
  2552. snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
  2553. /* reset mixer */
  2554. snd_cmipci_mixer_write(cm, 0, 0);
  2555. free_irq(cm->irq, cm);
  2556. }
  2557. snd_cmipci_free_gameport(cm);
  2558. pci_release_regions(cm->pci);
  2559. pci_disable_device(cm->pci);
  2560. kfree(cm);
  2561. return 0;
  2562. }
  2563. static int snd_cmipci_dev_free(struct snd_device *device)
  2564. {
  2565. struct cmipci *cm = device->device_data;
  2566. return snd_cmipci_free(cm);
  2567. }
  2568. static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
  2569. {
  2570. long iosynth;
  2571. unsigned int val;
  2572. struct snd_opl3 *opl3;
  2573. int err;
  2574. if (!fm_port)
  2575. goto disable_fm;
  2576. if (cm->chip_version >= 39) {
  2577. /* first try FM regs in PCI port range */
  2578. iosynth = cm->iobase + CM_REG_FM_PCI;
  2579. err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
  2580. OPL3_HW_OPL3, 1, &opl3);
  2581. } else {
  2582. err = -EIO;
  2583. }
  2584. if (err < 0) {
  2585. /* then try legacy ports */
  2586. val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
  2587. iosynth = fm_port;
  2588. switch (iosynth) {
  2589. case 0x3E8: val |= CM_FMSEL_3E8; break;
  2590. case 0x3E0: val |= CM_FMSEL_3E0; break;
  2591. case 0x3C8: val |= CM_FMSEL_3C8; break;
  2592. case 0x388: val |= CM_FMSEL_388; break;
  2593. default:
  2594. goto disable_fm;
  2595. }
  2596. snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
  2597. /* enable FM */
  2598. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
  2599. if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
  2600. OPL3_HW_OPL3, 0, &opl3) < 0) {
  2601. dev_err(cm->card->dev,
  2602. "no OPL device at %#lx, skipping...\n",
  2603. iosynth);
  2604. goto disable_fm;
  2605. }
  2606. }
  2607. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  2608. dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
  2609. return err;
  2610. }
  2611. return 0;
  2612. disable_fm:
  2613. snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
  2614. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
  2615. return 0;
  2616. }
  2617. static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
  2618. int dev, struct cmipci **rcmipci)
  2619. {
  2620. struct cmipci *cm;
  2621. int err;
  2622. static const struct snd_device_ops ops = {
  2623. .dev_free = snd_cmipci_dev_free,
  2624. };
  2625. unsigned int val;
  2626. long iomidi = 0;
  2627. int integrated_midi = 0;
  2628. char modelstr[16];
  2629. int pcm_index, pcm_spdif_index;
  2630. static const struct pci_device_id intel_82437vx[] = {
  2631. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
  2632. { },
  2633. };
  2634. *rcmipci = NULL;
  2635. if ((err = pci_enable_device(pci)) < 0)
  2636. return err;
  2637. cm = kzalloc(sizeof(*cm), GFP_KERNEL);
  2638. if (cm == NULL) {
  2639. pci_disable_device(pci);
  2640. return -ENOMEM;
  2641. }
  2642. spin_lock_init(&cm->reg_lock);
  2643. mutex_init(&cm->open_mutex);
  2644. cm->device = pci->device;
  2645. cm->card = card;
  2646. cm->pci = pci;
  2647. cm->irq = -1;
  2648. cm->channel[0].ch = 0;
  2649. cm->channel[1].ch = 1;
  2650. cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
  2651. if ((err = pci_request_regions(pci, card->driver)) < 0) {
  2652. kfree(cm);
  2653. pci_disable_device(pci);
  2654. return err;
  2655. }
  2656. cm->iobase = pci_resource_start(pci, 0);
  2657. if (request_irq(pci->irq, snd_cmipci_interrupt,
  2658. IRQF_SHARED, KBUILD_MODNAME, cm)) {
  2659. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2660. snd_cmipci_free(cm);
  2661. return -EBUSY;
  2662. }
  2663. cm->irq = pci->irq;
  2664. card->sync_irq = cm->irq;
  2665. pci_set_master(cm->pci);
  2666. /*
  2667. * check chip version, max channels and capabilities
  2668. */
  2669. cm->chip_version = 0;
  2670. cm->max_channels = 2;
  2671. cm->do_soft_ac3 = soft_ac3[dev];
  2672. if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
  2673. pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
  2674. query_chip(cm);
  2675. /* added -MCx suffix for chip supporting multi-channels */
  2676. if (cm->can_multi_ch)
  2677. sprintf(cm->card->driver + strlen(cm->card->driver),
  2678. "-MC%d", cm->max_channels);
  2679. else if (cm->can_ac3_sw)
  2680. strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
  2681. cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
  2682. cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
  2683. #if CM_CH_PLAY == 1
  2684. cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
  2685. #else
  2686. cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
  2687. #endif
  2688. /* initialize codec registers */
  2689. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
  2690. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
  2691. snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
  2692. snd_cmipci_ch_reset(cm, CM_CH_PLAY);
  2693. snd_cmipci_ch_reset(cm, CM_CH_CAPT);
  2694. snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
  2695. snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
  2696. snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
  2697. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
  2698. #if CM_CH_PLAY == 1
  2699. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
  2700. #else
  2701. snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
  2702. #endif
  2703. if (cm->chip_version) {
  2704. snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
  2705. snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
  2706. }
  2707. /* Set Bus Master Request */
  2708. snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
  2709. /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
  2710. switch (pci->device) {
  2711. case PCI_DEVICE_ID_CMEDIA_CM8738:
  2712. case PCI_DEVICE_ID_CMEDIA_CM8738B:
  2713. if (!pci_dev_present(intel_82437vx))
  2714. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
  2715. break;
  2716. default:
  2717. break;
  2718. }
  2719. if (cm->chip_version < 68) {
  2720. val = pci->device < 0x110 ? 8338 : 8738;
  2721. } else {
  2722. switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
  2723. case 0:
  2724. val = 8769;
  2725. break;
  2726. case 2:
  2727. val = 8762;
  2728. break;
  2729. default:
  2730. switch ((pci->subsystem_vendor << 16) |
  2731. pci->subsystem_device) {
  2732. case 0x13f69761:
  2733. case 0x584d3741:
  2734. case 0x584d3751:
  2735. case 0x584d3761:
  2736. case 0x584d3771:
  2737. case 0x72848384:
  2738. val = 8770;
  2739. break;
  2740. default:
  2741. val = 8768;
  2742. break;
  2743. }
  2744. }
  2745. }
  2746. sprintf(card->shortname, "C-Media CMI%d", val);
  2747. if (cm->chip_version < 68)
  2748. sprintf(modelstr, " (model %d)", cm->chip_version);
  2749. else
  2750. modelstr[0] = '\0';
  2751. sprintf(card->longname, "%s%s at %#lx, irq %i",
  2752. card->shortname, modelstr, cm->iobase, cm->irq);
  2753. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
  2754. snd_cmipci_free(cm);
  2755. return err;
  2756. }
  2757. if (cm->chip_version >= 39) {
  2758. val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
  2759. if (val != 0x00 && val != 0xff) {
  2760. if (mpu_port[dev])
  2761. iomidi = cm->iobase + CM_REG_MPU_PCI;
  2762. integrated_midi = 1;
  2763. }
  2764. }
  2765. if (!integrated_midi) {
  2766. val = 0;
  2767. iomidi = mpu_port[dev];
  2768. switch (iomidi) {
  2769. case 0x320: val = CM_VMPU_320; break;
  2770. case 0x310: val = CM_VMPU_310; break;
  2771. case 0x300: val = CM_VMPU_300; break;
  2772. case 0x330: val = CM_VMPU_330; break;
  2773. default:
  2774. iomidi = 0; break;
  2775. }
  2776. if (iomidi > 0) {
  2777. snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
  2778. /* enable UART */
  2779. snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
  2780. if (inb(iomidi + 1) == 0xff) {
  2781. dev_err(cm->card->dev,
  2782. "cannot enable MPU-401 port at %#lx\n",
  2783. iomidi);
  2784. snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
  2785. CM_UART_EN);
  2786. iomidi = 0;
  2787. }
  2788. }
  2789. }
  2790. if (cm->chip_version < 68) {
  2791. err = snd_cmipci_create_fm(cm, fm_port[dev]);
  2792. if (err < 0)
  2793. return err;
  2794. }
  2795. /* reset mixer */
  2796. snd_cmipci_mixer_write(cm, 0, 0);
  2797. snd_cmipci_proc_init(cm);
  2798. /* create pcm devices */
  2799. pcm_index = pcm_spdif_index = 0;
  2800. if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
  2801. return err;
  2802. pcm_index++;
  2803. if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
  2804. return err;
  2805. pcm_index++;
  2806. if (cm->can_ac3_hw || cm->can_ac3_sw) {
  2807. pcm_spdif_index = pcm_index;
  2808. if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
  2809. return err;
  2810. }
  2811. /* create mixer interface & switches */
  2812. if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
  2813. return err;
  2814. if (iomidi > 0) {
  2815. if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
  2816. iomidi,
  2817. (integrated_midi ?
  2818. MPU401_INFO_INTEGRATED : 0) |
  2819. MPU401_INFO_IRQ_HOOK,
  2820. -1, &cm->rmidi)) < 0) {
  2821. dev_err(cm->card->dev,
  2822. "no UART401 device at 0x%lx\n", iomidi);
  2823. }
  2824. }
  2825. #ifdef USE_VAR48KRATE
  2826. for (val = 0; val < ARRAY_SIZE(rates); val++)
  2827. snd_cmipci_set_pll(cm, rates[val], val);
  2828. /*
  2829. * (Re-)Enable external switch spdo_48k
  2830. */
  2831. snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
  2832. #endif /* USE_VAR48KRATE */
  2833. if (snd_cmipci_create_gameport(cm, dev) < 0)
  2834. snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
  2835. *rcmipci = cm;
  2836. return 0;
  2837. }
  2838. /*
  2839. */
  2840. MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
  2841. static int snd_cmipci_probe(struct pci_dev *pci,
  2842. const struct pci_device_id *pci_id)
  2843. {
  2844. static int dev;
  2845. struct snd_card *card;
  2846. struct cmipci *cm;
  2847. int err;
  2848. if (dev >= SNDRV_CARDS)
  2849. return -ENODEV;
  2850. if (! enable[dev]) {
  2851. dev++;
  2852. return -ENOENT;
  2853. }
  2854. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  2855. 0, &card);
  2856. if (err < 0)
  2857. return err;
  2858. switch (pci->device) {
  2859. case PCI_DEVICE_ID_CMEDIA_CM8738:
  2860. case PCI_DEVICE_ID_CMEDIA_CM8738B:
  2861. strcpy(card->driver, "CMI8738");
  2862. break;
  2863. case PCI_DEVICE_ID_CMEDIA_CM8338A:
  2864. case PCI_DEVICE_ID_CMEDIA_CM8338B:
  2865. strcpy(card->driver, "CMI8338");
  2866. break;
  2867. default:
  2868. strcpy(card->driver, "CMIPCI");
  2869. break;
  2870. }
  2871. err = snd_cmipci_create(card, pci, dev, &cm);
  2872. if (err < 0)
  2873. goto free_card;
  2874. card->private_data = cm;
  2875. err = snd_card_register(card);
  2876. if (err < 0)
  2877. goto free_card;
  2878. pci_set_drvdata(pci, card);
  2879. dev++;
  2880. return 0;
  2881. free_card:
  2882. snd_card_free(card);
  2883. return err;
  2884. }
  2885. static void snd_cmipci_remove(struct pci_dev *pci)
  2886. {
  2887. snd_card_free(pci_get_drvdata(pci));
  2888. }
  2889. #ifdef CONFIG_PM_SLEEP
  2890. /*
  2891. * power management
  2892. */
  2893. static const unsigned char saved_regs[] = {
  2894. CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
  2895. CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL,
  2896. CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
  2897. CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
  2898. CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
  2899. };
  2900. static const unsigned char saved_mixers[] = {
  2901. SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
  2902. SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
  2903. SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
  2904. SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
  2905. SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
  2906. SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
  2907. CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
  2908. SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
  2909. };
  2910. static int snd_cmipci_suspend(struct device *dev)
  2911. {
  2912. struct snd_card *card = dev_get_drvdata(dev);
  2913. struct cmipci *cm = card->private_data;
  2914. int i;
  2915. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2916. /* save registers */
  2917. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  2918. cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
  2919. for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
  2920. cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
  2921. /* disable ints */
  2922. snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
  2923. return 0;
  2924. }
  2925. static int snd_cmipci_resume(struct device *dev)
  2926. {
  2927. struct snd_card *card = dev_get_drvdata(dev);
  2928. struct cmipci *cm = card->private_data;
  2929. int i;
  2930. /* reset / initialize to a sane state */
  2931. snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
  2932. snd_cmipci_ch_reset(cm, CM_CH_PLAY);
  2933. snd_cmipci_ch_reset(cm, CM_CH_CAPT);
  2934. snd_cmipci_mixer_write(cm, 0, 0);
  2935. /* restore registers */
  2936. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  2937. snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
  2938. for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
  2939. snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
  2940. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2941. return 0;
  2942. }
  2943. static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
  2944. #define SND_CMIPCI_PM_OPS &snd_cmipci_pm
  2945. #else
  2946. #define SND_CMIPCI_PM_OPS NULL
  2947. #endif /* CONFIG_PM_SLEEP */
  2948. static struct pci_driver cmipci_driver = {
  2949. .name = KBUILD_MODNAME,
  2950. .id_table = snd_cmipci_ids,
  2951. .probe = snd_cmipci_probe,
  2952. .remove = snd_cmipci_remove,
  2953. .driver = {
  2954. .pm = SND_CMIPCI_PM_OPS,
  2955. },
  2956. };
  2957. module_pci_driver(cmipci_driver);